dd5ad5fb77| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | host_smoke | i2c_host_smoke | 2.043m | 9.458ms | 50 | 50 | 100.00 |
| V1 | target_smoke | i2c_target_smoke | 57.960s | 1.931ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | i2c_csr_hw_reset | 0.770s | 19.161us | 5 | 5 | 100.00 |
| V1 | csr_rw | i2c_csr_rw | 2.370s | 736.389us | 19 | 20 | 95.00 |
| V1 | csr_bit_bash | i2c_csr_bit_bash | 6.250s | 629.644us | 4 | 5 | 80.00 |
| V1 | csr_aliasing | i2c_csr_aliasing | 2.240s | 492.048us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | i2c_csr_mem_rw_with_rand_reset | 1.370s | 57.475us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | i2c_csr_rw | 2.370s | 736.389us | 19 | 20 | 95.00 |
| i2c_csr_aliasing | 2.240s | 492.048us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 153 | 155 | 98.71 | |||
| V2 | host_error_intr | i2c_host_error_intr | 15.390s | 1.457ms | 49 | 50 | 98.00 |
| V2 | host_stress_all | i2c_host_stress_all | 55.998m | 32.467ms | 43 | 50 | 86.00 |
| V2 | host_maxperf | i2c_host_perf | 35.639m | 51.854ms | 50 | 50 | 100.00 |
| V2 | host_override | i2c_host_override | 0.760s | 34.866us | 50 | 50 | 100.00 |
| V2 | host_fifo_watermark | i2c_host_fifo_watermark | 7.761m | 10.299ms | 50 | 50 | 100.00 |
| V2 | host_fifo_overflow | i2c_host_fifo_overflow | 3.436m | 5.901ms | 50 | 50 | 100.00 |
| V2 | host_fifo_reset | i2c_host_fifo_reset_fmt | 1.310s | 175.427us | 50 | 50 | 100.00 |
| i2c_host_fifo_fmt_empty | 32.420s | 1.157ms | 50 | 50 | 100.00 | ||
| i2c_host_fifo_reset_rx | 12.550s | 992.395us | 50 | 50 | 100.00 | ||
| V2 | host_fifo_full | i2c_host_fifo_full | 3.821m | 18.453ms | 50 | 50 | 100.00 |
| V2 | host_timeout | i2c_host_stretch_timeout | 45.110s | 2.013ms | 50 | 50 | 100.00 |
| V2 | host_rx_oversample | i2c_host_rx_oversample | 0 | 0 | -- | ||
| V2 | i2c_host_mode_toggle | i2c_host_mode_toggle | 2.070m | 2.400ms | 50 | 50 | 100.00 |
| V2 | target_error_intr | i2c_target_unexp_stop | 31.005m | 50.000ms | 0 | 50 | 0.00 |
| V2 | target_glitch | i2c_target_glitch | 11.590s | 2.530ms | 2 | 2 | 100.00 |
| V2 | target_stress_all | i2c_target_stress_all | 11.608m | 32.250ms | 1 | 50 | 2.00 |
| V2 | target_maxperf | i2c_target_perf | 1.090s | 261.993us | 0 | 50 | 0.00 |
| V2 | target_fifo_empty | i2c_target_stress_rd | 1.290m | 1.814ms | 50 | 50 | 100.00 |
| i2c_target_intr_smoke | 8.110s | 1.559ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_reset | i2c_target_fifo_reset_acq | 50.820s | 10.125ms | 50 | 50 | 100.00 |
| i2c_target_fifo_reset_tx | 1.343m | 10.138ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_full | i2c_target_stress_wr | 54.356m | 68.954ms | 50 | 50 | 100.00 |
| i2c_target_stress_rd | 1.290m | 1.814ms | 50 | 50 | 100.00 | ||
| i2c_target_intr_stress_wr | 11.317m | 27.791ms | 50 | 50 | 100.00 | ||
| V2 | target_timeout | i2c_target_timeout | 8.370s | 1.593ms | 50 | 50 | 100.00 |
| V2 | target_clock_stretch | i2c_target_stretch | 58.557m | 19.167ms | 46 | 50 | 92.00 |
| V2 | bad_address | i2c_target_bad_addr | 6.230s | 4.345ms | 50 | 50 | 100.00 |
| V2 | target_mode_glitch | i2c_target_hrst | 3.210s | 557.772us | 50 | 50 | 100.00 |
| V2 | target_fifo_watermark | i2c_target_fifo_watermarks_acq | 6.670s | 1.387ms | 50 | 50 | 100.00 |
| i2c_target_fifo_watermarks_tx | 5.930s | 1.037ms | 50 | 50 | 100.00 | ||
| V2 | host_mode_config_perf | host_mode_config_perf | 0 | 0 | -- | ||
| V2 | host_mode_clock_stretching | host_mode_clock_stretching | 0 | 0 | -- | ||
| V2 | target_mode_tx_stretch_ctrl | i2c_target_tx_stretch_ctrl | 26.350s | 2.288ms | 50 | 50 | 100.00 |
| V2 | target_mode_nack_generation | target_mode_nack_generation | 0 | 0 | -- | ||
| V2 | host_mode_halt_on_nak | host_mode_halt_on_nak | 0 | 0 | -- | ||
| V2 | target_mode_n_byte_ack_control | target_mode_n_byte_ack_control | 0 | 0 | -- | ||
| V2 | target_mode_bus_timeout | target_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_timeout | controller_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_idle_delay | controller_mode_bus_idle_delay | 0 | 0 | -- | ||
| V2 | loopback_test | loopback_test | 0 | 0 | -- | ||
| V2 | multi_controller_clock_synchronization | multi_controller_clock_synchronization | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost_interference | multi_controller_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost | multi_controller_arbitration_lost | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost_interference | target_mode_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost | target_mode_arbitration_lost | 0 | 0 | -- | ||
| V2 | alert_test | i2c_alert_test | 0.720s | 46.584us | 50 | 50 | 100.00 |
| V2 | intr_test | i2c_intr_test | 0.770s | 30.303us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | i2c_tl_errors | 2.890s | 250.064us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | i2c_tl_errors | 2.890s | 250.064us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | i2c_csr_hw_reset | 0.770s | 19.161us | 5 | 5 | 100.00 |
| i2c_csr_rw | 2.370s | 736.389us | 19 | 20 | 95.00 | ||
| i2c_csr_aliasing | 2.240s | 492.048us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.380s | 91.256us | 17 | 20 | 85.00 | ||
| V2 | tl_d_partial_access | i2c_csr_hw_reset | 0.770s | 19.161us | 5 | 5 | 100.00 |
| i2c_csr_rw | 2.370s | 736.389us | 19 | 20 | 95.00 | ||
| i2c_csr_aliasing | 2.240s | 492.048us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.380s | 91.256us | 17 | 20 | 85.00 | ||
| V2 | TOTAL | 1378 | 1542 | 89.36 | |||
| V2S | tl_intg_err | i2c_tl_intg_err | 2.540s | 265.556us | 20 | 20 | 100.00 |
| i2c_sec_cm | 0.960s | 74.744us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | i2c_tl_intg_err | 2.540s | 265.556us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | host_stress_all_with_rand_reset | i2c_host_stress_all_with_rand_reset | 19.037m | 20.522ms | 0 | 50 | 0.00 |
| V3 | target_stress_all_with_rand_reset | i2c_target_stress_all_with_rand_reset | 4.092m | 15.540ms | 0 | 50 | 0.00 |
| V3 | target_loopback | 0 | 0 | -- | |||
| V3 | TOTAL | 0 | 100 | 0.00 | |||
| Unmapped tests | i2c_host_may_nack | 27.090s | 2.634ms | 50 | 50 | 100.00 | |
| TOTAL | 1606 | 1872 | 85.79 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 1 | 1 | 1 | 100.00 |
| V1 | 7 | 7 | 5 | 71.43 |
| V2 | 48 | 33 | 26 | 54.17 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 3 | 2 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 90.80 | 96.57 | 89.80 | 97.22 | 69.05 | 93.55 | 98.44 | 90.95 |
UVM_ERROR (i2c_monitor.sv:317) [monitor] Check failed r_bit === *'b* (* [*] vs * [*]) has 93 failures:
0.i2c_target_perf.6210684187414042113921180628842917123160087100529596348168314179552504850965
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_perf/latest/run.log
UVM_ERROR @ 272154177 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 272154177 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_perf.92059613134706577780177086017593735940683010999180570829555058583865087798620
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_perf/latest/run.log
UVM_ERROR @ 29488312 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 29488312 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 47 more failures.
0.i2c_target_stress_all.14483176829503076758734603458232920208158345230909920724116830891082419711443
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 222747831 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 222747831 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_stress_all.33978204271533229284155909637058916892799700199668145639241042119366716718956
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 19532321924 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 19532321924 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 19 more failures.
0.i2c_target_stress_all_with_rand_reset.103778139346046878230817688742977999008248782769677570750859246387293897931652
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 32680416 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 32680416 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.i2c_target_stress_all_with_rand_reset.87957306111384756719152742500552990651843130203662342391073701962021565820100
Line 287, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 20840247582 ps: (i2c_monitor.sv:317) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 20840247582 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 21 more failures.
UVM_ERROR (cip_base_vseq.sv:828) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 53 failures:
0.i2c_host_stress_all_with_rand_reset.98616545196778640791478722598370146458854161769814230063940924665211890486779
Line 3185, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 4868896982 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 4868896982 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_host_stress_all_with_rand_reset.45069852997775941793587074450019661373270473350600569020685605887574040401442
Line 685, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 5739878946 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 5739878946 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 44 more failures.
3.i2c_target_stress_all_with_rand_reset.2657782331039780630652946088474854003689614620547385410632415948797283395622
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1844619249 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1844619249 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.i2c_target_stress_all_with_rand_reset.93375722849093674888607833563203520555242062632348179038994466909222961589179
Line 265, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 3407003215 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3407003215 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
UVM_ERROR (i2c_scoreboard.sv:788) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 49 failures:
1.i2c_target_stress_all_with_rand_reset.89671549022576978117482974387768554269432290899778397218378887143297681390012
Line 308, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 4540660376 ps: (i2c_scoreboard.sv:788) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 57 [0x39])
UVM_INFO @ 4540660376 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
11.i2c_target_stress_all_with_rand_reset.50535685492473521614004070213169833097904020088150724008781184708954884428925
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/11.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1664752167 ps: (i2c_scoreboard.sv:788) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 219 [0xdb])
UVM_INFO @ 1664752167 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
2.i2c_target_stress_all.33906689705520751753247085439481123144316989747737947575539155007017176902011
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 5452376704 ps: (i2c_scoreboard.sv:788) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 182 [0xb6])
UVM_INFO @ 5452376704 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.i2c_target_stress_all.41580255811642016333676212118714380123794051334588981944576509177375051357721
Line 289, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 49853517360 ps: (i2c_scoreboard.sv:788) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 182 [0xb6])
UVM_INFO @ 49853517360 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 14 more failures.
3.i2c_target_unexp_stop.83663172303843575880471137042867216143919708241058353420307250414704031339531
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 50716983 ps: (i2c_scoreboard.sv:788) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 90 [0x5a])
UVM_INFO @ 50716983 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.i2c_target_unexp_stop.107126340011072351288447705081308460087570113986385920193564122408788210556481
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 188726592 ps: (i2c_scoreboard.sv:788) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 102 [0x66])
UVM_INFO @ 188726592 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 22 more failures.
UVM_ERROR (i2c_scoreboard.sv:774) [scoreboard] Check failed obs.stop == exp.stop (* [*] vs * [*]) has 33 failures:
1.i2c_target_unexp_stop.36080617538894975999220497923328357371091862169627538641621978386491085117422
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 273716676 ps: (i2c_scoreboard.sv:774) [uvm_test_top.env.scoreboard] Check failed obs.stop == exp.stop (1 [0x1] vs 0 [0x0])
UVM_INFO @ 273716676 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_unexp_stop.30068077928483296265637755115536485857823850132246179607570579245342602149415
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 121603230 ps: (i2c_scoreboard.sv:774) [uvm_test_top.env.scoreboard] Check failed obs.stop == exp.stop (1 [0x1] vs 0 [0x0])
UVM_INFO @ 121603230 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 14 more failures.
2.i2c_target_stress_all_with_rand_reset.45789746258808006589055552864679772543727547523602666459872860226466670513385
Line 279, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2548811713 ps: (i2c_scoreboard.sv:774) [uvm_test_top.env.scoreboard] Check failed obs.stop == exp.stop (1 [0x1] vs 0 [0x0])
UVM_INFO @ 2548811713 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
12.i2c_target_stress_all_with_rand_reset.107358008626693432042324273691668822770287043395503603938118451568195040343796
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/12.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 80820567 ps: (i2c_scoreboard.sv:774) [uvm_test_top.env.scoreboard] Check failed obs.stop == exp.stop (1 [0x1] vs 0 [0x0])
UVM_INFO @ 80820567 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
5.i2c_target_stress_all.65046633606664205262647093389114939372960126432266193050802153539943028137698
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 218619437 ps: (i2c_scoreboard.sv:774) [uvm_test_top.env.scoreboard] Check failed obs.stop == exp.stop (1 [0x1] vs 0 [0x0])
UVM_INFO @ 218619437 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.i2c_target_stress_all.114877214227056990248629634377754625513711691222414408446306978615881996334293
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 1476107606 ps: (i2c_scoreboard.sv:774) [uvm_test_top.env.scoreboard] Check failed obs.stop == exp.stop (1 [0x1] vs 0 [0x0])
UVM_INFO @ 1476107606 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
13.i2c_target_perf.94391645714981105986250844023516851911217000896271411992252926017043476956128
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/13.i2c_target_perf/latest/run.log
UVM_ERROR @ 58888161 ps: (i2c_scoreboard.sv:774) [uvm_test_top.env.scoreboard] Check failed obs.stop == exp.stop (1 [0x1] vs 0 [0x0])
UVM_INFO @ 58888161 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job i2c-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 14 failures:
Test i2c_target_stretch has 4 failures.
4.i2c_target_stretch.2191639112714225984581429395206073157455207499074332630968115305313533271764
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stretch/latest/run.log
Job ID: smart:6f0e6d73-a5f9-4702-9007-2418be277e60
10.i2c_target_stretch.98108561460734341364864901257227144022313508622656413994152058975651939647759
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/10.i2c_target_stretch/latest/run.log
Job ID: smart:27cc7f1a-dac1-42a7-82d0-a33c59e9a8be
... and 2 more failures.
Test i2c_host_stress_all has 4 failures.
5.i2c_host_stress_all.54678616289289478198639190117373984422055074049577628291426109559826937765082
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_host_stress_all/latest/run.log
Job ID: smart:40c61565-4561-4640-92eb-016f229e6ceb
20.i2c_host_stress_all.57278149878638507167388666891693855866302764249878829908038878707414123193850
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/20.i2c_host_stress_all/latest/run.log
Job ID: smart:0184b9ff-8a05-4b77-9950-4a717313f2c8
... and 2 more failures.
Test i2c_target_unexp_stop has 1 failures.
11.i2c_target_unexp_stop.81732193305418333222059179579995609884665379894589120545302565360384315937207
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/11.i2c_target_unexp_stop/latest/run.log
Job ID: smart:c8a5d495-91df-4c66-a259-fd73473ce0ce
Test i2c_target_stress_all has 3 failures.
14.i2c_target_stress_all.67031135775443523512271373595391180547422193782016932184010014904986526085286
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/14.i2c_target_stress_all/latest/run.log
Job ID: smart:ee6075b6-8234-4915-9a2d-56da44f97d3f
41.i2c_target_stress_all.72846980349167075470668346883893693993903682792157325067655974960075985879504
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/41.i2c_target_stress_all/latest/run.log
Job ID: smart:5c425f72-9c25-47de-9a34-1e131aa3de62
... and 1 more failures.
Test i2c_host_stress_all_with_rand_reset has 2 failures.
23.i2c_host_stress_all_with_rand_reset.10223766587527518969322040813237579200188080111760771190014587077570655177220
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/23.i2c_host_stress_all_with_rand_reset/latest/run.log
Job ID: smart:afa3f592-4dd0-4290-9529-840fe7708eff
24.i2c_host_stress_all_with_rand_reset.27758837452834752224790228808406462480281081617113140707026193581617133836168
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/24.i2c_host_stress_all_with_rand_reset/latest/run.log
Job ID: smart:cdc12876-ea15-4666-bf25-a41a5ecd4b70
UVM_ERROR (i2c_scoreboard.sv:695) scoreboard [scoreboard] has 6 failures:
Test i2c_host_error_intr has 1 failures.
4.i2c_host_error_intr.76671282280615560458496429246025724588245545400242356254889458746816113826212
Line 1348, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_host_error_intr/latest/run.log
UVM_ERROR @ 255184067 ps: (i2c_scoreboard.sv:695) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
direction READ item mismatch!
--> EXP:
-----------------------------------------------
Name Type Size Value
Test i2c_host_stress_all_with_rand_reset has 2 failures.
6.i2c_host_stress_all_with_rand_reset.98195928444263769117863191155864023485538284409901468627773340579068659001493
Line 1437, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 5222976837 ps: (i2c_scoreboard.sv:695) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
direction READ item mismatch!
--> EXP:
-----------------------------------------------
Name Type Size Value
45.i2c_host_stress_all_with_rand_reset.27890543979450759207479091792283758213003632232227066721768700119654420613137
Line 8920, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/45.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 9348649958 ps: (i2c_scoreboard.sv:695) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
direction READ item mismatch!
--> EXP:
-----------------------------------------------
Name Type Size Value
Test i2c_host_stress_all has 3 failures.
10.i2c_host_stress_all.38598035404487119792779693464775277835796245612445338062680210301930955286880
Line 5836, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/10.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 32467399718 ps: (i2c_scoreboard.sv:695) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
direction WRITE item mismatch!
--> EXP:
------------------------------------------------
Name Type Size Value
23.i2c_host_stress_all.29152286074466569447571982113039784267362198973834090110025263762715141734957
Line 1195, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/23.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 1066928714 ps: (i2c_scoreboard.sv:695) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
direction WRITE item mismatch!
--> EXP:
------------------------------------------------
Name Type Size Value
... and 1 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 4 failures:
0.i2c_target_unexp_stop.81112385814879921033973878084799227367498563889784024375846000603286441417641
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
10.i2c_target_unexp_stop.99043958230663165318702983784587063235775103990946688912489954371432755281036
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/10.i2c_target_unexp_stop/latest/run.log
UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_ERROR (i2c_base_vseq.sv:992) virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout has 4 failures:
23.i2c_target_unexp_stop.20813776495965372413999230620136711888902964884286327490259405771758654960497
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/23.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 4191028621 ps: (i2c_base_vseq.sv:992) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
UVM_INFO @ 4191028621 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
33.i2c_target_unexp_stop.65510348080260924539897400410008844345081910610890050222914870532957330024426
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/33.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 740320085 ps: (i2c_base_vseq.sv:992) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
UVM_INFO @ 740320085 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_FATAL (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=*) == * has 3 failures:
19.i2c_target_stress_all_with_rand_reset.104815436066137747562281010436097879096581827184531049872835597610696244685560
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/19.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 10919632779 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=0x4eb14514) == 0x0
UVM_INFO @ 10919632779 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
27.i2c_target_stress_all_with_rand_reset.96386418197193523981148120077624483711719956831989161947161573214188051832105
Line 355, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/27.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 71358894999 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=0xaa91fd94) == 0x0
UVM_INFO @ 71358894999 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (cip_base_vseq.sv:503) [i2c_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) has 2 failures:
9.i2c_same_csr_outstanding.55280207810336757510432968792529119428484718382346829853412302842450343013485
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_same_csr_outstanding/latest/run.log
UVM_ERROR @ 32693211 ps: (cip_base_vseq.sv:503) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed data & ~ro_mask == 0 (64 [0x40] vs 0 [0x0])
UVM_INFO @ 32693211 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
10.i2c_same_csr_outstanding.12904400028165022466372615119877391594688555412223374312736977298356717033986
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/10.i2c_same_csr_outstanding/latest/run.log
UVM_ERROR @ 78404332 ps: (cip_base_vseq.sv:503) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed data & ~ro_mask == 0 (64 [0x40] vs 0 [0x0])
UVM_INFO @ 78404332 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.controller_events.arbitration_lost reset value: * has 1 failures:
0.i2c_csr_rw.110790656258696400793260054377435399795226983466859629153146359165118841752019
Line 249, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_csr_rw/latest/run.log
UVM_ERROR @ 8048111 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.controller_events.arbitration_lost reset value: 0x0
UVM_INFO @ 8048111 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 1 failures:
1.i2c_csr_bit_bash.90792944547410685316135970490936520664856143802165702055609870929321100660373
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_csr_bit_bash/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 890272107 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 890272107 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:250) [i2c_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch has 1 failures:
3.i2c_same_csr_outstanding.39579031678740914152960370872362014239656166579724029001724249553609459256692
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_same_csr_outstanding/latest/run.log
UVM_ERROR @ 35060785 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed masked_data == exp_data (8 [0x8] vs 0 [0x0]) addr 0x4a6b7f8 read out mismatch
UVM_INFO @ 35060785 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:784) [scoreboard] Check failed obs.num_data == exp.num_data (* [*] vs * [*]) has 1 failures:
6.i2c_target_unexp_stop.27264819800270093945168459346990050081149064621962481883105405799324505354148
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 59009714 ps: (i2c_scoreboard.sv:784) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (6 [0x6] vs 5 [0x5])
UVM_INFO @ 59009714 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_driver.sv:237) [i2c_drv_scl] wait timeout occurred! has 1 failures:
34.i2c_target_stress_all.93895118917841686955795351121019158650201834971650680103868904237265351912973
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/34.i2c_target_stress_all/latest/run.log
UVM_FATAL @ 102271060893 ps: (i2c_driver.sv:237) [i2c_drv_scl] wait timeout occurred!
UVM_INFO @ 102271060893 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---