25e609d6bb| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | host_smoke | i2c_host_smoke | 1.839m | 8.803ms | 50 | 50 | 100.00 |
| V1 | target_smoke | i2c_target_smoke | 58.840s | 1.471ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | i2c_csr_hw_reset | 0.810s | 26.804us | 5 | 5 | 100.00 |
| V1 | csr_rw | i2c_csr_rw | 0.840s | 27.882us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | i2c_csr_bit_bash | 4.480s | 1.671ms | 3 | 5 | 60.00 |
| V1 | csr_aliasing | i2c_csr_aliasing | 2.090s | 711.286us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | i2c_csr_mem_rw_with_rand_reset | 1.730s | 390.798us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | i2c_csr_rw | 0.840s | 27.882us | 20 | 20 | 100.00 |
| i2c_csr_aliasing | 2.090s | 711.286us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 153 | 155 | 98.71 | |||
| V2 | host_error_intr | i2c_host_error_intr | 23.650s | 2.170ms | 49 | 50 | 98.00 |
| V2 | host_stress_all | i2c_host_stress_all | 58.216m | 118.976ms | 45 | 50 | 90.00 |
| V2 | host_maxperf | i2c_host_perf | 31.744m | 95.850ms | 49 | 50 | 98.00 |
| V2 | host_override | i2c_host_override | 0.720s | 27.029us | 50 | 50 | 100.00 |
| V2 | host_fifo_watermark | i2c_host_fifo_watermark | 6.055m | 20.814ms | 50 | 50 | 100.00 |
| V2 | host_fifo_overflow | i2c_host_fifo_overflow | 3.224m | 2.735ms | 50 | 50 | 100.00 |
| V2 | host_fifo_reset | i2c_host_fifo_reset_fmt | 1.240s | 712.640us | 50 | 50 | 100.00 |
| i2c_host_fifo_fmt_empty | 29.910s | 571.074us | 50 | 50 | 100.00 | ||
| i2c_host_fifo_reset_rx | 13.490s | 240.466us | 50 | 50 | 100.00 | ||
| V2 | host_fifo_full | i2c_host_fifo_full | 3.396m | 2.853ms | 49 | 50 | 98.00 |
| V2 | host_timeout | i2c_host_stretch_timeout | 48.310s | 1.262ms | 50 | 50 | 100.00 |
| V2 | host_rx_oversample | i2c_host_rx_oversample | 0 | 0 | -- | ||
| V2 | i2c_host_mode_toggle | i2c_host_mode_toggle | 2.175m | 2.375ms | 49 | 50 | 98.00 |
| V2 | target_error_intr | i2c_target_unexp_stop | 39.551m | 50.000ms | 0 | 50 | 0.00 |
| V2 | target_glitch | i2c_target_glitch | 10.030s | 7.948ms | 2 | 2 | 100.00 |
| V2 | target_stress_all | i2c_target_stress_all | 42.969m | 100.352ms | 0 | 50 | 0.00 |
| V2 | target_maxperf | i2c_target_perf | 14.728m | 20.000ms | 0 | 50 | 0.00 |
| V2 | target_fifo_empty | i2c_target_stress_rd | 1.297m | 6.895ms | 50 | 50 | 100.00 |
| i2c_target_intr_smoke | 8.310s | 6.496ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_reset | i2c_target_fifo_reset_acq | 1.730s | 277.184us | 50 | 50 | 100.00 |
| i2c_target_fifo_reset_tx | 1.550s | 280.989us | 50 | 50 | 100.00 | ||
| V2 | target_fifo_full | i2c_target_stress_wr | 41.168m | 70.828ms | 50 | 50 | 100.00 |
| i2c_target_stress_rd | 1.297m | 6.895ms | 50 | 50 | 100.00 | ||
| i2c_target_intr_stress_wr | 6.393m | 18.979ms | 50 | 50 | 100.00 | ||
| V2 | target_timeout | i2c_target_timeout | 8.940s | 1.629ms | 50 | 50 | 100.00 |
| V2 | target_clock_stretch | i2c_target_stretch | 43.461m | 38.319ms | 50 | 50 | 100.00 |
| V2 | bad_address | i2c_target_bad_addr | 5.830s | 1.326ms | 50 | 50 | 100.00 |
| V2 | target_mode_glitch | i2c_target_hrst | 2.295m | 10.147ms | 30 | 50 | 60.00 |
| V2 | target_fifo_watermark | i2c_target_fifo_watermarks_acq | 3.040s | 3.821ms | 50 | 50 | 100.00 |
| i2c_target_fifo_watermarks_tx | 1.390s | 644.881us | 50 | 50 | 100.00 | ||
| V2 | host_mode_config_perf | i2c_host_perf | 31.744m | 95.850ms | 49 | 50 | 98.00 |
| i2c_host_perf_precise | 50.880m | 24.316ms | 49 | 50 | 98.00 | ||
| V2 | host_mode_clock_stretching | i2c_host_stretch_timeout | 48.310s | 1.262ms | 50 | 50 | 100.00 |
| V2 | target_mode_tx_stretch_ctrl | i2c_target_tx_stretch_ctrl | 2.990s | 198.706us | 0 | 50 | 0.00 |
| V2 | target_mode_nack_generation | target_mode_nack_generation | 0 | 0 | -- | ||
| V2 | host_mode_halt_on_nak | host_mode_halt_on_nak | 0 | 0 | -- | ||
| V2 | target_mode_n_byte_ack_control | target_mode_n_byte_ack_control | 0 | 0 | -- | ||
| V2 | target_mode_bus_timeout | target_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_timeout | controller_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_idle_delay | controller_mode_bus_idle_delay | 0 | 0 | -- | ||
| V2 | loopback_test | loopback_test | 0 | 0 | -- | ||
| V2 | multi_controller_clock_synchronization | multi_controller_clock_synchronization | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost_interference | multi_controller_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost | multi_controller_arbitration_lost | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost_interference | target_mode_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost | target_mode_arbitration_lost | 0 | 0 | -- | ||
| V2 | alert_test | i2c_alert_test | 0.700s | 44.954us | 50 | 50 | 100.00 |
| V2 | intr_test | i2c_intr_test | 0.750s | 17.650us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | i2c_tl_errors | 2.820s | 166.636us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | i2c_tl_errors | 2.820s | 166.636us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | i2c_csr_hw_reset | 0.810s | 26.804us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.840s | 27.882us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 2.090s | 711.286us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.270s | 54.902us | 19 | 20 | 95.00 | ||
| V2 | tl_d_partial_access | i2c_csr_hw_reset | 0.810s | 26.804us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.840s | 27.882us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 2.090s | 711.286us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.270s | 54.902us | 19 | 20 | 95.00 | ||
| V2 | TOTAL | 1361 | 1592 | 85.49 | |||
| V2S | tl_intg_err | i2c_tl_intg_err | 2.450s | 160.555us | 20 | 20 | 100.00 |
| i2c_sec_cm | 0.930s | 87.908us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | i2c_tl_intg_err | 2.450s | 160.555us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | host_stress_all_with_rand_reset | i2c_host_stress_all_with_rand_reset | 9.905m | 31.360ms | 0 | 10 | 0.00 |
| V3 | target_stress_all_with_rand_reset | i2c_target_stress_all_with_rand_reset | 2.111m | 11.120ms | 0 | 10 | 0.00 |
| V3 | target_loopback | 0 | 0 | -- | |||
| V3 | TOTAL | 0 | 20 | 0.00 | |||
| Unmapped tests | i2c_host_may_nack | 27.150s | 1.337ms | 50 | 50 | 100.00 | |
| TOTAL | 1589 | 1842 | 86.26 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 1 | 1 | 1 | 100.00 |
| V1 | 7 | 7 | 6 | 85.71 |
| V2 | 47 | 34 | 22 | 46.81 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 3 | 2 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 90.91 | 96.60 | 89.80 | 97.22 | 69.64 | 93.62 | 98.44 | 91.05 |
UVM_ERROR (i2c_scoreboard.sv:604) [scoreboard] Check failed obs.num_data == exp.num_data (* [*] vs * [*]) has 53 failures:
0.i2c_target_stress_all_with_rand_reset.90577880045779324323712972185524031196218944930748330221993805898112865394876
Line 294, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 6968406621 ps: (i2c_scoreboard.sv:604) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (6 [0x6] vs 9 [0x9])
UVM_INFO @ 6968406621 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.i2c_target_stress_all_with_rand_reset.17811960310102354428806256819090424675805404100338591783430709535977386190075
Line 265, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 7508022182 ps: (i2c_scoreboard.sv:604) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (3 [0x3] vs 14 [0xe])
UVM_INFO @ 7508022182 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
1.i2c_target_unexp_stop.36666626816380673714963876939024092853269537736163571713836474708798322963599
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 54730599 ps: (i2c_scoreboard.sv:604) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (0 [0x0] vs 3 [0x3])
UVM_INFO @ 54730599 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
16.i2c_target_unexp_stop.44978831638848943888005573560734548049013605140415577952420879276320684951229
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/16.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 149678441 ps: (i2c_scoreboard.sv:604) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (0 [0x0] vs 14 [0xe])
UVM_INFO @ 149678441 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 15 more failures.
1.i2c_target_stress_all.102818479437627643465232178126017244675085648741601420684591059500105793980571
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 1460917725 ps: (i2c_scoreboard.sv:604) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (19 [0x13] vs 15 [0xf])
UVM_INFO @ 1460917725 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_stress_all.96872399829918256334479522642501473529082415107004622040409612765894962954431
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 473808484 ps: (i2c_scoreboard.sv:604) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (0 [0x0] vs 3 [0x3])
UVM_INFO @ 473808484 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 25 more failures.
10.i2c_target_hrst.28589668801594374323287516659631325386883421234247636249102745574260943065951
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/10.i2c_target_hrst/latest/run.log
UVM_ERROR @ 229783221 ps: (i2c_scoreboard.sv:604) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (40 [0x28] vs 1 [0x1])
UVM_INFO @ 229783221 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
14.i2c_target_hrst.40567172020498731365955423120252711456570573382328146109261088846713362992123
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/14.i2c_target_hrst/latest/run.log
UVM_ERROR @ 44967182 ps: (i2c_scoreboard.sv:604) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (5 [0x5] vs 2 [0x2])
UVM_INFO @ 44967182 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
UVM_FATAL (i2c_driver.sv:148) driver [driver] has 50 failures:
0.i2c_target_tx_stretch_ctrl.16607901859405250853909568608062189505880432594753728904735328601728558144603
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_tx_stretch_ctrl/latest/run.log
UVM_FATAL @ 13688921 ps: (i2c_driver.sv:148) uvm_test_top.env.m_i2c_agent.driver [uvm_test_top.env.m_i2c_agent.driver]
host_driver, received invalid request
UVM_INFO @ 13688921 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_tx_stretch_ctrl.104174198327055761182644271863103603446748898145712462771914846814500835407482
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_tx_stretch_ctrl/latest/run.log
UVM_FATAL @ 2229064 ps: (i2c_driver.sv:148) uvm_test_top.env.m_i2c_agent.driver [uvm_test_top.env.m_i2c_agent.driver]
host_driver, received invalid request
UVM_INFO @ 2229064 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 48 more failures.
UVM_FATAL (i2c_base_vseq.sv:1175) [stop_interrupt_handler] wait timeout occurred! has 34 failures:
1.i2c_target_perf.66960655251067396084892255258113180446528050050647454342946814626749317292801
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_perf/latest/run.log
UVM_FATAL @ 13451434193 ps: (i2c_base_vseq.sv:1175) [stop_interrupt_handler] wait timeout occurred!
UVM_INFO @ 13451434193 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.i2c_target_perf.18326662765659994805866975232608057789430289526290400977856148851046893893678
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_perf/latest/run.log
UVM_FATAL @ 11874440489 ps: (i2c_base_vseq.sv:1175) [stop_interrupt_handler] wait timeout occurred!
UVM_INFO @ 11874440489 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 26 more failures.
4.i2c_target_stress_all.14637431347506692054779326656958063808264231323828849741503248801955704925413
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_all/latest/run.log
UVM_FATAL @ 11006557685 ps: (i2c_base_vseq.sv:1175) [stop_interrupt_handler] wait timeout occurred!
UVM_INFO @ 11006557685 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.i2c_target_stress_all.42526803426642019762941913855079581750251193884385776218814030344563724539740
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_stress_all/latest/run.log
UVM_FATAL @ 11172002083 ps: (i2c_base_vseq.sv:1175) [stop_interrupt_handler] wait timeout occurred!
UVM_INFO @ 11172002083 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 27 failures:
0.i2c_target_unexp_stop.48186392737618958754128425093023402691971779997231650447687157185627276926481
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.i2c_target_unexp_stop.45314660115228606081899061985894995021856887744273995539518838501031596673792
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_unexp_stop/latest/run.log
UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 12 more failures.
0.i2c_target_perf.61761730521732579140181730940230037027877795487016200082090638691548804398381
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_perf/latest/run.log
UVM_FATAL @ 20000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 20000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 20000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_perf.2292444587765289542228443894773039833574326303542976305829556719494646515190
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_perf/latest/run.log
UVM_FATAL @ 20000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 20000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 20000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 11 more failures.
Job i2c-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 23 failures:
Test i2c_host_stress_all has 1 failures.
3.i2c_host_stress_all.37306252772223606017337134382581079527216732904609910446992640110036162364458
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_host_stress_all/latest/run.log
Job ID: smart:7b002316-67c8-45b8-aeca-172ad039248d
Test i2c_target_unexp_stop has 11 failures.
3.i2c_target_unexp_stop.33142470765981350341234773740417703322105821006043842343895357700556718079902
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_unexp_stop/latest/run.log
Job ID: smart:5a29d549-49cc-435c-8c9c-07419a0a7882
4.i2c_target_unexp_stop.75777903532635602073825011117777977704532841389357039541808171301607946424099
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_unexp_stop/latest/run.log
Job ID: smart:4d4862df-d2a2-4ccc-a4d4-37264c05c3a3
... and 9 more failures.
Test i2c_host_stress_all_with_rand_reset has 2 failures.
4.i2c_host_stress_all_with_rand_reset.10939407484138007730701076429011048486130012564881871451651976953612485419729
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_host_stress_all_with_rand_reset/latest/run.log
Job ID: smart:86803402-787a-4474-83ed-b7b7d593c1db
7.i2c_host_stress_all_with_rand_reset.96009454742301677255430419952192290658865934385192329132514902019477097988147
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_host_stress_all_with_rand_reset/latest/run.log
Job ID: smart:4502580b-5087-48a9-a95d-648f43913e44
Test i2c_target_stress_all has 8 failures.
5.i2c_target_stress_all.31288156224855988984949314741920925870585587982114475352827425458076299749328
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_stress_all/latest/run.log
Job ID: smart:7efdbb7f-f98b-4c13-9392-45a6424cd50e
7.i2c_target_stress_all.68322107075754967119370462469010596283859536820051847727325470479907875861342
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_stress_all/latest/run.log
Job ID: smart:f99729f1-14a9-433c-992e-ea58a6ebafef
... and 6 more failures.
Test i2c_host_perf has 1 failures.
42.i2c_host_perf.38471691205049998720705313559600533669682436362249001322376857961378509929684
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/42.i2c_host_perf/latest/run.log
Job ID: smart:3809f199-c413-4a85-b904-609fe31f3724
UVM_ERROR (i2c_scoreboard.sv:608) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 18 failures:
Test i2c_target_stress_all_with_rand_reset has 3 failures.
1.i2c_target_stress_all_with_rand_reset.3449537717871726990660902354512261663869658772617616911797353038498632988421
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 54940743 ps: (i2c_scoreboard.sv:608) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 207 [0xcf])
UVM_INFO @ 54940743 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_stress_all_with_rand_reset.947512714704836735621348428434897389976961283228881966395704224170574476419
Line 265, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 5835382335 ps: (i2c_scoreboard.sv:608) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (178 [0xb2] vs 212 [0xd4])
UVM_INFO @ 5835382335 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Test i2c_target_perf has 9 failures.
7.i2c_target_perf.38134321398476464518113205587647673919781519086456494227357145558285781086411
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_perf/latest/run.log
UVM_ERROR @ 32332754 ps: (i2c_scoreboard.sv:608) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 24 [0x18])
UVM_INFO @ 32332754 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
21.i2c_target_perf.67062738366536249108536741762904734974301381696904899798766731981039860578558
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/21.i2c_target_perf/latest/run.log
UVM_ERROR @ 46754649 ps: (i2c_scoreboard.sv:608) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 241 [0xf1])
UVM_INFO @ 46754649 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
Test i2c_target_hrst has 1 failures.
7.i2c_target_hrst.106778021329492929231295010976836950715096539071818508941603322168261799069767
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_hrst/latest/run.log
UVM_ERROR @ 34659181 ps: (i2c_scoreboard.sv:608) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (64 [0x40] vs 93 [0x5d])
UVM_INFO @ 34659181 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test i2c_target_stress_all has 5 failures.
9.i2c_target_stress_all.115524904390281387991418404286116498717169022486622936895715789512702255850619
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 19835126169 ps: (i2c_scoreboard.sv:608) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (142 [0x8e] vs 8 [0x8])
UVM_INFO @ 19835126169 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
22.i2c_target_stress_all.97327130819805272931124103846075519842546083814075026080240122141433680224059
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/22.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 89303888 ps: (i2c_scoreboard.sv:608) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 163 [0xa3])
UVM_INFO @ 89303888 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_ERROR (cip_base_vseq.sv:828) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 9 failures:
0.i2c_host_stress_all_with_rand_reset.44788648536166149886412249070429364609945848152434911691266909615348675235998
Line 945, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 669729280 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 669729280 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_host_stress_all_with_rand_reset.7016325479403755265843612387724440041282456722669841248003145404166139529664
Line 2728, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 40552865848 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 40552865848 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
5.i2c_target_stress_all_with_rand_reset.99142651865448513196501794858840669954688387148319593303904979321438841177437
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 170261519 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 170261519 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_base_vseq.sv:992) virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout has 8 failures:
2.i2c_target_unexp_stop.64538649182209805233497890859568018205506792741396905287238901349109109805760
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 797499453 ps: (i2c_base_vseq.sv:992) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
UVM_INFO @ 797499453 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
13.i2c_target_unexp_stop.18500643853097539603008285403777403774887537700267164078114908325499351785665
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/13.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 1434788480 ps: (i2c_base_vseq.sv:992) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
UVM_INFO @ 1434788480 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
UVM_ERROR (i2c_scoreboard.sv:559) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite has 5 failures:
Test i2c_host_error_intr has 1 failures.
1.i2c_host_error_intr.39778058673735111113123815295016314197324185659314386521313744353302343301605
Line 896, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_error_intr/latest/run.log
UVM_ERROR @ 365538793 ps: (i2c_scoreboard.sv:559) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite
--> EXP:
-----------------------------------------------------
Name Type Size Value
-----------------------------------------------------
Test i2c_host_stress_all has 4 failures.
7.i2c_host_stress_all.98320800304163300573638301263092233906247702953142039271074911327737213040413
Line 4395, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 36776263870 ps: (i2c_scoreboard.sv:559) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite
--> EXP:
-----------------------------------------------------
Name Type Size Value
-----------------------------------------------------
9.i2c_host_stress_all.21924674261944284550484706923725231531798903430995589059587531052789823298393
Line 2618, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 47559363311 ps: (i2c_scoreboard.sv:559) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite
--> EXP:
-----------------------------------------------------
Name Type Size Value
-----------------------------------------------------
... and 2 more failures.
UVM_FATAL (i2c_target_hrst_vseq.sv:193) [i2c_target_hrst_vseq] Timed-out waiting for target_mode_wr_exp_fifo to become empty. has 5 failures:
2.i2c_target_hrst.105495375430036822887402601985284817542294291106509599427004677063976567614764
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10146506382 ps: (i2c_target_hrst_vseq.sv:193) [uvm_test_top.env.virtual_sequencer.i2c_target_hrst_vseq] Timed-out waiting for target_mode_wr_exp_fifo to become empty.
UVM_INFO @ 10146506382 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.i2c_target_hrst.12872471262700285373221454813792064572292358658455974716211565994040272990282
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10228390251 ps: (i2c_target_hrst_vseq.sv:193) [uvm_test_top.env.virtual_sequencer.i2c_target_hrst_vseq] Timed-out waiting for target_mode_wr_exp_fifo to become empty.
UVM_INFO @ 10228390251 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_FATAL (i2c_driver.sv:234) [i2c_drv_scl] wait timeout occurred! has 4 failures:
0.i2c_target_stress_all.60479726898809257211836521003226220665676483438560756878624472723782670381694
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all/latest/run.log
UVM_FATAL @ 100351923557 ps: (i2c_driver.sv:234) [i2c_drv_scl] wait timeout occurred!
UVM_INFO @ 100351923557 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
33.i2c_target_stress_all.44121849979119799105795227817778566685884834087807585681126276167251463322023
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/33.i2c_target_stress_all/latest/run.log
UVM_FATAL @ 100752253980 ps: (i2c_driver.sv:234) [i2c_drv_scl] wait timeout occurred!
UVM_INFO @ 100752253980 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_ERROR (i2c_scoreboard.sv:584) [scoreboard] Check failed obs.start == exp.start (* [*] vs * [*]) has 4 failures:
5.i2c_target_hrst.86115036745552889250618151680090103214292745092283014716294558133556063408076
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_hrst/latest/run.log
UVM_ERROR @ 64814992 ps: (i2c_scoreboard.sv:584) [uvm_test_top.env.scoreboard] Check failed obs.start == exp.start (1 [0x1] vs 0 [0x0])
UVM_INFO @ 64814992 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
13.i2c_target_hrst.75915612946764008082524962037723871966786726505959864312283734760670865259040
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/13.i2c_target_hrst/latest/run.log
UVM_ERROR @ 61320143 ps: (i2c_scoreboard.sv:584) [uvm_test_top.env.scoreboard] Check failed obs.start == exp.start (1 [0x1] vs 0 [0x0])
UVM_INFO @ 61320143 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_ERROR (i2c_scoreboard.sv:587) [scoreboard] Check failed obs.wdata == exp.wdata (* [*] vs * [*]) has 3 failures:
0.i2c_target_hrst.82843695151679373486044692153866199104529757995412020032669314233496747223228
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log
UVM_ERROR @ 6269473 ps: (i2c_scoreboard.sv:587) [uvm_test_top.env.scoreboard] Check failed obs.wdata == exp.wdata (84 [0x54] vs 85 [0x55])
UVM_INFO @ 6269473 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
27.i2c_target_hrst.5401291136551906910110155845253451413859552264469470234931838450157825581780
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/27.i2c_target_hrst/latest/run.log
UVM_ERROR @ 28467017 ps: (i2c_scoreboard.sv:587) [uvm_test_top.env.scoreboard] Check failed obs.wdata == exp.wdata (174 [0xae] vs 175 [0xaf])
UVM_INFO @ 28467017 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=*) == * has 3 failures:
4.i2c_target_stress_all_with_rand_reset.9170534796711998918924041188970511921760151302517719049114577573273590631185
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 10346678134 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=0xc6c37294) == 0x0
UVM_INFO @ 10346678134 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.i2c_target_stress_all_with_rand_reset.67234762144524018875934279192487711883466295565744100928148266110196822328601
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 11119925332 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=0xbdb64814) == 0x0
UVM_INFO @ 11119925332 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (i2c_scoreboard.sv:559) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 2 failures:
Test i2c_host_fifo_full has 1 failures.
22.i2c_host_fifo_full.12433634850440605431033013347275009630602677144618840123422459784142660757685
Line 964, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/22.i2c_host_fifo_full/latest/run.log
UVM_ERROR @ 1500618221 ps: (i2c_scoreboard.sv:559) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
Test i2c_host_perf_precise has 1 failures.
29.i2c_host_perf_precise.90470766820808967098549567203924330744836538628030166084096195013059572446163
Line 258, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/29.i2c_host_perf_precise/latest/run.log
UVM_ERROR @ 458577617 ps: (i2c_scoreboard.sv:559) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 1 failures:
0.i2c_csr_bit_bash.62564374062018831946310466227910038625832784319294365287099079164875192864015
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_csr_bit_bash/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 1671277608 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 1671277608 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:250) [i2c_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch has 1 failures:
0.i2c_same_csr_outstanding.34234483668203804772914476095293914166390906622199099607528301688901719985317
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_same_csr_outstanding/latest/run.log
UVM_ERROR @ 114226760 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed masked_data == exp_data (8 [0x8] vs 0 [0x0]) addr 0xefa9f078 read out mismatch
UVM_INFO @ 114226760 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '($stable(fmt_fifo_wvalid_i) && $stable(fmt_fifo_wdata_i))' has 1 failures:
3.i2c_csr_bit_bash.84550282534528487956892344020293198225894992552628024056396521739809376896986
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_csr_bit_bash/latest/run.log
Offending '($stable(fmt_fifo_wvalid_i) && $stable(fmt_fifo_wdata_i))'
UVM_ERROR @ 365145999 ps: (i2c_fifos.sv:310) [ASSERT FAILED] FmtWriteStableBeforeHandshake_A
UVM_INFO @ 365145999 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 1 failures:
31.i2c_target_hrst.55075820305721854866557972520750403091994612029631097280996724854178633431217
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/31.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10025613256 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10025613256 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending 'scl_o' has 1 failures:
33.i2c_host_mode_toggle.2279040516077996311429223259131214707974154158586285750745120078220952006839
Line 259, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/33.i2c_host_mode_toggle/latest/run.log
Offending 'scl_o'
UVM_ERROR @ 29388197 ps: (i2c_controller_fsm.sv:976) [ASSERT FAILED] SclOutputGlitch_A
UVM_INFO @ 29388197 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---