de38ce313c| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | host_smoke | i2c_host_smoke | 1.791m | 8.595ms | 50 | 50 | 100.00 |
| V1 | target_smoke | i2c_target_smoke | 49.710s | 5.074ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | i2c_csr_hw_reset | 0.790s | 25.264us | 5 | 5 | 100.00 |
| V1 | csr_rw | i2c_csr_rw | 0.810s | 25.129us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | i2c_csr_bit_bash | 5.870s | 6.989ms | 4 | 5 | 80.00 |
| V1 | csr_aliasing | i2c_csr_aliasing | 2.240s | 783.538us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | i2c_csr_mem_rw_with_rand_reset | 1.460s | 34.730us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | i2c_csr_rw | 0.810s | 25.129us | 20 | 20 | 100.00 |
| i2c_csr_aliasing | 2.240s | 783.538us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 154 | 155 | 99.35 | |||
| V2 | host_error_intr | i2c_host_error_intr | 19.410s | 1.736ms | 50 | 50 | 100.00 |
| V2 | host_stress_all | i2c_host_stress_all | 58.787m | 252.097ms | 44 | 50 | 88.00 |
| V2 | host_maxperf | i2c_host_perf | 34.148m | 71.657ms | 49 | 50 | 98.00 |
| V2 | host_override | i2c_host_override | 0.840s | 52.975us | 50 | 50 | 100.00 |
| V2 | host_fifo_watermark | i2c_host_fifo_watermark | 6.648m | 36.538ms | 50 | 50 | 100.00 |
| V2 | host_fifo_overflow | i2c_host_fifo_overflow | 3.407m | 2.614ms | 50 | 50 | 100.00 |
| V2 | host_fifo_reset | i2c_host_fifo_reset_fmt | 1.260s | 216.775us | 50 | 50 | 100.00 |
| i2c_host_fifo_fmt_empty | 27.150s | 1.985ms | 50 | 50 | 100.00 | ||
| i2c_host_fifo_reset_rx | 13.510s | 244.526us | 50 | 50 | 100.00 | ||
| V2 | host_fifo_full | i2c_host_fifo_full | 3.580m | 3.127ms | 50 | 50 | 100.00 |
| V2 | host_timeout | i2c_host_stretch_timeout | 47.080s | 2.069ms | 50 | 50 | 100.00 |
| V2 | host_rx_oversample | i2c_host_rx_oversample | 0 | 0 | -- | ||
| V2 | i2c_host_mode_toggle | i2c_host_mode_toggle | 2.062m | 4.438ms | 47 | 50 | 94.00 |
| V2 | target_error_intr | i2c_target_unexp_stop | 19.260m | 50.000ms | 0 | 50 | 0.00 |
| V2 | target_glitch | i2c_target_glitch | 11.460s | 2.777ms | 2 | 2 | 100.00 |
| V2 | target_stress_all | i2c_target_stress_all | 55.337m | 100.991ms | 0 | 50 | 0.00 |
| V2 | target_maxperf | i2c_target_perf | 15.568m | 20.000ms | 0 | 50 | 0.00 |
| V2 | target_fifo_empty | i2c_target_stress_rd | 1.193m | 27.072ms | 50 | 50 | 100.00 |
| i2c_target_intr_smoke | 8.100s | 6.106ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_reset | i2c_target_fifo_reset_acq | 1.750s | 261.622us | 50 | 50 | 100.00 |
| i2c_target_fifo_reset_tx | 1.610s | 253.578us | 50 | 50 | 100.00 | ||
| V2 | target_fifo_full | i2c_target_stress_wr | 32.745m | 62.629ms | 50 | 50 | 100.00 |
| i2c_target_stress_rd | 1.193m | 27.072ms | 50 | 50 | 100.00 | ||
| i2c_target_intr_stress_wr | 8.350m | 22.829ms | 50 | 50 | 100.00 | ||
| V2 | target_timeout | i2c_target_timeout | 8.250s | 1.569ms | 50 | 50 | 100.00 |
| V2 | target_clock_stretch | i2c_target_stretch | 37.581m | 33.384ms | 47 | 50 | 94.00 |
| V2 | bad_address | i2c_target_bad_addr | 6.330s | 1.227ms | 50 | 50 | 100.00 |
| V2 | target_mode_glitch | i2c_target_hrst | 5.130s | 516.574us | 29 | 50 | 58.00 |
| V2 | target_fifo_watermark | i2c_target_fifo_watermarks_acq | 3.240s | 3.277ms | 50 | 50 | 100.00 |
| i2c_target_fifo_watermarks_tx | 1.390s | 336.877us | 48 | 50 | 96.00 | ||
| V2 | host_mode_config_perf | i2c_host_perf | 34.148m | 71.657ms | 49 | 50 | 98.00 |
| i2c_host_perf_precise | 18.228m | 24.340ms | 50 | 50 | 100.00 | ||
| V2 | host_mode_clock_stretching | i2c_host_stretch_timeout | 47.080s | 2.069ms | 50 | 50 | 100.00 |
| V2 | target_mode_tx_stretch_ctrl | i2c_target_tx_stretch_ctrl | 3.830s | 256.574us | 0 | 50 | 0.00 |
| V2 | target_mode_nack_generation | target_mode_nack_generation | 0 | 0 | -- | ||
| V2 | host_mode_halt_on_nak | host_mode_halt_on_nak | 0 | 0 | -- | ||
| V2 | target_mode_n_byte_ack_control | target_mode_n_byte_ack_control | 0 | 0 | -- | ||
| V2 | target_mode_bus_timeout | target_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_timeout | controller_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_idle_delay | controller_mode_bus_idle_delay | 0 | 0 | -- | ||
| V2 | loopback_test | loopback_test | 0 | 0 | -- | ||
| V2 | multi_controller_clock_synchronization | multi_controller_clock_synchronization | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost_interference | multi_controller_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost | multi_controller_arbitration_lost | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost_interference | target_mode_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost | target_mode_arbitration_lost | 0 | 0 | -- | ||
| V2 | alert_test | i2c_alert_test | 0.680s | 19.165us | 50 | 50 | 100.00 |
| V2 | intr_test | i2c_intr_test | 0.710s | 15.260us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | i2c_tl_errors | 2.820s | 242.655us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | i2c_tl_errors | 2.820s | 242.655us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | i2c_csr_hw_reset | 0.790s | 25.264us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.810s | 25.129us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 2.240s | 783.538us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.260s | 140.773us | 19 | 20 | 95.00 | ||
| V2 | tl_d_partial_access | i2c_csr_hw_reset | 0.790s | 25.264us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.810s | 25.129us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 2.240s | 783.538us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.260s | 140.773us | 19 | 20 | 95.00 | ||
| V2 | TOTAL | 1355 | 1592 | 85.11 | |||
| V2S | tl_intg_err | i2c_tl_intg_err | 2.540s | 157.038us | 20 | 20 | 100.00 |
| i2c_sec_cm | 0.970s | 58.657us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | i2c_tl_intg_err | 2.540s | 157.038us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | host_stress_all_with_rand_reset | i2c_host_stress_all_with_rand_reset | 9.446m | 15.332ms | 0 | 10 | 0.00 |
| V3 | target_stress_all_with_rand_reset | i2c_target_stress_all_with_rand_reset | 6.672m | 10.187ms | 0 | 10 | 0.00 |
| V3 | target_loopback | 0 | 0 | -- | |||
| V3 | TOTAL | 0 | 20 | 0.00 | |||
| Unmapped tests | i2c_host_may_nack | 24.850s | 684.485us | 50 | 50 | 100.00 | |
| TOTAL | 1584 | 1842 | 85.99 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 1 | 1 | 1 | 100.00 |
| V1 | 7 | 7 | 6 | 85.71 |
| V2 | 47 | 34 | 23 | 48.94 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 3 | 2 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 90.94 | 96.60 | 89.73 | 97.22 | 70.24 | 93.62 | 98.44 | 90.74 |
UVM_ERROR (i2c_scoreboard.sv:604) [scoreboard] Check failed obs.num_data == exp.num_data (* [*] vs * [*]) has 66 failures:
0.i2c_target_unexp_stop.70405082060506308574108384505501266888142131762374026339784588762446683170286
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 42966012 ps: (i2c_scoreboard.sv:604) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (0 [0x0] vs 4 [0x4])
UVM_INFO @ 42966012 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_unexp_stop.25913023815893810114846106946200849483048770881380288384942408074265216347939
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 10448822 ps: (i2c_scoreboard.sv:604) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (0 [0x0] vs 3 [0x3])
UVM_INFO @ 10448822 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 21 more failures.
1.i2c_target_stress_all.30895772116469231938769185882926128344745342947337376896234979731023624285589
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 994010400 ps: (i2c_scoreboard.sv:604) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (2 [0x2] vs 1 [0x1])
UVM_INFO @ 994010400 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.i2c_target_stress_all.33962374019537367206794660670265774028094197226354600835805741522009300699803
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 23355646214 ps: (i2c_scoreboard.sv:604) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (11 [0xb] vs 23 [0x17])
UVM_INFO @ 23355646214 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 26 more failures.
2.i2c_target_stress_all_with_rand_reset.97304173007970054106395585060480479733374835726031230241605804618050163514351
Line 275, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 3104799893 ps: (i2c_scoreboard.sv:604) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (4 [0x4] vs 3 [0x3])
UVM_INFO @ 3104799893 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.i2c_target_stress_all_with_rand_reset.67910009240906903978197860994022481110790944429449427507873780721923123586573
Line 268, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2797519096 ps: (i2c_scoreboard.sv:604) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (9 [0x9] vs 3 [0x3])
UVM_INFO @ 2797519096 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
5.i2c_target_hrst.48624171155390810301527465239827799639218688176605036538136291922154570227609
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_hrst/latest/run.log
UVM_ERROR @ 84763850 ps: (i2c_scoreboard.sv:604) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (9 [0x9] vs 5 [0x5])
UVM_INFO @ 84763850 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.i2c_target_hrst.76182461733614146270132480860031716218064020743164851662308890448549442820674
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_hrst/latest/run.log
UVM_ERROR @ 449724647 ps: (i2c_scoreboard.sv:604) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (7 [0x7] vs 3 [0x3])
UVM_INFO @ 449724647 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 9 more failures.
UVM_FATAL (i2c_driver.sv:148) driver [driver] has 50 failures:
0.i2c_target_tx_stretch_ctrl.87035571538427141910860714780462413202332711619084332811574310023617843256035
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_tx_stretch_ctrl/latest/run.log
UVM_FATAL @ 14876569 ps: (i2c_driver.sv:148) uvm_test_top.env.m_i2c_agent.driver [uvm_test_top.env.m_i2c_agent.driver]
host_driver, received invalid request
UVM_INFO @ 14876569 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_tx_stretch_ctrl.79293483740166550201571767525879042664188557423108958156943215186219761491169
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_tx_stretch_ctrl/latest/run.log
UVM_FATAL @ 5865157 ps: (i2c_driver.sv:148) uvm_test_top.env.m_i2c_agent.driver [uvm_test_top.env.m_i2c_agent.driver]
host_driver, received invalid request
UVM_INFO @ 5865157 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 48 more failures.
UVM_FATAL (i2c_base_vseq.sv:1175) [stop_interrupt_handler] wait timeout occurred! has 43 failures:
0.i2c_target_perf.109523349707221757837359241387763738156821566637783786771010357162338485647677
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_perf/latest/run.log
UVM_FATAL @ 10737186251 ps: (i2c_base_vseq.sv:1175) [stop_interrupt_handler] wait timeout occurred!
UVM_INFO @ 10737186251 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_perf.84887388991822426344208630384556661539327773102467168528349272499316050137209
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_perf/latest/run.log
UVM_FATAL @ 13234281221 ps: (i2c_base_vseq.sv:1175) [stop_interrupt_handler] wait timeout occurred!
UVM_INFO @ 13234281221 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 32 more failures.
3.i2c_target_stress_all.14335184922368908110216193308462534368512782281132695826587027457859368106415
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all/latest/run.log
UVM_FATAL @ 10592705028 ps: (i2c_base_vseq.sv:1175) [stop_interrupt_handler] wait timeout occurred!
UVM_INFO @ 10592705028 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
9.i2c_target_stress_all.60608257341290251686837471980144579754328421593558134210933483624999313501845
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_target_stress_all/latest/run.log
UVM_FATAL @ 10380674303 ps: (i2c_base_vseq.sv:1175) [stop_interrupt_handler] wait timeout occurred!
UVM_INFO @ 10380674303 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
Job i2c-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 23 failures:
Test i2c_host_stress_all_with_rand_reset has 1 failures.
2.i2c_host_stress_all_with_rand_reset.51701065327907464616697756958838483912685790893529180721805264897361134717079
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_stress_all_with_rand_reset/latest/run.log
Job ID: smart:808be286-ce6c-4647-a0fd-04c5396a75c0
Test i2c_target_stress_all has 6 failures.
7.i2c_target_stress_all.41072697930142696399756217422188841272053704157151100718818589738846253143990
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_stress_all/latest/run.log
Job ID: smart:704bc1da-2354-4211-b1f0-a4562b40e0a3
18.i2c_target_stress_all.66200155687073129907808185414155660596085919931959362330484677820013386052914
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/18.i2c_target_stress_all/latest/run.log
Job ID: smart:b8b8aa83-3ba1-419d-a29b-89c356b80f9b
... and 4 more failures.
Test i2c_host_stress_all has 3 failures.
10.i2c_host_stress_all.31916740335087536175899679910689050449628680855941075807064690915325587128039
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/10.i2c_host_stress_all/latest/run.log
Job ID: smart:d3b34628-5ba4-4943-9604-b1229d77fe66
32.i2c_host_stress_all.106545573729276519092034742294649872595758521460131760792939981851685012371719
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/32.i2c_host_stress_all/latest/run.log
Job ID: smart:06f05cef-5a1e-454b-8a42-b622638592f0
... and 1 more failures.
Test i2c_target_unexp_stop has 9 failures.
14.i2c_target_unexp_stop.52524877504656136498456249107150075834596010627128073946770315629819580113999
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/14.i2c_target_unexp_stop/latest/run.log
Job ID: smart:579dce86-89e9-4c57-a790-da1413f701c9
22.i2c_target_unexp_stop.92068504981954030609267644880850567229720091258331224866328429605600362560435
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/22.i2c_target_unexp_stop/latest/run.log
Job ID: smart:f030daa3-6784-4552-95ba-e0bfea2a34b1
... and 7 more failures.
Test i2c_target_stretch has 3 failures.
41.i2c_target_stretch.108057940253216105397476543429769117259568800181171757112923780547533137127882
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/41.i2c_target_stretch/latest/run.log
Job ID: smart:fce9433b-377f-4125-9f73-8149039ee902
46.i2c_target_stretch.49731202752913284453746553867618536310517770050110753738944859482159106839523
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/46.i2c_target_stretch/latest/run.log
Job ID: smart:b8e3e1ac-aede-4aea-90b9-7b550474cd66
... and 1 more failures.
... and 1 more tests.
UVM_ERROR (i2c_scoreboard.sv:608) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 19 failures:
Test i2c_target_stress_all has 4 failures.
2.i2c_target_stress_all.67062648034307627601975894171636971533652684489763545236349829659766643792319
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 30853117 ps: (i2c_scoreboard.sv:608) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 225 [0xe1])
UVM_INFO @ 30853117 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.i2c_target_stress_all.4385687633115871675696697036951933280038290031752464815992422231503219809491
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 46874303 ps: (i2c_scoreboard.sv:608) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 68 [0x44])
UVM_INFO @ 46874303 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
Test i2c_target_stress_all_with_rand_reset has 2 failures.
4.i2c_target_stress_all_with_rand_reset.83812540140314343760913368913438283474933679818057746200490652408081737369557
Line 268, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 211522340 ps: (i2c_scoreboard.sv:608) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 163 [0xa3])
UVM_INFO @ 211522340 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.i2c_target_stress_all_with_rand_reset.12242975503353565610786668632774221056962050779577201765187096735807479694702
Line 280, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2359347971 ps: (i2c_scoreboard.sv:608) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 172 [0xac])
UVM_INFO @ 2359347971 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test i2c_target_perf has 13 failures.
8.i2c_target_perf.20257381431022543989502574533471720215231210524518416990822756232421859985687
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_target_perf/latest/run.log
UVM_ERROR @ 129113540 ps: (i2c_scoreboard.sv:608) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 249 [0xf9])
UVM_INFO @ 129113540 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
9.i2c_target_perf.49051279450161940145632852274576767440738700330868847231191311370864153247156
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_target_perf/latest/run.log
UVM_ERROR @ 33806856 ps: (i2c_scoreboard.sv:608) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 29 [0x1d])
UVM_INFO @ 33806856 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 11 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 15 failures:
5.i2c_target_unexp_stop.19100718680089380795237406562789615621496081839286402735375738578365251554250
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_unexp_stop/latest/run.log
UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
9.i2c_target_unexp_stop.86316583487412231038299383302241664211974017697689783825198321206784194980471
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_target_unexp_stop/latest/run.log
UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 10 more failures.
40.i2c_target_perf.111853148139720232438327272047826633077990900177021532629869190719255656997241
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/40.i2c_target_perf/latest/run.log
UVM_FATAL @ 20000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 20000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 20000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
41.i2c_target_perf.11251824511769372624247255115795299113593422030493710011845363050968683449684
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/41.i2c_target_perf/latest/run.log
UVM_FATAL @ 20000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 20000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 20000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (cip_base_vseq.sv:828) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 11 failures:
0.i2c_host_stress_all_with_rand_reset.113243907685305226300372384355902897132645057803709930867622025349563115680284
Line 1299, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 3458690049 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3458690049 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_host_stress_all_with_rand_reset.816689643751943210094392899010813247996302407741567235640303524336300410674
Line 1065, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 3243660057 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3243660057 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
3.i2c_target_stress_all_with_rand_reset.79390547517913710849493891279450159911575692191288554443186805950840850299939
Line 266, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 3033252672 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3033252672 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
9.i2c_target_stress_all_with_rand_reset.96923264824047699760581924003652366847010314611051399706145678990256831550558
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 3313366039 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3313366039 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_base_vseq.sv:992) virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout has 7 failures:
7.i2c_target_unexp_stop.62239098208739271837705911715176900531914832984964922915998240605615179764712
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 4011798038 ps: (i2c_base_vseq.sv:992) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
UVM_INFO @ 4011798038 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
10.i2c_target_unexp_stop.25387697906971407277436669913846562955137493843340542867676402913215862181247
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/10.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 3273700085 ps: (i2c_base_vseq.sv:992) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
UVM_INFO @ 3273700085 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
33.i2c_target_stress_all.35952079748518923329673778234354889874837307985560635842780965885953725647042
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/33.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 1450621349 ps: (i2c_base_vseq.sv:992) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
UVM_INFO @ 1450621349 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:587) [scoreboard] Check failed obs.wdata == exp.wdata (* [*] vs * [*]) has 6 failures:
Test i2c_target_stress_all_with_rand_reset has 1 failures.
0.i2c_target_stress_all_with_rand_reset.30942991510079004028541863980857125522730080696376423038060718173461093706126
Line 345, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 8148158709 ps: (i2c_scoreboard.sv:587) [uvm_test_top.env.scoreboard] Check failed obs.wdata == exp.wdata (126 [0x7e] vs 144 [0x90])
UVM_INFO @ 8148158709 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test i2c_target_hrst has 5 failures.
1.i2c_target_hrst.20969485546053791437561023394938227036387641223265796006644853569151161636210
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_hrst/latest/run.log
UVM_ERROR @ 26909669 ps: (i2c_scoreboard.sv:587) [uvm_test_top.env.scoreboard] Check failed obs.wdata == exp.wdata (60 [0x3c] vs 61 [0x3d])
UVM_INFO @ 26909669 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
11.i2c_target_hrst.80849663839840515595125015216937540288710890080057708094234081477437122901702
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/11.i2c_target_hrst/latest/run.log
UVM_ERROR @ 4079077 ps: (i2c_scoreboard.sv:587) [uvm_test_top.env.scoreboard] Check failed obs.wdata == exp.wdata (126 [0x7e] vs 127 [0x7f])
UVM_INFO @ 4079077 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_ERROR (i2c_scoreboard.sv:584) [scoreboard] Check failed obs.start == exp.start (* [*] vs * [*]) has 4 failures:
0.i2c_target_hrst.35308550525662452330807469512977775451316841508612762006709910692400185549024
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log
UVM_ERROR @ 6234190 ps: (i2c_scoreboard.sv:584) [uvm_test_top.env.scoreboard] Check failed obs.start == exp.start (1 [0x1] vs 0 [0x0])
UVM_INFO @ 6234190 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_hrst.83278813898820979242815279488727772124987842232038714140470358354388651486327
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_hrst/latest/run.log
UVM_ERROR @ 66802921 ps: (i2c_scoreboard.sv:584) [uvm_test_top.env.scoreboard] Check failed obs.start == exp.start (1 [0x1] vs 0 [0x0])
UVM_INFO @ 66802921 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_ERROR (i2c_scoreboard.sv:559) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite has 3 failures:
1.i2c_host_stress_all.104640029475665283168624887599075235398581580246065777735174548989296776987351
Line 5556, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 8747375067 ps: (i2c_scoreboard.sv:559) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite
--> EXP:
-----------------------------------------------------
Name Type Size Value
-----------------------------------------------------
36.i2c_host_stress_all.68454659367335741899095009605286302482062493917530289272607372667961975171849
Line 5487, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/36.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 43057837391 ps: (i2c_scoreboard.sv:559) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite
--> EXP:
-----------------------------------------------------
Name Type Size Value
-----------------------------------------------------
... and 1 more failures.
UVM_FATAL (i2c_driver.sv:234) [i2c_drv_scl] wait timeout occurred! has 2 failures:
0.i2c_target_stress_all.34889182924717314579243303428672023573844139244872041669750573204858176425818
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all/latest/run.log
UVM_FATAL @ 100990845348 ps: (i2c_driver.sv:234) [i2c_drv_scl] wait timeout occurred!
UVM_INFO @ 100990845348 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
14.i2c_target_stress_all.31002766955972643628619234482486207114221788598994044741101784872549322120869
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/14.i2c_target_stress_all/latest/run.log
UVM_FATAL @ 100787589784 ps: (i2c_driver.sv:234) [i2c_drv_scl] wait timeout occurred!
UVM_INFO @ 100787589784 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Error-[CNST-CIF] Constraints inconsistency failure has 2 failures:
6.i2c_target_fifo_watermarks_tx.8740020165694753420193213664090595907367914590103683357418674034379674707380
Line 292, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_fifo_watermarks_tx/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 723
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
24.i2c_target_fifo_watermarks_tx.84037256905082304500155046097176117777202855238944406588611684028658337467777
Line 292, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/24.i2c_target_fifo_watermarks_tx/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 723
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
Offending 'scl_o' has 2 failures:
19.i2c_host_mode_toggle.96425995368550635662622186867010082686804429383366219391925487808780581795099
Line 259, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/19.i2c_host_mode_toggle/latest/run.log
Offending 'scl_o'
UVM_ERROR @ 4865492 ps: (i2c_controller_fsm.sv:976) [ASSERT FAILED] SclOutputGlitch_A
UVM_INFO @ 4865492 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
25.i2c_host_mode_toggle.98527692783993487619217139701154185058674503870974786801019531357082847385276
Line 255, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/25.i2c_host_mode_toggle/latest/run.log
Offending 'scl_o'
UVM_ERROR @ 13316209 ps: (i2c_controller_fsm.sv:976) [ASSERT FAILED] SclOutputGlitch_A
UVM_INFO @ 13316209 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '($stable(fmt_fifo_wvalid_i) && $stable(fmt_fifo_wdata_i))' has 1 failures:
0.i2c_csr_bit_bash.59000438651371073446603566541062201646733558464923976134678787914424703325405
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_csr_bit_bash/latest/run.log
Offending '($stable(fmt_fifo_wvalid_i) && $stable(fmt_fifo_wdata_i))'
UVM_ERROR @ 63007426 ps: (i2c_fifos.sv:310) [ASSERT FAILED] FmtWriteStableBeforeHandshake_A
UVM_INFO @ 63007426 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=*) == * has 1 failures:
1.i2c_target_stress_all_with_rand_reset.33280182750667977937157241135430880257611414332025985186717173176710268958553
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 10187057211 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=0xced76c14) == 0x0
UVM_INFO @ 10187057211 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:250) [i2c_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch has 1 failures:
4.i2c_same_csr_outstanding.19688277577065807645113357535321692545740388335288679070006499213113266282486
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_same_csr_outstanding/latest/run.log
UVM_ERROR @ 26286113 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed masked_data == exp_data (8 [0x8] vs 0 [0x0]) addr 0xabc9eaf8 read out mismatch
UVM_INFO @ 26286113 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:559) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 1 failures:
29.i2c_host_perf.112675855777477105054566331646010835438253604066034045273340870570742478983414
Line 258, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/29.i2c_host_perf/latest/run.log
UVM_ERROR @ 239600906 ps: (i2c_scoreboard.sv:559) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 1 failures:
43.i2c_target_hrst.47302841717010726470874228246477238244037055078691145605742323322212790106993
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/43.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10026276984 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10026276984 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---