548a3880d8| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | host_smoke | i2c_host_smoke | 1.534m | 1.954ms | 50 | 50 | 100.00 |
| V1 | target_smoke | i2c_target_smoke | 1.035m | 1.534ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | i2c_csr_hw_reset | 0.800s | 44.283us | 5 | 5 | 100.00 |
| V1 | csr_rw | i2c_csr_rw | 12.940s | 26.947ms | 19 | 20 | 95.00 |
| V1 | csr_bit_bash | i2c_csr_bit_bash | 6.110s | 650.905us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | i2c_csr_aliasing | 2.330s | 152.054us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | i2c_csr_mem_rw_with_rand_reset | 1.720s | 35.257us | 19 | 20 | 95.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | i2c_csr_rw | 12.940s | 26.947ms | 19 | 20 | 95.00 |
| i2c_csr_aliasing | 2.330s | 152.054us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 153 | 155 | 98.71 | |||
| V2 | host_error_intr | i2c_host_error_intr | 10.700s | 275.761us | 50 | 50 | 100.00 |
| V2 | host_stress_all | i2c_host_stress_all | 44.348m | 49.434ms | 44 | 50 | 88.00 |
| V2 | host_maxperf | i2c_host_perf | 44.289m | 73.230ms | 50 | 50 | 100.00 |
| V2 | host_override | i2c_host_override | 0.740s | 41.797us | 50 | 50 | 100.00 |
| V2 | host_fifo_watermark | i2c_host_fifo_watermark | 6.678m | 10.227ms | 50 | 50 | 100.00 |
| V2 | host_fifo_overflow | i2c_host_fifo_overflow | 3.427m | 5.340ms | 50 | 50 | 100.00 |
| V2 | host_fifo_reset | i2c_host_fifo_reset_fmt | 1.230s | 555.404us | 50 | 50 | 100.00 |
| i2c_host_fifo_fmt_empty | 26.590s | 489.911us | 50 | 50 | 100.00 | ||
| i2c_host_fifo_reset_rx | 13.260s | 1.662ms | 50 | 50 | 100.00 | ||
| V2 | host_fifo_full | i2c_host_fifo_full | 3.231m | 30.941ms | 50 | 50 | 100.00 |
| V2 | host_timeout | i2c_host_stretch_timeout | 41.650s | 1.881ms | 50 | 50 | 100.00 |
| V2 | host_rx_oversample | i2c_host_rx_oversample | 0 | 0 | -- | ||
| V2 | i2c_host_mode_toggle | i2c_host_mode_toggle | 1.842m | 2.469ms | 50 | 50 | 100.00 |
| V2 | target_error_intr | i2c_target_unexp_stop | 42.601m | 50.000ms | 0 | 50 | 0.00 |
| V2 | target_glitch | i2c_target_glitch | 10.840s | 4.104ms | 2 | 2 | 100.00 |
| V2 | target_stress_all | i2c_target_stress_all | 53.274m | 100.542ms | 0 | 50 | 0.00 |
| V2 | target_maxperf | i2c_target_perf | 0.980s | 874.862us | 0 | 50 | 0.00 |
| V2 | target_fifo_empty | i2c_target_stress_rd | 1.284m | 3.476ms | 50 | 50 | 100.00 |
| i2c_target_intr_smoke | 8.250s | 5.976ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_reset | i2c_target_fifo_reset_acq | 1.086m | 10.147ms | 49 | 50 | 98.00 |
| i2c_target_fifo_reset_tx | 1.405m | 10.094ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_full | i2c_target_stress_wr | 33.841m | 61.046ms | 50 | 50 | 100.00 |
| i2c_target_stress_rd | 1.284m | 3.476ms | 50 | 50 | 100.00 | ||
| i2c_target_intr_stress_wr | 8.576m | 23.873ms | 50 | 50 | 100.00 | ||
| V2 | target_timeout | i2c_target_timeout | 8.340s | 10.978ms | 50 | 50 | 100.00 |
| V2 | target_clock_stretch | i2c_target_stretch | 57.499m | 20.598ms | 48 | 50 | 96.00 |
| V2 | bad_address | i2c_target_bad_addr | 6.230s | 2.897ms | 50 | 50 | 100.00 |
| V2 | target_mode_glitch | i2c_target_hrst | 18.110s | 10.271ms | 33 | 50 | 66.00 |
| V2 | target_fifo_watermark | i2c_target_fifo_watermarks_acq | 6.920s | 1.563ms | 50 | 50 | 100.00 |
| i2c_target_fifo_watermarks_tx | 6.950s | 1.057ms | 50 | 50 | 100.00 | ||
| V2 | host_mode_config_perf | i2c_host_perf | 44.289m | 73.230ms | 50 | 50 | 100.00 |
| i2c_host_perf_precise | 14.944m | 24.279ms | 50 | 50 | 100.00 | ||
| V2 | host_mode_clock_stretching | i2c_host_stretch_timeout | 41.650s | 1.881ms | 50 | 50 | 100.00 |
| V2 | target_mode_tx_stretch_ctrl | i2c_target_tx_stretch_ctrl | 28.400s | 2.229ms | 50 | 50 | 100.00 |
| V2 | target_mode_nack_generation | target_mode_nack_generation | 0 | 0 | -- | ||
| V2 | host_mode_halt_on_nak | host_mode_halt_on_nak | 0 | 0 | -- | ||
| V2 | target_mode_n_byte_ack_control | target_mode_n_byte_ack_control | 0 | 0 | -- | ||
| V2 | target_mode_bus_timeout | target_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_timeout | controller_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_idle_delay | controller_mode_bus_idle_delay | 0 | 0 | -- | ||
| V2 | loopback_test | loopback_test | 0 | 0 | -- | ||
| V2 | multi_controller_clock_synchronization | multi_controller_clock_synchronization | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost_interference | multi_controller_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost | multi_controller_arbitration_lost | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost_interference | target_mode_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost | target_mode_arbitration_lost | 0 | 0 | -- | ||
| V2 | alert_test | i2c_alert_test | 0.690s | 17.179us | 50 | 50 | 100.00 |
| V2 | intr_test | i2c_intr_test | 0.750s | 19.050us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | i2c_tl_errors | 2.820s | 429.432us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | i2c_tl_errors | 2.820s | 429.432us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | i2c_csr_hw_reset | 0.800s | 44.283us | 5 | 5 | 100.00 |
| i2c_csr_rw | 12.940s | 26.947ms | 19 | 20 | 95.00 | ||
| i2c_csr_aliasing | 2.330s | 152.054us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.220s | 85.764us | 19 | 20 | 95.00 | ||
| V2 | tl_d_partial_access | i2c_csr_hw_reset | 0.800s | 44.283us | 5 | 5 | 100.00 |
| i2c_csr_rw | 12.940s | 26.947ms | 19 | 20 | 95.00 | ||
| i2c_csr_aliasing | 2.330s | 152.054us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.220s | 85.764us | 19 | 20 | 95.00 | ||
| V2 | TOTAL | 1415 | 1592 | 88.88 | |||
| V2S | tl_intg_err | i2c_tl_intg_err | 2.570s | 581.247us | 19 | 20 | 95.00 |
| i2c_sec_cm | 0.990s | 59.727us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | i2c_tl_intg_err | 2.570s | 581.247us | 19 | 20 | 95.00 |
| V2S | TOTAL | 24 | 25 | 96.00 | |||
| V3 | host_stress_all_with_rand_reset | i2c_host_stress_all_with_rand_reset | 13.932m | 45.682ms | 0 | 50 | 0.00 |
| V3 | target_stress_all_with_rand_reset | i2c_target_stress_all_with_rand_reset | 11.323m | 49.852ms | 0 | 50 | 0.00 |
| V3 | target_loopback | 0 | 0 | -- | |||
| V3 | TOTAL | 0 | 100 | 0.00 | |||
| Unmapped tests | i2c_host_may_nack | 29.910s | 1.488ms | 50 | 50 | 100.00 | |
| TOTAL | 1642 | 1922 | 85.43 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 1 | 1 | 1 | 100.00 |
| V1 | 7 | 7 | 5 | 71.43 |
| V2 | 47 | 34 | 26 | 55.32 |
| V2S | 2 | 2 | 1 | 50.00 |
| V3 | 3 | 2 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 90.60 | 96.51 | 89.88 | 97.22 | 68.45 | 93.48 | 98.44 | 90.21 |
UVM_ERROR (i2c_monitor.sv:425) [monitor] Check failed r_bit === *'b* (* [*] vs * [*]) has 81 failures:
0.i2c_target_perf.60791060270610014559097474617974860476886695608797505171684705460468182226735
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_perf/latest/run.log
UVM_ERROR @ 428688028 ps: (i2c_monitor.sv:425) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 428688028 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_perf.19922980502698198784724994954615151628762329572138386705828950523657292799523
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_perf/latest/run.log
UVM_ERROR @ 150885807 ps: (i2c_monitor.sv:425) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 150885807 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 48 more failures.
0.i2c_target_stress_all_with_rand_reset.95289671749245456357807919901743339270852622093092373246437915405657432437611
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 19117072 ps: (i2c_monitor.sv:425) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 19117072 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_stress_all_with_rand_reset.9289341594276930388957340994250736677274660954498333452646915981068745174384
Line 262, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 64658335 ps: (i2c_monitor.sv:425) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 64658335 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 20 more failures.
1.i2c_target_stress_all.24062551974670646430898411376345496893961817487234512467596203895945629877721
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 582791874 ps: (i2c_monitor.sv:425) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 582791874 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.i2c_target_stress_all.113361127465371244785960906983559671135073725287823125413518454783225493975163
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 26877742 ps: (i2c_monitor.sv:425) [uvm_test_top.env.m_i2c_agent.monitor] Check failed r_bit === 1'b0 (0x1 [1] vs 0x0 [0])
UVM_INFO @ 26877742 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
UVM_ERROR (i2c_scoreboard.sv:637) [scoreboard] Check failed obs.num_data == exp.num_data (* [*] vs * [*]) has 59 failures:
5.i2c_target_unexp_stop.598334949635649498863800217406796630164818897194939490573202591892917675797
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 84785998 ps: (i2c_scoreboard.sv:637) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (0 [0x0] vs 8 [0x8])
UVM_INFO @ 84785998 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.i2c_target_unexp_stop.46017565166732945207467560777434425321742319992646593204945602666390855725599
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 153600958 ps: (i2c_scoreboard.sv:637) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (0 [0x0] vs 9 [0x9])
UVM_INFO @ 153600958 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 12 more failures.
5.i2c_target_stress_all.486218810008830961354820974287106492176505946736122987989183752345366467163
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 9947081856 ps: (i2c_scoreboard.sv:637) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (6 [0x6] vs 5 [0x5])
UVM_INFO @ 9947081856 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.i2c_target_stress_all.21245968097285733366304459123173414055961316743474256047541043964102185161771
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 7519452455 ps: (i2c_scoreboard.sv:637) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (1 [0x1] vs 10 [0xa])
UVM_INFO @ 7519452455 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 23 more failures.
6.i2c_target_stress_all_with_rand_reset.52560293128409467385550333915060253689929776994285845947214696758596932276480
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 44650028 ps: (i2c_scoreboard.sv:637) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (0 [0x0] vs 12 [0xc])
UVM_INFO @ 44650028 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
9.i2c_target_stress_all_with_rand_reset.77085156743380816616134560351322097032280838465256112335179734299203487138193
Line 272, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 5864998487 ps: (i2c_scoreboard.sv:637) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (0 [0x0] vs 10 [0xa])
UVM_INFO @ 5864998487 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 15 more failures.
11.i2c_target_hrst.90263486843778196111410950913639646068439760000367596906563440504551948781538
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/11.i2c_target_hrst/latest/run.log
UVM_ERROR @ 96735617 ps: (i2c_scoreboard.sv:637) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (5 [0x5] vs 4 [0x4])
UVM_INFO @ 96735617 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
32.i2c_target_hrst.105358092731389539751628217044127534195254459983137266546708167976896805455595
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/32.i2c_target_hrst/latest/run.log
UVM_ERROR @ 526412677 ps: (i2c_scoreboard.sv:637) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (9 [0x9] vs 28 [0x1c])
UVM_INFO @ 526412677 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (cip_base_vseq.sv:828) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 50 failures:
0.i2c_host_stress_all_with_rand_reset.37509924269126779866585125718499003286672536440238117276227446935084436390543
Line 4363, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 14523824284 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 14523824284 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_host_stress_all_with_rand_reset.35028628193870040538896347038914248124394107573852738140944048960999671123697
Line 369, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 10877636514 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 10877636514 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 42 more failures.
2.i2c_target_stress_all_with_rand_reset.32477588753680287172248102754526522318591380032576577473757191598515660076590
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 392647974 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 392647974 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.i2c_target_stress_all_with_rand_reset.92471536278065664222651463151433053376531952402327007809330454859915189252949
Line 257, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1348667376 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1348667376 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
Job i2c-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 26 failures:
Test i2c_target_unexp_stop has 8 failures.
1.i2c_target_unexp_stop.105686473331409712024399955832560517198862729508349616871675118772022478525870
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
Job ID: smart:df6f3365-a38e-416c-9f40-e905abf253db
6.i2c_target_unexp_stop.22892754678640486775698072932058902313222743373760000421334357977176671059094
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_unexp_stop/latest/run.log
Job ID: smart:bb49001c-b931-404e-a6b1-31a271baf4bc
... and 6 more failures.
Test i2c_host_stress_all has 4 failures.
2.i2c_host_stress_all.71336417416640932278140597505198766710543969310320272287069319892893285299799
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_stress_all/latest/run.log
Job ID: smart:da699769-b465-468d-90b0-984700146b9e
7.i2c_host_stress_all.32742166704402834801450448703985466087708492419827332824512463594108917250058
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_host_stress_all/latest/run.log
Job ID: smart:59585d31-1aed-4fd3-a8ee-f2891753dda2
... and 2 more failures.
Test i2c_target_stress_all has 9 failures.
3.i2c_target_stress_all.113028515025663401301361172107837624565378076996159928846264864760318997680907
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all/latest/run.log
Job ID: smart:132453fe-748c-4ce3-aeb7-c34a2644bdb1
4.i2c_target_stress_all.27234946227864415296052123864545354783202345408832136263683293481596152993775
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_all/latest/run.log
Job ID: smart:2f6b26f3-8cfb-40d5-8e53-68c89286ea90
... and 7 more failures.
Test i2c_target_stretch has 2 failures.
19.i2c_target_stretch.54017557767425399315990038906444202043515555088176530666106409112029009758745
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/19.i2c_target_stretch/latest/run.log
Job ID: smart:16de8db7-9f75-4a35-833c-f60dd8bbb9af
25.i2c_target_stretch.109424302490393876707271652695677996811259246728932541004587698137842701172441
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/25.i2c_target_stretch/latest/run.log
Job ID: smart:ece7cbdc-167d-4ebd-b6a0-e72e20520860
Test i2c_host_stress_all_with_rand_reset has 3 failures.
33.i2c_host_stress_all_with_rand_reset.59668276558359896725918451394620048680918890627576431545569885113965110070605
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/33.i2c_host_stress_all_with_rand_reset/latest/run.log
Job ID: smart:e442772c-ce87-4a31-a1a0-759bc157ca9a
34.i2c_host_stress_all_with_rand_reset.81524275208756214729727560607406282093194685632353582969183555882321308276527
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/34.i2c_host_stress_all_with_rand_reset/latest/run.log
Job ID: smart:a7cd0bd2-fda7-42af-8e33-7e92a5a2000d
... and 1 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 18 failures:
0.i2c_target_unexp_stop.57695076659088212067614123976935642868098061009832957845607859459136349523027
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.i2c_target_unexp_stop.52201794819740073618647724312557667619143707626983342503442530025144272315694
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_unexp_stop/latest/run.log
UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 15 more failures.
22.i2c_host_stress_all.99303746276695056701495565941776273861747288016547054343169675612879061135660
Line 4456, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/22.i2c_host_stress_all/latest/run.log
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_base_vseq.sv:992) virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout has 10 failures:
2.i2c_target_unexp_stop.3445090167363847318493970951774511675375509047009421802112978448306119451698
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 1525271959 ps: (i2c_base_vseq.sv:992) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
UVM_INFO @ 1525271959 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
29.i2c_target_unexp_stop.70767735188918666836082331477817623890726575951430987173005682198014241094131
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/29.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 1593863341 ps: (i2c_base_vseq.sv:992) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
UVM_INFO @ 1593863341 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
16.i2c_target_stress_all.1164864331767964343295121130373363743723295308387751655951117995611564588880
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/16.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 2806480187 ps: (i2c_base_vseq.sv:992) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
UVM_INFO @ 2806480187 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
39.i2c_target_stress_all.3935646183290164587037642442618414308194317238271321290953106627703670742915
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/39.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 9770728686 ps: (i2c_base_vseq.sv:992) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
UVM_INFO @ 9770728686 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:621) [scoreboard] Check failed obs.start == exp.start (* [*] vs * [*]) has 7 failures:
10.i2c_target_hrst.1248569852475819322752468036917788473692071573269133182643738372565627594618
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/10.i2c_target_hrst/latest/run.log
UVM_ERROR @ 102682430 ps: (i2c_scoreboard.sv:621) [uvm_test_top.env.scoreboard] Check failed obs.start == exp.start (1 [0x1] vs 0 [0x0])
UVM_INFO @ 102682430 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
20.i2c_target_hrst.1552700270714095755893983228961092492027524250513440359427644392705423846511
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/20.i2c_target_hrst/latest/run.log
UVM_ERROR @ 10967164 ps: (i2c_scoreboard.sv:621) [uvm_test_top.env.scoreboard] Check failed obs.start == exp.start (1 [0x1] vs 0 [0x0])
UVM_INFO @ 10967164 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
24.i2c_target_fifo_reset_acq.43980964705505548489377647514144819365156960477713000747198155877650012850631
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/24.i2c_target_fifo_reset_acq/latest/run.log
UVM_ERROR @ 5553673097 ps: (i2c_scoreboard.sv:621) [uvm_test_top.env.scoreboard] Check failed obs.start == exp.start (0 [0x0] vs 1 [0x1])
UVM_INFO @ 5553673097 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:624) [scoreboard] Check failed obs.wdata == exp.wdata (* [*] vs * [*]) has 6 failures:
3.i2c_target_hrst.99575095608328695618780303667736317668541594298847825012511593265044798449556
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_hrst/latest/run.log
UVM_ERROR @ 55485258 ps: (i2c_scoreboard.sv:624) [uvm_test_top.env.scoreboard] Check failed obs.wdata == exp.wdata (90 [0x5a] vs 180 [0xb4])
UVM_INFO @ 55485258 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.i2c_target_hrst.114260550619292825313918460962876806768491748132243070051300365666626549413362
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_hrst/latest/run.log
UVM_ERROR @ 16106933 ps: (i2c_scoreboard.sv:624) [uvm_test_top.env.scoreboard] Check failed obs.wdata == exp.wdata (236 [0xec] vs 237 [0xed])
UVM_INFO @ 16106933 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
15.i2c_target_stress_all_with_rand_reset.109582703889122887270472945356018697392904186721039129157640059439723354355952
Line 395, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/15.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 8625292903 ps: (i2c_scoreboard.sv:624) [uvm_test_top.env.scoreboard] Check failed obs.wdata == exp.wdata (207 [0xcf] vs 104 [0x68])
UVM_INFO @ 8625292903 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
22.i2c_target_stress_all_with_rand_reset.58978342664712168951872822587225134858772822071172108749387556946698835166748
Line 384, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/22.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 7868021107 ps: (i2c_scoreboard.sv:624) [uvm_test_top.env.scoreboard] Check failed obs.wdata == exp.wdata (152 [0x98] vs 121 [0x79])
UVM_INFO @ 7868021107 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_driver.sv:234) [i2c_drv_scl] wait timeout occurred! has 4 failures:
0.i2c_target_stress_all.11074392474028005888354059001249335186219290905917882644398565664149994604473
Line 268, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all/latest/run.log
UVM_FATAL @ 134214966820 ps: (i2c_driver.sv:234) [i2c_drv_scl] wait timeout occurred!
UVM_INFO @ 134214966820 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_stress_all.39759812969646937881884094258410015825741058716494520503292214055859757734605
Line 268, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all/latest/run.log
UVM_FATAL @ 115541794851 ps: (i2c_driver.sv:234) [i2c_drv_scl] wait timeout occurred!
UVM_INFO @ 115541794851 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_FATAL (i2c_target_hrst_vseq.sv:193) [i2c_target_hrst_vseq] Timed-out waiting for target_mode_wr_exp_fifo to become empty. has 4 failures:
5.i2c_target_hrst.65504468496168879420151390013393617996336580977059749926865854517963077847246
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10439465872 ps: (i2c_target_hrst_vseq.sv:193) [uvm_test_top.env.virtual_sequencer.i2c_target_hrst_vseq] Timed-out waiting for target_mode_wr_exp_fifo to become empty.
UVM_INFO @ 10439465872 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
14.i2c_target_hrst.79137560536633674164047662894565610462926741935015202115811800310243769100300
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/14.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10270857092 ps: (i2c_target_hrst_vseq.sv:193) [uvm_test_top.env.virtual_sequencer.i2c_target_hrst_vseq] Timed-out waiting for target_mode_wr_exp_fifo to become empty.
UVM_INFO @ 10270857092 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.controller_events.arbitration_lost reset value: * has 2 failures:
Test i2c_tl_intg_err has 1 failures.
2.i2c_tl_intg_err.81761082229848004449408057564650941823967354829351033822152331720449186787474
Line 304, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_tl_intg_err/latest/run.log
UVM_ERROR @ 36715284 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.controller_events.arbitration_lost reset value: 0x0
UVM_INFO @ 36715284 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test i2c_csr_mem_rw_with_rand_reset has 1 failures.
8.i2c_csr_mem_rw_with_rand_reset.48676958912722806923427804231344594216391595557449631297624977789815639548108
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 29695196 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.controller_events.arbitration_lost reset value: 0x0
UVM_INFO @ 29695196 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:641) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 2 failures:
Test i2c_target_stress_all_with_rand_reset has 1 failures.
3.i2c_target_stress_all_with_rand_reset.66014226360731713568880995023800533835768015679105388752750758728540780572570
Line 267, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1579990477 ps: (i2c_scoreboard.sv:641) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (181 [0xb5] vs 229 [0xe5])
UVM_INFO @ 1579990477 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test i2c_target_stress_all has 1 failures.
18.i2c_target_stress_all.89995466304999174421105415149677222682932279840781303186374649844285194466551
Line 282, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/18.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 93090707277 ps: (i2c_scoreboard.sv:641) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (148 [0x94] vs 116 [0x74])
UVM_INFO @ 93090707277 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:600) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite has 2 failures:
Test i2c_host_stress_all has 1 failures.
12.i2c_host_stress_all.104018149517934851438691835581912569207412870549838012486997301674216214051519
Line 2389, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/12.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 31873280031 ps: (i2c_scoreboard.sv:600) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite
--> EXP:
-----------------------------------------------------
Name Type Size Value
-----------------------------------------------------
Test i2c_host_stress_all_with_rand_reset has 1 failures.
25.i2c_host_stress_all_with_rand_reset.42342239130984877011039835597328843626827444907594262151416407200824711903835
Line 4565, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/25.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 4645929512 ps: (i2c_scoreboard.sv:600) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite
--> EXP:
-----------------------------------------------------
Name Type Size Value
-----------------------------------------------------
UVM_FATAL (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=*) == * has 2 failures:
16.i2c_target_stress_all_with_rand_reset.103858300274083800979986899383009067759741529654930327593396925889966939925956
Line 266, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/16.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 14778565705 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=0x247a8d14) == 0x0
UVM_INFO @ 14778565705 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
41.i2c_target_stress_all_with_rand_reset.12658221908679754181235231473686100626685692631073808647667194170555429184151
Line 266, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/41.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 13864725386 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=0x7dc29b14) == 0x0
UVM_INFO @ 13864725386 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_host_fifo_watermark_vseq.sv:60) [i2c_host_fifo_watermark_vseq] Check failed cnt_fmt_threshold <= * (* [*] vs * [*]) has 2 failures:
22.i2c_host_stress_all_with_rand_reset.33265959068172461631852967427115600219195127558356409330779346990987169971488
Line 2446, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/22.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2323734673 ps: (i2c_host_fifo_watermark_vseq.sv:60) [uvm_test_top.env.virtual_sequencer.i2c_host_fifo_watermark_vseq] Check failed cnt_fmt_threshold <= 3 (5 [0x5] vs 3 [0x3])
UVM_INFO @ 2323734673 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
29.i2c_host_stress_all_with_rand_reset.17059783016449833519980916005813015550202061417820691459649873278625233823141
Line 517, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/29.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 173810720 ps: (i2c_host_fifo_watermark_vseq.sv:60) [uvm_test_top.env.virtual_sequencer.i2c_host_fifo_watermark_vseq] Check failed cnt_fmt_threshold <= 3 (4 [0x4] vs 3 [0x3])
UVM_INFO @ 173810720 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 2 failures:
36.i2c_target_unexp_stop.9921815530519608211438513538109012168167156477430730009483688532054013721705
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/36.i2c_target_unexp_stop/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 385963013 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 385963013 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
45.i2c_target_unexp_stop.75851567369483330749266808276116720587191362485839379447566986604773827812890
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/45.i2c_target_unexp_stop/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 233081597 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 233081597 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_smoke_vseq.sv:99) [target_smoke_vseq] wait timeout occurred! has 1 failures:
17.i2c_target_unexp_stop.106800055528921835234863357752958492486313048012486489632865663766439933277677
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/17.i2c_target_unexp_stop/latest/run.log
UVM_FATAL @ 10351135759 ps: (i2c_target_smoke_vseq.sv:99) [target_smoke_vseq] wait timeout occurred!
UVM_INFO @ 10351135759 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.controller_events reset value: * has 1 failures:
17.i2c_csr_rw.52211728780102434454748548133364637131476622230252895029655184565818098387195
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/17.i2c_csr_rw/latest/run.log
UVM_ERROR @ 22977477 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (8 [0x8] vs 0 [0x0]) Regname: i2c_reg_block.controller_events reset value: 0x0
UVM_INFO @ 22977477 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:250) [i2c_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch has 1 failures:
18.i2c_same_csr_outstanding.22248313668467233005194464487262640871924694292965481769365132496559732457911
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/18.i2c_same_csr_outstanding/latest/run.log
UVM_ERROR @ 58137630 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed masked_data == exp_data (8 [0x8] vs 0 [0x0]) addr 0x1982f978 read out mismatch
UVM_INFO @ 58137630 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---