6e698b4dfe| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | host_smoke | i2c_host_smoke | 1.776m | 7.481ms | 50 | 50 | 100.00 |
| V1 | target_smoke | i2c_target_smoke | 1.043m | 17.218ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | i2c_csr_hw_reset | 0.810s | 66.350us | 5 | 5 | 100.00 |
| V1 | csr_rw | i2c_csr_rw | 0.830s | 44.535us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | i2c_csr_bit_bash | 3.720s | 1.295ms | 4 | 5 | 80.00 |
| V1 | csr_aliasing | i2c_csr_aliasing | 2.190s | 121.010us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | i2c_csr_mem_rw_with_rand_reset | 1.430s | 49.299us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | i2c_csr_rw | 0.830s | 44.535us | 20 | 20 | 100.00 |
| i2c_csr_aliasing | 2.190s | 121.010us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 154 | 155 | 99.35 | |||
| V2 | host_error_intr | i2c_host_error_intr | 12.970s | 289.032us | 49 | 50 | 98.00 |
| V2 | host_stress_all | i2c_host_stress_all | 31.786m | 115.073ms | 39 | 50 | 78.00 |
| V2 | host_maxperf | i2c_host_perf | 21.094m | 95.861ms | 48 | 50 | 96.00 |
| V2 | host_override | i2c_host_override | 0.740s | 50.176us | 50 | 50 | 100.00 |
| V2 | host_fifo_watermark | i2c_host_fifo_watermark | 6.475m | 10.127ms | 50 | 50 | 100.00 |
| V2 | host_fifo_overflow | i2c_host_fifo_overflow | 3.682m | 2.746ms | 50 | 50 | 100.00 |
| V2 | host_fifo_reset | i2c_host_fifo_reset_fmt | 1.290s | 619.887us | 50 | 50 | 100.00 |
| i2c_host_fifo_fmt_empty | 25.300s | 484.834us | 50 | 50 | 100.00 | ||
| i2c_host_fifo_reset_rx | 12.340s | 839.334us | 50 | 50 | 100.00 | ||
| V2 | host_fifo_full | i2c_host_fifo_full | 3.858m | 3.319ms | 50 | 50 | 100.00 |
| V2 | host_timeout | i2c_host_stretch_timeout | 45.990s | 3.996ms | 50 | 50 | 100.00 |
| V2 | host_rx_oversample | i2c_host_rx_oversample | 0 | 0 | -- | ||
| V2 | i2c_host_mode_toggle | i2c_host_mode_toggle | 2.026m | 2.552ms | 50 | 50 | 100.00 |
| V2 | target_error_intr | i2c_target_unexp_stop | 29.954m | 50.000ms | 0 | 50 | 0.00 |
| V2 | target_glitch | i2c_target_glitch | 12.150s | 9.211ms | 2 | 2 | 100.00 |
| V2 | target_stress_all | i2c_target_stress_all | 36.878m | 105.287ms | 0 | 50 | 0.00 |
| V2 | target_maxperf | i2c_target_perf | 3.238m | 10.319ms | 0 | 50 | 0.00 |
| V2 | target_fifo_empty | i2c_target_stress_rd | 1.158m | 1.748ms | 50 | 50 | 100.00 |
| i2c_target_intr_smoke | 8.870s | 8.247ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_reset | i2c_target_fifo_reset_acq | 1.700s | 526.163us | 50 | 50 | 100.00 |
| i2c_target_fifo_reset_tx | 1.660s | 795.637us | 50 | 50 | 100.00 | ||
| V2 | target_fifo_full | i2c_target_stress_wr | 50.295m | 76.745ms | 50 | 50 | 100.00 |
| i2c_target_stress_rd | 1.158m | 1.748ms | 50 | 50 | 100.00 | ||
| i2c_target_intr_stress_wr | 7.521m | 21.746ms | 50 | 50 | 100.00 | ||
| V2 | target_timeout | i2c_target_timeout | 9.320s | 1.985ms | 50 | 50 | 100.00 |
| V2 | target_clock_stretch | i2c_target_stretch | 41.812m | 36.933ms | 43 | 50 | 86.00 |
| V2 | bad_address | i2c_target_bad_addr | 6.380s | 1.401ms | 50 | 50 | 100.00 |
| V2 | target_mode_glitch | i2c_target_hrst | 22.760s | 10.758ms | 38 | 50 | 76.00 |
| V2 | target_fifo_watermark | i2c_target_fifo_watermarks_acq | 3.110s | 849.517us | 50 | 50 | 100.00 |
| i2c_target_fifo_watermarks_tx | 1.540s | 575.308us | 50 | 50 | 100.00 | ||
| V2 | host_mode_config_perf | i2c_host_perf | 21.094m | 95.861ms | 48 | 50 | 96.00 |
| i2c_host_perf_precise | 14.907m | 24.304ms | 50 | 50 | 100.00 | ||
| V2 | host_mode_clock_stretching | i2c_host_stretch_timeout | 45.990s | 3.996ms | 50 | 50 | 100.00 |
| V2 | target_mode_tx_stretch_ctrl | i2c_target_tx_stretch_ctrl | 3.290s | 213.145us | 0 | 50 | 0.00 |
| V2 | target_mode_nack_generation | target_mode_nack_generation | 0 | 0 | -- | ||
| V2 | host_mode_halt_on_nak | host_mode_halt_on_nak | 0 | 0 | -- | ||
| V2 | target_mode_n_byte_ack_control | target_mode_n_byte_ack_control | 0 | 0 | -- | ||
| V2 | target_mode_bus_timeout | target_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_timeout | controller_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_idle_delay | controller_mode_bus_idle_delay | 0 | 0 | -- | ||
| V2 | loopback_test | loopback_test | 0 | 0 | -- | ||
| V2 | multi_controller_clock_synchronization | multi_controller_clock_synchronization | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost_interference | multi_controller_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost | multi_controller_arbitration_lost | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost_interference | target_mode_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost | target_mode_arbitration_lost | 0 | 0 | -- | ||
| V2 | alert_test | i2c_alert_test | 0.720s | 18.045us | 50 | 50 | 100.00 |
| V2 | intr_test | i2c_intr_test | 0.730s | 20.342us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | i2c_tl_errors | 2.540s | 133.923us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | i2c_tl_errors | 2.540s | 133.923us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | i2c_csr_hw_reset | 0.810s | 66.350us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.830s | 44.535us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 2.190s | 121.010us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.250s | 221.541us | 18 | 20 | 90.00 | ||
| V2 | tl_d_partial_access | i2c_csr_hw_reset | 0.810s | 66.350us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.830s | 44.535us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 2.190s | 121.010us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.250s | 221.541us | 18 | 20 | 90.00 | ||
| V2 | TOTAL | 1357 | 1592 | 85.24 | |||
| V2S | tl_intg_err | i2c_tl_intg_err | 2.480s | 136.006us | 19 | 20 | 95.00 |
| i2c_sec_cm | 1.050s | 71.885us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | i2c_tl_intg_err | 2.480s | 136.006us | 19 | 20 | 95.00 |
| V2S | TOTAL | 24 | 25 | 96.00 | |||
| V3 | host_stress_all_with_rand_reset | i2c_host_stress_all_with_rand_reset | 5.439m | 9.342ms | 0 | 10 | 0.00 |
| V3 | target_stress_all_with_rand_reset | i2c_target_stress_all_with_rand_reset | 7.758m | 17.073ms | 0 | 10 | 0.00 |
| V3 | target_loopback | 0 | 0 | -- | |||
| V3 | TOTAL | 0 | 20 | 0.00 | |||
| Unmapped tests | i2c_host_may_nack | 25.070s | 2.414ms | 50 | 50 | 100.00 | |
| TOTAL | 1585 | 1842 | 86.05 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 1 | 1 | 1 | 100.00 |
| V1 | 7 | 7 | 6 | 85.71 |
| V2 | 47 | 34 | 24 | 51.06 |
| V2S | 2 | 2 | 1 | 50.00 |
| V3 | 3 | 2 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 90.68 | 96.51 | 89.46 | 97.22 | 69.05 | 93.48 | 98.44 | 90.63 |
UVM_ERROR (i2c_scoreboard.sv:604) [scoreboard] Check failed obs.num_data == exp.num_data (* [*] vs * [*]) has 54 failures:
0.i2c_target_stress_all.63637359050351486566170945173832927454653136690971405261505670078260368961486
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 9364418 ps: (i2c_scoreboard.sv:604) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (0 [0x0] vs 1 [0x1])
UVM_INFO @ 9364418 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_stress_all.109846974355602389721127680952869962822151350635576564602448260419418474975858
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 112264350 ps: (i2c_scoreboard.sv:604) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (0 [0x0] vs 1 [0x1])
UVM_INFO @ 112264350 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 31 more failures.
0.i2c_target_stress_all_with_rand_reset.28235451604084112396128221340861710440754024454742280519286605964847732277154
Line 265, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 3532254363 ps: (i2c_scoreboard.sv:604) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (1 [0x1] vs 11 [0xb])
UVM_INFO @ 3532254363 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_stress_all_with_rand_reset.14929724758419028389657810331894350548321158550164373931488310252192035706011
Line 270, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1772795016 ps: (i2c_scoreboard.sv:604) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (7 [0x7] vs 23 [0x17])
UVM_INFO @ 1772795016 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
1.i2c_target_unexp_stop.95038460380802781039591257557508641690348712218491324190021292098429375391496
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 98814180 ps: (i2c_scoreboard.sv:604) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (0 [0x0] vs 15 [0xf])
UVM_INFO @ 98814180 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_unexp_stop.74876473408925533550878968750378600722375035273456833137984500826746264132210
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 51906384 ps: (i2c_scoreboard.sv:604) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (0 [0x0] vs 2 [0x2])
UVM_INFO @ 51906384 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 14 more failures.
15.i2c_target_hrst.111117097048455927366546728535886895842697335420908426400656786772072801670602
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/15.i2c_target_hrst/latest/run.log
UVM_ERROR @ 59651402 ps: (i2c_scoreboard.sv:604) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (5 [0x5] vs 1 [0x1])
UVM_INFO @ 59651402 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
48.i2c_target_hrst.96636288853330651302231273654447009326690686557553549076109817684572971579594
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/48.i2c_target_hrst/latest/run.log
UVM_ERROR @ 50894609 ps: (i2c_scoreboard.sv:604) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (23 [0x17] vs 4 [0x4])
UVM_INFO @ 50894609 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_driver.sv:148) driver [driver] has 50 failures:
0.i2c_target_tx_stretch_ctrl.50520419010567226712297580368622817875311855374378483062354832290641970744292
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_tx_stretch_ctrl/latest/run.log
UVM_FATAL @ 48234755 ps: (i2c_driver.sv:148) uvm_test_top.env.m_i2c_agent.driver [uvm_test_top.env.m_i2c_agent.driver]
host_driver, received invalid request
UVM_INFO @ 48234755 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_tx_stretch_ctrl.50897483080664837349094051109781933724409415414143246386324567972335514193637
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_tx_stretch_ctrl/latest/run.log
UVM_FATAL @ 57129869 ps: (i2c_driver.sv:148) uvm_test_top.env.m_i2c_agent.driver [uvm_test_top.env.m_i2c_agent.driver]
host_driver, received invalid request
UVM_INFO @ 57129869 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 48 more failures.
Job i2c-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 36 failures:
Test i2c_target_stress_all has 6 failures.
1.i2c_target_stress_all.9939537624069711069819506229533258033986832236488557466688876103863912876350
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all/latest/run.log
Job ID: smart:baf29997-5653-403d-a895-9051181aa814
3.i2c_target_stress_all.75889880273718917245931275525149743292047634802495166353493727324895244465306
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all/latest/run.log
Job ID: smart:7cdc2fb7-887b-48d0-afe8-4d957b9959c6
... and 4 more failures.
Test i2c_target_stretch has 7 failures.
2.i2c_target_stretch.2049666284957182557998071436342375884939162261817072165607897718797890830744
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stretch/latest/run.log
Job ID: smart:b4748837-fc84-422e-8462-0a04e618f5e9
16.i2c_target_stretch.108960047296629190998346516774166459506603192122320460562380052460043002696096
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/16.i2c_target_stretch/latest/run.log
Job ID: smart:38228c33-d2a7-4f17-8dff-ba75580006f4
... and 5 more failures.
Test i2c_host_stress_all_with_rand_reset has 2 failures.
4.i2c_host_stress_all_with_rand_reset.35260134629562918776178398083628775807055092132193175440454321610163284852399
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_host_stress_all_with_rand_reset/latest/run.log
Job ID: smart:017e83ca-b1bd-4772-89a1-050a183eece9
6.i2c_host_stress_all_with_rand_reset.109955001173169939145558877446454432257009992523792844893903848941432281088440
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_host_stress_all_with_rand_reset/latest/run.log
Job ID: smart:9ee9fcfc-1403-4943-95ff-dbb9db4154a1
Test i2c_target_unexp_stop has 14 failures.
9.i2c_target_unexp_stop.71607291843995604236538453256984429570495624689917162031644093957393689775206
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_target_unexp_stop/latest/run.log
Job ID: smart:cb6c88e8-3947-4e4f-be35-d1e9ab56cb00
10.i2c_target_unexp_stop.33113472106548675113939753445553268012108669591939543483274320851482094014386
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/10.i2c_target_unexp_stop/latest/run.log
Job ID: smart:2144dc2d-a0a7-4830-b590-4dd87d468378
... and 12 more failures.
Test i2c_host_perf has 2 failures.
20.i2c_host_perf.53345736650172123702981851433278585884077823942720991184849929995360863388497
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/20.i2c_host_perf/latest/run.log
Job ID: smart:9c9f21b6-d44f-4272-a1f0-b0f0823ce30a
39.i2c_host_perf.94178512603643036186133568423446578443857034715058729869503491773376661478783
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/39.i2c_host_perf/latest/run.log
Job ID: smart:b798b561-de6a-484e-955f-9677e75e6088
... and 1 more tests.
UVM_FATAL (i2c_base_vseq.sv:1175) [stop_interrupt_handler] wait timeout occurred! has 35 failures:
0.i2c_target_perf.88413604131616964707468660756839649958733607268398683706298072035113058880131
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_perf/latest/run.log
UVM_FATAL @ 10319106583 ps: (i2c_base_vseq.sv:1175) [stop_interrupt_handler] wait timeout occurred!
UVM_INFO @ 10319106583 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_perf.98493847155907630393242835628921410533235050676422049496934277487512245905035
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_perf/latest/run.log
UVM_FATAL @ 12607117578 ps: (i2c_base_vseq.sv:1175) [stop_interrupt_handler] wait timeout occurred!
UVM_INFO @ 12607117578 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 29 more failures.
29.i2c_target_stress_all.51956843647208904771612961779262694994626120366926698588458173936614486702430
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/29.i2c_target_stress_all/latest/run.log
UVM_FATAL @ 10826169691 ps: (i2c_base_vseq.sv:1175) [stop_interrupt_handler] wait timeout occurred!
UVM_INFO @ 10826169691 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
39.i2c_target_stress_all.21132299826804522414528667930168996397649631535218718441195121771330275069883
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/39.i2c_target_stress_all/latest/run.log
UVM_FATAL @ 33161090213 ps: (i2c_base_vseq.sv:1175) [stop_interrupt_handler] wait timeout occurred!
UVM_INFO @ 33161090213 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_ERROR (i2c_scoreboard.sv:608) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 17 failures:
4.i2c_target_perf.58521005326180029751300990242519422410513668284334144991669242569320152014814
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_perf/latest/run.log
UVM_ERROR @ 185935346 ps: (i2c_scoreboard.sv:608) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 91 [0x5b])
UVM_INFO @ 185935346 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.i2c_target_perf.84114770533967229043411879522038351422952210574800757385880283882509737415448
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_perf/latest/run.log
UVM_ERROR @ 182450566 ps: (i2c_scoreboard.sv:608) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 144 [0x90])
UVM_INFO @ 182450566 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 13 more failures.
27.i2c_target_stress_all.83346131037424841183981849844019903289065525157991206238644382901171131671676
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/27.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 33119419 ps: (i2c_scoreboard.sv:608) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 220 [0xdc])
UVM_INFO @ 33119419 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
41.i2c_target_stress_all.32477418527113183647631074481685873628329824916652614126580005896115770301285
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/41.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 99268076 ps: (i2c_scoreboard.sv:608) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 67 [0x43])
UVM_INFO @ 99268076 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 16 failures:
0.i2c_target_unexp_stop.115108640024088958309262167635022174018592514670228733072515270874983164974245
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.i2c_target_unexp_stop.30236581831704338605305109112292466570585632909456769352549439164276836453555
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_unexp_stop/latest/run.log
UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 10 more failures.
2.i2c_target_perf.51547431370128157921099087922727341419922353757455046077397119019041698450446
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_perf/latest/run.log
UVM_FATAL @ 20000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 20000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 20000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
33.i2c_target_perf.48587768683142782359526434388604650931272316216180520391052874016002654429084
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/33.i2c_target_perf/latest/run.log
UVM_FATAL @ 20000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 20000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 20000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_ERROR (cip_base_vseq.sv:828) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 11 failures:
0.i2c_host_stress_all_with_rand_reset.78405465287362079708384927254079190252429442466832687518132621529290057116349
Line 516, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 106015486 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 106015486 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_host_stress_all_with_rand_reset.77097280200389451248778509438839858826452781151185770677873311033411397651876
Line 1315, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 761536403 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 761536403 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
1.i2c_target_stress_all_with_rand_reset.16597266141334375282970666832697167452452576392648328274219606761499274101151
Line 263, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2296230654 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2296230654 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.i2c_target_stress_all_with_rand_reset.98967455364043729913734500078136867871318770377034445942159996155996480186210
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2635595499 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2635595499 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (i2c_base_vseq.sv:992) virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout has 9 failures:
4.i2c_target_unexp_stop.57031621847319811619075099318736972791766019743822142004604229129651305082830
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 767205490 ps: (i2c_base_vseq.sv:992) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
UVM_INFO @ 767205490 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.i2c_target_unexp_stop.94110075757480610930257936824880483359725429943283666458339443057551079174465
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 700768097 ps: (i2c_base_vseq.sv:992) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
UVM_INFO @ 700768097 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
14.i2c_target_stress_all.107368486027009594423499900064780225956373496067183973757961324658794877218997
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/14.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 3015052701 ps: (i2c_base_vseq.sv:992) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
UVM_INFO @ 3015052701 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:559) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite has 7 failures:
0.i2c_host_stress_all.26731956301024339420458994436267101115642967517007390931791983112096467982807
Line 8763, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 60342541415 ps: (i2c_scoreboard.sv:559) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite
--> EXP:
-----------------------------------------------------
Name Type Size Value
-----------------------------------------------------
4.i2c_host_stress_all.51342166363116756453379598762440469092956300634648885318331456304091755632335
Line 1786, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 7875652094 ps: (i2c_scoreboard.sv:559) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite
--> EXP:
-----------------------------------------------------
Name Type Size Value
-----------------------------------------------------
... and 4 more failures.
23.i2c_host_error_intr.6804841018366823247622898377619656803269634705826658829542121891817687219808
Line 1204, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/23.i2c_host_error_intr/latest/run.log
UVM_ERROR @ 313643775 ps: (i2c_scoreboard.sv:559) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite
--> EXP:
-----------------------------------------------------
Name Type Size Value
-----------------------------------------------------
UVM_ERROR (i2c_scoreboard.sv:584) [scoreboard] Check failed obs.start == exp.start (* [*] vs * [*]) has 5 failures:
Test i2c_target_stress_all_with_rand_reset has 1 failures.
3.i2c_target_stress_all_with_rand_reset.44318086747237110191935023880958172913972455567491896512750236696586122473385
Line 380, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 6870321939 ps: (i2c_scoreboard.sv:584) [uvm_test_top.env.scoreboard] Check failed obs.start == exp.start (0 [0x0] vs 1 [0x1])
UVM_INFO @ 6870321939 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test i2c_target_hrst has 4 failures.
7.i2c_target_hrst.18645886455456093925767917668684020421239662129020926879219986921360673699731
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_hrst/latest/run.log
UVM_ERROR @ 27171062 ps: (i2c_scoreboard.sv:584) [uvm_test_top.env.scoreboard] Check failed obs.start == exp.start (1 [0x1] vs 0 [0x0])
UVM_INFO @ 27171062 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
31.i2c_target_hrst.99043704223672664572010870196048518243888687131139729414079800228810421839229
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/31.i2c_target_hrst/latest/run.log
UVM_ERROR @ 5841641 ps: (i2c_scoreboard.sv:584) [uvm_test_top.env.scoreboard] Check failed obs.start == exp.start (1 [0x1] vs 0 [0x0])
UVM_INFO @ 5841641 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_ERROR (i2c_scoreboard.sv:587) [scoreboard] Check failed obs.wdata == exp.wdata (* [*] vs * [*]) has 5 failures:
6.i2c_target_hrst.24181938935480871218967173279267282035601514380906084189183273364733225151124
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_hrst/latest/run.log
UVM_ERROR @ 7707468 ps: (i2c_scoreboard.sv:587) [uvm_test_top.env.scoreboard] Check failed obs.wdata == exp.wdata (136 [0x88] vs 176 [0xb0])
UVM_INFO @ 7707468 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
14.i2c_target_hrst.27088708494835629265784705955526768090923710516184181663798737720092581395932
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/14.i2c_target_hrst/latest/run.log
UVM_ERROR @ 13245108 ps: (i2c_scoreboard.sv:587) [uvm_test_top.env.scoreboard] Check failed obs.wdata == exp.wdata (150 [0x96] vs 151 [0x97])
UVM_INFO @ 13245108 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
8.i2c_target_stress_all_with_rand_reset.94130801403759082416722156357530157793191016664462857591608092166102340843211
Line 348, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 12132264698 ps: (i2c_scoreboard.sv:587) [uvm_test_top.env.scoreboard] Check failed obs.wdata == exp.wdata (150 [0x96] vs 44 [0x2c])
UVM_INFO @ 12132264698 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_driver.sv:234) [i2c_drv_scl] wait timeout occurred! has 4 failures:
16.i2c_target_stress_all.87313207483649897043959297216064919429299785337932721751068907732075729975259
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/16.i2c_target_stress_all/latest/run.log
UVM_FATAL @ 108891607155 ps: (i2c_driver.sv:234) [i2c_drv_scl] wait timeout occurred!
UVM_INFO @ 108891607155 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
18.i2c_target_stress_all.92089258687350113689584262269633421864479323352365141814521914847572510032076
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/18.i2c_target_stress_all/latest/run.log
UVM_FATAL @ 110114868138 ps: (i2c_driver.sv:234) [i2c_drv_scl] wait timeout occurred!
UVM_INFO @ 110114868138 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_ERROR (cip_base_vseq.sv:250) [i2c_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch has 2 failures:
14.i2c_same_csr_outstanding.69225870063351314490289368511635211275167086092952180116198974671795781399723
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/14.i2c_same_csr_outstanding/latest/run.log
UVM_ERROR @ 79174629 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed masked_data == exp_data (8 [0x8] vs 0 [0x0]) addr 0x183cf778 read out mismatch
UVM_INFO @ 79174629 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
19.i2c_same_csr_outstanding.78014073910221128439936325542725774126057464487271675938583575614715111940784
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/19.i2c_same_csr_outstanding/latest/run.log
UVM_ERROR @ 33453745 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed masked_data == exp_data (8 [0x8] vs 0 [0x0]) addr 0x405e3f8 read out mismatch
UVM_INFO @ 33453745 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:752) [i2c_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
4.i2c_target_stress_all_with_rand_reset.12596010191515268629713500854032713519595846336306897541201410069294907386241
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1249693126 ps: (cip_base_vseq.sv:752) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1249693126 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 1 failures:
4.i2c_csr_bit_bash.64997505633445125720676526976196923800128505443804614774290230278085827463321
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_csr_bit_bash/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 1295179572 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 1295179572 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=*) == * has 1 failures:
5.i2c_target_stress_all_with_rand_reset.25421925277562575863099360362425557549001827379766073598137576800618109380894
Line 320, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 17072637056 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=0xceb3b94) == 0x0
UVM_INFO @ 17072637056 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.controller_events reset value: * has 1 failures:
14.i2c_tl_intg_err.87551057439806655858259454707513565693354718754117963678000178092420199482116
Line 263, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/14.i2c_tl_intg_err/latest/run.log
UVM_ERROR @ 5307176 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (8 [0x8] vs 0 [0x0]) Regname: i2c_reg_block.controller_events reset value: 0x0
UVM_INFO @ 5307176 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:193) [i2c_target_hrst_vseq] Timed-out waiting for target_mode_wr_exp_fifo to become empty. has 1 failures:
35.i2c_target_hrst.77261749161505522353920003253985321941623600948589327362325948534219897689270
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/35.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10758289946 ps: (i2c_target_hrst_vseq.sv:193) [uvm_test_top.env.virtual_sequencer.i2c_target_hrst_vseq] Timed-out waiting for target_mode_wr_exp_fifo to become empty.
UVM_INFO @ 10758289946 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 1 failures:
36.i2c_target_hrst.66995314233671807030349693280873397847769711237844095858847623967599255195647
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/36.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10094257512 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10094257512 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---