3fd3528c8c| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | host_smoke | i2c_host_smoke | 1.787m | 27.417ms | 50 | 50 | 100.00 |
| V1 | target_smoke | i2c_target_smoke | 53.640s | 5.427ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | i2c_csr_hw_reset | 0.820s | 21.045us | 5 | 5 | 100.00 |
| V1 | csr_rw | i2c_csr_rw | 0.880s | 25.847us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | i2c_csr_bit_bash | 4.170s | 329.933us | 2 | 5 | 40.00 |
| V1 | csr_aliasing | i2c_csr_aliasing | 2.280s | 424.285us | 4 | 5 | 80.00 |
| V1 | csr_mem_rw_with_rand_reset | i2c_csr_mem_rw_with_rand_reset | 1.470s | 52.740us | 19 | 20 | 95.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | i2c_csr_rw | 0.880s | 25.847us | 20 | 20 | 100.00 |
| i2c_csr_aliasing | 2.280s | 424.285us | 4 | 5 | 80.00 | ||
| V1 | TOTAL | 150 | 155 | 96.77 | |||
| V2 | host_error_intr | i2c_host_error_intr | 10.810s | 983.063us | 50 | 50 | 100.00 |
| V2 | host_stress_all | i2c_host_stress_all | 59.305m | 43.880ms | 44 | 50 | 88.00 |
| V2 | host_maxperf | i2c_host_perf | 21.100m | 31.365ms | 50 | 50 | 100.00 |
| V2 | host_override | i2c_host_override | 0.740s | 48.264us | 50 | 50 | 100.00 |
| V2 | host_fifo_watermark | i2c_host_fifo_watermark | 7.076m | 5.147ms | 50 | 50 | 100.00 |
| V2 | host_fifo_overflow | i2c_host_fifo_overflow | 3.392m | 10.005ms | 50 | 50 | 100.00 |
| V2 | host_fifo_reset | i2c_host_fifo_reset_fmt | 1.330s | 673.482us | 50 | 50 | 100.00 |
| i2c_host_fifo_fmt_empty | 27.390s | 519.838us | 50 | 50 | 100.00 | ||
| i2c_host_fifo_reset_rx | 12.890s | 440.238us | 50 | 50 | 100.00 | ||
| V2 | host_fifo_full | i2c_host_fifo_full | 4.265m | 12.524ms | 49 | 50 | 98.00 |
| V2 | host_timeout | i2c_host_stretch_timeout | 41.050s | 892.647us | 50 | 50 | 100.00 |
| V2 | host_rx_oversample | i2c_host_rx_oversample | 0 | 0 | -- | ||
| V2 | i2c_host_mode_toggle | i2c_host_mode_toggle | 1.728m | 8.702ms | 50 | 50 | 100.00 |
| V2 | target_error_intr | i2c_target_unexp_stop | 19.376m | 50.000ms | 0 | 50 | 0.00 |
| V2 | target_glitch | i2c_target_glitch | 10.870s | 2.185ms | 2 | 2 | 100.00 |
| V2 | target_stress_all | i2c_target_stress_all | 52.906m | 116.356ms | 0 | 50 | 0.00 |
| V2 | target_maxperf | i2c_target_perf | 40.688m | 20.000ms | 0 | 50 | 0.00 |
| V2 | target_fifo_empty | i2c_target_stress_rd | 1.307m | 6.478ms | 50 | 50 | 100.00 |
| i2c_target_intr_smoke | 8.610s | 6.113ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_reset | i2c_target_fifo_reset_acq | 1.960s | 344.777us | 50 | 50 | 100.00 |
| i2c_target_fifo_reset_tx | 1.640s | 579.455us | 50 | 50 | 100.00 | ||
| V2 | target_fifo_full | i2c_target_stress_wr | 45.111m | 67.710ms | 50 | 50 | 100.00 |
| i2c_target_stress_rd | 1.307m | 6.478ms | 50 | 50 | 100.00 | ||
| i2c_target_intr_stress_wr | 6.039m | 21.245ms | 50 | 50 | 100.00 | ||
| V2 | target_timeout | i2c_target_timeout | 8.810s | 1.615ms | 50 | 50 | 100.00 |
| V2 | target_clock_stretch | i2c_target_stretch | 51.709m | 44.004ms | 47 | 50 | 94.00 |
| V2 | bad_address | i2c_target_bad_addr | 5.310s | 1.012ms | 50 | 50 | 100.00 |
| V2 | target_mode_glitch | i2c_target_hrst | 2.172m | 10.024ms | 36 | 50 | 72.00 |
| V2 | target_fifo_watermark | i2c_target_fifo_watermarks_acq | 3.230s | 3.347ms | 50 | 50 | 100.00 |
| i2c_target_fifo_watermarks_tx | 1.380s | 818.259us | 48 | 50 | 96.00 | ||
| V2 | host_mode_config_perf | i2c_host_perf | 21.100m | 31.365ms | 50 | 50 | 100.00 |
| i2c_host_perf_precise | 24.992m | 23.272ms | 49 | 50 | 98.00 | ||
| V2 | host_mode_clock_stretching | i2c_host_stretch_timeout | 41.050s | 892.647us | 50 | 50 | 100.00 |
| V2 | target_mode_tx_stretch_ctrl | i2c_target_tx_stretch_ctrl | 3.680s | 265.246us | 0 | 50 | 0.00 |
| V2 | target_mode_nack_generation | target_mode_nack_generation | 0 | 0 | -- | ||
| V2 | host_mode_halt_on_nak | host_mode_halt_on_nak | 0 | 0 | -- | ||
| V2 | target_mode_n_byte_ack_control | target_mode_n_byte_ack_control | 0 | 0 | -- | ||
| V2 | target_mode_bus_timeout | target_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_timeout | controller_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_idle_delay | controller_mode_bus_idle_delay | 0 | 0 | -- | ||
| V2 | loopback_test | loopback_test | 0 | 0 | -- | ||
| V2 | multi_controller_clock_synchronization | multi_controller_clock_synchronization | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost_interference | multi_controller_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost | multi_controller_arbitration_lost | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost_interference | target_mode_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost | target_mode_arbitration_lost | 0 | 0 | -- | ||
| V2 | alert_test | i2c_alert_test | 0.710s | 18.696us | 50 | 50 | 100.00 |
| V2 | intr_test | i2c_intr_test | 0.740s | 49.335us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | i2c_tl_errors | 3.030s | 174.918us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | i2c_tl_errors | 3.030s | 174.918us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | i2c_csr_hw_reset | 0.820s | 21.045us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.880s | 25.847us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 2.280s | 424.285us | 4 | 5 | 80.00 | ||
| i2c_same_csr_outstanding | 1.420s | 76.018us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | i2c_csr_hw_reset | 0.820s | 21.045us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.880s | 25.847us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 2.280s | 424.285us | 4 | 5 | 80.00 | ||
| i2c_same_csr_outstanding | 1.420s | 76.018us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 1365 | 1592 | 85.74 | |||
| V2S | tl_intg_err | i2c_tl_intg_err | 2.550s | 160.750us | 16 | 20 | 80.00 |
| i2c_sec_cm | 1.050s | 207.888us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | i2c_tl_intg_err | 2.550s | 160.750us | 16 | 20 | 80.00 |
| V2S | TOTAL | 21 | 25 | 84.00 | |||
| V3 | host_stress_all_with_rand_reset | i2c_host_stress_all_with_rand_reset | 18.926m | 10.328ms | 0 | 10 | 0.00 |
| V3 | target_stress_all_with_rand_reset | i2c_target_stress_all_with_rand_reset | 4.352m | 27.658ms | 0 | 10 | 0.00 |
| V3 | target_loopback | 0 | 0 | -- | |||
| V3 | TOTAL | 0 | 20 | 0.00 | |||
| Unmapped tests | i2c_host_may_nack | 29.970s | 1.417ms | 50 | 50 | 100.00 | |
| TOTAL | 1586 | 1842 | 86.10 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 1 | 1 | 1 | 100.00 |
| V1 | 7 | 7 | 4 | 57.14 |
| V2 | 47 | 34 | 24 | 51.06 |
| V2S | 2 | 2 | 1 | 50.00 |
| V3 | 3 | 2 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 90.75 | 96.57 | 89.39 | 97.22 | 69.05 | 93.55 | 98.44 | 91.05 |
UVM_ERROR (i2c_scoreboard.sv:604) [scoreboard] Check failed obs.num_data == exp.num_data (* [*] vs * [*]) has 62 failures:
0.i2c_target_unexp_stop.23045137621207164049683238541191323365376573393839739326212687009798906383233
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 71723986 ps: (i2c_scoreboard.sv:604) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (0 [0x0] vs 25 [0x19])
UVM_INFO @ 71723986 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_unexp_stop.105589212127288270950152498483811436837525580299907370843837094293855958483290
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 18985721 ps: (i2c_scoreboard.sv:604) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (0 [0x0] vs 3 [0x3])
UVM_INFO @ 18985721 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 25 more failures.
0.i2c_target_hrst.9414722518303540340409351203098549678152175856160136808499206502031944177391
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log
UVM_ERROR @ 330401426 ps: (i2c_scoreboard.sv:604) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (1 [0x1] vs 8 [0x8])
UVM_INFO @ 330401426 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
12.i2c_target_hrst.12483995966909355357245740889596648060837929612604980886520561880555267983709
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/12.i2c_target_hrst/latest/run.log
UVM_ERROR @ 180893837 ps: (i2c_scoreboard.sv:604) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (6 [0x6] vs 20 [0x14])
UVM_INFO @ 180893837 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
0.i2c_target_stress_all_with_rand_reset.18050282830144255346973974175026548680618141845381128337516186223827735636134
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 38821335 ps: (i2c_scoreboard.sv:604) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (0 [0x0] vs 6 [0x6])
UVM_INFO @ 38821335 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_stress_all_with_rand_reset.35493698588985281216487243488671605086540083802037218055394349646515682819855
Line 276, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 11461058717 ps: (i2c_scoreboard.sv:604) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (2 [0x2] vs 4 [0x4])
UVM_INFO @ 11461058717 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
1.i2c_target_stress_all.30061917801369817541864328986823918583043596532879432922081242207551742622123
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 1785580838 ps: (i2c_scoreboard.sv:604) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (0 [0x0] vs 14 [0xe])
UVM_INFO @ 1785580838 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_stress_all.3090339521773546653892556917554640348612219505075494568630767509706500593179
Line 268, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 24075314434 ps: (i2c_scoreboard.sv:604) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (5 [0x5] vs 14 [0xe])
UVM_INFO @ 24075314434 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 25 more failures.
UVM_FATAL (i2c_driver.sv:148) driver [driver] has 50 failures:
0.i2c_target_tx_stretch_ctrl.29838600706103973976416933866794542495455735545892497761589085832029963312133
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_tx_stretch_ctrl/latest/run.log
UVM_FATAL @ 6232976 ps: (i2c_driver.sv:148) uvm_test_top.env.m_i2c_agent.driver [uvm_test_top.env.m_i2c_agent.driver]
host_driver, received invalid request
UVM_INFO @ 6232976 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_tx_stretch_ctrl.19942788445501136609055908152411615418688450230287446616729951205483514922162
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_tx_stretch_ctrl/latest/run.log
UVM_FATAL @ 18058228 ps: (i2c_driver.sv:148) uvm_test_top.env.m_i2c_agent.driver [uvm_test_top.env.m_i2c_agent.driver]
host_driver, received invalid request
UVM_INFO @ 18058228 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 48 more failures.
UVM_FATAL (i2c_base_vseq.sv:1175) [stop_interrupt_handler] wait timeout occurred! has 35 failures:
0.i2c_target_perf.90993487295955212008868341769317626169686637980644763498398168284994454388515
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_perf/latest/run.log
UVM_FATAL @ 10630440925 ps: (i2c_base_vseq.sv:1175) [stop_interrupt_handler] wait timeout occurred!
UVM_INFO @ 10630440925 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_perf.53198519871792619820405606254752895936356848525567692984801507193859461039364
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_perf/latest/run.log
UVM_FATAL @ 12034013537 ps: (i2c_base_vseq.sv:1175) [stop_interrupt_handler] wait timeout occurred!
UVM_INFO @ 12034013537 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 25 more failures.
6.i2c_target_stress_all.48364210250208177960529119300754610946026731975963538180580512678425953159538
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_stress_all/latest/run.log
UVM_FATAL @ 10348329034 ps: (i2c_base_vseq.sv:1175) [stop_interrupt_handler] wait timeout occurred!
UVM_INFO @ 10348329034 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
10.i2c_target_stress_all.24145995812127071585819927612240346336446342487911527016814859556339487510775
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/10.i2c_target_stress_all/latest/run.log
UVM_FATAL @ 20052503797 ps: (i2c_base_vseq.sv:1175) [stop_interrupt_handler] wait timeout occurred!
UVM_INFO @ 20052503797 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
UVM_ERROR (i2c_scoreboard.sv:608) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 21 failures:
1.i2c_target_perf.16060032436049830600903210697682487508502101302824470944189671151348644806152
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_perf/latest/run.log
UVM_ERROR @ 257180130 ps: (i2c_scoreboard.sv:608) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 185 [0xb9])
UVM_INFO @ 257180130 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.i2c_target_perf.78333332124756103606265351239417860072017501236888302521462098569774476827436
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_perf/latest/run.log
UVM_ERROR @ 27124313 ps: (i2c_scoreboard.sv:608) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 43 [0x2b])
UVM_INFO @ 27124313 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 14 more failures.
20.i2c_target_stress_all.47812152473640104452315236767306597824932489119168354957712304850559292222834
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/20.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 18129017 ps: (i2c_scoreboard.sv:608) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 23 [0x17])
UVM_INFO @ 18129017 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
21.i2c_target_stress_all.17862071495743587187862473505944116294547349965308636799462598801698700762202
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/21.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 9553116229 ps: (i2c_scoreboard.sv:608) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (91 [0x5b] vs 84 [0x54])
UVM_INFO @ 9553116229 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 19 failures:
1.i2c_target_unexp_stop.38719243946038632238403503148264118029246498814642514286061323347634417096433
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.i2c_target_unexp_stop.10138901463449941236228987823961582778702381680921477326096250203424197679500
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_unexp_stop/latest/run.log
UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 9 more failures.
7.i2c_target_perf.109578047300549455080670807388106548221337510615833185521275466543983042034754
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_perf/latest/run.log
UVM_FATAL @ 20000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 20000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 20000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
9.i2c_target_perf.113783800434293335164191429575365887595978698817500289255143630185089605228536
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_target_perf/latest/run.log
UVM_FATAL @ 20000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 20000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 20000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
27.i2c_host_perf_precise.17119477319567484945059024125204533366651629355019761315881364486143376985927
Line 272, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/27.i2c_host_perf_precise/latest/run.log
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job i2c-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 16 failures:
Test i2c_target_stretch has 3 failures.
4.i2c_target_stretch.89258816970155357896932939161341935374942294827380198089055775467806755207019
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stretch/latest/run.log
Job ID: smart:9ff892cd-2634-4e98-93e1-11be215af10c
22.i2c_target_stretch.110689220308707454567379712708703545206776788335480862835742071501350765123664
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/22.i2c_target_stretch/latest/run.log
Job ID: smart:28944269-e188-418c-a876-faf3d79a6bb3
... and 1 more failures.
Test i2c_host_stress_all_with_rand_reset has 2 failures.
6.i2c_host_stress_all_with_rand_reset.12284319774737552414361130571581412033625961874036547726643642043864543817365
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_host_stress_all_with_rand_reset/latest/run.log
Job ID: smart:571c7c62-1eda-4c54-82fe-070b93a4fde0
8.i2c_host_stress_all_with_rand_reset.97854558463008297945020509516395460163532683296771610864831369123981667627284
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_host_stress_all_with_rand_reset/latest/run.log
Job ID: smart:8426dc4d-6dfa-4799-9854-ccdacbf1efb2
Test i2c_target_unexp_stop has 5 failures.
13.i2c_target_unexp_stop.108214139192258639094497055099179533513191502602932374546626102026877222931498
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/13.i2c_target_unexp_stop/latest/run.log
Job ID: smart:070ec6cb-0bfb-4868-a340-df2c8ec44bda
18.i2c_target_unexp_stop.101903380476631175273198731887133293341787602880908754341759961935347975220756
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/18.i2c_target_unexp_stop/latest/run.log
Job ID: smart:30108122-ea66-4185-87d3-e27914dbc417
... and 3 more failures.
Test i2c_target_stress_all has 5 failures.
14.i2c_target_stress_all.25551702157293260885758203748823955122068517362934748509419231696665512688603
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/14.i2c_target_stress_all/latest/run.log
Job ID: smart:6f77c14f-89c5-42b5-8d4d-54ed4673f12a
35.i2c_target_stress_all.84133135494681940489232729009816728740616517024257549378708870637198744439118
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/35.i2c_target_stress_all/latest/run.log
Job ID: smart:56d32eca-71a7-41e8-ba14-e0f58dc05885
... and 3 more failures.
Test i2c_host_stress_all has 1 failures.
44.i2c_host_stress_all.2221603258176221515031508976728555897303093448274312016972396625497126306192
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/44.i2c_host_stress_all/latest/run.log
Job ID: smart:8f03cab0-b67f-4174-9ebc-60f09ffb3536
UVM_ERROR (cip_base_vseq.sv:828) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 13 failures:
0.i2c_host_stress_all_with_rand_reset.93693259286898717953738580055536266622215839410903076704448747509166297553516
Line 4831, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 10328380243 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 10328380243 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_host_stress_all_with_rand_reset.24791858285944394868425201679517886376082873409423256060548977617967839768032
Line 6006, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 58686210243 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 58686210243 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
1.i2c_target_stress_all_with_rand_reset.33594226592136824400141081020979072501347831253563636146947162642159730718948
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 206546545 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 206546545 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.i2c_target_stress_all_with_rand_reset.1643340563296540783366333228509904247649346297309787317028237397107696550058
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 7758492590 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 7758492590 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_ERROR (i2c_base_vseq.sv:992) virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout has 8 failures:
12.i2c_target_unexp_stop.68457968917098625708356281507926641015716546592900671395277586400524558571919
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/12.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 1720168988 ps: (i2c_base_vseq.sv:992) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
UVM_INFO @ 1720168988 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
17.i2c_target_unexp_stop.105117289986431739616109335667427700906329873169241179604278518503821426117808
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/17.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 3365058473 ps: (i2c_base_vseq.sv:992) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
UVM_INFO @ 3365058473 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
46.i2c_target_stress_all.73459781290749086102057433663718242132488752689348079982597316837058037618654
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/46.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 816804659 ps: (i2c_base_vseq.sv:992) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
UVM_INFO @ 816804659 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:587) [scoreboard] Check failed obs.wdata == exp.wdata (* [*] vs * [*]) has 5 failures:
3.i2c_target_hrst.61871381510461999144798276728342851252109698146031135565611090564757297418869
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_hrst/latest/run.log
UVM_ERROR @ 4789803 ps: (i2c_scoreboard.sv:587) [uvm_test_top.env.scoreboard] Check failed obs.wdata == exp.wdata (88 [0x58] vs 57 [0x39])
UVM_INFO @ 4789803 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
9.i2c_target_hrst.62706151603685914739003221789836101610942261653338644394940465627514827347270
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_target_hrst/latest/run.log
UVM_ERROR @ 9020074 ps: (i2c_scoreboard.sv:587) [uvm_test_top.env.scoreboard] Check failed obs.wdata == exp.wdata (204 [0xcc] vs 101 [0x65])
UVM_INFO @ 9020074 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.controller_events reset value: * has 4 failures:
Test i2c_csr_aliasing has 1 failures.
1.i2c_csr_aliasing.61227914328587868243953566724007663580747166828537259733196739735681485090918
Line 249, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_csr_aliasing/latest/run.log
UVM_ERROR @ 51879682 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (8 [0x8] vs 0 [0x0]) Regname: i2c_reg_block.controller_events reset value: 0x0
UVM_INFO @ 51879682 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test i2c_tl_intg_err has 3 failures.
3.i2c_tl_intg_err.102508655692456064186120446843993456934522944665324192874907850555728571904524
Line 279, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_tl_intg_err/latest/run.log
UVM_ERROR @ 33490381 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (8 [0x8] vs 0 [0x0]) Regname: i2c_reg_block.controller_events reset value: 0x0
UVM_INFO @ 33490381 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.i2c_tl_intg_err.5707378923789619998871738593272601655049177752921353207925299224707017851107
Line 379, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_tl_intg_err/latest/run.log
UVM_ERROR @ 120896551 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (8 [0x8] vs 0 [0x0]) Regname: i2c_reg_block.controller_events reset value: 0x0
UVM_INFO @ 120896551 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (i2c_scoreboard.sv:559) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite has 4 failures:
9.i2c_host_stress_all.69055076342818340218590444566722919410554135202603322597562745628244453170924
Line 1284, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 5444753634 ps: (i2c_scoreboard.sv:559) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite
--> EXP:
-----------------------------------------------------
Name Type Size Value
-----------------------------------------------------
23.i2c_host_stress_all.76488301726776891274670649955612482633139950499869425287150446400250171183745
Line 1597, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/23.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 5798988474 ps: (i2c_scoreboard.sv:559) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite
--> EXP:
-----------------------------------------------------
Name Type Size Value
-----------------------------------------------------
... and 2 more failures.
UVM_FATAL (i2c_driver.sv:234) [i2c_drv_scl] wait timeout occurred! has 3 failures:
0.i2c_target_stress_all.53655615138070819375940310341411511970539300501712679443648567817065888924901
Line 268, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all/latest/run.log
UVM_FATAL @ 116355846806 ps: (i2c_driver.sv:234) [i2c_drv_scl] wait timeout occurred!
UVM_INFO @ 116355846806 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
13.i2c_target_stress_all.58251791724548809740377306485943431748620655458810760710494623798885533712573
Line 268, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/13.i2c_target_stress_all/latest/run.log
UVM_FATAL @ 110701502982 ps: (i2c_driver.sv:234) [i2c_drv_scl] wait timeout occurred!
UVM_INFO @ 110701502982 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 3 failures:
Test i2c_csr_bit_bash has 2 failures.
1.i2c_csr_bit_bash.104486976619904827054450729315363040782948039890408258560526700977113113406660
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_csr_bit_bash/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 70836560 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 70836560 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_csr_bit_bash.84261100210978244876380398113995726900031979928479980903207432711448013150326
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_csr_bit_bash/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 842255842 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 842255842 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test i2c_target_stress_all has 1 failures.
4.i2c_target_stress_all.6728606478628573713346914725033802668344021627031345791399804909160779174609
Line 255, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_all/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 540306142 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 540306142 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:193) [i2c_target_hrst_vseq] Timed-out waiting for target_mode_wr_exp_fifo to become empty. has 3 failures:
6.i2c_target_hrst.96686624684708403297889808475487955873703930963789019553469507385311499661687
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10132619505 ps: (i2c_target_hrst_vseq.sv:193) [uvm_test_top.env.virtual_sequencer.i2c_target_hrst_vseq] Timed-out waiting for target_mode_wr_exp_fifo to become empty.
UVM_INFO @ 10132619505 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
15.i2c_target_hrst.112498717152003904592329646608233770648457399193601185473924171590545106015736
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/15.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10024349381 ps: (i2c_target_hrst_vseq.sv:193) [uvm_test_top.env.virtual_sequencer.i2c_target_hrst_vseq] Timed-out waiting for target_mode_wr_exp_fifo to become empty.
UVM_INFO @ 10024349381 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.controller_events.arbitration_lost reset value: * has 2 failures:
Test i2c_csr_mem_rw_with_rand_reset has 1 failures.
4.i2c_csr_mem_rw_with_rand_reset.57410820137202721698365679022543208076507236263106190433908652835149143353888
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 2326285 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.controller_events.arbitration_lost reset value: 0x0
UVM_INFO @ 2326285 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test i2c_tl_intg_err has 1 failures.
11.i2c_tl_intg_err.52053791491335221816099562281142935444231508102256329207122605058466117184181
Line 327, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/11.i2c_tl_intg_err/latest/run.log
UVM_ERROR @ 408629362 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.controller_events.arbitration_lost reset value: 0x0
UVM_INFO @ 408629362 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:584) [scoreboard] Check failed obs.start == exp.start (* [*] vs * [*]) has 2 failures:
5.i2c_target_hrst.80058134532228495111521616465034020761565926161128690519824957318973205283611
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_hrst/latest/run.log
UVM_ERROR @ 20445652 ps: (i2c_scoreboard.sv:584) [uvm_test_top.env.scoreboard] Check failed obs.start == exp.start (1 [0x1] vs 0 [0x0])
UVM_INFO @ 20445652 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
26.i2c_target_hrst.77116853128289903731290846948531194186856850999788472330452532781594519115967
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/26.i2c_target_hrst/latest/run.log
UVM_ERROR @ 68061011 ps: (i2c_scoreboard.sv:584) [uvm_test_top.env.scoreboard] Check failed obs.start == exp.start (1 [0x1] vs 0 [0x0])
UVM_INFO @ 68061011 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Error-[CNST-CIF] Constraints inconsistency failure has 2 failures:
9.i2c_target_fifo_watermarks_tx.47198543678156534284484773734241987244961763016889493297138621851145165245822
Line 292, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_target_fifo_watermarks_tx/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 723
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
34.i2c_target_fifo_watermarks_tx.110510543096523978284187228020760892711525209632054752472007203288919060823562
Line 292, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/34.i2c_target_fifo_watermarks_tx/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 723
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
UVM_ERROR (i2c_scoreboard.sv:559) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 2 failures:
Test i2c_host_stress_all has 1 failures.
35.i2c_host_stress_all.79261635430401811089273718126055122121407012316801560780579718112290364758040
Line 10960, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/35.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 27776850290 ps: (i2c_scoreboard.sv:559) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
Test i2c_host_fifo_full has 1 failures.
43.i2c_host_fifo_full.22402561809768762219389982050568045883769698778092353098692839081000180297181
Line 936, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/43.i2c_host_fifo_full/latest/run.log
UVM_ERROR @ 338120947 ps: (i2c_scoreboard.sv:559) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
Offending '($stable(fmt_fifo_wvalid_i) && $stable(fmt_fifo_wdata_i))' has 1 failures:
3.i2c_csr_bit_bash.36955314294418761513269483152830144706760590121393919525651333930085920018937
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_csr_bit_bash/latest/run.log
Offending '($stable(fmt_fifo_wvalid_i) && $stable(fmt_fifo_wdata_i))'
UVM_ERROR @ 329932990 ps: (i2c_fifos.sv:310) [ASSERT FAILED] FmtWriteStableBeforeHandshake_A
UVM_INFO @ 329932990 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=*) == * has 1 failures:
9.i2c_target_stress_all_with_rand_reset.89793121842779142502064293982962848922335281536195169050611630113658399103234
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 10326425872 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=0xc19a8594) == 0x0
UVM_INFO @ 10326425872 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---