I2C Simulation Results

Wednesday June 26 2024 23:02:36 UTC

GitHub Revision: `be1c4a4f52`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 44766564427213563291105655232733134394512207819884794315335669279596867428010

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	1.868m	20.525ms	50	50	100.00
V1	target_smoke	i2c_target_smoke	56.520s	6.027ms	50	50	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	0.810s	69.209us	5	5	100.00
V1	csr_rw	i2c_csr_rw	0.860s	55.990us	20	20	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	6.240s	8.312ms	4	5	80.00
V1	csr_aliasing	i2c_csr_aliasing	2.130s	697.754us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.310s	30.602us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	0.860s	55.990us	20	20	100.00
		i2c_csr_aliasing	2.130s	697.754us	5	5	100.00
V1		TOTAL			154	155	99.35
V2	host_error_intr	i2c_host_error_intr	13.600s	322.717us	50	50	100.00
V2	host_stress_all	i2c_host_stress_all	53.644m	85.321ms	38	50	76.00
V2	host_maxperf	i2c_host_perf	47.113m	24.008ms	49	50	98.00
V2	host_override	i2c_host_override	0.750s	126.525us	50	50	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	6.333m	35.212ms	50	50	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	3.564m	2.730ms	50	50	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.340s	1.077ms	50	50	100.00
		i2c_host_fifo_fmt_empty	26.700s	514.841us	50	50	100.00
		i2c_host_fifo_reset_rx	12.430s	228.602us	50	50	100.00
V2	host_fifo_full	i2c_host_fifo_full	3.436m	3.668ms	50	50	100.00
V2	host_timeout	i2c_host_stretch_timeout	43.670s	923.409us	50	50	100.00
V2	host_rx_oversample	i2c_host_rx_oversample			0	0	--
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	1.990m	8.986ms	50	50	100.00
V2	target_error_intr	i2c_target_unexp_stop	52.745m	50.000ms	0	50	0.00
V2	target_glitch	i2c_target_glitch	9.530s	1.874ms	2	2	100.00
V2	target_stress_all	i2c_target_stress_all	54.589m	103.594ms	0	50	0.00
V2	target_maxperf	i2c_target_perf	11.810m	20.000ms	0	50	0.00
V2	target_fifo_empty	i2c_target_stress_rd	1.232m	1.716ms	50	50	100.00
		i2c_target_intr_smoke	8.510s	3.686ms	50	50	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.590s	272.757us	50	50	100.00
		i2c_target_fifo_reset_tx	1.860s	297.024us	50	50	100.00
V2	target_fifo_full	i2c_target_stress_wr	53.364m	71.283ms	50	50	100.00
		i2c_target_stress_rd	1.232m	1.716ms	50	50	100.00
		i2c_target_intr_stress_wr	5.741m	18.115ms	50	50	100.00
V2	target_timeout	i2c_target_timeout	8.530s	1.662ms	50	50	100.00
V2	target_clock_stretch	i2c_target_stretch	44.272m	34.918ms	47	50	94.00
V2	bad_address	i2c_target_bad_addr	6.540s	1.218ms	50	50	100.00
V2	target_mode_glitch	i2c_target_hrst	18.330s	10.421ms	34	50	68.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	3.150s	590.422us	50	50	100.00
		i2c_target_fifo_watermarks_tx	1.440s	200.160us	50	50	100.00
V2	host_mode_config_perf	i2c_host_perf	47.113m	24.008ms	49	50	98.00
		i2c_host_perf_precise	21.072m	24.274ms	50	50	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	43.670s	923.409us	50	50	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	2.280s	131.314us	0	50	0.00
V2	target_mode_nack_generation	target_mode_nack_generation			0	0	--
V2	host_mode_halt_on_nak	host_mode_halt_on_nak			0	0	--
V2	target_mode_n_byte_ack_control	target_mode_n_byte_ack_control			0	0	--
V2	target_mode_bus_timeout	target_mode_bus_timeout			0	0	--
V2	controller_mode_bus_timeout	controller_mode_bus_timeout			0	0	--
V2	controller_mode_bus_idle_delay	controller_mode_bus_idle_delay			0	0	--
V2	loopback_test	loopback_test			0	0	--
V2	multi_controller_clock_synchronization	multi_controller_clock_synchronization			0	0	--
V2	multi_controller_arbitration_lost_interference	multi_controller_arbitration_lost_interference			0	0	--
V2	multi_controller_arbitration_lost	multi_controller_arbitration_lost			0	0	--
V2	target_mode_arbitration_lost_interference	target_mode_arbitration_lost_interference			0	0	--
V2	target_mode_arbitration_lost	target_mode_arbitration_lost			0	0	--
V2	alert_test	i2c_alert_test	0.690s	19.385us	50	50	100.00
V2	intr_test	i2c_intr_test	0.770s	22.045us	50	50	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.780s	160.156us	20	20	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.780s	160.156us	20	20	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	0.810s	69.209us	5	5	100.00
		i2c_csr_rw	0.860s	55.990us	20	20	100.00
		i2c_csr_aliasing	2.130s	697.754us	5	5	100.00
		i2c_same_csr_outstanding	1.370s	280.193us	20	20	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	0.810s	69.209us	5	5	100.00
		i2c_csr_rw	0.860s	55.990us	20	20	100.00
		i2c_csr_aliasing	2.130s	697.754us	5	5	100.00
		i2c_same_csr_outstanding	1.370s	280.193us	20	20	100.00
V2		TOTAL			1360	1592	85.43
V2S	tl_intg_err	i2c_tl_intg_err	2.720s	166.107us	20	20	100.00
		i2c_sec_cm	0.950s	59.166us	5	5	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.720s	166.107us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	15.248m	38.685ms	0	10	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	2.367m	7.162ms	0	10	0.00
V3	target_loopback				0	0	--
V3		TOTAL			0	20	0.00
	Unmapped tests	i2c_host_may_nack	26.440s	2.490ms	50	50	100.00
		TOTAL			1589	1842	86.26

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	7	7	6	85.71
V2	47	34	26	55.32
V2S	2	2	2	100.00
V3	3	2	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
91.06	96.69	89.76	97.22	70.83	93.76	98.44	90.74

Failure Buckets

UVM_ERROR (i2c_scoreboard.sv:604) [scoreboard] Check failed obs.num_data == exp.num_data (* [*] vs * [*]) has 62 failures:

Test i2c_target_stress_all has 36 failures.

0.i2c_target_stress_all.2216633094581217174975226772289384753355963160389251682374256072750251243263
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all/latest/run.log

  UVM_ERROR @ 9132467464 ps: (i2c_scoreboard.sv:604) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (3 [0x3] vs 7 [0x7])
  UVM_INFO @ 9132467464 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.i2c_target_stress_all.6183947178952287652981954203172247711803575426505162730293168080640030956978
Line 275, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all/latest/run.log

  UVM_ERROR @ 15001959828 ps: (i2c_scoreboard.sv:604) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (5 [0x5] vs 1 [0x1])
  UVM_INFO @ 15001959828 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 34 more failures.

Test i2c_target_unexp_stop has 17 failures.

4.i2c_target_unexp_stop.108209648076657796796495275512049544798723530909178510046818035930902518948313
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_unexp_stop/latest/run.log

  UVM_ERROR @  23843043 ps: (i2c_scoreboard.sv:604) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (0 [0x0] vs 1 [0x1])
  UVM_INFO @  23843043 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.i2c_target_unexp_stop.33261631829240209325085626437931909255444675965911791845974525479423920197665
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_unexp_stop/latest/run.log

  UVM_ERROR @ 142547111 ps: (i2c_scoreboard.sv:604) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (0 [0x0] vs 10 [0xa])
  UVM_INFO @ 142547111 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 15 more failures.

Test i2c_target_stress_all_with_rand_reset has 1 failures.
- 4.i2c_target_stress_all_with_rand_reset.37884431493795584762886833346667390755774033489379051615920429109945511520791
  Line 267, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1528406743 ps: (i2c_scoreboard.sv:604) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (16 [0x10] vs 1 [0x1])
  UVM_INFO @ 1528406743 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Test i2c_target_hrst has 8 failures.

10.i2c_target_hrst.95567481553029083264278215761238972479415818696927093736881353673365339763874
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/10.i2c_target_hrst/latest/run.log

  UVM_ERROR @ 623056851 ps: (i2c_scoreboard.sv:604) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (19 [0x13] vs 17 [0x11])
  UVM_INFO @ 623056851 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

13.i2c_target_hrst.75059061292824398692358810905831461023746574643155408672336236878094847140450
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/13.i2c_target_hrst/latest/run.log

  UVM_ERROR @  91398673 ps: (i2c_scoreboard.sv:604) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (13 [0xd] vs 30 [0x1e])
  UVM_INFO @  91398673 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

UVM_FATAL (i2c_driver.sv:148) driver [driver] has 50 failures:
- Test i2c_target_tx_stretch_ctrl has 50 failures.
  - 0.i2c_target_tx_stretch_ctrl.107587895668513490206898949642367446940907035709786234124063853336517558109262
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_tx_stretch_ctrl/latest/run.log
```
  UVM_FATAL @  51000450 ps: (i2c_driver.sv:148) uvm_test_top.env.m_i2c_agent.driver [uvm_test_top.env.m_i2c_agent.driver]
    host_driver, received invalid request
  UVM_INFO @  51000450 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 1.i2c_target_tx_stretch_ctrl.96760759307929493899723389619119057074146506754285458062248224734252593624069
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_tx_stretch_ctrl/latest/run.log
```
  UVM_FATAL @   6674457 ps: (i2c_driver.sv:148) uvm_test_top.env.m_i2c_agent.driver [uvm_test_top.env.m_i2c_agent.driver]
    host_driver, received invalid request
  UVM_INFO @   6674457 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - ... and 48 more failures.
UVM_FATAL (i2c_base_vseq.sv:1175) [stop_interrupt_handler] wait timeout occurred! has 47 failures:
- Test i2c_target_perf has 40 failures.
  - 0.i2c_target_perf.51940801028682922602641652080963805328867196484191719603207497025457993023255
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_perf/latest/run.log
```
  UVM_FATAL @ 10510309461 ps: (i2c_base_vseq.sv:1175) [stop_interrupt_handler] wait timeout occurred!
  UVM_INFO @ 10510309461 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.i2c_target_perf.52904364313343119203807102371195011739017930268743115636184398246901052159262
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_perf/latest/run.log
```
  UVM_FATAL @ 10453728894 ps: (i2c_base_vseq.sv:1175) [stop_interrupt_handler] wait timeout occurred!
  UVM_INFO @ 10453728894 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 38 more failures.
- Test i2c_target_stress_all has 7 failures.
  - 22.i2c_target_stress_all.112424885071869430525385173491585956323096111769874639764343529090764184428333
    Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/22.i2c_target_stress_all/latest/run.log
```
  UVM_FATAL @ 11787090544 ps: (i2c_base_vseq.sv:1175) [stop_interrupt_handler] wait timeout occurred!
  UVM_INFO @ 11787090544 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 28.i2c_target_stress_all.48757015960827566878884490452162551660271581918630276601955741041519847094196
    Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/28.i2c_target_stress_all/latest/run.log
```
  UVM_FATAL @ 11260997850 ps: (i2c_base_vseq.sv:1175) [stop_interrupt_handler] wait timeout occurred!
  UVM_INFO @ 11260997850 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.
Job i2c-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 21 failures:
- Test i2c_target_unexp_stop has 11 failures.
  - 1.i2c_target_unexp_stop.40504930373952377798210555778859270605415678192557302893002259875621792645096
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
```
  Job ID: smart:4b69a236-38da-492d-b7cc-f031dac51d88
```
  - 2.i2c_target_unexp_stop.41630105679252235966407612243932476619274660550593507341319905174693161807032
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_unexp_stop/latest/run.log
```
  Job ID: smart:5e257c58-ceb7-4dc3-b67d-7833241c92b1
```
  - ... and 9 more failures.
- Test i2c_target_stress_all has 1 failures.
  - 1.i2c_target_stress_all.53614985478825238944669042363263741964422969599638113567052158152299780097875
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all/latest/run.log
```
  Job ID: smart:5e9fb66e-4948-410c-a0d9-d6d5092f3451
```
- Test i2c_host_stress_all_with_rand_reset has 1 failures.
  - 2.i2c_host_stress_all_with_rand_reset.58063541366844378434376699985428699172507418661885280683315970124923729163721
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:ae6f53b7-15b1-401f-9e60-21084b090d30
```
- Test i2c_host_stress_all has 4 failures.
  - 6.i2c_host_stress_all.74553349015439114407815252135914587564438722675979791106446339864099391977329
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_host_stress_all/latest/run.log
```
  Job ID: smart:1a217121-0f51-48cf-9dbc-9b2a86d250af
```
  - 19.i2c_host_stress_all.10872565097975889444964715296241896018423402957897008819432774712352901528506
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/19.i2c_host_stress_all/latest/run.log
```
  Job ID: smart:bea15219-97ef-43ac-829f-c01a3581829e
```
  - ... and 2 more failures.
- Test i2c_host_perf has 1 failures.
  - 16.i2c_host_perf.72731038466118676272343594123332614929271194176122872280601946366715514930007
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/16.i2c_host_perf/latest/run.log
```
  Job ID: smart:5e6d2e27-dd94-4472-912c-5a3752c0e034
```
- ... and 1 more tests.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 20 failures:
- Test i2c_target_unexp_stop has 16 failures.
  - 0.i2c_target_unexp_stop.23912575459384602656035711620483636605591974639646360765402403028938478607017
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
```
  UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.i2c_target_unexp_stop.64148229291992915678936972644970703524764655194605213372465328378084637399207
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_unexp_stop/latest/run.log
```
  UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 14 more failures.
- Test i2c_target_perf has 4 failures.
  - 2.i2c_target_perf.61135617509499346632639597462689293236360889107109361540071416865794132562267
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_perf/latest/run.log
```
  UVM_FATAL @ 20000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 20000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 20000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 18.i2c_target_perf.103034222258329966533980984146367014711866097833873283533507948508609605301205
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/18.i2c_target_perf/latest/run.log
```
  UVM_FATAL @ 20000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 20000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 20000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.

UVM_ERROR (cip_base_vseq.sv:828) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 11 failures:

Test i2c_host_stress_all_with_rand_reset has 9 failures.

0.i2c_host_stress_all_with_rand_reset.14826367187670321368076616214014614690149561986078516127196573784646997582147
Line 4146, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 27690427704 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 27690427704 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_host_stress_all_with_rand_reset.93115876110439914490149503610801455224971062708855488504098169700350490099785
Line 1556, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 10635196000 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 10635196000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 7 more failures.

Test i2c_target_stress_all_with_rand_reset has 2 failures.

0.i2c_target_stress_all_with_rand_reset.23345985579091530459917694922797064357264799231024119504053882956778061148886
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2179413439 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2179413439 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

9.i2c_target_stress_all_with_rand_reset.97345666024686143001478303679481916804900176984429059307583580484066903015950
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2070719945 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2070719945 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (i2c_scoreboard.sv:608) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 11 failures:

Test i2c_target_stress_all_with_rand_reset has 3 failures.
- 5.i2c_target_stress_all_with_rand_reset.76511006775956463521297066673117747138162337010498545692521932871788427606549
  Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 220983967 ps: (i2c_scoreboard.sv:608) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 128 [0x80])
  UVM_INFO @ 220983967 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
- 6.i2c_target_stress_all_with_rand_reset.11078577767655944182172608520553096704502823903302792106529552007665750468301
  Line 262, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 109532588 ps: (i2c_scoreboard.sv:608) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 83 [0x53])
  UVM_INFO @ 109532588 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
- ... and 1 more failures.

Test i2c_target_perf has 5 failures.

16.i2c_target_perf.87911342393929486762149935699266266427494119464841002268520805412459721322600
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/16.i2c_target_perf/latest/run.log

  UVM_ERROR @  88192841 ps: (i2c_scoreboard.sv:608) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 25 [0x19])
  UVM_INFO @  88192841 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

20.i2c_target_perf.47910478094595538210755312677369882295854630573709462275616584784525377631206
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/20.i2c_target_perf/latest/run.log

  UVM_ERROR @ 242356686 ps: (i2c_scoreboard.sv:608) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 44 [0x2c])
  UVM_INFO @ 242356686 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Test i2c_target_stress_all has 3 failures.

18.i2c_target_stress_all.89036445824800771337603351040630183053002942030091124389462484218677853345009
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/18.i2c_target_stress_all/latest/run.log

  UVM_ERROR @ 149765751 ps: (i2c_scoreboard.sv:608) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 50 [0x32])
  UVM_INFO @ 149765751 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

29.i2c_target_stress_all.114388312080300982740485770233944296025194862108144970574958847612434454045826
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/29.i2c_target_stress_all/latest/run.log

  UVM_ERROR @ 14821353283 ps: (i2c_scoreboard.sv:608) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 89 [0x59])
  UVM_INFO @ 14821353283 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR (i2c_scoreboard.sv:559) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite has 7 failures:

Test i2c_host_stress_all has 7 failures.

5.i2c_host_stress_all.41400433639585790723310627446158582121383958006263612743303939495632814111490
Line 6347, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 25750292404 ps: (i2c_scoreboard.sv:559) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite
  --> EXP:
  -----------------------------------------------------
  Name              Type               Size  Value
  -----------------------------------------------------

8.i2c_host_stress_all.35917880995667631169332416274552369512484751790588650032718136170321048957536
Line 8496, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 19308651734 ps: (i2c_scoreboard.sv:559) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite
  --> EXP:
  -----------------------------------------------------
  Name              Type               Size  Value
  -----------------------------------------------------

... and 5 more failures.

UVM_ERROR (i2c_base_vseq.sv:992) virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout has 6 failures:
- Test i2c_target_unexp_stop has 5 failures.
  - 15.i2c_target_unexp_stop.60560437562521624438577981381145072452340164144192353337203919402365091525526
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/15.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 3235934260 ps: (i2c_base_vseq.sv:992) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
  UVM_INFO @ 3235934260 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 17.i2c_target_unexp_stop.44853679614835333397955251809521976977622351937729415359098319557801716463608
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/17.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 1788389131 ps: (i2c_base_vseq.sv:992) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
  UVM_INFO @ 1788389131 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
- Test i2c_target_stress_all has 1 failures.
  - 15.i2c_target_stress_all.57883919901741569986142970329834737607720565704503148450166806340949961647609
    Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/15.i2c_target_stress_all/latest/run.log
```
  UVM_ERROR @ 4849478832 ps: (i2c_base_vseq.sv:992) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
  UVM_INFO @ 4849478832 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (i2c_scoreboard.sv:587) [scoreboard] Check failed obs.wdata == exp.wdata (* [*] vs * [*]) has 4 failures:
- Test i2c_target_hrst has 4 failures.
  - 32.i2c_target_hrst.98491272963337287288538886488134344229834437376989138074453862314512594303385
    Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/32.i2c_target_hrst/latest/run.log
```
  UVM_ERROR @   5938712 ps: (i2c_scoreboard.sv:587) [uvm_test_top.env.scoreboard] Check failed obs.wdata == exp.wdata (238 [0xee] vs 2 [0x2])
  UVM_INFO @   5938712 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 35.i2c_target_hrst.86845346687271528981775790373308366427198871910226141594838916845950270082189
    Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/35.i2c_target_hrst/latest/run.log
```
  UVM_ERROR @  15014337 ps: (i2c_scoreboard.sv:587) [uvm_test_top.env.scoreboard] Check failed obs.wdata == exp.wdata (190 [0xbe] vs 51 [0x33])
  UVM_INFO @  15014337 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
UVM_FATAL (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=*) == * has 3 failures:
- Test i2c_target_stress_all_with_rand_reset has 3 failures.
  - 2.i2c_target_stress_all_with_rand_reset.114980890294969549446543570280383640930819445713588770546542388843696156699934
    Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 11858372369 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=0x9d33ae14) == 0x0
  UVM_INFO @ 11858372369 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.i2c_target_stress_all_with_rand_reset.105970726678777139683833453113675531522037062670546476702106615783390497034204
    Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 15045723932 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=0x4c6b4494) == 0x0
  UVM_INFO @ 15045723932 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR (i2c_scoreboard.sv:584) [scoreboard] Check failed obs.start == exp.start (* [*] vs * [*]) has 3 failures:
- Test i2c_target_hrst has 3 failures.
  - 19.i2c_target_hrst.43876267473705827986732479586608445683344731177553496778990176220896002423146
    Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/19.i2c_target_hrst/latest/run.log
```
  UVM_ERROR @  67377243 ps: (i2c_scoreboard.sv:584) [uvm_test_top.env.scoreboard] Check failed obs.start == exp.start (1 [0x1] vs 0 [0x0])
  UVM_INFO @  67377243 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 23.i2c_target_hrst.68949641727751280648623422762068194142788837239301673901353185452462731801284
    Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/23.i2c_target_hrst/latest/run.log
```
  UVM_ERROR @  62804298 ps: (i2c_scoreboard.sv:584) [uvm_test_top.env.scoreboard] Check failed obs.start == exp.start (1 [0x1] vs 0 [0x0])
  UVM_INFO @  62804298 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL (i2c_driver.sv:234) [i2c_drv_scl] wait timeout occurred! has 2 failures:
- Test i2c_target_stress_all has 2 failures.
  - 25.i2c_target_stress_all.2920715334178365524831252297219368266763280568350933823672857243626386878830
    Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/25.i2c_target_stress_all/latest/run.log
```
  UVM_FATAL @ 101641291540 ps: (i2c_driver.sv:234) [i2c_drv_scl] wait timeout occurred!
  UVM_INFO @ 101641291540 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 45.i2c_target_stress_all.8060407439824318323400971011743772976390906497098610303193336750427983682983
    Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/45.i2c_target_stress_all/latest/run.log
```
  UVM_FATAL @ 103593811596 ps: (i2c_driver.sv:234) [i2c_drv_scl] wait timeout occurred!
  UVM_INFO @ 103593811596 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:752) [i2c_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 1.i2c_target_stress_all_with_rand_reset.59876636637787784501249227312146218504700832297395641739855072045448132983626
    Line 287, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2833678749 ps: (cip_base_vseq.sv:752) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 2833678749 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '($stable(fmt_fifo_wvalid_i) && $stable(fmt_fifo_wdata_i))' has 1 failures:
- Test i2c_csr_bit_bash has 1 failures.
  - 4.i2c_csr_bit_bash.76097092428642477398644223926960771058877549148651186311185940055080112990030
    Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_csr_bit_bash/latest/run.log
```
      Offending '($stable(fmt_fifo_wvalid_i) && $stable(fmt_fifo_wdata_i))'
  UVM_ERROR @  70049693 ps: (i2c_fifos.sv:310) [ASSERT FAILED] FmtWriteStableBeforeHandshake_A
  UVM_INFO @  70049693 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (i2c_target_smoke_vseq.sv:99) [target_smoke_vseq] wait timeout occurred! has 1 failures:
- Test i2c_target_unexp_stop has 1 failures.
  - 16.i2c_target_unexp_stop.47472420918362189587761608676146087683913220244881973495032462552336999674162
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/16.i2c_target_unexp_stop/latest/run.log
```
  UVM_FATAL @ 11055052740 ps: (i2c_target_smoke_vseq.sv:99) [target_smoke_vseq] wait timeout occurred!
  UVM_INFO @ 11055052740 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (i2c_monitor.sv:587) monitor [monitor] ack_stop detected has 1 failures:
- Test i2c_target_perf has 1 failures.
  - 24.i2c_target_perf.84549834649674152001323332527179841454128570385958297244910516350644932988426
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/24.i2c_target_perf/latest/run.log
```
  UVM_ERROR @ 171699511 ps: (i2c_monitor.sv:587) uvm_test_top.env.m_i2c_agent.monitor [uvm_test_top.env.m_i2c_agent.monitor] ack_stop detected
  UVM_INFO @ 171699511 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (i2c_target_hrst_vseq.sv:193) [i2c_target_hrst_vseq] Timed-out waiting for target_mode_wr_exp_fifo to become empty. has 1 failures:
- Test i2c_target_hrst has 1 failures.
  - 34.i2c_target_hrst.24170174873679477029483610800507012030349081228707309859211320592097680426852
    Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/34.i2c_target_hrst/latest/run.log
```
  UVM_FATAL @ 10420586371 ps: (i2c_target_hrst_vseq.sv:193) [uvm_test_top.env.virtual_sequencer.i2c_target_hrst_vseq] Timed-out waiting for target_mode_wr_exp_fifo to become empty.
  UVM_INFO @ 10420586371 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (i2c_scoreboard.sv:559) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 1 failures:
- Test i2c_host_stress_all has 1 failures.
  - 43.i2c_host_stress_all.60584786086970535873937180629626052740834191230888694680556125532945555086669
    Line 15135, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/43.i2c_host_stress_all/latest/run.log
```
  UVM_ERROR @ 262916725407 ps: (i2c_scoreboard.sv:559) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
  --> EXP:
  ----------------------------------------------------
  Name              Type               Size  Value
  ----------------------------------------------------
```