I2C Simulation Results

Thursday June 27 2024 23:02:31 UTC

GitHub Revision: `8db2a18db1`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 100513533386727882033709335126269317053614297947080434367729937568368619502352

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	1.733m	2.227ms	50	50	100.00
V1	target_smoke	i2c_target_smoke	48.740s	1.219ms	50	50	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	0.750s	43.256us	5	5	100.00
V1	csr_rw	i2c_csr_rw	0.820s	49.375us	20	20	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	5.380s	530.649us	3	5	60.00
V1	csr_aliasing	i2c_csr_aliasing	1.870s	286.470us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.520s	156.081us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	0.820s	49.375us	20	20	100.00
		i2c_csr_aliasing	1.870s	286.470us	5	5	100.00
V1		TOTAL			153	155	98.71
V2	host_error_intr	i2c_host_error_intr	13.780s	908.916us	49	50	98.00
V2	host_stress_all	i2c_host_stress_all	53.204m	19.985ms	43	50	86.00
V2	host_maxperf	i2c_host_perf	43.331m	50.583ms	50	50	100.00
V2	host_override	i2c_host_override	0.760s	15.496us	50	50	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	6.341m	25.291ms	50	50	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	3.294m	24.551ms	50	50	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.250s	194.503us	50	50	100.00
		i2c_host_fifo_fmt_empty	29.250s	3.736ms	50	50	100.00
		i2c_host_fifo_reset_rx	11.290s	844.598us	50	50	100.00
V2	host_fifo_full	i2c_host_fifo_full	3.719m	3.066ms	50	50	100.00
V2	host_timeout	i2c_host_stretch_timeout	45.830s	1.046ms	50	50	100.00
V2	host_rx_oversample	i2c_host_rx_oversample			0	0	--
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	1.947m	9.067ms	49	50	98.00
V2	target_error_intr	i2c_target_unexp_stop	54.653m	50.000ms	0	50	0.00
V2	target_glitch	i2c_target_glitch	11.950s	2.517ms	2	2	100.00
V2	target_stress_all	i2c_target_stress_all	51.263m	100.177ms	0	50	0.00
V2	target_maxperf	i2c_target_perf	16.470m	20.000ms	0	50	0.00
V2	target_fifo_empty	i2c_target_stress_rd	1.203m	1.700ms	50	50	100.00
		i2c_target_intr_smoke	8.520s	6.423ms	50	50	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.700s	292.004us	50	50	100.00
		i2c_target_fifo_reset_tx	1.560s	273.666us	50	50	100.00
V2	target_fifo_full	i2c_target_stress_wr	17.891m	51.002ms	50	50	100.00
		i2c_target_stress_rd	1.203m	1.700ms	50	50	100.00
		i2c_target_intr_stress_wr	8.133m	23.456ms	50	50	100.00
V2	target_timeout	i2c_target_timeout	8.270s	1.677ms	50	50	100.00
V2	target_clock_stretch	i2c_target_stretch	41.760m	18.269ms	47	50	94.00
V2	bad_address	i2c_target_bad_addr	6.800s	1.358ms	50	50	100.00
V2	target_mode_glitch	i2c_target_hrst	48.090s	10.258ms	37	50	74.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	3.080s	616.388us	50	50	100.00
		i2c_target_fifo_watermarks_tx	1.430s	749.408us	50	50	100.00
V2	host_mode_config_perf	i2c_host_perf	43.331m	50.583ms	50	50	100.00
		i2c_host_perf_precise	4.079m	6.053ms	50	50	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	45.830s	1.046ms	50	50	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	3.740s	255.183us	0	50	0.00
V2	target_mode_nack_generation	target_mode_nack_generation			0	0	--
V2	host_mode_halt_on_nak	host_mode_halt_on_nak			0	0	--
V2	target_mode_n_byte_ack_control	target_mode_n_byte_ack_control			0	0	--
V2	target_mode_bus_timeout	target_mode_bus_timeout			0	0	--
V2	controller_mode_bus_timeout	controller_mode_bus_timeout			0	0	--
V2	controller_mode_bus_idle_delay	controller_mode_bus_idle_delay			0	0	--
V2	loopback_test	loopback_test			0	0	--
V2	multi_controller_clock_synchronization	multi_controller_clock_synchronization			0	0	--
V2	multi_controller_arbitration_lost_interference	multi_controller_arbitration_lost_interference			0	0	--
V2	multi_controller_arbitration_lost	multi_controller_arbitration_lost			0	0	--
V2	target_mode_arbitration_lost_interference	target_mode_arbitration_lost_interference			0	0	--
V2	target_mode_arbitration_lost	target_mode_arbitration_lost			0	0	--
V2	alert_test	i2c_alert_test	0.720s	17.178us	50	50	100.00
V2	intr_test	i2c_intr_test	0.760s	26.043us	50	50	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	3.060s	288.058us	20	20	100.00
V2	tl_d_illegal_access	i2c_tl_errors	3.060s	288.058us	20	20	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	0.750s	43.256us	5	5	100.00
		i2c_csr_rw	0.820s	49.375us	20	20	100.00
		i2c_csr_aliasing	1.870s	286.470us	5	5	100.00
		i2c_same_csr_outstanding	1.170s	56.947us	20	20	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	0.750s	43.256us	5	5	100.00
		i2c_csr_rw	0.820s	49.375us	20	20	100.00
		i2c_csr_aliasing	1.870s	286.470us	5	5	100.00
		i2c_same_csr_outstanding	1.170s	56.947us	20	20	100.00
V2		TOTAL			1367	1592	85.87
V2S	tl_intg_err	i2c_tl_intg_err	2.600s	284.003us	19	20	95.00
		i2c_sec_cm	0.920s	113.691us	5	5	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.600s	284.003us	19	20	95.00
V2S		TOTAL			24	25	96.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	14.194m	265.411ms	0	10	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	10.061m	192.496ms	0	10	0.00
V3	target_loopback				0	0	--
V3		TOTAL			0	20	0.00
	Unmapped tests	i2c_host_may_nack	25.780s	2.510ms	50	50	100.00
		TOTAL			1594	1842	86.54

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	7	7	6	85.71
V2	47	34	25	53.19
V2S	2	2	1	50.00
V3	3	2	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
90.75	96.57	89.50	97.22	69.05	93.55	98.44	90.95

Failure Buckets

UVM_ERROR (i2c_scoreboard.sv:604) [scoreboard] Check failed obs.num_data == exp.num_data (* [*] vs * [*]) has 65 failures:

Test i2c_target_stress_all has 32 failures.

0.i2c_target_stress_all.78079177825571470670150677378562301760349300049044787158607702152424240120378
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all/latest/run.log

  UVM_ERROR @ 4114413760 ps: (i2c_scoreboard.sv:604) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (9 [0x9] vs 6 [0x6])
  UVM_INFO @ 4114413760 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_target_stress_all.7629236969160397304387424424287683307249559658019506741331025597266748540940
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all/latest/run.log

  UVM_ERROR @ 120195321 ps: (i2c_scoreboard.sv:604) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (0 [0x0] vs 3 [0x3])
  UVM_INFO @ 120195321 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 30 more failures.

Test i2c_target_stress_all_with_rand_reset has 5 failures.
- 0.i2c_target_stress_all_with_rand_reset.81151668665709018655908873059831125025328484425535368053384951985456155127791
  Line 265, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2301803116 ps: (i2c_scoreboard.sv:604) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (1 [0x1] vs 8 [0x8])
  UVM_INFO @ 2301803116 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
- 3.i2c_target_stress_all_with_rand_reset.57183887769173943164113516070895282488926587794045981853690567173816898470361
  Line 265, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 5612751095 ps: (i2c_scoreboard.sv:604) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (9 [0x9] vs 16 [0x10])
  UVM_INFO @ 5612751095 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
- ... and 3 more failures.

Test i2c_target_unexp_stop has 23 failures.

1.i2c_target_unexp_stop.99051120492429641660505913231693623308993975768205901340113594927891417989212
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log

  UVM_ERROR @ 161802140 ps: (i2c_scoreboard.sv:604) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (0 [0x0] vs 6 [0x6])
  UVM_INFO @ 161802140 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.i2c_target_unexp_stop.1798719061208686132656861619955650459933374618592415625887433371709649668075
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_unexp_stop/latest/run.log

  UVM_ERROR @  33366302 ps: (i2c_scoreboard.sv:604) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (0 [0x0] vs 11 [0xb])
  UVM_INFO @  33366302 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 21 more failures.

Test i2c_target_hrst has 5 failures.

3.i2c_target_hrst.31395729537950641258648062778897052711082556685527656798288091068457484416986
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_hrst/latest/run.log

  UVM_ERROR @ 170706348 ps: (i2c_scoreboard.sv:604) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (13 [0xd] vs 23 [0x17])
  UVM_INFO @ 170706348 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

11.i2c_target_hrst.30357060012560998599650105954469111236554898729783688526037587815167875595300
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/11.i2c_target_hrst/latest/run.log

  UVM_ERROR @ 802122980 ps: (i2c_scoreboard.sv:604) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (14 [0xe] vs 1 [0x1])
  UVM_INFO @ 802122980 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_FATAL (i2c_driver.sv:148) driver [driver] has 50 failures:
- Test i2c_target_tx_stretch_ctrl has 50 failures.
  - 0.i2c_target_tx_stretch_ctrl.29262040104825720646442419217934036544232399240725132538390056658395600641704
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_tx_stretch_ctrl/latest/run.log
```
  UVM_FATAL @   9235769 ps: (i2c_driver.sv:148) uvm_test_top.env.m_i2c_agent.driver [uvm_test_top.env.m_i2c_agent.driver]
    host_driver, received invalid request
  UVM_INFO @   9235769 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 1.i2c_target_tx_stretch_ctrl.94135933306524866614914346138654100781084831118100199011953974094934702169956
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_tx_stretch_ctrl/latest/run.log
```
  UVM_FATAL @   8270360 ps: (i2c_driver.sv:148) uvm_test_top.env.m_i2c_agent.driver [uvm_test_top.env.m_i2c_agent.driver]
    host_driver, received invalid request
  UVM_INFO @   8270360 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - ... and 48 more failures.
UVM_FATAL (i2c_base_vseq.sv:1175) [stop_interrupt_handler] wait timeout occurred! has 45 failures:
- Test i2c_target_perf has 37 failures.
  - 1.i2c_target_perf.24911134155611662507600166008519717071633970306625869337638029861497540094864
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_perf/latest/run.log
```
  UVM_FATAL @ 10807205566 ps: (i2c_base_vseq.sv:1175) [stop_interrupt_handler] wait timeout occurred!
  UVM_INFO @ 10807205566 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.i2c_target_perf.62273742925754510872103081762684018277626265675488720706544085368360157156828
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_perf/latest/run.log
```
  UVM_FATAL @ 10506003390 ps: (i2c_base_vseq.sv:1175) [stop_interrupt_handler] wait timeout occurred!
  UVM_INFO @ 10506003390 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 35 more failures.
- Test i2c_target_stress_all has 8 failures.
  - 6.i2c_target_stress_all.37753370884991873050022785906774129890623713813305928150757928596206064327363
    Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_stress_all/latest/run.log
```
  UVM_FATAL @ 13029449347 ps: (i2c_base_vseq.sv:1175) [stop_interrupt_handler] wait timeout occurred!
  UVM_INFO @ 13029449347 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 12.i2c_target_stress_all.54853902734826694300127681196781577116193595743634780841088454675245748343231
    Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/12.i2c_target_stress_all/latest/run.log
```
  UVM_FATAL @ 19636691694 ps: (i2c_base_vseq.sv:1175) [stop_interrupt_handler] wait timeout occurred!
  UVM_INFO @ 19636691694 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.
Job i2c-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 21 failures:
- Test i2c_host_stress_all has 3 failures.
  - 1.i2c_host_stress_all.41277137042792659874041320936274120415962489583022391991054342140834809351264
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all/latest/run.log
```
  Job ID: smart:167a61ab-d58d-428d-8c4e-a8b48cbf1139
```
  - 15.i2c_host_stress_all.95248703156662140112031932229406986996829234388031549234888532083662829502
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/15.i2c_host_stress_all/latest/run.log
```
  Job ID: smart:c2e1f367-a13a-4ddb-a08a-2c912c063e79
```
  - ... and 1 more failures.
- Test i2c_target_unexp_stop has 11 failures.
  - 7.i2c_target_unexp_stop.102640548224302698345576748220954541143225643796079463877619671015996741183508
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_unexp_stop/latest/run.log
```
  Job ID: smart:3371d781-3b51-425a-b082-d1fe409e5e19
```
  - 14.i2c_target_unexp_stop.15876514249037146057269493314013976891158048619639463943663018011831367613799
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/14.i2c_target_unexp_stop/latest/run.log
```
  Job ID: smart:aa4cd1fb-6f09-471c-9644-aba0b1f1343a
```
  - ... and 9 more failures.
- Test i2c_target_stress_all has 3 failures.
  - 9.i2c_target_stress_all.40048920976962025134472157209423487504496062217663520975529556996847584183328
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_target_stress_all/latest/run.log
```
  Job ID: smart:e4891553-a76c-4410-9abd-538e0e329583
```
  - 20.i2c_target_stress_all.61574605518555816883307237842569261031493226488987261057897818508532071315944
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/20.i2c_target_stress_all/latest/run.log
```
  Job ID: smart:2c234091-9a31-4730-9f5f-c1d7d41e2c7d
```
  - ... and 1 more failures.
- Test i2c_host_stress_all_with_rand_reset has 1 failures.
  - 9.i2c_host_stress_all_with_rand_reset.114343914442823765458692038950251836679477683177368305337816397099369006537763
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:d364633e-3a2d-41f5-a161-ba1b2cd9775e
```
- Test i2c_target_stretch has 3 failures.
  - 28.i2c_target_stretch.54902708093821495412543510788185613556428526079081605573835440600478803169974
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/28.i2c_target_stretch/latest/run.log
```
  Job ID: smart:a82c6857-ac92-4883-afc9-4c2b4e1165d0
```
  - 34.i2c_target_stretch.35141306706466222730852356596189723435811392721694584523681365536861687945975
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/34.i2c_target_stretch/latest/run.log
```
  Job ID: smart:fa4fa86c-0896-4217-a661-48bdc9a111a3
```
  - ... and 1 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 17 failures:
- Test i2c_target_unexp_stop has 13 failures.
  - 0.i2c_target_unexp_stop.78774211177468772478859965944943034268234791399213940979599705031229809484834
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
```
  UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.i2c_target_unexp_stop.105658070732776095630914827809186365637765366683821448715819156566465966675629
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_unexp_stop/latest/run.log
```
  UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 11 more failures.
- Test i2c_target_perf has 4 failures.
  - 20.i2c_target_perf.24424077342653763814074442916212024867060208940119942001062963290878398773023
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/20.i2c_target_perf/latest/run.log
```
  UVM_FATAL @ 20000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 20000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 20000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 41.i2c_target_perf.27167188835191020649395119850187396275084061315327759816656795670384696757960
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/41.i2c_target_perf/latest/run.log
```
  UVM_FATAL @ 20000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 20000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 20000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.

UVM_ERROR (cip_base_vseq.sv:828) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 11 failures:

Test i2c_host_stress_all_with_rand_reset has 7 failures.

0.i2c_host_stress_all_with_rand_reset.83250410273422161636907043760025273018543249677461892290812628632122415500052
Line 331, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 500318827 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 500318827 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_host_stress_all_with_rand_reset.102763267468201372734658031834024890046182285164251514739033522384449226924147
Line 276, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 4167295933 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 4167295933 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

Test i2c_target_stress_all_with_rand_reset has 4 failures.

1.i2c_target_stress_all_with_rand_reset.73743754796090972172423706747155847738197986350470034712625776299334506916897
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 105201467 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 105201467 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.i2c_target_stress_all_with_rand_reset.43456959114832545607451483711587891018775518932135904867573754829953811135836
Line 524, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 192496053317 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 192496053317 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_ERROR (i2c_scoreboard.sv:608) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 10 failures:

Test i2c_target_perf has 8 failures.

0.i2c_target_perf.91643205904022541840648859987289997243167181103141161557411867039730549825093
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_perf/latest/run.log

  UVM_ERROR @  18713839 ps: (i2c_scoreboard.sv:608) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 109 [0x6d])
  UVM_INFO @  18713839 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.i2c_target_perf.17011476603895982020432482983637227778710257245059930751110422809316859083594
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_perf/latest/run.log

  UVM_ERROR @ 193432171 ps: (i2c_scoreboard.sv:608) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 125 [0x7d])
  UVM_INFO @ 193432171 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

Test i2c_target_stress_all has 2 failures.

8.i2c_target_stress_all.36128433458110270742985172087064333345475344153516667035723340867515089831692
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_target_stress_all/latest/run.log

  UVM_ERROR @  32427754 ps: (i2c_scoreboard.sv:608) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 111 [0x6f])
  UVM_INFO @  32427754 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

48.i2c_target_stress_all.52580447542506963636812037320188728178584318268070756626253343087694756010501
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/48.i2c_target_stress_all/latest/run.log

  UVM_ERROR @ 17361307740 ps: (i2c_scoreboard.sv:608) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (24 [0x18] vs 191 [0xbf])
  UVM_INFO @ 17361307740 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (i2c_scoreboard.sv:559) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite has 5 failures:

Test i2c_host_stress_all has 4 failures.

4.i2c_host_stress_all.70270253783519943574262041408471429957784010318099684000826755708736226006915
Line 2419, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 2942272347 ps: (i2c_scoreboard.sv:559) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite
  --> EXP:
  -----------------------------------------------------
  Name              Type               Size  Value
  -----------------------------------------------------

23.i2c_host_stress_all.66275534371160418766687340862715407907770085191902510349782224382432369386737
Line 2344, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/23.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 18589880145 ps: (i2c_scoreboard.sv:559) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite
  --> EXP:
  -----------------------------------------------------
  Name              Type               Size  Value
  -----------------------------------------------------

... and 2 more failures.

Test i2c_host_error_intr has 1 failures.

13.i2c_host_error_intr.28296478836166974968538576368657185324595505984338259442701605122353152011727
Line 286, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/13.i2c_host_error_intr/latest/run.log

  UVM_ERROR @   7407289 ps: (i2c_scoreboard.sv:559) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite
  --> EXP:
  -----------------------------------------------------
  Name              Type               Size  Value
  -----------------------------------------------------

UVM_FATAL (i2c_driver.sv:234) [i2c_drv_scl] wait timeout occurred! has 5 failures:
- Test i2c_target_stress_all has 5 failures.
  - 5.i2c_target_stress_all.39986785446665544933162545811627977764164814987965301515435726480501011954917
    Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_stress_all/latest/run.log
```
  UVM_FATAL @ 100407338257 ps: (i2c_driver.sv:234) [i2c_drv_scl] wait timeout occurred!
  UVM_INFO @ 100407338257 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 22.i2c_target_stress_all.64511770535846305354060280494267173774057072141827654576163622253469772575370
    Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/22.i2c_target_stress_all/latest/run.log
```
  UVM_FATAL @ 108060945310 ps: (i2c_driver.sv:234) [i2c_drv_scl] wait timeout occurred!
  UVM_INFO @ 108060945310 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
UVM_ERROR (i2c_scoreboard.sv:584) [scoreboard] Check failed obs.start == exp.start (* [*] vs * [*]) has 4 failures:
- Test i2c_target_hrst has 4 failures.
  - 1.i2c_target_hrst.15170688543111372532698367808077291967215076936287789872552135886064422426075
    Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_hrst/latest/run.log
```
  UVM_ERROR @   5837870 ps: (i2c_scoreboard.sv:584) [uvm_test_top.env.scoreboard] Check failed obs.start == exp.start (1 [0x1] vs 0 [0x0])
  UVM_INFO @   5837870 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 14.i2c_target_hrst.32265533447984735670852183498648239391100019209934071207051313897767416967094
    Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/14.i2c_target_hrst/latest/run.log
```
  UVM_ERROR @  17874902 ps: (i2c_scoreboard.sv:584) [uvm_test_top.env.scoreboard] Check failed obs.start == exp.start (1 [0x1] vs 0 [0x0])
  UVM_INFO @  17874902 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.

UVM_FATAL (i2c_target_hrst_vseq.sv:193) [i2c_target_hrst_vseq] Timed-out waiting for target_mode_wr_exp_fifo to become empty. has 3 failures:

Test i2c_target_hrst has 3 failures.

4.i2c_target_hrst.35767216903370842548278031208286475773414549473133423379322883053632461435007
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_hrst/latest/run.log

  UVM_FATAL @ 10004560510 ps: (i2c_target_hrst_vseq.sv:193) [uvm_test_top.env.virtual_sequencer.i2c_target_hrst_vseq] Timed-out waiting for target_mode_wr_exp_fifo to become empty.
  UVM_INFO @ 10004560510 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

20.i2c_target_hrst.14136206427478297072670718821680530852866629615049532197107581089686100245609
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/20.i2c_target_hrst/latest/run.log

  UVM_FATAL @ 10213583805 ps: (i2c_target_hrst_vseq.sv:193) [uvm_test_top.env.virtual_sequencer.i2c_target_hrst_vseq] Timed-out waiting for target_mode_wr_exp_fifo to become empty.
  UVM_INFO @ 10213583805 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 2 failures:
- Test i2c_csr_bit_bash has 1 failures.
  - 0.i2c_csr_bit_bash.96657173722458788664221880388847923496708190755922806590554163557028972756441
    Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_csr_bit_bash/latest/run.log
```
      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @ 391062834 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @ 391062834 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test i2c_target_unexp_stop has 1 failures.
  - 3.i2c_target_unexp_stop.67330618867533707085521102346105778951752360711540026078328552005698156690673
    Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_unexp_stop/latest/run.log
```
      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @ 109175342 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @ 109175342 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (i2c_base_vseq.sv:992) virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout has 2 failures:
- Test i2c_target_unexp_stop has 2 failures.
  - 40.i2c_target_unexp_stop.32136193394668024770136355208776994715981102223755807393510923811710666462078
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/40.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 706733952 ps: (i2c_base_vseq.sv:992) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
  UVM_INFO @ 706733952 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 41.i2c_target_unexp_stop.26154298789200443237404006982383621570786774307772109056198868211748977427558
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/41.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 769518105 ps: (i2c_base_vseq.sv:992) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
  UVM_INFO @ 769518105 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.controller_events.arbitration_lost reset value: * has 1 failures:
- Test i2c_tl_intg_err has 1 failures.
  - 1.i2c_tl_intg_err.33758991212812467867061257389906637116066361042218081591203940183361156621763
    Line 398, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_tl_intg_err/latest/run.log
```
  UVM_ERROR @ 1853177157 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.controller_events.arbitration_lost reset value: 0x0
  UVM_INFO @ 1853177157 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=*) == * has 1 failures:
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 2.i2c_target_stress_all_with_rand_reset.72794739501682865031675842505229556126036719374941385817518646593257306981270
    Line 284, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 11768248212 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=0x9240d094) == 0x0
  UVM_INFO @ 11768248212 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '($stable(fmt_fifo_wvalid_i) && $stable(fmt_fifo_wdata_i))' has 1 failures:
- Test i2c_csr_bit_bash has 1 failures.
  - 2.i2c_csr_bit_bash.108121945997623083475671179949834144167025105352976535586722620346019271436420
    Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_csr_bit_bash/latest/run.log
```
      Offending '($stable(fmt_fifo_wvalid_i) && $stable(fmt_fifo_wdata_i))'
  UVM_ERROR @ 932465894 ps: (i2c_fifos.sv:310) [ASSERT FAILED] FmtWriteStableBeforeHandshake_A
  UVM_INFO @ 932465894 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (i2c_scoreboard.sv:559) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 1 failures:
- Test i2c_host_stress_all_with_rand_reset has 1 failures.
  - 5.i2c_host_stress_all_with_rand_reset.72750561929061355205519846927531229397110510403318673258304354698196162686465
    Line 5123, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 265410581576 ps: (i2c_scoreboard.sv:559) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
  --> EXP:
  ----------------------------------------------------
  Name              Type               Size  Value
  ----------------------------------------------------
```
UVM_ERROR (i2c_host_fifo_watermark_vseq.sv:60) [i2c_host_fifo_watermark_vseq] Check failed cnt_fmt_threshold <= * (* [*] vs * [*]) has 1 failures:
- Test i2c_host_stress_all_with_rand_reset has 1 failures.
  - 6.i2c_host_stress_all_with_rand_reset.103095428348168887313845185419097165912602607481806148297848249795035934201061
    Line 1692, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 5821641339 ps: (i2c_host_fifo_watermark_vseq.sv:60) [uvm_test_top.env.virtual_sequencer.i2c_host_fifo_watermark_vseq] Check failed cnt_fmt_threshold <= 3 (6 [0x6] vs 3 [0x3])
  UVM_INFO @ 5821641339 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending 'scl_o' has 1 failures:
- Test i2c_host_mode_toggle has 1 failures.
  - 30.i2c_host_mode_toggle.43304613864513600167725132564296839428439457268940927499796931132486268155909
    Line 259, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/30.i2c_host_mode_toggle/latest/run.log
```
      Offending 'scl_o'
  UVM_ERROR @  60126357 ps: (i2c_controller_fsm.sv:976) [ASSERT FAILED] SclOutputGlitch_A
  UVM_INFO @  60126357 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (i2c_scoreboard.sv:587) [scoreboard] Check failed obs.wdata == exp.wdata (* [*] vs * [*]) has 1 failures:
- Test i2c_target_hrst has 1 failures.
  - 31.i2c_target_hrst.56879814993140827039751310113286895709263652394509461694433937399388523691884
    Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/31.i2c_target_hrst/latest/run.log
```
  UVM_ERROR @  16075481 ps: (i2c_scoreboard.sv:587) [uvm_test_top.env.scoreboard] Check failed obs.wdata == exp.wdata (182 [0xb6] vs 76 [0x4c])
  UVM_INFO @  16075481 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (i2c_monitor.sv:587) monitor [monitor] ack_stop detected has 1 failures:
- Test i2c_target_perf has 1 failures.
  - 45.i2c_target_perf.64698263544316772754305663504698331875021487932102449656613005704968853549513
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/45.i2c_target_perf/latest/run.log
```
  UVM_ERROR @ 937302582 ps: (i2c_monitor.sv:587) uvm_test_top.env.m_i2c_agent.monitor [uvm_test_top.env.m_i2c_agent.monitor] ack_stop detected
  UVM_INFO @ 937302582 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```