3d5220a43f| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | host_smoke | i2c_host_smoke | 1.836m | 4.631ms | 50 | 50 | 100.00 |
| V1 | target_smoke | i2c_target_smoke | 56.480s | 1.681ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | i2c_csr_hw_reset | 0.770s | 55.322us | 5 | 5 | 100.00 |
| V1 | csr_rw | i2c_csr_rw | 0.860s | 179.256us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | i2c_csr_bit_bash | 5.400s | 135.830us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | i2c_csr_aliasing | 2.100s | 217.223us | 4 | 5 | 80.00 |
| V1 | csr_mem_rw_with_rand_reset | i2c_csr_mem_rw_with_rand_reset | 1.440s | 33.813us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | i2c_csr_rw | 0.860s | 179.256us | 20 | 20 | 100.00 |
| i2c_csr_aliasing | 2.100s | 217.223us | 4 | 5 | 80.00 | ||
| V1 | TOTAL | 154 | 155 | 99.35 | |||
| V2 | host_error_intr | i2c_host_error_intr | 15.320s | 384.229us | 50 | 50 | 100.00 |
| V2 | host_stress_all | i2c_host_stress_all | 58.980m | 67.071ms | 41 | 50 | 82.00 |
| V2 | host_maxperf | i2c_host_perf | 33.319m | 50.616ms | 50 | 50 | 100.00 |
| V2 | host_override | i2c_host_override | 0.770s | 28.848us | 50 | 50 | 100.00 |
| V2 | host_fifo_watermark | i2c_host_fifo_watermark | 6.258m | 32.056ms | 50 | 50 | 100.00 |
| V2 | host_fifo_overflow | i2c_host_fifo_overflow | 3.374m | 2.605ms | 50 | 50 | 100.00 |
| V2 | host_fifo_reset | i2c_host_fifo_reset_fmt | 1.190s | 526.107us | 50 | 50 | 100.00 |
| i2c_host_fifo_fmt_empty | 35.710s | 2.618ms | 50 | 50 | 100.00 | ||
| i2c_host_fifo_reset_rx | 12.170s | 211.182us | 50 | 50 | 100.00 | ||
| V2 | host_fifo_full | i2c_host_fifo_full | 3.419m | 11.223ms | 50 | 50 | 100.00 |
| V2 | host_timeout | i2c_host_stretch_timeout | 47.240s | 1.064ms | 50 | 50 | 100.00 |
| V2 | host_rx_oversample | i2c_host_rx_oversample | 0 | 0 | -- | ||
| V2 | i2c_host_mode_toggle | i2c_host_mode_toggle | 1.995m | 2.497ms | 50 | 50 | 100.00 |
| V2 | target_error_intr | i2c_target_unexp_stop | 55.354m | 50.000ms | 0 | 50 | 0.00 |
| V2 | target_glitch | i2c_target_glitch | 10.540s | 2.085ms | 2 | 2 | 100.00 |
| V2 | target_stress_all | i2c_target_stress_all | 40.222m | 106.404ms | 0 | 50 | 0.00 |
| V2 | target_maxperf | i2c_target_perf | 3.616m | 10.646ms | 0 | 50 | 0.00 |
| V2 | target_fifo_empty | i2c_target_stress_rd | 1.227m | 1.722ms | 50 | 50 | 100.00 |
| i2c_target_intr_smoke | 7.880s | 6.044ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_reset | i2c_target_fifo_reset_acq | 1.590s | 306.033us | 50 | 50 | 100.00 |
| i2c_target_fifo_reset_tx | 1.530s | 251.266us | 50 | 50 | 100.00 | ||
| V2 | target_fifo_full | i2c_target_stress_wr | 19.910m | 53.122ms | 50 | 50 | 100.00 |
| i2c_target_stress_rd | 1.227m | 1.722ms | 50 | 50 | 100.00 | ||
| i2c_target_intr_stress_wr | 8.420m | 26.640ms | 50 | 50 | 100.00 | ||
| V2 | target_timeout | i2c_target_timeout | 8.380s | 6.469ms | 50 | 50 | 100.00 |
| V2 | target_clock_stretch | i2c_target_stretch | 56.143m | 42.272ms | 48 | 50 | 96.00 |
| V2 | bad_address | i2c_target_bad_addr | 6.880s | 6.044ms | 49 | 50 | 98.00 |
| V2 | target_mode_glitch | i2c_target_hrst | 21.100s | 10.132ms | 40 | 50 | 80.00 |
| V2 | target_fifo_watermark | i2c_target_fifo_watermarks_acq | 3.060s | 641.844us | 50 | 50 | 100.00 |
| i2c_target_fifo_watermarks_tx | 1.380s | 656.003us | 50 | 50 | 100.00 | ||
| V2 | host_mode_config_perf | i2c_host_perf | 33.319m | 50.616ms | 50 | 50 | 100.00 |
| i2c_host_perf_precise | 15.327m | 23.263ms | 49 | 50 | 98.00 | ||
| V2 | host_mode_clock_stretching | i2c_host_stretch_timeout | 47.240s | 1.064ms | 50 | 50 | 100.00 |
| V2 | target_mode_tx_stretch_ctrl | i2c_target_tx_stretch_ctrl | 5.410s | 434.847us | 0 | 50 | 0.00 |
| V2 | target_mode_nack_generation | target_mode_nack_generation | 0 | 0 | -- | ||
| V2 | host_mode_halt_on_nak | host_mode_halt_on_nak | 0 | 0 | -- | ||
| V2 | target_mode_n_byte_ack_control | target_mode_n_byte_ack_control | 0 | 0 | -- | ||
| V2 | target_mode_bus_timeout | target_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_timeout | controller_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_idle_delay | controller_mode_bus_idle_delay | 0 | 0 | -- | ||
| V2 | loopback_test | loopback_test | 0 | 0 | -- | ||
| V2 | multi_controller_clock_synchronization | multi_controller_clock_synchronization | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost_interference | multi_controller_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost | multi_controller_arbitration_lost | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost_interference | target_mode_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost | target_mode_arbitration_lost | 0 | 0 | -- | ||
| V2 | alert_test | i2c_alert_test | 0.730s | 39.648us | 50 | 50 | 100.00 |
| V2 | intr_test | i2c_intr_test | 0.770s | 83.898us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | i2c_tl_errors | 2.670s | 119.766us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | i2c_tl_errors | 2.670s | 119.766us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | i2c_csr_hw_reset | 0.770s | 55.322us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.860s | 179.256us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 2.100s | 217.223us | 4 | 5 | 80.00 | ||
| i2c_same_csr_outstanding | 1.180s | 57.448us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | i2c_csr_hw_reset | 0.770s | 55.322us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.860s | 179.256us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 2.100s | 217.223us | 4 | 5 | 80.00 | ||
| i2c_same_csr_outstanding | 1.180s | 57.448us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 1369 | 1592 | 85.99 | |||
| V2S | tl_intg_err | i2c_tl_intg_err | 2.580s | 501.048us | 18 | 20 | 90.00 |
| i2c_sec_cm | 1.070s | 64.010us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | i2c_tl_intg_err | 2.580s | 501.048us | 18 | 20 | 90.00 |
| V2S | TOTAL | 23 | 25 | 92.00 | |||
| V3 | host_stress_all_with_rand_reset | i2c_host_stress_all_with_rand_reset | 11.828m | 32.880ms | 0 | 10 | 0.00 |
| V3 | target_stress_all_with_rand_reset | i2c_target_stress_all_with_rand_reset | 2.640m | 10.249ms | 0 | 10 | 0.00 |
| V3 | target_loopback | 0 | 0 | -- | |||
| V3 | TOTAL | 0 | 20 | 0.00 | |||
| Unmapped tests | i2c_host_may_nack | 26.110s | 643.823us | 50 | 50 | 100.00 | |
| TOTAL | 1596 | 1842 | 86.64 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 1 | 1 | 1 | 100.00 |
| V1 | 7 | 7 | 6 | 85.71 |
| V2 | 47 | 34 | 25 | 53.19 |
| V2S | 2 | 2 | 1 | 50.00 |
| V3 | 3 | 2 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 90.81 | 96.51 | 89.46 | 97.22 | 70.24 | 93.48 | 98.44 | 90.32 |
UVM_ERROR (i2c_scoreboard.sv:604) [scoreboard] Check failed obs.num_data == exp.num_data (* [*] vs * [*]) has 56 failures:
Test i2c_target_unexp_stop has 26 failures.
1.i2c_target_unexp_stop.3196690942692928834854269547438322005735542486933082263744473812656592250194
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 59270617 ps: (i2c_scoreboard.sv:604) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (0 [0x0] vs 4 [0x4])
UVM_INFO @ 59270617 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_unexp_stop.85647502472058325788114214159853292332789409030175411887178928576307433221885
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 67670716 ps: (i2c_scoreboard.sv:604) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (0 [0x0] vs 6 [0x6])
UVM_INFO @ 67670716 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 24 more failures.
Test i2c_target_stress_all has 25 failures.
4.i2c_target_stress_all.28447838704301262133334144443406829597585316343755138530551896717208431657378
Line 275, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 54144284663 ps: (i2c_scoreboard.sv:604) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (7 [0x7] vs 2 [0x2])
UVM_INFO @ 54144284663 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
11.i2c_target_stress_all.7826643312083336321401474681925506407936675044740295258461236499247927552498
Line 275, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/11.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 39418697769 ps: (i2c_scoreboard.sv:604) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (8 [0x8] vs 2 [0x2])
UVM_INFO @ 39418697769 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 23 more failures.
Test i2c_target_stress_all_with_rand_reset has 2 failures.
5.i2c_target_stress_all_with_rand_reset.34744091636626908118572798707132103661317912708451532349962633105907351847573
Line 379, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 28983103831 ps: (i2c_scoreboard.sv:604) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (14 [0xe] vs 2 [0x2])
UVM_INFO @ 28983103831 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.i2c_target_stress_all_with_rand_reset.46305470644707341800217875168465099190387052599720941867391724638042964788807
Line 367, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 9162973306 ps: (i2c_scoreboard.sv:604) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (5 [0x5] vs 2 [0x2])
UVM_INFO @ 9162973306 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test i2c_target_hrst has 3 failures.
10.i2c_target_hrst.32657685822537689681257440607340037389588241747164888520348465065457746349203
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/10.i2c_target_hrst/latest/run.log
UVM_ERROR @ 359128991 ps: (i2c_scoreboard.sv:604) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (18 [0x12] vs 2 [0x2])
UVM_INFO @ 359128991 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
25.i2c_target_hrst.446462134849763194361991831407406382911104428311150950216053456084885065460
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/25.i2c_target_hrst/latest/run.log
UVM_ERROR @ 60209308 ps: (i2c_scoreboard.sv:604) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (14 [0xe] vs 7 [0x7])
UVM_INFO @ 60209308 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL (i2c_driver.sv:148) driver [driver] has 50 failures:
0.i2c_target_tx_stretch_ctrl.20705011581743385139765491425294631338596493392977897405258370044105351155957
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_tx_stretch_ctrl/latest/run.log
UVM_FATAL @ 230205056 ps: (i2c_driver.sv:148) uvm_test_top.env.m_i2c_agent.driver [uvm_test_top.env.m_i2c_agent.driver]
host_driver, received invalid request
UVM_INFO @ 230205056 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_tx_stretch_ctrl.12144504322977983718848782585742141243613501975150963652665715899784332183351
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_tx_stretch_ctrl/latest/run.log
UVM_FATAL @ 133912339 ps: (i2c_driver.sv:148) uvm_test_top.env.m_i2c_agent.driver [uvm_test_top.env.m_i2c_agent.driver]
host_driver, received invalid request
UVM_INFO @ 133912339 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 48 more failures.
UVM_FATAL (i2c_base_vseq.sv:1175) [stop_interrupt_handler] wait timeout occurred! has 43 failures:
0.i2c_target_perf.21163085348557761152944089696540126432842043120101308701924478517386639691612
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_perf/latest/run.log
UVM_FATAL @ 13907704615 ps: (i2c_base_vseq.sv:1175) [stop_interrupt_handler] wait timeout occurred!
UVM_INFO @ 13907704615 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_perf.95522543392658657186585545050850943618836804903826595123637693675246528941882
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_perf/latest/run.log
UVM_FATAL @ 11269172633 ps: (i2c_base_vseq.sv:1175) [stop_interrupt_handler] wait timeout occurred!
UVM_INFO @ 11269172633 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 33 more failures.
1.i2c_target_stress_all.34566961179594153076642797214194481686782027092436923332110656521041937762374
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all/latest/run.log
UVM_FATAL @ 10892862474 ps: (i2c_base_vseq.sv:1175) [stop_interrupt_handler] wait timeout occurred!
UVM_INFO @ 10892862474 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_stress_all.70884860256983504188013415202504382315812985946820077791339784633480421231847
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all/latest/run.log
UVM_FATAL @ 10607532893 ps: (i2c_base_vseq.sv:1175) [stop_interrupt_handler] wait timeout occurred!
UVM_INFO @ 10607532893 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
Job i2c-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 26 failures:
Test i2c_target_stress_all has 7 failures.
0.i2c_target_stress_all.53881441127106233456023254397022969284412141386710801347985815506793704005111
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all/latest/run.log
Job ID: smart:d62368f2-aa1a-4f39-b434-6eaa7202ce4d
3.i2c_target_stress_all.72807238638805149014780856102771101577099357894722539928105634007012296997700
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all/latest/run.log
Job ID: smart:63a36026-a243-4364-b3b4-9837f0debbcc
... and 5 more failures.
Test i2c_host_stress_all has 4 failures.
7.i2c_host_stress_all.114340005437323153665402103676798907646425803511658503138630871655910027802661
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_host_stress_all/latest/run.log
Job ID: smart:fa398225-44da-46ec-81c0-3a8fa777b75f
9.i2c_host_stress_all.110643378243003581071071010074043139364342321227649165188735860876446737391315
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_host_stress_all/latest/run.log
Job ID: smart:c2500723-e547-4290-88f4-1ee9402563c1
... and 2 more failures.
Test i2c_target_unexp_stop has 12 failures.
9.i2c_target_unexp_stop.101430549684872753394566881008098997608071117781618851785291712853743162103226
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_target_unexp_stop/latest/run.log
Job ID: smart:6af79ca6-75c1-4faa-9f6b-20f4924ed79e
14.i2c_target_unexp_stop.58506660156566531128075849729542481948421220965609815291338832550343676404452
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/14.i2c_target_unexp_stop/latest/run.log
Job ID: smart:85b3af5c-579e-4961-a360-9296deda9dcc
... and 10 more failures.
Test i2c_host_perf_precise has 1 failures.
12.i2c_host_perf_precise.64829412855480280798261550413551957893088621022941820742128345276651378265720
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/12.i2c_host_perf_precise/latest/run.log
Job ID: smart:e93f0f27-c055-4e6a-b75c-434626c6815f
Test i2c_target_stretch has 2 failures.
38.i2c_target_stretch.47412196341995049682848305359855125043510785392496166467030056479115744973308
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/38.i2c_target_stretch/latest/run.log
Job ID: smart:caa727f2-b60e-4c1d-a665-8c725cb48fd6
47.i2c_target_stretch.108884516543095855518302875450494571890198714973406256475374334751686138504053
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/47.i2c_target_stretch/latest/run.log
Job ID: smart:88a0fc8f-caf3-4d9c-94e9-d04f30fb1fc6
UVM_ERROR (i2c_scoreboard.sv:608) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 20 failures:
1.i2c_target_stress_all_with_rand_reset.94944813412019746562037805920304588303445706582277191451711957665672692568879
Line 268, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 59250709 ps: (i2c_scoreboard.sv:608) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 139 [0x8b])
UVM_INFO @ 59250709 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.i2c_target_stress_all_with_rand_reset.58872766090905939930481391702001957751127388646335145848647393082761070605806
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 49718670 ps: (i2c_scoreboard.sv:608) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 198 [0xc6])
UVM_INFO @ 49718670 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
5.i2c_target_perf.42467831515275256266005324254026127963424637573520600181238948194225906660404
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_perf/latest/run.log
UVM_ERROR @ 105783430 ps: (i2c_scoreboard.sv:608) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 209 [0xd1])
UVM_INFO @ 105783430 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.i2c_target_perf.66207739113341497149375597059843937829935960138653332617686235573505353266725
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_target_perf/latest/run.log
UVM_ERROR @ 13758186 ps: (i2c_scoreboard.sv:608) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 202 [0xca])
UVM_INFO @ 13758186 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 12 more failures.
8.i2c_target_stress_all.58359421856170984760060637478691540881030325568593017331533936068416415138933
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 69249174 ps: (i2c_scoreboard.sv:608) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 197 [0xc5])
UVM_INFO @ 69249174 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
10.i2c_target_stress_all.76726845257349984926331679051704076614006494110466058362510693116044063581764
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/10.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 86821491 ps: (i2c_scoreboard.sv:608) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 231 [0xe7])
UVM_INFO @ 86821491 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (cip_base_vseq.sv:828) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 11 failures:
0.i2c_host_stress_all_with_rand_reset.10668377862499556748069578569980983339525103508967986297229943460735262562956
Line 4192, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 15483590163 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 15483590163 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_host_stress_all_with_rand_reset.64396205026326740331169936151418980257557190322452995710576371105659067463968
Line 293, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 627395697 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 627395697 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
4.i2c_target_stress_all_with_rand_reset.10058257064109736567710404917816733805489311260732972561839324991871583911921
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1833057019 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1833057019 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.i2c_target_stress_all_with_rand_reset.14302759397964055804041014755131822282784847836121465279574040382537451125400
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 5751529228 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 5751529228 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 10 failures:
Test i2c_target_unexp_stop has 8 failures.
0.i2c_target_unexp_stop.14032817372942393525968560219292001869662885505177748717722555663067631910185
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.i2c_target_unexp_stop.66133429136948921919836696764943625439956681399105679956465081269025812080610
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_unexp_stop/latest/run.log
UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
Test i2c_target_perf has 1 failures.
24.i2c_target_perf.111097168512559819116329837930291711925739657745037064325553004938506631526484
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/24.i2c_target_perf/latest/run.log
UVM_FATAL @ 20000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 20000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 20000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test i2c_target_bad_addr has 1 failures.
27.i2c_target_bad_addr.108913297352557432998610815592890835146748938411792208967073741836014823309103
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/27.i2c_target_bad_addr/latest/run.log
UVM_FATAL @ 20000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 20000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 20000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_base_vseq.sv:992) virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout has 6 failures:
Test i2c_target_stress_all has 2 failures.
12.i2c_target_stress_all.14521963339808458502233695169364323507641767410523553697922040022546070089439
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/12.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 1424735850 ps: (i2c_base_vseq.sv:992) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
UVM_INFO @ 1424735850 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
35.i2c_target_stress_all.20106109168308039003940073374997619830014002807239554039561360130644027247915
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/35.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 1660675763 ps: (i2c_base_vseq.sv:992) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
UVM_INFO @ 1660675763 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test i2c_target_unexp_stop has 4 failures.
17.i2c_target_unexp_stop.48691905510169638291619882124032883560089184500763426638390459773656905909864
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/17.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 786886507 ps: (i2c_base_vseq.sv:992) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
UVM_INFO @ 786886507 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
20.i2c_target_unexp_stop.35961978919394874505843708024361982222570271800912791141104168752844886118565
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/20.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 4245732995 ps: (i2c_base_vseq.sv:992) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
UVM_INFO @ 4245732995 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_FATAL (i2c_driver.sv:234) [i2c_drv_scl] wait timeout occurred! has 5 failures:
6.i2c_target_stress_all.91245549750146669304556375539439560014679175994583740384406686107538409843359
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_stress_all/latest/run.log
UVM_FATAL @ 102971117226 ps: (i2c_driver.sv:234) [i2c_drv_scl] wait timeout occurred!
UVM_INFO @ 102971117226 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
17.i2c_target_stress_all.92291713248443375721304423485762836194040466209515075252646746369313828220875
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/17.i2c_target_stress_all/latest/run.log
UVM_FATAL @ 102703891328 ps: (i2c_driver.sv:234) [i2c_drv_scl] wait timeout occurred!
UVM_INFO @ 102703891328 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_ERROR (i2c_scoreboard.sv:559) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite has 5 failures:
11.i2c_host_stress_all.13003941164101813521892399288849121768788936073262128525159564771093208918631
Line 2203, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/11.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 7491933170 ps: (i2c_scoreboard.sv:559) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite
--> EXP:
-----------------------------------------------------
Name Type Size Value
-----------------------------------------------------
24.i2c_host_stress_all.82728421029975171736771740522248865453442685244676564896633849317514704616707
Line 1573, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/24.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 1228428977 ps: (i2c_scoreboard.sv:559) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite
--> EXP:
-----------------------------------------------------
Name Type Size Value
-----------------------------------------------------
... and 3 more failures.
UVM_ERROR (i2c_scoreboard.sv:584) [scoreboard] Check failed obs.start == exp.start (* [*] vs * [*]) has 3 failures:
11.i2c_target_hrst.62367758095331850628943714449889909327926924516795260949023036641529093347519
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/11.i2c_target_hrst/latest/run.log
UVM_ERROR @ 18674608 ps: (i2c_scoreboard.sv:584) [uvm_test_top.env.scoreboard] Check failed obs.start == exp.start (1 [0x1] vs 0 [0x0])
UVM_INFO @ 18674608 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
34.i2c_target_hrst.8253766687628126942855695740431604417427233218681325950401040344702131652742
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/34.i2c_target_hrst/latest/run.log
UVM_ERROR @ 71899053 ps: (i2c_scoreboard.sv:584) [uvm_test_top.env.scoreboard] Check failed obs.start == exp.start (1 [0x1] vs 0 [0x0])
UVM_INFO @ 71899053 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL (i2c_target_hrst_vseq.sv:193) [i2c_target_hrst_vseq] Timed-out waiting for target_mode_wr_exp_fifo to become empty. has 2 failures:
2.i2c_target_hrst.3609354182725919010246150213534157794389984558399444511484523201072442151334
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10131664602 ps: (i2c_target_hrst_vseq.sv:193) [uvm_test_top.env.virtual_sequencer.i2c_target_hrst_vseq] Timed-out waiting for target_mode_wr_exp_fifo to become empty.
UVM_INFO @ 10131664602 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
40.i2c_target_hrst.26611018800616470214317383242605723236689435507072446796863587309762585783663
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/40.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10120433161 ps: (i2c_target_hrst_vseq.sv:193) [uvm_test_top.env.virtual_sequencer.i2c_target_hrst_vseq] Timed-out waiting for target_mode_wr_exp_fifo to become empty.
UVM_INFO @ 10120433161 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.controller_events.arbitration_lost reset value: * has 2 failures:
13.i2c_tl_intg_err.96521914758950929464519979256218171850742292199101936840971856273865242615580
Line 317, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/13.i2c_tl_intg_err/latest/run.log
UVM_ERROR @ 190907404 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.controller_events.arbitration_lost reset value: 0x0
UVM_INFO @ 190907404 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
15.i2c_tl_intg_err.16150022195926491129335134049654881344490035150419040289892821078118934427283
Line 376, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/15.i2c_tl_intg_err/latest/run.log
UVM_ERROR @ 530301724 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.controller_events.arbitration_lost reset value: 0x0
UVM_INFO @ 530301724 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:587) [scoreboard] Check failed obs.wdata == exp.wdata (* [*] vs * [*]) has 2 failures:
33.i2c_target_hrst.7732788714092612521484480215585258128843168951369108542488800645845412148967
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/33.i2c_target_hrst/latest/run.log
UVM_ERROR @ 30451937 ps: (i2c_scoreboard.sv:587) [uvm_test_top.env.scoreboard] Check failed obs.wdata == exp.wdata (202 [0xca] vs 203 [0xcb])
UVM_INFO @ 30451937 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
42.i2c_target_hrst.110552973999530704783301082218586383659027448514180380200352625741257626589728
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/42.i2c_target_hrst/latest/run.log
UVM_ERROR @ 33894091 ps: (i2c_scoreboard.sv:587) [uvm_test_top.env.scoreboard] Check failed obs.wdata == exp.wdata (50 [0x32] vs 122 [0x7a])
UVM_INFO @ 33894091 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=*) == * has 1 failures:
0.i2c_target_stress_all_with_rand_reset.76317733576300257885074590788524183310096942383702793813450911024871257709300
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 10248574200 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=0x69c98794) == 0x0
UVM_INFO @ 10248574200 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_host_fifo_watermark_vseq.sv:60) [i2c_host_fifo_watermark_vseq] Check failed cnt_fmt_threshold <= * (* [*] vs * [*]) has 1 failures:
2.i2c_host_stress_all_with_rand_reset.18723552576987824492713755329501726922964039435943480435696292894164912425021
Line 613, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 6940155223 ps: (i2c_host_fifo_watermark_vseq.sv:60) [uvm_test_top.env.virtual_sequencer.i2c_host_fifo_watermark_vseq] Check failed cnt_fmt_threshold <= 3 (7 [0x7] vs 3 [0x3])
UVM_INFO @ 6940155223 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 1 failures:
2.i2c_target_stress_all_with_rand_reset.9708717623922883511819996375167494053245207738026210295742236704441228476641
Line 257, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 461411975 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 461411975 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.controller_events reset value: * has 1 failures:
4.i2c_csr_aliasing.87402712269991287946071507839257993273934041705617864197173393871318976920815
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_csr_aliasing/latest/run.log
UVM_ERROR @ 42771966 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (8 [0x8] vs 0 [0x0]) Regname: i2c_reg_block.controller_events reset value: 0x0
UVM_INFO @ 42771966 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:559) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 1 failures:
6.i2c_host_stress_all_with_rand_reset.115128968745590723100489921489267870318321201246443908962195266665950688498937
Line 1553, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 5895228301 ps: (i2c_scoreboard.sv:559) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------