b33f0bcb4a| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | host_smoke | i2c_host_smoke | 1.681m | 8.008ms | 50 | 50 | 100.00 |
| V1 | target_smoke | i2c_target_smoke | 59.730s | 6.096ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | i2c_csr_hw_reset | 0.800s | 20.508us | 5 | 5 | 100.00 |
| V1 | csr_rw | i2c_csr_rw | 0.870s | 45.199us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | i2c_csr_bit_bash | 5.950s | 2.250ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | i2c_csr_aliasing | 2.280s | 110.584us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | i2c_csr_mem_rw_with_rand_reset | 1.470s | 30.701us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | i2c_csr_rw | 0.870s | 45.199us | 20 | 20 | 100.00 |
| i2c_csr_aliasing | 2.280s | 110.584us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 155 | 155 | 100.00 | |||
| V2 | host_error_intr | i2c_host_error_intr | 15.960s | 1.619ms | 49 | 50 | 98.00 |
| V2 | host_stress_all | i2c_host_stress_all | 47.499m | 51.287ms | 42 | 50 | 84.00 |
| V2 | host_maxperf | i2c_host_perf | 12.629m | 13.917ms | 47 | 50 | 94.00 |
| V2 | host_override | i2c_host_override | 0.760s | 28.570us | 50 | 50 | 100.00 |
| V2 | host_fifo_watermark | i2c_host_fifo_watermark | 6.474m | 34.631ms | 50 | 50 | 100.00 |
| V2 | host_fifo_overflow | i2c_host_fifo_overflow | 3.229m | 10.613ms | 50 | 50 | 100.00 |
| V2 | host_fifo_reset | i2c_host_fifo_reset_fmt | 1.420s | 720.545us | 50 | 50 | 100.00 |
| i2c_host_fifo_fmt_empty | 25.240s | 494.299us | 50 | 50 | 100.00 | ||
| i2c_host_fifo_reset_rx | 12.460s | 1.441ms | 50 | 50 | 100.00 | ||
| V2 | host_fifo_full | i2c_host_fifo_full | 3.763m | 6.033ms | 50 | 50 | 100.00 |
| V2 | host_timeout | i2c_host_stretch_timeout | 50.770s | 1.634ms | 50 | 50 | 100.00 |
| V2 | host_rx_oversample | i2c_host_rx_oversample | 0 | 0 | -- | ||
| V2 | i2c_host_mode_toggle | i2c_host_mode_toggle | 2.104m | 48.609ms | 49 | 50 | 98.00 |
| V2 | target_error_intr | i2c_target_unexp_stop | 24.569m | 50.000ms | 0 | 50 | 0.00 |
| V2 | target_glitch | i2c_target_glitch | 12.170s | 2.399ms | 2 | 2 | 100.00 |
| V2 | target_stress_all | i2c_target_stress_all | 21.569m | 113.141ms | 0 | 50 | 0.00 |
| V2 | target_maxperf | i2c_target_perf | 19.933m | 20.000ms | 0 | 50 | 0.00 |
| V2 | target_fifo_empty | i2c_target_stress_rd | 1.116m | 1.543ms | 50 | 50 | 100.00 |
| i2c_target_intr_smoke | 8.810s | 6.035ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_reset | i2c_target_fifo_reset_acq | 1.640s | 501.228us | 50 | 50 | 100.00 |
| i2c_target_fifo_reset_tx | 1.640s | 260.467us | 50 | 50 | 100.00 | ||
| V2 | target_fifo_full | i2c_target_stress_wr | 40.543m | 63.797ms | 50 | 50 | 100.00 |
| i2c_target_stress_rd | 1.116m | 1.543ms | 50 | 50 | 100.00 | ||
| i2c_target_intr_stress_wr | 7.103m | 21.298ms | 50 | 50 | 100.00 | ||
| V2 | target_timeout | i2c_target_timeout | 8.510s | 5.612ms | 50 | 50 | 100.00 |
| V2 | target_clock_stretch | i2c_target_stretch | 54.194m | 20.548ms | 46 | 50 | 92.00 |
| V2 | bad_address | i2c_target_bad_addr | 5.960s | 1.196ms | 50 | 50 | 100.00 |
| V2 | target_mode_glitch | i2c_target_hrst | 1.956m | 10.017ms | 38 | 50 | 76.00 |
| V2 | target_fifo_watermark | i2c_target_fifo_watermarks_acq | 3.520s | 1.113ms | 50 | 50 | 100.00 |
| i2c_target_fifo_watermarks_tx | 1.400s | 169.084us | 49 | 50 | 98.00 | ||
| V2 | host_mode_config_perf | i2c_host_perf | 12.629m | 13.917ms | 47 | 50 | 94.00 |
| i2c_host_perf_precise | 25.955m | 23.270ms | 50 | 50 | 100.00 | ||
| V2 | host_mode_clock_stretching | i2c_host_stretch_timeout | 50.770s | 1.634ms | 50 | 50 | 100.00 |
| V2 | target_mode_tx_stretch_ctrl | i2c_target_tx_stretch_ctrl | 3.490s | 264.024us | 0 | 50 | 0.00 |
| V2 | target_mode_nack_generation | target_mode_nack_generation | 0 | 0 | -- | ||
| V2 | host_mode_halt_on_nak | host_mode_halt_on_nak | 0 | 0 | -- | ||
| V2 | target_mode_n_byte_ack_control | target_mode_n_byte_ack_control | 0 | 0 | -- | ||
| V2 | target_mode_bus_timeout | target_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_timeout | controller_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_idle_delay | controller_mode_bus_idle_delay | 0 | 0 | -- | ||
| V2 | loopback_test | loopback_test | 0 | 0 | -- | ||
| V2 | multi_controller_clock_synchronization | multi_controller_clock_synchronization | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost_interference | multi_controller_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost | multi_controller_arbitration_lost | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost_interference | target_mode_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost | target_mode_arbitration_lost | 0 | 0 | -- | ||
| V2 | alert_test | i2c_alert_test | 0.680s | 66.768us | 50 | 50 | 100.00 |
| V2 | intr_test | i2c_intr_test | 0.740s | 22.155us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | i2c_tl_errors | 2.690s | 241.995us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | i2c_tl_errors | 2.690s | 241.995us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | i2c_csr_hw_reset | 0.800s | 20.508us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.870s | 45.199us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 2.280s | 110.584us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.240s | 71.649us | 18 | 20 | 90.00 | ||
| V2 | tl_d_partial_access | i2c_csr_hw_reset | 0.800s | 20.508us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.870s | 45.199us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 2.280s | 110.584us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.240s | 71.649us | 18 | 20 | 90.00 | ||
| V2 | TOTAL | 1360 | 1592 | 85.43 | |||
| V2S | tl_intg_err | i2c_tl_intg_err | 2.600s | 146.483us | 19 | 20 | 95.00 |
| i2c_sec_cm | 1.000s | 70.745us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | i2c_tl_intg_err | 2.600s | 146.483us | 19 | 20 | 95.00 |
| V2S | TOTAL | 24 | 25 | 96.00 | |||
| V3 | host_stress_all_with_rand_reset | i2c_host_stress_all_with_rand_reset | 7.079m | 15.060ms | 0 | 10 | 0.00 |
| V3 | target_stress_all_with_rand_reset | i2c_target_stress_all_with_rand_reset | 7.604m | 37.008ms | 0 | 10 | 0.00 |
| V3 | target_loopback | 0 | 0 | -- | |||
| V3 | TOTAL | 0 | 20 | 0.00 | |||
| Unmapped tests | i2c_host_may_nack | 27.510s | 719.985us | 50 | 50 | 100.00 | |
| TOTAL | 1589 | 1842 | 86.26 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 1 | 1 | 1 | 100.00 |
| V1 | 7 | 7 | 7 | 100.00 |
| V2 | 47 | 34 | 22 | 46.81 |
| V2S | 2 | 2 | 1 | 50.00 |
| V3 | 3 | 2 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 90.68 | 96.57 | 89.54 | 97.22 | 69.05 | 93.55 | 98.44 | 90.42 |
UVM_ERROR (i2c_scoreboard.sv:604) [scoreboard] Check failed obs.num_data == exp.num_data (* [*] vs * [*]) has 52 failures:
0.i2c_target_unexp_stop.105106819890269523472234631154195355451618920555488414533940789997073389418299
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 122433726 ps: (i2c_scoreboard.sv:604) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (0 [0x0] vs 6 [0x6])
UVM_INFO @ 122433726 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_unexp_stop.40806441516415230023768720288996461827402011435891907074093098479606755832702
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 1250351917 ps: (i2c_scoreboard.sv:604) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (0 [0x0] vs 27 [0x1b])
UVM_INFO @ 1250351917 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 19 more failures.
1.i2c_target_stress_all.108322487807805095312925654467295640676696105614500971658067280227773070415750
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 16407559829 ps: (i2c_scoreboard.sv:604) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (5 [0x5] vs 25 [0x19])
UVM_INFO @ 16407559829 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_stress_all.75637710831712199768900627633317063654585180631734717016234203022257754230347
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 6016582887 ps: (i2c_scoreboard.sv:604) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (10 [0xa] vs 4 [0x4])
UVM_INFO @ 6016582887 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 20 more failures.
1.i2c_target_stress_all_with_rand_reset.20506767111862305955215842704724987956328643330361209856532326567858512720754
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 43979499 ps: (i2c_scoreboard.sv:604) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (0 [0x0] vs 1 [0x1])
UVM_INFO @ 43979499 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.i2c_target_stress_all_with_rand_reset.11904683080156328374723903917972671959934387645407325766692074552231310961936
Line 266, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1208916232 ps: (i2c_scoreboard.sv:604) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (8 [0x8] vs 17 [0x11])
UVM_INFO @ 1208916232 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
3.i2c_target_hrst.43539660368125892779334945836712358215650861603196870941399192770252758363727
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_hrst/latest/run.log
UVM_ERROR @ 267746762 ps: (i2c_scoreboard.sv:604) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (6 [0x6] vs 21 [0x15])
UVM_INFO @ 267746762 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
19.i2c_target_hrst.80848606687307635324569360260839921580383606363335788562947781157019192819064
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/19.i2c_target_hrst/latest/run.log
UVM_ERROR @ 323010766 ps: (i2c_scoreboard.sv:604) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (5 [0x5] vs 21 [0x15])
UVM_INFO @ 323010766 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_FATAL (i2c_driver.sv:148) driver [driver] has 50 failures:
0.i2c_target_tx_stretch_ctrl.16391471058407923652376787296724549016394780502567247318453652399472736455020
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_tx_stretch_ctrl/latest/run.log
UVM_FATAL @ 209069059 ps: (i2c_driver.sv:148) uvm_test_top.env.m_i2c_agent.driver [uvm_test_top.env.m_i2c_agent.driver]
host_driver, received invalid request
UVM_INFO @ 209069059 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_tx_stretch_ctrl.20958489376785762526876448143543663160326650729886060624750363288896011644225
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_tx_stretch_ctrl/latest/run.log
UVM_FATAL @ 15401276 ps: (i2c_driver.sv:148) uvm_test_top.env.m_i2c_agent.driver [uvm_test_top.env.m_i2c_agent.driver]
host_driver, received invalid request
UVM_INFO @ 15401276 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 48 more failures.
UVM_FATAL (i2c_base_vseq.sv:1175) [stop_interrupt_handler] wait timeout occurred! has 40 failures:
0.i2c_target_stress_all.77089470862077403212520022290611894631290813712732552521411664103171746073934
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all/latest/run.log
UVM_FATAL @ 13402565829 ps: (i2c_base_vseq.sv:1175) [stop_interrupt_handler] wait timeout occurred!
UVM_INFO @ 13402565829 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.i2c_target_stress_all.35447397879209844895145942535110753874732792355583339158593809363559155471115
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_all/latest/run.log
UVM_FATAL @ 11989628968 ps: (i2c_base_vseq.sv:1175) [stop_interrupt_handler] wait timeout occurred!
UVM_INFO @ 11989628968 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
1.i2c_target_perf.103378591561940459479396177844871735699278955182692418381910639860231571964898
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_perf/latest/run.log
UVM_FATAL @ 11182322347 ps: (i2c_base_vseq.sv:1175) [stop_interrupt_handler] wait timeout occurred!
UVM_INFO @ 11182322347 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_perf.49252088879606140349605954464974104114401970197924706591684922481976128664726
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_perf/latest/run.log
UVM_FATAL @ 10964859489 ps: (i2c_base_vseq.sv:1175) [stop_interrupt_handler] wait timeout occurred!
UVM_INFO @ 10964859489 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 31 more failures.
Job i2c-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 34 failures:
0.i2c_target_stretch.106714548245039446085499147175772513331283833256455879020881087361706637353251
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stretch/latest/run.log
Job ID: smart:2bb7f8fc-b526-45e6-85b2-863c8f04b03e
13.i2c_target_stretch.61203623108418121588567849271676126861979612754370672068730577166081344900404
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/13.i2c_target_stretch/latest/run.log
Job ID: smart:c23c92ab-8e9d-411f-abbb-4e9d3432ae9f
... and 2 more failures.
1.i2c_host_stress_all_with_rand_reset.93520471796549931088055082261700818991873506361313136489644318633233197782312
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log
Job ID: smart:c5c8c8dc-fa54-40e5-832f-9dbbfff3c63a
6.i2c_host_stress_all_with_rand_reset.52989521449820820247684250712302472886379073953156386817547490368256532489462
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_host_stress_all_with_rand_reset/latest/run.log
Job ID: smart:baa81d0b-aa83-47f8-8a5c-5bd25aaf8695
... and 2 more failures.
4.i2c_host_perf.54964725105614706337046704525467564603520389966352981925728468519667289696041
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_host_perf/latest/run.log
Job ID: smart:d002793a-f3d9-49e7-a7bb-0560747900c9
8.i2c_host_perf.61720178448178517563628887571612403274571256823480832499718632843470702560998
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_host_perf/latest/run.log
Job ID: smart:91f59afa-1d74-465a-973f-5a34d78d3f34
... and 1 more failures.
4.i2c_target_unexp_stop.88369993826536013503853147080623728004415651831963113511674597698123110420909
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_unexp_stop/latest/run.log
Job ID: smart:5f62fab8-8fc6-4786-949a-0d79ff142131
5.i2c_target_unexp_stop.35551172151830790689149271960929473288180916248573984003065418324044475400690
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_unexp_stop/latest/run.log
Job ID: smart:3041e50e-57e0-4573-a1ec-60d109ce88d2
... and 7 more failures.
6.i2c_target_stress_all.92960582491515382429184536059711983681366933915766998283105603295368322923235
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_stress_all/latest/run.log
Job ID: smart:bdb770bf-c0eb-49a6-9010-a8d3ada4e6f4
9.i2c_target_stress_all.115547022541810371244276118544487157805681773478607247311966376658761609842652
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_target_stress_all/latest/run.log
Job ID: smart:d6440c44-4567-444b-b42b-3fc769e6a6d0
... and 8 more failures.
UVM_ERROR (i2c_scoreboard.sv:608) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 18 failures:
0.i2c_target_perf.98091861143354971107631543902588161932275812764611390500166346704117188939056
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_perf/latest/run.log
UVM_ERROR @ 44331791 ps: (i2c_scoreboard.sv:608) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 95 [0x5f])
UVM_INFO @ 44331791 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.i2c_target_perf.94403917128491698158795227168861589875906006000574168563910163549203415117901
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_perf/latest/run.log
UVM_ERROR @ 287617927 ps: (i2c_scoreboard.sv:608) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 186 [0xba])
UVM_INFO @ 287617927 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 11 more failures.
7.i2c_target_stress_all.35051674814478476024598166345883685659500723382513361260564886712092672983066
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 1087951418 ps: (i2c_scoreboard.sv:608) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (240 [0xf0] vs 33 [0x21])
UVM_INFO @ 1087951418 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
20.i2c_target_stress_all.61049221390045930163979046739819071012568187671308607854587338195891342664813
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/20.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 34469948 ps: (i2c_scoreboard.sv:608) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 117 [0x75])
UVM_INFO @ 34469948 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_ERROR (i2c_base_vseq.sv:992) virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout has 13 failures:
3.i2c_target_stress_all.108346717956981516350589277951257973801384254015936711818618926091795440312180
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 1429618666 ps: (i2c_base_vseq.sv:992) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
UVM_INFO @ 1429618666 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
15.i2c_target_stress_all.26705879586366388687444456038889445279616861381855354303323908715249365197679
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/15.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 1563753878 ps: (i2c_base_vseq.sv:992) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
UVM_INFO @ 1563753878 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
7.i2c_target_unexp_stop.12490737259416720140633905498054637369832382477534276796938129514835327353627
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 2986548253 ps: (i2c_base_vseq.sv:992) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
UVM_INFO @ 2986548253 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
12.i2c_target_unexp_stop.72311405276218078034055166884136470657484230512001365474867185710615279935878
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/12.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 1596368738 ps: (i2c_base_vseq.sv:992) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
UVM_INFO @ 1596368738 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 12 failures:
10.i2c_target_unexp_stop.15466706286928535966393318983452297977722785852929276170579147077577034444894
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/10.i2c_target_unexp_stop/latest/run.log
UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
19.i2c_target_unexp_stop.35690235467242549368370587198857613721358950538917931206501210480040659242909
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/19.i2c_target_unexp_stop/latest/run.log
UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
28.i2c_target_perf.28980802900835680588970817705382343857801770745562162703507826819715297497998
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/28.i2c_target_perf/latest/run.log
UVM_FATAL @ 20000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 20000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 20000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
32.i2c_target_perf.63488090863996133901030849745932609744387201175677335265320728075814257688606
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/32.i2c_target_perf/latest/run.log
UVM_FATAL @ 20000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 20000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 20000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (cip_base_vseq.sv:828) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 9 failures:
0.i2c_host_stress_all_with_rand_reset.94265763908623459489267984037217958969347694294112305085882552942704012326283
Line 3653, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 16673548940 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 16673548940 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_host_stress_all_with_rand_reset.24324367918280990592840778181614104201077424778562677118741683400205480553348
Line 3527, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2895947745 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2895947745 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
2.i2c_target_stress_all_with_rand_reset.47342469759520638530418475581912589169523698702836375554404955419369465791553
Line 347, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 15105957417 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 15105957417 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.i2c_target_stress_all_with_rand_reset.24078121134336016385458814315012709049370719361671526578923578460836351809582
Line 379, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 37007556993 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 37007556993 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (i2c_scoreboard.sv:559) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite has 5 failures:
0.i2c_host_stress_all.22891193548160384870598984975298233414563310723035852814246874143354674876201
Line 6676, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 50440949187 ps: (i2c_scoreboard.sv:559) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite
--> EXP:
-----------------------------------------------------
Name Type Size Value
-----------------------------------------------------
2.i2c_host_stress_all.102718527206897132816169194181655315659140326767577090165715342912629820382748
Line 10896, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 41093553810 ps: (i2c_scoreboard.sv:559) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite
--> EXP:
-----------------------------------------------------
Name Type Size Value
-----------------------------------------------------
... and 2 more failures.
31.i2c_host_error_intr.31395920906184588227141846360736496476866290225240697667023097796419425658542
Line 686, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/31.i2c_host_error_intr/latest/run.log
UVM_ERROR @ 174622499 ps: (i2c_scoreboard.sv:559) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite
--> EXP:
-----------------------------------------------------
Name Type Size Value
-----------------------------------------------------
UVM_ERROR (i2c_scoreboard.sv:584) [scoreboard] Check failed obs.start == exp.start (* [*] vs * [*]) has 3 failures:
16.i2c_target_hrst.108647064776881790594749559319809945578464427552173670662825462616280857343520
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/16.i2c_target_hrst/latest/run.log
UVM_ERROR @ 7770940 ps: (i2c_scoreboard.sv:584) [uvm_test_top.env.scoreboard] Check failed obs.start == exp.start (1 [0x1] vs 0 [0x0])
UVM_INFO @ 7770940 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
21.i2c_target_hrst.6966884211065450854407784202489819248423140145041598019079373612716805213538
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/21.i2c_target_hrst/latest/run.log
UVM_ERROR @ 66977404 ps: (i2c_scoreboard.sv:584) [uvm_test_top.env.scoreboard] Check failed obs.start == exp.start (1 [0x1] vs 0 [0x0])
UVM_INFO @ 66977404 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL (i2c_driver.sv:234) [i2c_drv_scl] wait timeout occurred! has 3 failures:
18.i2c_target_stress_all.49482069029102484095199396771058994055027241412890872718900414373879882480760
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/18.i2c_target_stress_all/latest/run.log
UVM_FATAL @ 116751483667 ps: (i2c_driver.sv:234) [i2c_drv_scl] wait timeout occurred!
UVM_INFO @ 116751483667 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
41.i2c_target_stress_all.44732678746433607082974691164619107148068317936934795130212929598761323331456
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/41.i2c_target_stress_all/latest/run.log
UVM_FATAL @ 113140576133 ps: (i2c_driver.sv:234) [i2c_drv_scl] wait timeout occurred!
UVM_INFO @ 113140576133 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (i2c_scoreboard.sv:587) [scoreboard] Check failed obs.wdata == exp.wdata (* [*] vs * [*]) has 2 failures:
Test i2c_target_stress_all_with_rand_reset has 1 failures.
4.i2c_target_stress_all_with_rand_reset.93152219630050915022230512998050967246410204504199035522486264489832105165333
Line 370, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 18185219562 ps: (i2c_scoreboard.sv:587) [uvm_test_top.env.scoreboard] Check failed obs.wdata == exp.wdata (84 [0x54] vs 46 [0x2e])
UVM_INFO @ 18185219562 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test i2c_target_hrst has 1 failures.
35.i2c_target_hrst.93400572919577652294032844814215522672870212169354917217812790943868597443149
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/35.i2c_target_hrst/latest/run.log
UVM_ERROR @ 4034550 ps: (i2c_scoreboard.sv:587) [uvm_test_top.env.scoreboard] Check failed obs.wdata == exp.wdata (0 [0x0] vs 31 [0x1f])
UVM_INFO @ 4034550 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 2 failures:
8.i2c_target_hrst.70304802490046713788303770961718112445149118703546625073744628672705553340439
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10008337571 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10008337571 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
48.i2c_target_hrst.86142894739757040565976161710561339946407996264505846855923647977121321478797
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/48.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10050687808 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10050687808 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:193) [i2c_target_hrst_vseq] Timed-out waiting for target_mode_wr_exp_fifo to become empty. has 2 failures:
25.i2c_target_hrst.7923363899967883342173864045503918578974354652015393720673705312309571936457
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/25.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10230163302 ps: (i2c_target_hrst_vseq.sv:193) [uvm_test_top.env.virtual_sequencer.i2c_target_hrst_vseq] Timed-out waiting for target_mode_wr_exp_fifo to become empty.
UVM_INFO @ 10230163302 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
43.i2c_target_hrst.100754398790883780437590344168263897137195627622309571816670650607946002886473
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/43.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10016868866 ps: (i2c_target_hrst_vseq.sv:193) [uvm_test_top.env.virtual_sequencer.i2c_target_hrst_vseq] Timed-out waiting for target_mode_wr_exp_fifo to become empty.
UVM_INFO @ 10016868866 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_smoke_vseq.sv:99) [target_smoke_vseq] wait timeout occurred! has 1 failures:
0.i2c_target_stress_all_with_rand_reset.94567435197483888931588924080981525230119306935495601537989827438351469629604
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 10035599527 ps: (i2c_target_smoke_vseq.sv:99) [target_smoke_vseq] wait timeout occurred!
UVM_INFO @ 10035599527 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:503) [i2c_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) has 1 failures:
3.i2c_same_csr_outstanding.65689954510900290721282872953015660037527433270077883288962745332274570937343
Line 249, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_same_csr_outstanding/latest/run.log
UVM_ERROR @ 33187566 ps: (cip_base_vseq.sv:503) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed data & ~ro_mask == 0 (64 [0x40] vs 0 [0x0])
UVM_INFO @ 33187566 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.controller_events.arbitration_lost reset value: * has 1 failures:
7.i2c_tl_intg_err.22579918303606382406531535585302927734455952954908096784263227324212983854547
Line 271, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_tl_intg_err/latest/run.log
UVM_ERROR @ 18994431 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.controller_events.arbitration_lost reset value: 0x0
UVM_INFO @ 18994431 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:250) [i2c_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch has 1 failures:
8.i2c_same_csr_outstanding.105538942250768026801092989429132210901125747612170146339425036117206875252423
Line 249, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_same_csr_outstanding/latest/run.log
UVM_ERROR @ 50710426 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed masked_data == exp_data (8 [0x8] vs 0 [0x0]) addr 0x7dc9f578 read out mismatch
UVM_INFO @ 50710426 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Error-[CNST-CIF] Constraints inconsistency failure has 1 failures:
11.i2c_target_fifo_watermarks_tx.71154112598131769846420035809224784742879092722304231970640703004167352376988
Line 292, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/11.i2c_target_fifo_watermarks_tx/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 723
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 1 failures:
33.i2c_target_unexp_stop.69092899702532566294784719577401517385545166972860179994976934737245397161008
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/33.i2c_target_unexp_stop/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 967206734 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 967206734 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending 'scl_o' has 1 failures:
47.i2c_host_mode_toggle.12855830190262040070233457166641956754932383066004502670044630177120568124067
Line 255, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/47.i2c_host_mode_toggle/latest/run.log
Offending 'scl_o'
UVM_ERROR @ 48013689 ps: (i2c_controller_fsm.sv:976) [ASSERT FAILED] SclOutputGlitch_A
UVM_INFO @ 48013689 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_monitor.sv:587) monitor [monitor] ack_stop detected has 1 failures:
48.i2c_target_perf.25683139552381504292603668164832688249808557964503618925642356172850634653022
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/48.i2c_target_perf/latest/run.log
UVM_ERROR @ 568056022 ps: (i2c_monitor.sv:587) uvm_test_top.env.m_i2c_agent.monitor [uvm_test_top.env.m_i2c_agent.monitor] ack_stop detected
UVM_INFO @ 568056022 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---