I2C Simulation Results

Saturday June 29 2024 23:02:35 UTC

GitHub Revision: b33f0bcb4a

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 9407974028806500767465982655187958599819354731549473124644158596869486113221

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 host_smoke i2c_host_smoke 1.929m 2.385ms 50 50 100.00
V1 target_smoke i2c_target_smoke 1.069m 6.412ms 50 50 100.00
V1 csr_hw_reset i2c_csr_hw_reset 0.850s 22.999us 5 5 100.00
V1 csr_rw i2c_csr_rw 0.830s 72.822us 20 20 100.00
V1 csr_bit_bash i2c_csr_bit_bash 6.880s 663.309us 3 5 60.00
V1 csr_aliasing i2c_csr_aliasing 2.210s 353.161us 5 5 100.00
V1 csr_mem_rw_with_rand_reset i2c_csr_mem_rw_with_rand_reset 1.500s 33.212us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr i2c_csr_rw 0.830s 72.822us 20 20 100.00
i2c_csr_aliasing 2.210s 353.161us 5 5 100.00
V1 TOTAL 153 155 98.71
V2 host_error_intr i2c_host_error_intr 13.120s 313.990us 50 50 100.00
V2 host_stress_all i2c_host_stress_all 58.009m 20.617ms 41 50 82.00
V2 host_maxperf i2c_host_perf 27.105m 24.440ms 48 50 96.00
V2 host_override i2c_host_override 0.730s 89.784us 50 50 100.00
V2 host_fifo_watermark i2c_host_fifo_watermark 6.023m 7.567ms 50 50 100.00
V2 host_fifo_overflow i2c_host_fifo_overflow 3.342m 10.368ms 50 50 100.00
V2 host_fifo_reset i2c_host_fifo_reset_fmt 1.270s 195.847us 50 50 100.00
i2c_host_fifo_fmt_empty 23.130s 1.099ms 50 50 100.00
i2c_host_fifo_reset_rx 14.070s 523.093us 50 50 100.00
V2 host_fifo_full i2c_host_fifo_full 4.086m 4.011ms 50 50 100.00
V2 host_timeout i2c_host_stretch_timeout 49.890s 4.737ms 50 50 100.00
V2 host_rx_oversample i2c_host_rx_oversample 0 0 --
V2 i2c_host_mode_toggle i2c_host_mode_toggle 1.874m 2.631ms 50 50 100.00
V2 target_error_intr i2c_target_unexp_stop 39.216m 50.000ms 0 50 0.00
V2 target_glitch i2c_target_glitch 11.120s 4.052ms 2 2 100.00
V2 target_stress_all i2c_target_stress_all 29.533m 100.383ms 0 50 0.00
V2 target_maxperf i2c_target_perf 27.400m 20.000ms 0 50 0.00
V2 target_fifo_empty i2c_target_stress_rd 1.300m 3.490ms 50 50 100.00
i2c_target_intr_smoke 8.690s 6.511ms 50 50 100.00
V2 target_fifo_reset i2c_target_fifo_reset_acq 1.620s 303.478us 50 50 100.00
i2c_target_fifo_reset_tx 1.730s 295.925us 50 50 100.00
V2 target_fifo_full i2c_target_stress_wr 38.248m 68.016ms 50 50 100.00
i2c_target_stress_rd 1.300m 3.490ms 50 50 100.00
i2c_target_intr_stress_wr 10.202m 25.887ms 50 50 100.00
V2 target_timeout i2c_target_timeout 8.410s 3.457ms 50 50 100.00
V2 target_clock_stretch i2c_target_stretch 47.536m 34.608ms 48 50 96.00
V2 bad_address i2c_target_bad_addr 5.770s 1.330ms 50 50 100.00
V2 target_mode_glitch i2c_target_hrst 2.188m 10.052ms 37 50 74.00
V2 target_fifo_watermark i2c_target_fifo_watermarks_acq 3.050s 607.834us 50 50 100.00
i2c_target_fifo_watermarks_tx 1.390s 944.489us 50 50 100.00
V2 host_mode_config_perf i2c_host_perf 27.105m 24.440ms 48 50 96.00
i2c_host_perf_precise 28.456m 23.194ms 50 50 100.00
V2 host_mode_clock_stretching i2c_host_stretch_timeout 49.890s 4.737ms 50 50 100.00
V2 target_mode_tx_stretch_ctrl i2c_target_tx_stretch_ctrl 4.110s 301.468us 0 50 0.00
V2 target_mode_nack_generation target_mode_nack_generation 0 0 --
V2 host_mode_halt_on_nak host_mode_halt_on_nak 0 0 --
V2 target_mode_n_byte_ack_control target_mode_n_byte_ack_control 0 0 --
V2 target_mode_bus_timeout target_mode_bus_timeout 0 0 --
V2 controller_mode_bus_timeout controller_mode_bus_timeout 0 0 --
V2 controller_mode_bus_idle_delay controller_mode_bus_idle_delay 0 0 --
V2 loopback_test loopback_test 0 0 --
V2 multi_controller_clock_synchronization multi_controller_clock_synchronization 0 0 --
V2 multi_controller_arbitration_lost_interference multi_controller_arbitration_lost_interference 0 0 --
V2 multi_controller_arbitration_lost multi_controller_arbitration_lost 0 0 --
V2 target_mode_arbitration_lost_interference target_mode_arbitration_lost_interference 0 0 --
V2 target_mode_arbitration_lost target_mode_arbitration_lost 0 0 --
V2 alert_test i2c_alert_test 0.710s 51.181us 50 50 100.00
V2 intr_test i2c_intr_test 0.720s 19.931us 50 50 100.00
V2 tl_d_oob_addr_access i2c_tl_errors 2.370s 377.328us 20 20 100.00
V2 tl_d_illegal_access i2c_tl_errors 2.370s 377.328us 20 20 100.00
V2 tl_d_outstanding_access i2c_csr_hw_reset 0.850s 22.999us 5 5 100.00
i2c_csr_rw 0.830s 72.822us 20 20 100.00
i2c_csr_aliasing 2.210s 353.161us 5 5 100.00
i2c_same_csr_outstanding 1.310s 59.371us 19 20 95.00
V2 tl_d_partial_access i2c_csr_hw_reset 0.850s 22.999us 5 5 100.00
i2c_csr_rw 0.830s 72.822us 20 20 100.00
i2c_csr_aliasing 2.210s 353.161us 5 5 100.00
i2c_same_csr_outstanding 1.310s 59.371us 19 20 95.00
V2 TOTAL 1365 1592 85.74
V2S tl_intg_err i2c_tl_intg_err 2.680s 572.922us 19 20 95.00
i2c_sec_cm 1.320s 328.078us 5 5 100.00
V2S sec_cm_bus_integrity i2c_tl_intg_err 2.680s 572.922us 19 20 95.00
V2S TOTAL 24 25 96.00
V3 host_stress_all_with_rand_reset i2c_host_stress_all_with_rand_reset 8.622m 66.848ms 0 10 0.00
V3 target_stress_all_with_rand_reset i2c_target_stress_all_with_rand_reset 5.824m 10.050ms 0 10 0.00
V3 target_loopback 0 0 --
V3 TOTAL 0 20 0.00
Unmapped tests i2c_host_may_nack 24.970s 2.333ms 50 50 100.00
TOTAL 1592 1842 86.43

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 1 100.00
V1 7 7 6 85.71
V2 47 34 25 53.19
V2S 2 2 1 50.00
V3 3 2 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
91.09 96.63 89.84 97.22 70.83 93.62 98.44 91.05

Failure Buckets

Past Results