b33f0bcb4a| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | host_smoke | i2c_host_smoke | 1.929m | 2.385ms | 50 | 50 | 100.00 |
| V1 | target_smoke | i2c_target_smoke | 1.069m | 6.412ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | i2c_csr_hw_reset | 0.850s | 22.999us | 5 | 5 | 100.00 |
| V1 | csr_rw | i2c_csr_rw | 0.830s | 72.822us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | i2c_csr_bit_bash | 6.880s | 663.309us | 3 | 5 | 60.00 |
| V1 | csr_aliasing | i2c_csr_aliasing | 2.210s | 353.161us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | i2c_csr_mem_rw_with_rand_reset | 1.500s | 33.212us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | i2c_csr_rw | 0.830s | 72.822us | 20 | 20 | 100.00 |
| i2c_csr_aliasing | 2.210s | 353.161us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 153 | 155 | 98.71 | |||
| V2 | host_error_intr | i2c_host_error_intr | 13.120s | 313.990us | 50 | 50 | 100.00 |
| V2 | host_stress_all | i2c_host_stress_all | 58.009m | 20.617ms | 41 | 50 | 82.00 |
| V2 | host_maxperf | i2c_host_perf | 27.105m | 24.440ms | 48 | 50 | 96.00 |
| V2 | host_override | i2c_host_override | 0.730s | 89.784us | 50 | 50 | 100.00 |
| V2 | host_fifo_watermark | i2c_host_fifo_watermark | 6.023m | 7.567ms | 50 | 50 | 100.00 |
| V2 | host_fifo_overflow | i2c_host_fifo_overflow | 3.342m | 10.368ms | 50 | 50 | 100.00 |
| V2 | host_fifo_reset | i2c_host_fifo_reset_fmt | 1.270s | 195.847us | 50 | 50 | 100.00 |
| i2c_host_fifo_fmt_empty | 23.130s | 1.099ms | 50 | 50 | 100.00 | ||
| i2c_host_fifo_reset_rx | 14.070s | 523.093us | 50 | 50 | 100.00 | ||
| V2 | host_fifo_full | i2c_host_fifo_full | 4.086m | 4.011ms | 50 | 50 | 100.00 |
| V2 | host_timeout | i2c_host_stretch_timeout | 49.890s | 4.737ms | 50 | 50 | 100.00 |
| V2 | host_rx_oversample | i2c_host_rx_oversample | 0 | 0 | -- | ||
| V2 | i2c_host_mode_toggle | i2c_host_mode_toggle | 1.874m | 2.631ms | 50 | 50 | 100.00 |
| V2 | target_error_intr | i2c_target_unexp_stop | 39.216m | 50.000ms | 0 | 50 | 0.00 |
| V2 | target_glitch | i2c_target_glitch | 11.120s | 4.052ms | 2 | 2 | 100.00 |
| V2 | target_stress_all | i2c_target_stress_all | 29.533m | 100.383ms | 0 | 50 | 0.00 |
| V2 | target_maxperf | i2c_target_perf | 27.400m | 20.000ms | 0 | 50 | 0.00 |
| V2 | target_fifo_empty | i2c_target_stress_rd | 1.300m | 3.490ms | 50 | 50 | 100.00 |
| i2c_target_intr_smoke | 8.690s | 6.511ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_reset | i2c_target_fifo_reset_acq | 1.620s | 303.478us | 50 | 50 | 100.00 |
| i2c_target_fifo_reset_tx | 1.730s | 295.925us | 50 | 50 | 100.00 | ||
| V2 | target_fifo_full | i2c_target_stress_wr | 38.248m | 68.016ms | 50 | 50 | 100.00 |
| i2c_target_stress_rd | 1.300m | 3.490ms | 50 | 50 | 100.00 | ||
| i2c_target_intr_stress_wr | 10.202m | 25.887ms | 50 | 50 | 100.00 | ||
| V2 | target_timeout | i2c_target_timeout | 8.410s | 3.457ms | 50 | 50 | 100.00 |
| V2 | target_clock_stretch | i2c_target_stretch | 47.536m | 34.608ms | 48 | 50 | 96.00 |
| V2 | bad_address | i2c_target_bad_addr | 5.770s | 1.330ms | 50 | 50 | 100.00 |
| V2 | target_mode_glitch | i2c_target_hrst | 2.188m | 10.052ms | 37 | 50 | 74.00 |
| V2 | target_fifo_watermark | i2c_target_fifo_watermarks_acq | 3.050s | 607.834us | 50 | 50 | 100.00 |
| i2c_target_fifo_watermarks_tx | 1.390s | 944.489us | 50 | 50 | 100.00 | ||
| V2 | host_mode_config_perf | i2c_host_perf | 27.105m | 24.440ms | 48 | 50 | 96.00 |
| i2c_host_perf_precise | 28.456m | 23.194ms | 50 | 50 | 100.00 | ||
| V2 | host_mode_clock_stretching | i2c_host_stretch_timeout | 49.890s | 4.737ms | 50 | 50 | 100.00 |
| V2 | target_mode_tx_stretch_ctrl | i2c_target_tx_stretch_ctrl | 4.110s | 301.468us | 0 | 50 | 0.00 |
| V2 | target_mode_nack_generation | target_mode_nack_generation | 0 | 0 | -- | ||
| V2 | host_mode_halt_on_nak | host_mode_halt_on_nak | 0 | 0 | -- | ||
| V2 | target_mode_n_byte_ack_control | target_mode_n_byte_ack_control | 0 | 0 | -- | ||
| V2 | target_mode_bus_timeout | target_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_timeout | controller_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_idle_delay | controller_mode_bus_idle_delay | 0 | 0 | -- | ||
| V2 | loopback_test | loopback_test | 0 | 0 | -- | ||
| V2 | multi_controller_clock_synchronization | multi_controller_clock_synchronization | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost_interference | multi_controller_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost | multi_controller_arbitration_lost | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost_interference | target_mode_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost | target_mode_arbitration_lost | 0 | 0 | -- | ||
| V2 | alert_test | i2c_alert_test | 0.710s | 51.181us | 50 | 50 | 100.00 |
| V2 | intr_test | i2c_intr_test | 0.720s | 19.931us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | i2c_tl_errors | 2.370s | 377.328us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | i2c_tl_errors | 2.370s | 377.328us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | i2c_csr_hw_reset | 0.850s | 22.999us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.830s | 72.822us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 2.210s | 353.161us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.310s | 59.371us | 19 | 20 | 95.00 | ||
| V2 | tl_d_partial_access | i2c_csr_hw_reset | 0.850s | 22.999us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.830s | 72.822us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 2.210s | 353.161us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.310s | 59.371us | 19 | 20 | 95.00 | ||
| V2 | TOTAL | 1365 | 1592 | 85.74 | |||
| V2S | tl_intg_err | i2c_tl_intg_err | 2.680s | 572.922us | 19 | 20 | 95.00 |
| i2c_sec_cm | 1.320s | 328.078us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | i2c_tl_intg_err | 2.680s | 572.922us | 19 | 20 | 95.00 |
| V2S | TOTAL | 24 | 25 | 96.00 | |||
| V3 | host_stress_all_with_rand_reset | i2c_host_stress_all_with_rand_reset | 8.622m | 66.848ms | 0 | 10 | 0.00 |
| V3 | target_stress_all_with_rand_reset | i2c_target_stress_all_with_rand_reset | 5.824m | 10.050ms | 0 | 10 | 0.00 |
| V3 | target_loopback | 0 | 0 | -- | |||
| V3 | TOTAL | 0 | 20 | 0.00 | |||
| Unmapped tests | i2c_host_may_nack | 24.970s | 2.333ms | 50 | 50 | 100.00 | |
| TOTAL | 1592 | 1842 | 86.43 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 1 | 1 | 1 | 100.00 |
| V1 | 7 | 7 | 6 | 85.71 |
| V2 | 47 | 34 | 25 | 53.19 |
| V2S | 2 | 2 | 1 | 50.00 |
| V3 | 3 | 2 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 91.09 | 96.63 | 89.84 | 97.22 | 70.83 | 93.62 | 98.44 | 91.05 |
UVM_ERROR (i2c_scoreboard.sv:604) [scoreboard] Check failed obs.num_data == exp.num_data (* [*] vs * [*]) has 59 failures:
0.i2c_target_unexp_stop.39930991375031254525586170210597136872165748507510146947408017324839091474991
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 13872055 ps: (i2c_scoreboard.sv:604) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (0 [0x0] vs 5 [0x5])
UVM_INFO @ 13872055 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_unexp_stop.10905770178221449449318685362509280926822907615645756452786177609202432697140
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 56829889 ps: (i2c_scoreboard.sv:604) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (0 [0x0] vs 15 [0xf])
UVM_INFO @ 56829889 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 17 more failures.
0.i2c_target_stress_all.109813369497174091645889391154360743281845580628929871762611913099485265578713
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 167095899 ps: (i2c_scoreboard.sv:604) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (0 [0x0] vs 7 [0x7])
UVM_INFO @ 167095899 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_stress_all.66866195017007317350668606068847752333246028015909327529807109159917917829743
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 71086567 ps: (i2c_scoreboard.sv:604) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (0 [0x0] vs 11 [0xb])
UVM_INFO @ 71086567 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 29 more failures.
2.i2c_target_hrst.65274893163867520002751654892894762544729323234794492226218789550622281088049
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_hrst/latest/run.log
UVM_ERROR @ 28966782 ps: (i2c_scoreboard.sv:604) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (13 [0xd] vs 1 [0x1])
UVM_INFO @ 28966782 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
17.i2c_target_hrst.7760979942466925663401159274484162634198351696263076692678462614398571100323
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/17.i2c_target_hrst/latest/run.log
UVM_ERROR @ 261092692 ps: (i2c_scoreboard.sv:604) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (2 [0x2] vs 7 [0x7])
UVM_INFO @ 261092692 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
3.i2c_target_stress_all_with_rand_reset.46506364938487975359883873775920170812828837488482924158990962422557849954436
Line 328, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 9725403391 ps: (i2c_scoreboard.sv:604) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (18 [0x12] vs 5 [0x5])
UVM_INFO @ 9725403391 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.i2c_target_stress_all_with_rand_reset.103163574594777518944600636073018380668391751032017364699476397200826000471829
Line 266, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1467946171 ps: (i2c_scoreboard.sv:604) [uvm_test_top.env.scoreboard] Check failed obs.num_data == exp.num_data (4 [0x4] vs 6 [0x6])
UVM_INFO @ 1467946171 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL (i2c_driver.sv:148) driver [driver] has 50 failures:
0.i2c_target_tx_stretch_ctrl.47112567100593044416601460575664594981138616346669714824165602860639773882057
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_tx_stretch_ctrl/latest/run.log
UVM_FATAL @ 301468076 ps: (i2c_driver.sv:148) uvm_test_top.env.m_i2c_agent.driver [uvm_test_top.env.m_i2c_agent.driver]
host_driver, received invalid request
UVM_INFO @ 301468076 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_tx_stretch_ctrl.9643740527562596418228199014631518919526250021192062892946524920605871036953
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_tx_stretch_ctrl/latest/run.log
UVM_FATAL @ 6958898 ps: (i2c_driver.sv:148) uvm_test_top.env.m_i2c_agent.driver [uvm_test_top.env.m_i2c_agent.driver]
host_driver, received invalid request
UVM_INFO @ 6958898 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 48 more failures.
UVM_FATAL (i2c_base_vseq.sv:1175) [stop_interrupt_handler] wait timeout occurred! has 45 failures:
0.i2c_target_perf.100707129401637588938470785506867492700280651786478965186679656167822534500111
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_perf/latest/run.log
UVM_FATAL @ 10864896139 ps: (i2c_base_vseq.sv:1175) [stop_interrupt_handler] wait timeout occurred!
UVM_INFO @ 10864896139 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_perf.68030677712595870938225581339952646700816540176263222134560498306094416255070
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_perf/latest/run.log
UVM_FATAL @ 10910062338 ps: (i2c_base_vseq.sv:1175) [stop_interrupt_handler] wait timeout occurred!
UVM_INFO @ 10910062338 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 33 more failures.
4.i2c_target_stress_all.92068607929935727189516761234463030567007625322386150325025969867015276166371
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_all/latest/run.log
UVM_FATAL @ 15323342622 ps: (i2c_base_vseq.sv:1175) [stop_interrupt_handler] wait timeout occurred!
UVM_INFO @ 15323342622 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.i2c_target_stress_all.34222058373821782465460338715193137570881223726337958380060372604566661100962
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_stress_all/latest/run.log
UVM_FATAL @ 12558500042 ps: (i2c_base_vseq.sv:1175) [stop_interrupt_handler] wait timeout occurred!
UVM_INFO @ 12558500042 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 25 failures:
1.i2c_target_unexp_stop.48409052213457079759242169964754273380229894980068614831145309959840457922126
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.i2c_target_unexp_stop.50428555814604897214129877027642455880681828997206916600848547957309105882742
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_unexp_stop/latest/run.log
UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 18 more failures.
10.i2c_target_perf.26474899483921368390798829614005893648688059663706050874986011211229014300493
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/10.i2c_target_perf/latest/run.log
UVM_FATAL @ 20000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 20000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 20000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
20.i2c_target_perf.98548270476753557090759705629619236021151664958108149611752394480871273952995
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/20.i2c_target_perf/latest/run.log
UVM_FATAL @ 20000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 20000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 20000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
Job i2c-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 20 failures:
Test i2c_host_stress_all has 3 failures.
0.i2c_host_stress_all.7969629425582221797662276616805654962040652096000196691546784606889031355149
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log
Job ID: smart:9c9d2676-7ec0-42a9-b00b-e3135d16aba7
23.i2c_host_stress_all.40555809426620242753469826978697343270108265174627934923656503262542506547963
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/23.i2c_host_stress_all/latest/run.log
Job ID: smart:f0effcb9-18d1-4d4c-91a6-79a1ef5d2250
... and 1 more failures.
Test i2c_host_stress_all_with_rand_reset has 2 failures.
1.i2c_host_stress_all_with_rand_reset.111837273174939492582431220732591308464836354645761622961616184428720818802299
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log
Job ID: smart:a64e0871-c968-4814-963d-a54f8ea81b04
4.i2c_host_stress_all_with_rand_reset.78009277532930770328010032383306807722650978587633889112944434979567188536795
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_host_stress_all_with_rand_reset/latest/run.log
Job ID: smart:c47b2420-7a91-4d34-9272-23139805297b
Test i2c_target_stress_all has 6 failures.
5.i2c_target_stress_all.17719390836823592928726994976606770561840052743990433232049505590725563368702
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_stress_all/latest/run.log
Job ID: smart:a91a85ce-3da3-4314-9c1d-c326de8be44e
8.i2c_target_stress_all.33123225576298016574876121323307811791092733800991617868001573755698291729043
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_target_stress_all/latest/run.log
Job ID: smart:926c514e-5de9-4148-b7c2-8fb3f8568a81
... and 4 more failures.
Test i2c_target_unexp_stop has 5 failures.
10.i2c_target_unexp_stop.51245648504876482189038447121928787121282460178761162707459086873774618598851
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/10.i2c_target_unexp_stop/latest/run.log
Job ID: smart:232771c8-cca6-4d3c-9c9c-98a9199092ad
26.i2c_target_unexp_stop.6351691855699053590402937359571059699994416222383351748091511604467138736062
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/26.i2c_target_unexp_stop/latest/run.log
Job ID: smart:50e8dfec-a6bf-4bc6-8ed6-118c83c36e2a
... and 3 more failures.
Test i2c_target_stretch has 2 failures.
13.i2c_target_stretch.20297586805626045587050510970006956189217938230346231079577384552451447668096
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/13.i2c_target_stretch/latest/run.log
Job ID: smart:bbac04d4-a51c-48c9-9d2b-bc3a231a015f
17.i2c_target_stretch.48711805363212403159504682000411916860234342537978425394616733762269200959816
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/17.i2c_target_stretch/latest/run.log
Job ID: smart:19e4f8cb-de42-45af-9ab5-abf5b7b988eb
... and 1 more tests.
UVM_ERROR (i2c_scoreboard.sv:608) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 12 failures:
Test i2c_target_stress_all_with_rand_reset has 1 failures.
0.i2c_target_stress_all_with_rand_reset.77669053116193667061067993296869681258010514205938381769456916360435677372335
Line 314, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 5124190329 ps: (i2c_scoreboard.sv:608) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (170 [0xaa] vs 98 [0x62])
UVM_INFO @ 5124190329 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test i2c_target_perf has 10 failures.
2.i2c_target_perf.115375234430686679794804220242207764899932743719844649232464599690495529759372
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_perf/latest/run.log
UVM_ERROR @ 13158944 ps: (i2c_scoreboard.sv:608) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 206 [0xce])
UVM_INFO @ 13158944 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.i2c_target_perf.49804056227886019490834899666889886754244981452290291440276548959082457299833
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_perf/latest/run.log
UVM_ERROR @ 8546325 ps: (i2c_scoreboard.sv:608) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 58 [0x3a])
UVM_INFO @ 8546325 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
Test i2c_target_stress_all has 1 failures.
11.i2c_target_stress_all.46702459809062300500450475176747514201606452945557909202455468523689851210038
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/11.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 2450388069 ps: (i2c_scoreboard.sv:608) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 10 [0xa])
UVM_INFO @ 2450388069 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:828) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 10 failures:
0.i2c_host_stress_all_with_rand_reset.49777406210081224497514462815806567174924044889086025287200370597375441331528
Line 5120, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 66847908098 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 66847908098 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.i2c_host_stress_all_with_rand_reset.97266997841344865047292700814425799362175616863823014590509881172475543016386
Line 267, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 964303519 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 964303519 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
2.i2c_target_stress_all_with_rand_reset.69639234786082583169709007295740053922353523809157444811388934538195032703084
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 993765737 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 993765737 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.i2c_target_stress_all_with_rand_reset.33224283933089191056790750862449035814412807876519062177907514301709040133016
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 8365317988 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 8365317988 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (i2c_scoreboard.sv:559) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite has 5 failures:
1.i2c_host_stress_all.65575665680093882350564023654442151425307188629217616723054606729643112622065
Line 5238, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 45675661187 ps: (i2c_scoreboard.sv:559) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite
--> EXP:
-----------------------------------------------------
Name Type Size Value
-----------------------------------------------------
13.i2c_host_stress_all.26478542297698329068142422586281430271829973667453876296314928485616300157676
Line 6524, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/13.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 9701625409 ps: (i2c_scoreboard.sv:559) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite
--> EXP:
-----------------------------------------------------
Name Type Size Value
-----------------------------------------------------
... and 3 more failures.
UVM_ERROR (i2c_base_vseq.sv:992) virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout has 5 failures:
19.i2c_target_unexp_stop.30024908884685845942722332610162237815210129090033039530772623733115018530014
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/19.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 766301942 ps: (i2c_base_vseq.sv:992) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
UVM_INFO @ 766301942 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
20.i2c_target_unexp_stop.48391698876789083637294655931071042415512033265758613231869459661319309462208
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/20.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 2915279348 ps: (i2c_base_vseq.sv:992) uvm_test_top.env.virtual_sequencer [process_target_interrupts] Unexpected interrupt is set HostTimeout
UVM_INFO @ 2915279348 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_FATAL (i2c_target_hrst_vseq.sv:193) [i2c_target_hrst_vseq] Timed-out waiting for target_mode_wr_exp_fifo to become empty. has 3 failures:
1.i2c_target_hrst.96076396749773322893784341282824269599804936534664928171742295232798787902465
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10051972895 ps: (i2c_target_hrst_vseq.sv:193) [uvm_test_top.env.virtual_sequencer.i2c_target_hrst_vseq] Timed-out waiting for target_mode_wr_exp_fifo to become empty.
UVM_INFO @ 10051972895 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
10.i2c_target_hrst.111524434723076435636401055990072830887777624489427761167781742493807128785573
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/10.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10497991075 ps: (i2c_target_hrst_vseq.sv:193) [uvm_test_top.env.virtual_sequencer.i2c_target_hrst_vseq] Timed-out waiting for target_mode_wr_exp_fifo to become empty.
UVM_INFO @ 10497991075 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 3 failures:
34.i2c_target_hrst.230745913130970278169301311512989348931918637489415171300242794725543836224
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/34.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10161478015 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10161478015 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
35.i2c_target_hrst.10574472895577427104276338704147528585003008997204072266995447286877808318833
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/35.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10004597633 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10004597633 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (i2c_scoreboard.sv:587) [scoreboard] Check failed obs.wdata == exp.wdata (* [*] vs * [*]) has 2 failures:
Test i2c_target_stress_all_with_rand_reset has 1 failures.
1.i2c_target_stress_all_with_rand_reset.101456980052583937546207996465416713627736107278819971652214737505524617623903
Line 287, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 10122759136 ps: (i2c_scoreboard.sv:587) [uvm_test_top.env.scoreboard] Check failed obs.wdata == exp.wdata (155 [0x9b] vs 252 [0xfc])
UVM_INFO @ 10122759136 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test i2c_target_hrst has 1 failures.
9.i2c_target_hrst.76154346397797811551021205356810326001499981458404804821830314983854212967615
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_target_hrst/latest/run.log
UVM_ERROR @ 10375160 ps: (i2c_scoreboard.sv:587) [uvm_test_top.env.scoreboard] Check failed obs.wdata == exp.wdata (2 [0x2] vs 113 [0x71])
UVM_INFO @ 10375160 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '($stable(fmt_fifo_wvalid_i) && $stable(fmt_fifo_wdata_i))' has 2 failures:
3.i2c_csr_bit_bash.2516606763672265009941403692709322485370354527007795720147809628201956884593
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_csr_bit_bash/latest/run.log
Offending '($stable(fmt_fifo_wvalid_i) && $stable(fmt_fifo_wdata_i))'
UVM_ERROR @ 314402838 ps: (i2c_fifos.sv:310) [ASSERT FAILED] FmtWriteStableBeforeHandshake_A
UVM_INFO @ 314402838 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.i2c_csr_bit_bash.3184774461745403648527789039901028335689679921744951201038447775037702135143
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_csr_bit_bash/latest/run.log
Offending '($stable(fmt_fifo_wvalid_i) && $stable(fmt_fifo_wdata_i))'
UVM_ERROR @ 991779239 ps: (i2c_fifos.sv:310) [ASSERT FAILED] FmtWriteStableBeforeHandshake_A
UVM_INFO @ 991779239 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=*) == * has 2 failures:
6.i2c_target_stress_all_with_rand_reset.101227231315564377084540704788139975999810810403405087570003676510527042373539
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 10049914758 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=0xc8368194) == 0x0
UVM_INFO @ 10049914758 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.i2c_target_stress_all_with_rand_reset.8315304824963186316901745429483379981875583836667557523617467447991800911031
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 10260137483 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.txfull (addr=0xbef84d94) == 0x0
UVM_INFO @ 10260137483 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_driver.sv:234) [i2c_drv_scl] wait timeout occurred! has 2 failures:
23.i2c_target_stress_all.91234217772946891916947152070771762436407501508022547154129256503817601656058
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/23.i2c_target_stress_all/latest/run.log
UVM_FATAL @ 100725153982 ps: (i2c_driver.sv:234) [i2c_drv_scl] wait timeout occurred!
UVM_INFO @ 100725153982 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
32.i2c_target_stress_all.68015550150025805172337915990700250856058726882788652370791483810457615025686
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/32.i2c_target_stress_all/latest/run.log
UVM_FATAL @ 100383203126 ps: (i2c_driver.sv:234) [i2c_drv_scl] wait timeout occurred!
UVM_INFO @ 100383203126 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_host_fifo_watermark_vseq.sv:60) [i2c_host_fifo_watermark_vseq] Check failed cnt_fmt_threshold <= * (* [*] vs * [*]) has 1 failures:
2.i2c_host_stress_all_with_rand_reset.45079891086172922365843580313134135432731376581414528343529651549814601669531
Line 2110, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 7994595604 ps: (i2c_host_fifo_watermark_vseq.sv:60) [uvm_test_top.env.virtual_sequencer.i2c_host_fifo_watermark_vseq] Check failed cnt_fmt_threshold <= 3 (5 [0x5] vs 3 [0x3])
UVM_INFO @ 7994595604 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:250) [i2c_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch has 1 failures:
5.i2c_same_csr_outstanding.53828998235322293350261967479213206464883419745836564946297881582125225546431
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_same_csr_outstanding/latest/run.log
UVM_ERROR @ 140103890 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed masked_data == exp_data (8 [0x8] vs 0 [0x0]) addr 0x400eb78 read out mismatch
UVM_INFO @ 140103890 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_smoke_vseq.sv:99) [target_smoke_vseq] wait timeout occurred! has 1 failures:
15.i2c_target_unexp_stop.69365911705058098294114169263918082534602558529244164010530747972057759511879
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/15.i2c_target_unexp_stop/latest/run.log
UVM_FATAL @ 12812014805 ps: (i2c_target_smoke_vseq.sv:99) [target_smoke_vseq] wait timeout occurred!
UVM_INFO @ 12812014805 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:559) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 1 failures:
17.i2c_host_stress_all.86432284951512372005110209664549797396864152500209125881059854256858576317496
Line 7707, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/17.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 78246097115 ps: (i2c_scoreboard.sv:559) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.controller_events reset value: * has 1 failures:
17.i2c_tl_intg_err.2776959042370735704277487651123905436251333556076049062890379665443696698324
Line 351, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/17.i2c_tl_intg_err/latest/run.log
UVM_ERROR @ 152659228 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (8 [0x8] vs 0 [0x0]) Regname: i2c_reg_block.controller_events reset value: 0x0
UVM_INFO @ 152659228 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---