I2C Simulation Results

Tuesday July 09 2024 23:02:48 UTC

GitHub Revision: `6a84251492`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 61727890964832844865465694323650730626175387240181955975848876152363892893427

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	1.837m	12.980ms	50	50	100.00
V1	target_smoke	i2c_target_smoke	46.910s	2.811ms	50	50	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	0.790s	18.790us	5	5	100.00
V1	csr_rw	i2c_csr_rw	0.840s	79.579us	20	20	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	5.180s	1.110ms	5	5	100.00
V1	csr_aliasing	i2c_csr_aliasing	1.910s	94.022us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.600s	35.144us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	0.840s	79.579us	20	20	100.00
		i2c_csr_aliasing	1.910s	94.022us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	host_error_intr	i2c_host_error_intr	12.290s	1.067ms	38	50	76.00
V2	host_stress_all	i2c_host_stress_all	15.549m	21.110ms	1	50	2.00
V2	host_maxperf	i2c_host_perf	50.575m	49.175ms	28	50	56.00
V2	host_override	i2c_host_override	0.750s	28.067us	50	50	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	6.716m	8.294ms	50	50	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	9.380s	153.022us	0	50	0.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.450s	593.025us	50	50	100.00
		i2c_host_fifo_fmt_empty	28.190s	3.737ms	50	50	100.00
		i2c_host_fifo_reset_rx	14.220s	265.650us	50	50	100.00
V2	host_fifo_full	i2c_host_fifo_full	2.837m	2.734ms	12	50	24.00
V2	host_timeout	i2c_host_stretch_timeout	44.150s	2.470ms	50	50	100.00
V2	host_rx_oversample	i2c_host_rx_oversample			0	0	--
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	2.024m	5.304ms	50	50	100.00
V2	target_error_intr	i2c_target_unexp_stop	3.370s	578.679us	0	50	0.00
V2	target_glitch	i2c_target_glitch	10.960s	2.061ms	2	2	100.00
V2	target_stress_all	i2c_target_stress_all	16.014m	42.381ms	0	50	0.00
V2	target_maxperf	i2c_target_perf	3.410s	1.814ms	0	50	0.00
V2	target_fifo_empty	i2c_target_stress_rd	1.367m	3.566ms	50	50	100.00
		i2c_target_intr_smoke	8.080s	1.396ms	50	50	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.950s	291.909us	50	50	100.00
		i2c_target_fifo_reset_tx	1.990s	297.271us	50	50	100.00
V2	target_fifo_full	i2c_target_stress_wr	45.076m	64.904ms	50	50	100.00
		i2c_target_stress_rd	1.367m	3.566ms	50	50	100.00
		i2c_target_intr_stress_wr	12.341m	24.287ms	50	50	100.00
V2	target_timeout	i2c_target_timeout	8.300s	5.506ms	50	50	100.00
V2	target_clock_stretch	i2c_target_stretch	3.374m	5.142ms	43	50	86.00
V2	bad_address	i2c_target_bad_addr	8.240s	2.771ms	49	50	98.00
V2	target_mode_glitch	i2c_target_hrst	47.690s	10.001ms	0	50	0.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	3.440s	2.604ms	50	50	100.00
		i2c_target_fifo_watermarks_tx	1.630s	709.110us	49	50	98.00
V2	host_mode_config_perf	i2c_host_perf	50.575m	49.175ms	28	50	56.00
		i2c_host_perf_precise	17.542m	24.584ms	50	50	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	44.150s	2.470ms	50	50	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	38.070s	3.172ms	48	50	96.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	3.350s	1.265ms	50	50	100.00
		i2c_target_nack_acqfull_addr	3.100s	594.722us	50	50	100.00
		i2c_target_nack_txstretch	43.730s	20.000ms	0	50	0.00
V2	host_mode_halt_on_nak	host_mode_halt_on_nak			0	0	--
V2	target_mode_n_byte_ack_control	target_mode_n_byte_ack_control			0	0	--
V2	target_mode_bus_timeout	target_mode_bus_timeout			0	0	--
V2	controller_mode_bus_timeout	controller_mode_bus_timeout			0	0	--
V2	controller_mode_bus_idle_delay	controller_mode_bus_idle_delay			0	0	--
V2	loopback_test	loopback_test			0	0	--
V2	multi_controller_clock_synchronization	multi_controller_clock_synchronization			0	0	--
V2	multi_controller_arbitration_lost_interference	multi_controller_arbitration_lost_interference			0	0	--
V2	multi_controller_arbitration_lost	multi_controller_arbitration_lost			0	0	--
V2	target_mode_arbitration_lost_interference	target_mode_arbitration_lost_interference			0	0	--
V2	target_mode_arbitration_lost	target_mode_arbitration_lost			0	0	--
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	2.650s	575.089us	50	50	100.00
V2	alert_test	i2c_alert_test	0.780s	18.509us	50	50	100.00
V2	intr_test	i2c_intr_test	0.770s	19.309us	50	50	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.780s	158.345us	20	20	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.780s	158.345us	20	20	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	0.790s	18.790us	5	5	100.00
		i2c_csr_rw	0.840s	79.579us	20	20	100.00
		i2c_csr_aliasing	1.910s	94.022us	5	5	100.00
		i2c_same_csr_outstanding	1.260s	73.141us	20	20	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	0.790s	18.790us	5	5	100.00
		i2c_csr_rw	0.840s	79.579us	20	20	100.00
		i2c_csr_aliasing	1.910s	94.022us	5	5	100.00
		i2c_same_csr_outstanding	1.260s	73.141us	20	20	100.00
V2		TOTAL			1360	1792	75.89
V2S	tl_intg_err	i2c_tl_intg_err	2.470s	938.384us	20	20	100.00
		i2c_sec_cm	0.970s	111.865us	5	5	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.470s	938.384us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	5.883m	21.746ms	0	10	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	10.209m	30.507ms	0	10	0.00
V3	target_loopback				0	0	--
V3		TOTAL			0	20	0.00
	Unmapped tests	i2c_host_may_nack	6.120s	507.793us	0	50	0.00
		TOTAL			1540	2042	75.42

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	7	7	7	100.00
V2	50	38	24	48.00
V2S	2	2	2	100.00
V3	3	2	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
90.86	97.06	89.50	97.22	71.43	94.04	98.44	88.32

Failure Buckets

UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 177 failures:

Test i2c_host_fifo_overflow has 50 failures.

0.i2c_host_fifo_overflow.84051043715178833111416347657892498189028415819184941321272565852105337810600
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_fifo_overflow/latest/run.log

  UVM_ERROR @ 618970225 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
  --> EXP:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------

1.i2c_host_fifo_overflow.25722494398295214275818515862283440962943292943085478246598723613174145939215
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_fifo_overflow/latest/run.log

  UVM_ERROR @ 121295853 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
  --> EXP:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------

... and 48 more failures.

Test i2c_host_fifo_full has 38 failures.

0.i2c_host_fifo_full.101787389053380326849778192312198286548528919910906825937958120264249723717422
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_fifo_full/latest/run.log

  UVM_ERROR @ 509062113 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
  --> EXP:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------

2.i2c_host_fifo_full.74085510697071549105408198910199634273946422860708086841379307747938779761253
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_fifo_full/latest/run.log

  UVM_ERROR @ 410534965 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
  --> EXP:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------

... and 36 more failures.

Test i2c_host_stress_all has 40 failures.

0.i2c_host_stress_all.27323296458351453047054849872452151889761668547514723165892369455127189992971
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 275237016 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
  --> EXP:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------

1.i2c_host_stress_all.37192310628311488851791102900172593294937775108782171175955457133836554615410
Line 264, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 394772313 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
  --> EXP:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------

... and 38 more failures.

Test i2c_host_may_nack has 19 failures.

0.i2c_host_may_nack.92708862925308398455406003172110882820834041923694455161197397503521504467387
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_may_nack/latest/run.log

  UVM_ERROR @  41172302 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
  --> EXP:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------

2.i2c_host_may_nack.21198587987742523734132886155655555898053827013102424016179482004243434676821
Line 253, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_may_nack/latest/run.log

  UVM_ERROR @  20607827 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
  --> EXP:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------

... and 17 more failures.

Test i2c_host_error_intr has 7 failures.

1.i2c_host_error_intr.43800619965499576723159144949009647338159438632131622016259717233154948282158
Line 264, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_error_intr/latest/run.log

  UVM_ERROR @ 112887945 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
  --> EXP:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------

4.i2c_host_error_intr.111928335248408965715831037585044524385124626959431689183855235055744757745558
Line 282, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_host_error_intr/latest/run.log

  UVM_ERROR @ 2334762823 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
  --> EXP:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------

... and 5 more failures.

... and 2 more tests.

UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 123 failures:

Test i2c_target_unexp_stop has 31 failures.

0.i2c_target_unexp_stop.92595799179781600812343497684584909535363288633461086437817090246987027138895
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log

  UVM_ERROR @ 757735639 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 222 [0xde])
  UVM_INFO @ 757735639 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_target_unexp_stop.21981512315488266464839834813398890197457375151196913501330035052595541426469
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log

  UVM_ERROR @ 179243175 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 158 [0x9e])
  UVM_INFO @ 179243175 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 29 more failures.

Test i2c_target_perf has 50 failures.

0.i2c_target_perf.12743035257686825231644961445978793427328930196071039919651481190775721240071
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_perf/latest/run.log

  UVM_ERROR @ 228965752 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 0 [0x0])
  UVM_INFO @ 228965752 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_target_perf.38497401227819351435606649672576075788421919381022025506297036655106689563386
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_perf/latest/run.log

  UVM_ERROR @ 574745032 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 0 [0x0])
  UVM_INFO @ 574745032 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 48 more failures.

Test i2c_target_stress_all has 40 failures.

0.i2c_target_stress_all.86245958198911892972472580053853493080429041831428838321717573229212403332843
Line 268, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all/latest/run.log

  UVM_ERROR @ 10004108987 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (200 [0xc8] vs 2 [0x2])
  UVM_INFO @ 10004108987 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_target_stress_all.6558948441649617260876975256154354287245021197198467844626565746218673829067
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all/latest/run.log

  UVM_ERROR @  94886543 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 0 [0x0])
  UVM_INFO @  94886543 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 38 more failures.

Test i2c_target_stress_all_with_rand_reset has 2 failures.
- 7.i2c_target_stress_all_with_rand_reset.37683496535250327774693475033350280127789395643881174049556888484575455188655
  Line 272, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2064359934 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 0 [0x0])
  UVM_INFO @ 2064359934 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
- 9.i2c_target_stress_all_with_rand_reset.3311582188469046079145957115415824547197893697167726792318653155064041039790
  Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 125576599 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 21 [0x15])
  UVM_INFO @ 125576599 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite has 44 failures:

Test i2c_host_may_nack has 31 failures.

1.i2c_host_may_nack.12499779222869852192312124663980702193914209848553950012610177244647693142677
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_may_nack/latest/run.log

  UVM_ERROR @  27957239 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite
  --> EXP:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------

4.i2c_host_may_nack.46568403566121104241828214322131279619591816713003083602520282390038980653995
Line 269, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_host_may_nack/latest/run.log

  UVM_ERROR @ 129490240 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite
  --> EXP:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------

... and 29 more failures.

Test i2c_host_error_intr has 5 failures.

3.i2c_host_error_intr.61182203647619670515009596563715057777848757911740481496520667637370792313282
Line 276, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_host_error_intr/latest/run.log

  UVM_ERROR @ 1039170184 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite
  --> EXP:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------

17.i2c_host_error_intr.47427056046793166091868244428530985768631328018578237875962185653873927261482
Line 264, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/17.i2c_host_error_intr/latest/run.log

  UVM_ERROR @  34731566 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite
  --> EXP:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------

... and 3 more failures.

Test i2c_host_stress_all has 8 failures.

9.i2c_host_stress_all.5545199449617544839523602776421240061412121575236542444682853609634283601077
Line 286, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 1097660838 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite
  --> EXP:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------

14.i2c_host_stress_all.29265387555718455200657837287758102549546433626972152393495824833487849795889
Line 303, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/14.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 21109829898 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite
  --> EXP:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------

... and 6 more failures.

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 34 failures:
- Test i2c_target_nack_txstretch has 33 failures.
  - 0.i2c_target_nack_txstretch.62032983842508423265120955634422291155181237238537933172676080144321715737834
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_nack_txstretch/latest/run.log
```
  UVM_FATAL @ 20000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 20000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 20000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.i2c_target_nack_txstretch.1892871529292580567725292702006425103200821816315714910574214477820973023137
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_nack_txstretch/latest/run.log
```
  UVM_FATAL @ 20000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 20000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 20000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 31 more failures.
- Test i2c_target_bad_addr has 1 failures.
  - 17.i2c_target_bad_addr.47109680952980596094261574531436387271541786544229435687319841611567574941094
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/17.i2c_target_bad_addr/latest/run.log
```
  UVM_FATAL @ 20000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 20000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 20000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_FATAL (i2c_monitor.sv:474) monitor [monitor] State at start of controller_collect_thread() is unexpected! has 20 failures:

Test i2c_target_hrst has 20 failures.

1.i2c_target_hrst.111142685844408072611465410656614085435765582655363330164695195277428298001591
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_hrst/latest/run.log

  UVM_FATAL @ 167025347 ps: (i2c_monitor.sv:474) uvm_test_top.env.m_i2c_agent.monitor [uvm_test_top.env.m_i2c_agent.monitor] State at start of controller_collect_thread() is unexpected!
  UVM_INFO @ 167025347 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.i2c_target_hrst.87939827262745008701249173035962192660621111094770185498631113889876969821908
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_hrst/latest/run.log

  UVM_FATAL @  46039083 ps: (i2c_monitor.sv:474) uvm_test_top.env.m_i2c_agent.monitor [uvm_test_top.env.m_i2c_agent.monitor] State at start of controller_collect_thread() is unexpected!
  UVM_INFO @  46039083 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 18 more failures.

UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 19 failures:
- Test i2c_target_hrst has 19 failures.
  - 0.i2c_target_hrst.9855557059669910865090344167518830720078101223262669177565079203924062760865
    Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log
```
  UVM_FATAL @ 10088248927 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
  UVM_INFO @ 10088248927 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.i2c_target_hrst.61708331920103578267066465373162781583628860147601264278091142190535703609359
    Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_hrst/latest/run.log
```
  UVM_FATAL @ 10746334825 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
  UVM_INFO @ 10746334825 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 17 more failures.

Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 18 failures:

Test i2c_target_stress_all_with_rand_reset has 4 failures.

1.i2c_target_stress_all_with_rand_reset.98331760489275413742825961031836547838197679608538775682332395850921509618966
Line 257, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log

      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @  36753148 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @  36753148 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.i2c_target_stress_all_with_rand_reset.7441179456775459351415566643656265248253419409073285404055289118562101133452
Line 511, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log

      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @ 30507017386 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @ 30507017386 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Test i2c_target_stress_all has 9 failures.

8.i2c_target_stress_all.24276496032551882412551191949185674904140598174342809230456005557759911549935
Line 262, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_target_stress_all/latest/run.log

      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @ 21001594273 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @ 21001594273 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

17.i2c_target_stress_all.110804033792685700223636336853803881422391068565824677848394630358056166202498
Line 269, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/17.i2c_target_stress_all/latest/run.log

      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @ 9561289905 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @ 9561289905 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 7 more failures.

Test i2c_target_unexp_stop has 5 failures.

9.i2c_target_unexp_stop.61951971714332866446569378090141417164579927691458567533597506781450033521348
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_target_unexp_stop/latest/run.log

      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @ 201871291 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @ 201871291 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

13.i2c_target_unexp_stop.45948349452768923230133234578495431896049775455279385534548018030784179477001
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/13.i2c_target_unexp_stop/latest/run.log

      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @ 285401377 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @ 285401377 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 17 failures:
- Test i2c_target_nack_txstretch has 17 failures.
  - 5.i2c_target_nack_txstretch.112996355016924982627967354998070249183906279661881608289428526557798290587603
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_nack_txstretch/latest/run.log
```
  UVM_ERROR @ 822951780 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
  UVM_INFO @ 822951780 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 6.i2c_target_nack_txstretch.99585524719584479046858018076418064022930980187703053849033839315617393347192
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_nack_txstretch/latest/run.log
```
  UVM_ERROR @ 141535413 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
  UVM_INFO @ 141535413 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 15 more failures.
UVM_ERROR (i2c_base_vseq.sv:1473) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 14 failures:
- Test i2c_target_unexp_stop has 14 failures.
  - 2.i2c_target_unexp_stop.18547875827127412256340037969439499209574224886267232351732657333659151189155
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 328232668 ps: (i2c_base_vseq.sv:1473) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 328232668 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.i2c_target_unexp_stop.86864145890478892923219443988681398151413720258540847237853674954153805325095
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @  15543350 ps: (i2c_base_vseq.sv:1473) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
  UVM_INFO @  15543350 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 12 more failures.
UVM_FATAL (i2c_target_hrst_vseq.sv:384) [stop_interrupt_handler] wait timeout occurred! has 11 failures:
- Test i2c_target_hrst has 11 failures.
  - 7.i2c_target_hrst.71664277341534706161426109314334628248302623498201278224265778313939051871986
    Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_hrst/latest/run.log
```
  UVM_FATAL @ 10004557135 ps: (i2c_target_hrst_vseq.sv:384) [stop_interrupt_handler] wait timeout occurred!
  UVM_INFO @ 10004557135 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 9.i2c_target_hrst.19289465372941992177716854813088696039989113521198944874597018020616559305473
    Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_target_hrst/latest/run.log
```
  UVM_FATAL @ 10012169664 ps: (i2c_target_hrst_vseq.sv:384) [stop_interrupt_handler] wait timeout occurred!
  UVM_INFO @ 10012169664 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 9 more failures.

UVM_ERROR (cip_base_vseq.sv:825) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 9 failures:

Test i2c_host_stress_all_with_rand_reset has 7 failures.

0.i2c_host_stress_all_with_rand_reset.62311674053762559876056595375478106898959118099620437629281813376616594056558
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 211538878 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 211538878 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_host_stress_all_with_rand_reset.2172131392541890368431696735075030515114910612398864278010919519852699110075
Line 305, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3914053875 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 3914053875 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

Test i2c_target_stress_all_with_rand_reset has 2 failures.

0.i2c_target_stress_all_with_rand_reset.55549271561544038565662254277117953409867899412378888554910769930111141088974
Line 266, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1749353942 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1749353942 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.i2c_target_stress_all_with_rand_reset.55438319200583008407794042726826847012419806214888082181226843055228927336113
Line 258, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 5222809580 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 5222809580 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred! has 7 failures:
- Test i2c_target_stretch has 7 failures.
  - 4.i2c_target_stretch.30778252443297975642514065974122364459032514324102101044388230972656216803859
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stretch/latest/run.log
```
  UVM_FATAL @ 10009276998 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
  UVM_INFO @ 10009276998 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 11.i2c_target_stretch.70979843305931038143129474481966217059223245090048629931419098698298102455715
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/11.i2c_target_stretch/latest/run.log
```
  UVM_FATAL @ 10012235996 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
  UVM_INFO @ 10012235996 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.
Job i2c-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 4 failures:
- Test i2c_host_perf has 2 failures.
  - 16.i2c_host_perf.23241197516621341862440928315766012804983384373196628793297828804717029107266
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/16.i2c_host_perf/latest/run.log
```
  Job ID: smart:7b5aa810-a4be-4ddb-9fed-d2d7fe5a4700
```
  - 18.i2c_host_perf.52849470779802701395046947434528997243025350533831793522133348870811368771949
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/18.i2c_host_perf/latest/run.log
```
  Job ID: smart:09d6cbe6-a51d-45d2-8582-d746c387d397
```
- Test i2c_target_stress_all has 1 failures.
  - 35.i2c_target_stress_all.70257612038421539037573539750140027873206488194178663977645552023520514005172
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/35.i2c_target_stress_all/latest/run.log
```
  Job ID: smart:8d4b1023-701c-4b5e-9be3-dcdd32c6cab2
```
- Test i2c_host_stress_all has 1 failures.
  - 36.i2c_host_stress_all.108935465521802876248691078002796372105219981514984528980188319994289498087164
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/36.i2c_host_stress_all/latest/run.log
```
  Job ID: smart:93da6c6b-95c0-4513-82a9-411b216ec77c
```
Error-[CNST-CIF] Constraints inconsistency failure has 3 failures:
- Test i2c_target_fifo_watermarks_tx has 1 failures.
  - 6.i2c_target_fifo_watermarks_tx.5651642792723317676713178395813672386203136064481136216608757452216357820810
    Line 292, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_fifo_watermarks_tx/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 844
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
- Test i2c_target_tx_stretch_ctrl has 2 failures.
  - 16.i2c_target_tx_stretch_ctrl.79883225511274905220481590142334550200643750571475058090613025488268562530436
    Line 295, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/16.i2c_target_tx_stretch_ctrl/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 871
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
  - 37.i2c_target_tx_stretch_ctrl.110789059737773868736249389596805307735196446935863438483744388427462190495124
    Line 295, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/37.i2c_target_tx_stretch_ctrl/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 871
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
UVM_FATAL (i2c_base_vseq.sv:717) [i2c_target_smoke_vseq] wait timeout occurred! has 1 failures:
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 2.i2c_target_stress_all_with_rand_reset.23863003945849077073920997064926874076061296521127891957629131932970655098885
    Line 360, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10585370874 ps: (i2c_base_vseq.sv:717) [uvm_test_top.env.virtual_sequencer.i2c_target_smoke_vseq] wait timeout occurred!
  UVM_INFO @ 10585370874 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (i2c_base_vseq.sv:717) [i2c_target_stress_wr_vseq] wait timeout occurred! has 1 failures:
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 6.i2c_target_stress_all_with_rand_reset.87399494378346125166946911467387242902035155886596003577695941172268829077203
    Line 329, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 30440835115 ps: (i2c_base_vseq.sv:717) [uvm_test_top.env.virtual_sequencer.i2c_target_stress_wr_vseq] wait timeout occurred!
  UVM_INFO @ 30440835115 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```