I2C Simulation Results

Wednesday July 10 2024 23:02:26 UTC

GitHub Revision: `39211701b5`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 52262812535389540465251148247405743574935129745685597413714598750252192397067

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	1.789m	8.247ms	50	50	100.00
V1	target_smoke	i2c_target_smoke	47.010s	3.042ms	50	50	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	0.760s	26.976us	5	5	100.00
V1	csr_rw	i2c_csr_rw	0.820s	20.941us	20	20	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	5.260s	1.053ms	5	5	100.00
V1	csr_aliasing	i2c_csr_aliasing	2.010s	217.759us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.240s	27.880us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	0.820s	20.941us	20	20	100.00
		i2c_csr_aliasing	2.010s	217.759us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	host_error_intr	i2c_host_error_intr	18.690s	1.598ms	36	50	72.00
V2	host_stress_all	i2c_host_stress_all	32.166m	84.892ms	5	50	10.00
V2	host_maxperf	i2c_host_perf	23.372m	48.634ms	33	50	66.00
V2	host_override	i2c_host_override	0.740s	19.122us	50	50	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	6.110m	63.506ms	50	50	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	9.390s	292.949us	0	50	0.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.440s	169.963us	50	50	100.00
		i2c_host_fifo_fmt_empty	26.360s	481.892us	49	50	98.00
		i2c_host_fifo_reset_rx	14.910s	996.013us	50	50	100.00
V2	host_fifo_full	i2c_host_fifo_full	3.017m	10.823ms	14	50	28.00
V2	host_timeout	i2c_host_stretch_timeout	43.040s	4.433ms	50	50	100.00
V2	host_rx_oversample	i2c_host_rx_oversample			0	0	--
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	1.792m	15.955ms	50	50	100.00
V2	target_error_intr	i2c_target_unexp_stop	2.920s	1.237ms	0	50	0.00
V2	target_glitch	i2c_target_glitch	10.640s	7.897ms	2	2	100.00
V2	target_stress_all	i2c_target_stress_all	2.614m	21.139ms	0	50	0.00
V2	target_maxperf	i2c_target_perf	15.235m	20.000ms	0	50	0.00
V2	target_fifo_empty	i2c_target_stress_rd	1.459m	5.063ms	50	50	100.00
		i2c_target_intr_smoke	7.840s	5.649ms	50	50	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.970s	322.147us	50	50	100.00
		i2c_target_fifo_reset_tx	1.900s	267.896us	50	50	100.00
V2	target_fifo_full	i2c_target_stress_wr	35.162m	55.105ms	50	50	100.00
		i2c_target_stress_rd	1.459m	5.063ms	50	50	100.00
		i2c_target_intr_stress_wr	10.624m	23.478ms	50	50	100.00
V2	target_timeout	i2c_target_timeout	9.230s	1.576ms	50	50	100.00
V2	target_clock_stretch	i2c_target_stretch	2.532m	3.031ms	44	50	88.00
V2	bad_address	i2c_target_bad_addr	7.850s	12.632ms	50	50	100.00
V2	target_mode_glitch	i2c_target_hrst	43.690s	10.111ms	0	50	0.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	3.340s	2.351ms	50	50	100.00
		i2c_target_fifo_watermarks_tx	1.600s	804.826us	50	50	100.00
V2	host_mode_config_perf	i2c_host_perf	23.372m	48.634ms	33	50	66.00
		i2c_host_perf_precise	24.586m	23.249ms	50	50	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	43.040s	4.433ms	50	50	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	15.200s	1.280ms	50	50	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	3.390s	953.766us	50	50	100.00
		i2c_target_nack_acqfull_addr	3.190s	619.750us	50	50	100.00
		i2c_target_nack_txstretch	44.810s	20.000ms	0	50	0.00
V2	host_mode_halt_on_nak	host_mode_halt_on_nak			0	0	--
V2	target_mode_n_byte_ack_control	target_mode_n_byte_ack_control			0	0	--
V2	target_mode_bus_timeout	target_mode_bus_timeout			0	0	--
V2	controller_mode_bus_timeout	controller_mode_bus_timeout			0	0	--
V2	controller_mode_bus_idle_delay	controller_mode_bus_idle_delay			0	0	--
V2	loopback_test	loopback_test			0	0	--
V2	multi_controller_clock_synchronization	multi_controller_clock_synchronization			0	0	--
V2	multi_controller_arbitration_lost_interference	multi_controller_arbitration_lost_interference			0	0	--
V2	multi_controller_arbitration_lost	multi_controller_arbitration_lost			0	0	--
V2	target_mode_arbitration_lost_interference	target_mode_arbitration_lost_interference			0	0	--
V2	target_mode_arbitration_lost	target_mode_arbitration_lost			0	0	--
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	2.740s	540.680us	50	50	100.00
V2	alert_test	i2c_alert_test	0.680s	15.531us	50	50	100.00
V2	intr_test	i2c_intr_test	0.730s	24.857us	50	50	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.740s	205.525us	20	20	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.740s	205.525us	20	20	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	0.760s	26.976us	5	5	100.00
		i2c_csr_rw	0.820s	20.941us	20	20	100.00
		i2c_csr_aliasing	2.010s	217.759us	5	5	100.00
		i2c_same_csr_outstanding	1.210s	105.242us	19	20	95.00
V2	tl_d_partial_access	i2c_csr_hw_reset	0.760s	26.976us	5	5	100.00
		i2c_csr_rw	0.820s	20.941us	20	20	100.00
		i2c_csr_aliasing	2.010s	217.759us	5	5	100.00
		i2c_same_csr_outstanding	1.210s	105.242us	19	20	95.00
V2		TOTAL			1372	1792	76.56
V2S	tl_intg_err	i2c_tl_intg_err	2.390s	283.564us	20	20	100.00
		i2c_sec_cm	1.000s	75.300us	5	5	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.390s	283.564us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	6.682m	81.894ms	0	10	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	6.275m	50.186ms	0	10	0.00
V3	target_loopback				0	0	--
V3		TOTAL			0	20	0.00
	Unmapped tests	i2c_host_may_nack	6.090s	897.090us	0	50	0.00
		TOTAL			1552	2042	76.00

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	7	7	7	100.00
V2	50	38	25	50.00
V2S	2	2	2	100.00
V3	3	2	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
90.67	96.94	89.42	97.22	70.24	93.90	98.44	88.53

Failure Buckets

UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 176 failures:

Test i2c_host_fifo_overflow has 50 failures.

0.i2c_host_fifo_overflow.67216405644696201933164549812354293656719297138125417506260455824955574635391
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_fifo_overflow/latest/run.log

  UVM_ERROR @ 445152690 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
  --> EXP:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------

1.i2c_host_fifo_overflow.16451324312400995752029927128031356978521309685115477697654345139476831243967
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_fifo_overflow/latest/run.log

  UVM_ERROR @ 254302968 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
  --> EXP:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------

... and 48 more failures.

Test i2c_host_perf has 15 failures.

0.i2c_host_perf.17225301931902247479933079430315779697231095864399912649215941424031335925354
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_perf/latest/run.log

  UVM_ERROR @ 752705024 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
  --> EXP:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------

2.i2c_host_perf.65955475023201149035173736716326355228216531732181964592492906235455809717505
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_perf/latest/run.log

  UVM_ERROR @ 415060594 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
  --> EXP:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------

... and 13 more failures.

Test i2c_host_stress_all has 41 failures.

0.i2c_host_stress_all.88043960494797960896205902110514557323540452630114340338270831636179360473746
Line 311, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 2242633716 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
  --> EXP:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------

2.i2c_host_stress_all.8285343698403633003156293679466709588439748734147530968001193403476315929808
Line 263, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 5101367622 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
  --> EXP:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------

... and 39 more failures.

Test i2c_host_stress_all_with_rand_reset has 6 failures.

0.i2c_host_stress_all_with_rand_reset.27774758387112817670760163192123072618265618740222229202917918151253455103800
Line 333, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 6544095094 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
  --> EXP:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------

2.i2c_host_stress_all_with_rand_reset.3195114889597116019634333616765095576598808170941528035349842350962201346156
Line 271, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 7047572037 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
  --> EXP:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------

... and 4 more failures.

Test i2c_host_fifo_full has 36 failures.

1.i2c_host_fifo_full.9726132889202835525714055006814362219174485953583692093315561593841201144016
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_fifo_full/latest/run.log

  UVM_ERROR @ 4367182293 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
  --> EXP:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------

2.i2c_host_fifo_full.76129622133679727794867088497122420224922136699593618686697341578091202408031
Line 252, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_fifo_full/latest/run.log

  UVM_ERROR @ 1859299831 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
  --> EXP:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------

... and 34 more failures.

... and 2 more tests.

UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 115 failures:

Test i2c_target_perf has 47 failures.

0.i2c_target_perf.42836164644639152947957089609652546323452063675410799264093829496524179926555
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_perf/latest/run.log

  UVM_ERROR @  19395912 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 0 [0x0])
  UVM_INFO @  19395912 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_target_perf.101677274542318362685390510300757320022233586507055823512702623606712696182905
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_perf/latest/run.log

  UVM_ERROR @ 140499419 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 0 [0x0])
  UVM_INFO @ 140499419 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 45 more failures.

Test i2c_target_unexp_stop has 27 failures.

1.i2c_target_unexp_stop.67931202579311298443398938508776556272530970651934839600171071424342782680227
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log

  UVM_ERROR @ 138953296 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 50 [0x32])
  UVM_INFO @ 138953296 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.i2c_target_unexp_stop.34788513401407255583309274975129936699003707454497802857854724972674760504978
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_unexp_stop/latest/run.log

  UVM_ERROR @  93318770 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 37 [0x25])
  UVM_INFO @  93318770 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 25 more failures.

Test i2c_target_stress_all has 39 failures.

2.i2c_target_stress_all.103436754173132074345471387155940771614719598854734383342671690350735490328590
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all/latest/run.log

  UVM_ERROR @ 468036667 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 0 [0x0])
  UVM_INFO @ 468036667 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.i2c_target_stress_all.7826080087500221605855091598189949493719366849756620976134199249185418147870
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all/latest/run.log

  UVM_ERROR @ 4492953775 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 0 [0x0])
  UVM_INFO @ 4492953775 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 37 more failures.

Test i2c_target_stress_all_with_rand_reset has 2 failures.
- 4.i2c_target_stress_all_with_rand_reset.68013808672292088689152937005616251249405959775938263446423639455594668567729
  Line 257, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1607350811 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 22 [0x16])
  UVM_INFO @ 1607350811 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
- 6.i2c_target_stress_all_with_rand_reset.11597364933529296187187828862938931077303872970316877391178171158565873000060
  Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 334075202 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 219 [0xdb])
  UVM_INFO @ 334075202 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite has 39 failures:

Test i2c_host_may_nack has 28 failures.

0.i2c_host_may_nack.19501886486987093144540177946349326677357258741624717228711820576270154874987
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_may_nack/latest/run.log

  UVM_ERROR @  26116101 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite
  --> EXP:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------

1.i2c_host_may_nack.98938953101509131649756586565658547633879944783151764017545669883427833483017
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_may_nack/latest/run.log

  UVM_ERROR @ 116270610 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite
  --> EXP:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------

... and 26 more failures.

Test i2c_host_error_intr has 8 failures.

6.i2c_host_error_intr.84082454703458457444044573155194150953651995889281141748803893044932066136546
Line 276, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_host_error_intr/latest/run.log

  UVM_ERROR @ 196710795 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite
  --> EXP:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------

9.i2c_host_error_intr.65720387606107955654857912745017383458611803901988172521527973473264733008384
Line 288, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_host_error_intr/latest/run.log

  UVM_ERROR @ 214014941 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite
  --> EXP:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------

... and 6 more failures.

Test i2c_host_stress_all has 3 failures.

33.i2c_host_stress_all.57666806855055319840028361694879302105630455009016686325726448553704999756328
Line 386, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/33.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 38869243277 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite
  --> EXP:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------

39.i2c_host_stress_all.22834222243155880904272895079668479434754940510903844719925075344713701091151
Line 299, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/39.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 3645630977 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite
  --> EXP:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------

... and 1 more failures.

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 39 failures:
- Test i2c_target_nack_txstretch has 35 failures.
  - 3.i2c_target_nack_txstretch.44994282689757856664293986976877101899278951929570014687167200057186076916853
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_nack_txstretch/latest/run.log
```
  UVM_FATAL @ 20000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 20000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 20000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.i2c_target_nack_txstretch.79838149513188070292602451491235840303872427821845724521486166078581213740696
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_nack_txstretch/latest/run.log
```
  UVM_FATAL @ 20000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 20000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 20000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 33 more failures.
- Test i2c_target_perf has 2 failures.
  - 4.i2c_target_perf.106993698116091767017343007799447244180756065349356065679818860750452767688778
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_perf/latest/run.log
```
  UVM_FATAL @ 20000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 20000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 20000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 49.i2c_target_perf.93784544266592664948074014266539767536819265921247221587192467871356018546145
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/49.i2c_target_perf/latest/run.log
```
  UVM_FATAL @ 20000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 20000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 20000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test i2c_host_fifo_fmt_empty has 1 failures.
  - 9.i2c_host_fifo_fmt_empty.113538189628674181897002534085980882988487826831900159432649000705437323220390
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_host_fifo_fmt_empty/latest/run.log
```
  UVM_FATAL @ 10000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 10000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test i2c_host_stress_all has 1 failures.
  - 27.i2c_host_stress_all.38757109379863270430513801197793232706220789917799512761631179113267109501079
    Line 265, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/27.i2c_host_stress_all/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_FATAL (i2c_monitor.sv:474) monitor [monitor] State at start of controller_collect_thread() is unexpected! has 28 failures:

Test i2c_target_hrst has 28 failures.

1.i2c_target_hrst.34274496122426283768188073638571127257221929948490793516588846948758537586367
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_hrst/latest/run.log

  UVM_FATAL @  14036371 ps: (i2c_monitor.sv:474) uvm_test_top.env.m_i2c_agent.monitor [uvm_test_top.env.m_i2c_agent.monitor] State at start of controller_collect_thread() is unexpected!
  UVM_INFO @  14036371 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.i2c_target_hrst.32331209727482527151172308808863785796998596389151409732245301236696369074433
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_hrst/latest/run.log

  UVM_FATAL @ 121545768 ps: (i2c_monitor.sv:474) uvm_test_top.env.m_i2c_agent.monitor [uvm_test_top.env.m_i2c_agent.monitor] State at start of controller_collect_thread() is unexpected!
  UVM_INFO @ 121545768 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 26 more failures.

UVM_ERROR (i2c_base_vseq.sv:1473) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 24 failures:

Test i2c_target_unexp_stop has 17 failures.

0.i2c_target_unexp_stop.88430521957858455160790097623839070270883711148116756718168646831202202475855
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log

  UVM_ERROR @ 1676500753 ps: (i2c_base_vseq.sv:1473) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 1676500753 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.i2c_target_unexp_stop.19230099992223172342682643972947649819516090114356019402275566046302411856763
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_unexp_stop/latest/run.log

  UVM_ERROR @ 142454158 ps: (i2c_base_vseq.sv:1473) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 142454158 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 15 more failures.

Test i2c_target_stress_all has 7 failures.

1.i2c_target_stress_all.42547378686271127045011847086349205051506097187908815417986252453344823048677
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all/latest/run.log

  UVM_ERROR @ 124716821 ps: (i2c_base_vseq.sv:1473) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 124716821 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.i2c_target_stress_all.52790572401700907259058081582938922615157203653038440535092714673331822012918
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_all/latest/run.log

  UVM_ERROR @ 354322361 ps: (i2c_base_vseq.sv:1473) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 354322361 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 16 failures:

Test i2c_target_stress_all has 3 failures.

0.i2c_target_stress_all.92036479017312161325428094320545843514353908693073881557520467916528586142645
Line 269, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all/latest/run.log

      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @ 1593279211 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @ 1593279211 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

29.i2c_target_stress_all.102101444387867113725721512143928688970021422672926484217017899309145869340530
Line 255, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/29.i2c_target_stress_all/latest/run.log

      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @ 230747096 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @ 230747096 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test i2c_target_stress_all_with_rand_reset has 7 failures.

1.i2c_target_stress_all_with_rand_reset.41578950685818086468676846247350257349206913089263772377112197436243466990761
Line 301, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log

      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @ 3459731693 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @ 3459731693 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.i2c_target_stress_all_with_rand_reset.90594347247974155159400022620272614911033426799631476585586026278297029421975
Line 280, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log

      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @ 1261033879 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @ 1261033879 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

Test i2c_target_unexp_stop has 6 failures.

12.i2c_target_unexp_stop.79316702273016905788739400745348127036217100361287045694117839740351066602255
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/12.i2c_target_unexp_stop/latest/run.log

      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @ 1914796379 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @ 1914796379 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

20.i2c_target_unexp_stop.84322347370562413831540529585847737216812030821232048806083050173951354114779
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/20.i2c_target_unexp_stop/latest/run.log

      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @  69267487 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @  69267487 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 15 failures:
- Test i2c_target_nack_txstretch has 15 failures.
  - 0.i2c_target_nack_txstretch.92844088594226381217135918957437637102832596165963211169752011232420240489741
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_nack_txstretch/latest/run.log
```
  UVM_ERROR @ 162165741 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
  UVM_INFO @ 162165741 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.i2c_target_nack_txstretch.90035719600330896021534112289186093341107542927551858461371459501767995403708
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_nack_txstretch/latest/run.log
```
  UVM_ERROR @ 837975284 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
  UVM_INFO @ 837975284 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 13 more failures.
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 14 failures:
- Test i2c_target_hrst has 14 failures.
  - 0.i2c_target_hrst.98009855057574995259975347100595724353092034197436448807617498368422176167764
    Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log
```
  UVM_FATAL @ 10638360593 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
  UVM_INFO @ 10638360593 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.i2c_target_hrst.111478131291677999933120498182677508167458603347839573112835840837300053983080
    Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_hrst/latest/run.log
```
  UVM_FATAL @ 10179565807 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
  UVM_INFO @ 10179565807 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 12 more failures.
UVM_FATAL (i2c_target_hrst_vseq.sv:384) [stop_interrupt_handler] wait timeout occurred! has 8 failures:
- Test i2c_target_hrst has 8 failures.
  - 8.i2c_target_hrst.70409913859941309022617980922215586430285347584847584415873368355320908874244
    Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_target_hrst/latest/run.log
```
  UVM_FATAL @ 10013022293 ps: (i2c_target_hrst_vseq.sv:384) [stop_interrupt_handler] wait timeout occurred!
  UVM_INFO @ 10013022293 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 14.i2c_target_hrst.17616206011275873882157671994969762737145235545470321798193672601775923300715
    Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/14.i2c_target_hrst/latest/run.log
```
  UVM_FATAL @ 10053256490 ps: (i2c_target_hrst_vseq.sv:384) [stop_interrupt_handler] wait timeout occurred!
  UVM_INFO @ 10053256490 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.
UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred! has 6 failures:
- Test i2c_target_stretch has 6 failures.
  - 7.i2c_target_stretch.21701923602207531249700620782937419946697592290476967755211858347139025808193
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_stretch/latest/run.log
```
  UVM_FATAL @ 10006520426 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
  UVM_INFO @ 10006520426 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 10.i2c_target_stretch.16151464296280005853731027383306588691899368683306898351551033684828828324221
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/10.i2c_target_stretch/latest/run.log
```
  UVM_FATAL @ 10010158736 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
  UVM_INFO @ 10010158736 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.
UVM_ERROR (cip_base_vseq.sv:825) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 4 failures:
- Test i2c_host_stress_all_with_rand_reset has 4 failures.
  - 1.i2c_host_stress_all_with_rand_reset.95473495291690613709082823194332114592344168906716344942669263673321386406682
    Line 343, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 20169887744 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 20169887744 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.i2c_host_stress_all_with_rand_reset.37034782857070407081764010111993511655838044404130545583847583487588197385841
    Line 305, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 7663823945 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 7663823945 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
Job i2c-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 3 failures:
- Test i2c_host_perf has 2 failures.
  - 30.i2c_host_perf.63207403919543770233385021039516408122380394404937988241421087244801514835049
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/30.i2c_host_perf/latest/run.log
```
  Job ID: smart:d3c7621f-1d65-49d1-8085-b811edf83495
```
  - 37.i2c_host_perf.44021582678383759312149304205963296235282343786794334524970534391981026087454
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/37.i2c_host_perf/latest/run.log
```
  Job ID: smart:076aeede-84c7-4e39-8725-4047ed95f3c8
```
- Test i2c_target_stress_all has 1 failures.
  - 36.i2c_target_stress_all.86558018925342016638116339946896621789042271703199243679646894291573766733313
    Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/36.i2c_target_stress_all/latest/run.log
```
  Job ID: smart:16fa83ad-3db3-4d20-86d9-e396cf8dae8e
```
UVM_FATAL (i2c_base_vseq.sv:717) [i2c_target_stress_wr_vseq] wait timeout occurred! has 1 failures:
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 0.i2c_target_stress_all_with_rand_reset.25699378889588949531808888085250685601495278163693666024203799854705795840145
    Line 313, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 49009422659 ps: (i2c_base_vseq.sv:717) [uvm_test_top.env.virtual_sequencer.i2c_target_stress_wr_vseq] wait timeout occurred!
  UVM_INFO @ 49009422659 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:500) [i2c_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) has 1 failures:
- Test i2c_same_csr_outstanding has 1 failures.
  - 2.i2c_same_csr_outstanding.54816500558816155282373755917760748078508274928038696574697087630072584190026
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_same_csr_outstanding/latest/run.log
```
  UVM_ERROR @  48372602 ps: (cip_base_vseq.sv:500) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed data & ~ro_mask == 0 (64 [0x40] vs 0 [0x0])
  UVM_INFO @  48372602 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (i2c_base_vseq.sv:1342) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred! has 1 failures:
- Test i2c_target_perf has 1 failures.
  - 32.i2c_target_perf.102986650368554373500046423005795436563091116558821674758753906000067654269907
    Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/32.i2c_target_perf/latest/run.log
```
  UVM_FATAL @ 10622877885 ps: (i2c_base_vseq.sv:1342) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!
  UVM_INFO @ 10622877885 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```