edf2fd5092| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | host_smoke | i2c_host_smoke | 1.936m | 8.266ms | 50 | 50 | 100.00 |
| V1 | target_smoke | i2c_target_smoke | 45.550s | 2.826ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | i2c_csr_hw_reset | 0.790s | 23.195us | 5 | 5 | 100.00 |
| V1 | csr_rw | i2c_csr_rw | 0.840s | 29.292us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | i2c_csr_bit_bash | 5.130s | 1.832ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | i2c_csr_aliasing | 1.860s | 140.045us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | i2c_csr_mem_rw_with_rand_reset | 1.410s | 90.551us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | i2c_csr_rw | 0.840s | 29.292us | 20 | 20 | 100.00 |
| i2c_csr_aliasing | 1.860s | 140.045us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 155 | 155 | 100.00 | |||
| V2 | host_error_intr | i2c_host_error_intr | 10.030s | 231.098us | 50 | 50 | 100.00 |
| V2 | host_stress_all | i2c_host_stress_all | 58.507m | 18.050ms | 12 | 50 | 24.00 |
| V2 | host_maxperf | i2c_host_perf | 34.537m | 29.426ms | 49 | 50 | 98.00 |
| V2 | host_override | i2c_host_override | 0.750s | 25.880us | 50 | 50 | 100.00 |
| V2 | host_fifo_watermark | i2c_host_fifo_watermark | 6.999m | 51.880ms | 50 | 50 | 100.00 |
| V2 | host_fifo_overflow | i2c_host_fifo_overflow | 3.148m | 2.490ms | 50 | 50 | 100.00 |
| V2 | host_fifo_reset | i2c_host_fifo_reset_fmt | 1.370s | 422.809us | 50 | 50 | 100.00 |
| i2c_host_fifo_fmt_empty | 32.250s | 2.257ms | 50 | 50 | 100.00 | ||
| i2c_host_fifo_reset_rx | 11.360s | 1.869ms | 50 | 50 | 100.00 | ||
| V2 | host_fifo_full | i2c_host_fifo_full | 3.588m | 2.883ms | 50 | 50 | 100.00 |
| V2 | host_timeout | i2c_host_stretch_timeout | 44.840s | 4.047ms | 50 | 50 | 100.00 |
| V2 | host_rx_oversample | i2c_host_rx_oversample | 0 | 0 | -- | ||
| V2 | i2c_host_mode_toggle | i2c_host_mode_toggle | 1.770m | 9.146ms | 0 | 50 | 0.00 |
| V2 | target_error_intr | i2c_target_unexp_stop | 2.170s | 229.912us | 0 | 50 | 0.00 |
| V2 | target_glitch | i2c_target_glitch | 12.380s | 2.297ms | 2 | 2 | 100.00 |
| V2 | target_stress_all | i2c_target_stress_all | 55.417m | 54.710ms | 0 | 50 | 0.00 |
| V2 | target_maxperf | i2c_target_perf | 2.500s | 621.161us | 0 | 50 | 0.00 |
| V2 | target_fifo_empty | i2c_target_stress_rd | 1.377m | 7.921ms | 50 | 50 | 100.00 |
| i2c_target_intr_smoke | 8.870s | 1.576ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_reset | i2c_target_fifo_reset_acq | 1.800s | 411.461us | 50 | 50 | 100.00 |
| i2c_target_fifo_reset_tx | 1.970s | 293.557us | 50 | 50 | 100.00 | ||
| V2 | target_fifo_full | i2c_target_stress_wr | 45.249m | 62.834ms | 49 | 50 | 98.00 |
| i2c_target_stress_rd | 1.377m | 7.921ms | 50 | 50 | 100.00 | ||
| i2c_target_intr_stress_wr | 13.296m | 25.316ms | 50 | 50 | 100.00 | ||
| V2 | target_timeout | i2c_target_timeout | 8.670s | 3.434ms | 50 | 50 | 100.00 |
| V2 | target_clock_stretch | i2c_target_stretch | 3.790m | 4.285ms | 45 | 50 | 90.00 |
| V2 | bad_address | i2c_target_bad_addr | 8.030s | 6.486ms | 50 | 50 | 100.00 |
| V2 | target_mode_glitch | i2c_target_hrst | 43.420s | 10.083ms | 0 | 50 | 0.00 |
| V2 | target_fifo_watermark | i2c_target_fifo_watermarks_acq | 3.370s | 1.301ms | 50 | 50 | 100.00 |
| i2c_target_fifo_watermarks_tx | 1.680s | 225.145us | 49 | 50 | 98.00 | ||
| V2 | host_mode_config_perf | i2c_host_perf | 34.537m | 29.426ms | 49 | 50 | 98.00 |
| i2c_host_perf_precise | 15.424m | 23.229ms | 50 | 50 | 100.00 | ||
| V2 | host_mode_clock_stretching | i2c_host_stretch_timeout | 44.840s | 4.047ms | 50 | 50 | 100.00 |
| V2 | target_mode_tx_stretch_ctrl | i2c_target_tx_stretch_ctrl | 12.350s | 1.004ms | 49 | 50 | 98.00 |
| V2 | target_mode_nack_generation | i2c_target_nack_acqfull | 3.200s | 2.487ms | 50 | 50 | 100.00 |
| i2c_target_nack_acqfull_addr | 3.040s | 3.229ms | 50 | 50 | 100.00 | ||
| i2c_target_nack_txstretch | 41.700s | 20.000ms | 0 | 50 | 0.00 | ||
| V2 | host_mode_halt_on_nak | i2c_host_may_nack | 30.170s | 2.744ms | 50 | 50 | 100.00 |
| V2 | target_mode_n_byte_ack_control | target_mode_n_byte_ack_control | 0 | 0 | -- | ||
| V2 | target_mode_bus_timeout | target_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_timeout | controller_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_idle_delay | controller_mode_bus_idle_delay | 0 | 0 | -- | ||
| V2 | loopback_test | loopback_test | 0 | 0 | -- | ||
| V2 | multi_controller_clock_synchronization | multi_controller_clock_synchronization | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost_interference | multi_controller_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost | multi_controller_arbitration_lost | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost_interference | target_mode_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost | target_mode_arbitration_lost | 0 | 0 | -- | ||
| V2 | target_mode_smbus_maxlen | i2c_target_smbus_maxlen | 2.620s | 3.286ms | 50 | 50 | 100.00 |
| V2 | alert_test | i2c_alert_test | 0.690s | 28.714us | 50 | 50 | 100.00 |
| V2 | intr_test | i2c_intr_test | 0.770s | 18.192us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | i2c_tl_errors | 2.740s | 284.351us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | i2c_tl_errors | 2.740s | 284.351us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | i2c_csr_hw_reset | 0.790s | 23.195us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.840s | 29.292us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 1.860s | 140.045us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.220s | 220.023us | 19 | 20 | 95.00 | ||
| V2 | tl_d_partial_access | i2c_csr_hw_reset | 0.790s | 23.195us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.840s | 29.292us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 1.860s | 140.045us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.220s | 220.023us | 19 | 20 | 95.00 | ||
| V2 | TOTAL | 1494 | 1842 | 81.11 | |||
| V2S | tl_intg_err | i2c_tl_intg_err | 2.380s | 474.613us | 20 | 20 | 100.00 |
| i2c_sec_cm | 1.000s | 65.428us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | i2c_tl_intg_err | 2.380s | 474.613us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | host_stress_all_with_rand_reset | i2c_host_stress_all_with_rand_reset | 13.441m | 35.880ms | 0 | 10 | 0.00 |
| V3 | target_stress_all_with_rand_reset | i2c_target_stress_all_with_rand_reset | 1.959m | 11.305ms | 0 | 10 | 0.00 |
| V3 | target_loopback | 0 | 0 | -- | |||
| V3 | TOTAL | 0 | 20 | 0.00 | |||
| TOTAL | 1674 | 2042 | 81.98 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 7 | 7 | 7 | 100.00 |
| V2 | 50 | 39 | 26 | 52.00 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 3 | 2 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 91.03 | 97.09 | 89.46 | 97.22 | 70.83 | 94.04 | 98.44 | 90.11 |
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 124 failures:
0.i2c_target_perf.86643780107808557130337883791809710162597813517545020815170161563662593769837
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_perf/latest/run.log
UVM_ERROR @ 310610803 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (156 [0x9c] vs 114 [0x72])
UVM_INFO @ 310610803 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_perf.17358381015110868167367819792840640326121501771510502811944911096575388130640
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_perf/latest/run.log
UVM_ERROR @ 1004053281 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 0 [0x0])
UVM_INFO @ 1004053281 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 48 more failures.
0.i2c_target_stress_all.101927358777517648402254344333686810463890199255924116322601863400638581091271
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 24522663257 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 0 [0x0])
UVM_INFO @ 24522663257 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_stress_all.55725798985547815034996804960404843629408023204574482848699589575027819420107
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 85512881 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 147 [0x93])
UVM_INFO @ 85512881 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 39 more failures.
0.i2c_target_stress_all_with_rand_reset.36985812668190710425358997347683251959624108046600964951735557016973564901630
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 257839162 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 187 [0xbb])
UVM_INFO @ 257839162 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_stress_all_with_rand_reset.5340734271543474130843833970748788223411652450026407884628329193510561713326
Line 324, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 10550783090 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 171 [0xab])
UVM_INFO @ 10550783090 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
1.i2c_target_unexp_stop.46485521560914408715080022714790777933603522326295574114338942782149791075747
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 53037765 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 232 [0xe8])
UVM_INFO @ 53037765 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.i2c_target_unexp_stop.23592042592382195009637993432900306147786725292587773071042413681550620844945
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 188158015 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 97 [0x61])
UVM_INFO @ 188158015 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 28 more failures.
UVM_ERROR (i2c_scoreboard.sv:714) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 78 failures:
0.i2c_host_mode_toggle.89482771406444669281258877068565557318021785060581397681663550218186329895780
Line 255, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 2935904500 ps: (i2c_scoreboard.sv:714) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @14920
1.i2c_host_mode_toggle.79933773562854127491214712209808170534722287464208090625366163609667450345478
Line 255, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 1924310101 ps: (i2c_scoreboard.sv:714) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @20750
... and 47 more failures.
1.i2c_host_stress_all.64571452445752134499345028301126974336636931689543577998562383238197156723900
Line 287, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 12730800463 ps: (i2c_scoreboard.sv:714) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @1771837
3.i2c_host_stress_all.33693346476851794219522763484212139879801997061610916799324544371100176001398
Line 370, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 15489580676 ps: (i2c_scoreboard.sv:714) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @2643257
... and 27 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 36 failures:
0.i2c_target_nack_txstretch.111886904516776972599346511016863646222944294603285392097962826973646498202469
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_nack_txstretch/latest/run.log
UVM_FATAL @ 20000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 20000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 20000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_nack_txstretch.50116120965731527608994206676958570807511098478788577532498053352014691232585
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_nack_txstretch/latest/run.log
UVM_FATAL @ 20000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 20000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 20000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 34 more failures.
UVM_FATAL (i2c_monitor.sv:474) monitor [monitor] State at start of controller_collect_thread() is unexpected! has 31 failures:
0.i2c_target_hrst.37575182537998163748959454139643807801584075224960081532640808346229241757630
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log
UVM_FATAL @ 3879167 ps: (i2c_monitor.sv:474) uvm_test_top.env.m_i2c_agent.monitor [uvm_test_top.env.m_i2c_agent.monitor] State at start of controller_collect_thread() is unexpected!
UVM_INFO @ 3879167 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_hrst.89739577991015050889148313508734895297458008813426886802126637971204713224246
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_hrst/latest/run.log
UVM_FATAL @ 479050423 ps: (i2c_monitor.sv:474) uvm_test_top.env.m_i2c_agent.monitor [uvm_test_top.env.m_i2c_agent.monitor] State at start of controller_collect_thread() is unexpected!
UVM_INFO @ 479050423 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 29 more failures.
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 18 failures:
3.i2c_target_stress_all_with_rand_reset.74050884540252016115482243551253629591048497016901786114585339332710482487577
Line 257, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 11204559 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 11204559 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.i2c_target_stress_all_with_rand_reset.24182135343928629185877325758600080029901778642386449107611745535028813577096
Line 294, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_all_with_rand_reset/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 14621977010 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 14621977010 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
4.i2c_target_stress_all.6397993067815758219118739549906996304141018663744922462568798219055554446289
Line 276, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stress_all/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 46381059435 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 46381059435 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.i2c_target_stress_all.83132418974820427099421527756789181951801164156956713973116937913920255765566
Line 255, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_target_stress_all/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 1412233100 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 1412233100 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
5.i2c_target_unexp_stop.1946247631876691587850882294597855069220575071804212220096698803881251445892
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_target_unexp_stop/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 130238405 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 130238405 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
10.i2c_target_unexp_stop.31377543321744452728632472119541715893288149328278459285558942405454344814174
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/10.i2c_target_unexp_stop/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 181328306 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 181328306 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
UVM_ERROR (i2c_base_vseq.sv:1473) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 15 failures:
Test i2c_target_unexp_stop has 10 failures.
0.i2c_target_unexp_stop.95923921722099652960964970754337227177945357945930875705217975796843600409771
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 166211592 ps: (i2c_base_vseq.sv:1473) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 166211592 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_unexp_stop.94927039476455473737008041364340094269427584369762875669583165052576250072537
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 184338437 ps: (i2c_base_vseq.sv:1473) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 184338437 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
Test i2c_target_stress_all_with_rand_reset has 1 failures.
1.i2c_target_stress_all_with_rand_reset.38700123475396278850854523868182380876881055715327634854093826588162821721465
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 127085200 ps: (i2c_base_vseq.sv:1473) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 127085200 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test i2c_target_stress_all has 4 failures.
15.i2c_target_stress_all.86549892078852176417319912999896830236621041965577337900064470891239355767016
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/15.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 6957998019 ps: (i2c_base_vseq.sv:1473) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 6957998019 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
27.i2c_target_stress_all.104648492107100977108728649792014431251053725278747801944378476867222085721170
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/27.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 100850181 ps: (i2c_base_vseq.sv:1473) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 100850181 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 14 failures:
1.i2c_target_nack_txstretch.100871055707912653986761696940201418082969843927536354022445956819869714184942
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_nack_txstretch/latest/run.log
UVM_ERROR @ 265285578 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 265285578 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
9.i2c_target_nack_txstretch.109205620262732838597605102242869803094474582470420226426496532029843264967359
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/9.i2c_target_nack_txstretch/latest/run.log
UVM_ERROR @ 142691130 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 142691130 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 12 more failures.
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 13 failures:
1.i2c_target_hrst.110183830289358305265696190327765036743323404068415920426180222894740808064680
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10206608584 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10206608584 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.i2c_target_hrst.72400236987470711128710918511188394388861458461677109067157584481297720120885
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10338284294 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10338284294 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 11 more failures.
Job i2c-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 11 failures:
Test i2c_host_stress_all_with_rand_reset has 2 failures.
1.i2c_host_stress_all_with_rand_reset.71459650357886818294074173543133421450328600471727907764736891459466883871243
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log
Job ID: smart:9a108b73-e6a3-44e3-8649-86202d4432b6
3.i2c_host_stress_all_with_rand_reset.101000834842944138853974234445987230368040057906172309428093140703169106636841
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_host_stress_all_with_rand_reset/latest/run.log
Job ID: smart:346c5882-f6bf-4da6-bae8-188b759adb64
Test i2c_host_stress_all has 6 failures.
2.i2c_host_stress_all.91002462310394971939800254668286060332554475221155930220148293441034025628721
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_stress_all/latest/run.log
Job ID: smart:d2145f77-4687-4b30-9c16-a74608d380d8
15.i2c_host_stress_all.97495833278139211739087375086342960283445083952179873953991665817260149015476
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/15.i2c_host_stress_all/latest/run.log
Job ID: smart:295bd06b-34ed-4b51-9160-3868ebe82a7f
... and 4 more failures.
Test i2c_host_mode_toggle has 1 failures.
19.i2c_host_mode_toggle.45072801748644261819918143601339795641050285149881768286032623326666193341605
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/19.i2c_host_mode_toggle/latest/run.log
Job ID: smart:92346ea2-d3b7-445c-a5c4-e8462cc620f4
Test i2c_target_stress_wr has 1 failures.
35.i2c_target_stress_wr.100473824079844840506413592796761263892463699579767001561638503513728693813584
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/35.i2c_target_stress_wr/latest/run.log
Job ID: smart:87e0d09a-30f0-4e4e-9f09-a64c6deb2649
Test i2c_host_perf has 1 failures.
37.i2c_host_perf.25349922884076439148553797428515293227786601637125729731213596368953851232518
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/37.i2c_host_perf/latest/run.log
Job ID: smart:c901d68b-448a-4e2d-b0e1-b8c2e2020c16
UVM_ERROR (cip_base_vseq.sv:825) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 9 failures:
0.i2c_host_stress_all_with_rand_reset.66555945886072557696116264871446873190633048800098099693979943412715854232859
Line 300, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 61610801776 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 61610801776 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_host_stress_all_with_rand_reset.47957888433021826814275861796635975267560540170790972105451187796977603077073
Line 344, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 19935816121 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 19935816121 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
8.i2c_target_stress_all_with_rand_reset.20331769429129644093998477770203910899740594438567930200693920243630509003615
Line 266, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 5159578364 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 5159578364 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:384) [stop_interrupt_handler] wait timeout occurred! has 6 failures:
7.i2c_target_hrst.104397235286204935546405563956872780632481613726009021528786066853817274121027
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10004059640 ps: (i2c_target_hrst_vseq.sv:384) [stop_interrupt_handler] wait timeout occurred!
UVM_INFO @ 10004059640 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
13.i2c_target_hrst.78788145348031794007691057463415493614632516975139482024828263863605483563797
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/13.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10093812085 ps: (i2c_target_hrst_vseq.sv:384) [stop_interrupt_handler] wait timeout occurred!
UVM_INFO @ 10093812085 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred! has 5 failures:
3.i2c_target_stretch.56630494280221644599506729672001042615764327065967791496378066266535079058813
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stretch/latest/run.log
UVM_FATAL @ 10006461105 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
UVM_INFO @ 10006461105 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.i2c_target_stretch.54064406199693707410858755680642086314815564575505217453413267515788687224293
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_stretch/latest/run.log
UVM_FATAL @ 10009370708 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
UVM_INFO @ 10009370708 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_FATAL (i2c_base_vseq.sv:717) [i2c_target_perf_vseq] wait timeout occurred! has 2 failures:
6.i2c_target_stress_all_with_rand_reset.51865934813246101165173213875575315517382070870502559870651490245923828472548
Line 293, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 14809192986 ps: (i2c_base_vseq.sv:717) [uvm_test_top.env.virtual_sequencer.i2c_target_perf_vseq] wait timeout occurred!
UVM_INFO @ 14809192986 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.i2c_target_stress_all_with_rand_reset.70292941617555011760759849451023629983760760946636884080447084703636728241019
Line 299, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/7.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 14691799317 ps: (i2c_base_vseq.sv:717) [uvm_test_top.env.virtual_sequencer.i2c_target_perf_vseq] wait timeout occurred!
UVM_INFO @ 14691799317 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:715) [scoreboard] controller_mode_wr_obs_fifo item uncompared: has 2 failures:
11.i2c_host_stress_all.17892766159045622826285776675541577020911179631260641573114098257231082482966
Line 321, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/11.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 64103994826 ps: (i2c_scoreboard.sv:715) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @20403265
27.i2c_host_stress_all.29914094587174099518366288962585626706889896453057600680830007094023930031762
Line 366, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/27.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 42270284149 ps: (i2c_scoreboard.sv:715) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @3635355
Error-[CNST-CIF] Constraints inconsistency failure has 2 failures:
Test i2c_target_fifo_watermarks_tx has 1 failures.
19.i2c_target_fifo_watermarks_tx.20638352446188474820595899746649628360380565007749048349048340568278099513860
Line 292, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/19.i2c_target_fifo_watermarks_tx/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 844
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
Test i2c_target_tx_stretch_ctrl has 1 failures.
47.i2c_target_tx_stretch_ctrl.52230621756153463765209138437503964219185758014229198573076434100093968793694
Line 295, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/47.i2c_target_tx_stretch_ctrl/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 871
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
UVM_ERROR (cip_base_vseq.sv:500) [i2c_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) has 1 failures:
0.i2c_same_csr_outstanding.22113844473899320523245686517931461275859382247432521885425112050891288801029
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_same_csr_outstanding/latest/run.log
UVM_ERROR @ 38801713 ps: (cip_base_vseq.sv:500) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed data & ~ro_mask == 0 (64 [0x40] vs 0 [0x0])
UVM_INFO @ 38801713 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.fmtfull (addr=*) == * has 1 failures:
40.i2c_host_stress_all.44272236307008732753489248395773187935558421653213632075406706763987983638306
Line 273, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/40.i2c_host_stress_all/latest/run.log
UVM_FATAL @ 11847247977 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.fmtfull (addr=0x2a818894) == 0x0
UVM_INFO @ 11847247977 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---