5967df933a| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | host_smoke | i2c_host_smoke | 1.888m | 2.203ms | 50 | 50 | 100.00 |
| V1 | target_smoke | i2c_target_smoke | 37.180s | 2.439ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | i2c_csr_hw_reset | 0.760s | 43.862us | 5 | 5 | 100.00 |
| V1 | csr_rw | i2c_csr_rw | 4.250s | 2.246ms | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | i2c_csr_bit_bash | 5.310s | 1.533ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | i2c_csr_aliasing | 2.000s | 111.757us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | i2c_csr_mem_rw_with_rand_reset | 1.470s | 209.699us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | i2c_csr_rw | 4.250s | 2.246ms | 20 | 20 | 100.00 |
| i2c_csr_aliasing | 2.000s | 111.757us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 155 | 155 | 100.00 | |||
| V2 | host_error_intr | i2c_host_error_intr | 12.700s | 1.461ms | 50 | 50 | 100.00 |
| V2 | host_stress_all | i2c_host_stress_all | 55.179m | 62.002ms | 17 | 50 | 34.00 |
| V2 | host_maxperf | i2c_host_perf | 46.124m | 69.705ms | 47 | 50 | 94.00 |
| V2 | host_override | i2c_host_override | 0.770s | 82.686us | 50 | 50 | 100.00 |
| V2 | host_fifo_watermark | i2c_host_fifo_watermark | 6.910m | 5.259ms | 50 | 50 | 100.00 |
| V2 | host_fifo_overflow | i2c_host_fifo_overflow | 3.384m | 5.291ms | 50 | 50 | 100.00 |
| V2 | host_fifo_reset | i2c_host_fifo_reset_fmt | 1.370s | 157.561us | 50 | 50 | 100.00 |
| i2c_host_fifo_fmt_empty | 27.830s | 1.556ms | 50 | 50 | 100.00 | ||
| i2c_host_fifo_reset_rx | 12.890s | 1.271ms | 50 | 50 | 100.00 | ||
| V2 | host_fifo_full | i2c_host_fifo_full | 3.782m | 2.800ms | 50 | 50 | 100.00 |
| V2 | host_timeout | i2c_host_stretch_timeout | 44.300s | 7.327ms | 50 | 50 | 100.00 |
| V2 | host_rx_oversample | i2c_host_rx_oversample | 0 | 0 | -- | ||
| V2 | i2c_host_mode_toggle | i2c_host_mode_toggle | 1.881m | 8.677ms | 0 | 50 | 0.00 |
| V2 | target_error_intr | i2c_target_unexp_stop | 3.950s | 4.558ms | 0 | 50 | 0.00 |
| V2 | target_glitch | i2c_target_glitch | 11.920s | 9.563ms | 2 | 2 | 100.00 |
| V2 | target_stress_all | i2c_target_stress_all | 16.773m | 44.628ms | 0 | 50 | 0.00 |
| V2 | target_maxperf | i2c_target_perf | 2.290s | 924.822us | 0 | 50 | 0.00 |
| V2 | target_fifo_empty | i2c_target_stress_rd | 1.265m | 6.302ms | 50 | 50 | 100.00 |
| i2c_target_intr_smoke | 9.010s | 1.412ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_reset | i2c_target_fifo_reset_acq | 1.960s | 803.328us | 50 | 50 | 100.00 |
| i2c_target_fifo_reset_tx | 2.030s | 314.847us | 50 | 50 | 100.00 | ||
| V2 | target_fifo_full | i2c_target_stress_wr | 30.745m | 52.748ms | 50 | 50 | 100.00 |
| i2c_target_stress_rd | 1.265m | 6.302ms | 50 | 50 | 100.00 | ||
| i2c_target_intr_stress_wr | 9.644m | 24.165ms | 50 | 50 | 100.00 | ||
| V2 | target_timeout | i2c_target_timeout | 8.770s | 3.115ms | 50 | 50 | 100.00 |
| V2 | target_clock_stretch | i2c_target_stretch | 3.179m | 5.022ms | 44 | 50 | 88.00 |
| V2 | bad_address | i2c_target_bad_addr | 8.230s | 2.906ms | 50 | 50 | 100.00 |
| V2 | target_mode_glitch | i2c_target_hrst | 41.310s | 10.011ms | 0 | 50 | 0.00 |
| V2 | target_fifo_watermark | i2c_target_fifo_watermarks_acq | 3.890s | 3.128ms | 50 | 50 | 100.00 |
| i2c_target_fifo_watermarks_tx | 1.610s | 1.208ms | 48 | 50 | 96.00 | ||
| V2 | host_mode_config_perf | i2c_host_perf | 46.124m | 69.705ms | 47 | 50 | 94.00 |
| i2c_host_perf_precise | 3.879m | 5.819ms | 50 | 50 | 100.00 | ||
| V2 | host_mode_clock_stretching | i2c_host_stretch_timeout | 44.300s | 7.327ms | 50 | 50 | 100.00 |
| V2 | target_mode_tx_stretch_ctrl | i2c_target_tx_stretch_ctrl | 16.330s | 1.304ms | 49 | 50 | 98.00 |
| V2 | target_mode_nack_generation | i2c_target_nack_acqfull | 3.370s | 612.225us | 50 | 50 | 100.00 |
| i2c_target_nack_acqfull_addr | 3.110s | 603.003us | 50 | 50 | 100.00 | ||
| i2c_target_nack_txstretch | 44.210s | 20.000ms | 0 | 50 | 0.00 | ||
| V2 | host_mode_halt_on_nak | i2c_host_may_nack | 25.600s | 3.478ms | 50 | 50 | 100.00 |
| V2 | target_mode_n_byte_ack_control | target_mode_n_byte_ack_control | 0 | 0 | -- | ||
| V2 | target_mode_bus_timeout | target_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_timeout | controller_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_idle_delay | controller_mode_bus_idle_delay | 0 | 0 | -- | ||
| V2 | loopback_test | loopback_test | 0 | 0 | -- | ||
| V2 | multi_controller_clock_synchronization | multi_controller_clock_synchronization | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost_interference | multi_controller_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost | multi_controller_arbitration_lost | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost_interference | target_mode_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost | target_mode_arbitration_lost | 0 | 0 | -- | ||
| V2 | target_mode_smbus_maxlen | i2c_target_smbus_maxlen | 2.550s | 2.711ms | 50 | 50 | 100.00 |
| V2 | alert_test | i2c_alert_test | 0.720s | 50.671us | 50 | 50 | 100.00 |
| V2 | intr_test | i2c_intr_test | 0.770s | 15.637us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | i2c_tl_errors | 2.670s | 168.708us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | i2c_tl_errors | 2.670s | 168.708us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | i2c_csr_hw_reset | 0.760s | 43.862us | 5 | 5 | 100.00 |
| i2c_csr_rw | 4.250s | 2.246ms | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 2.000s | 111.757us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.190s | 65.151us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | i2c_csr_hw_reset | 0.760s | 43.862us | 5 | 5 | 100.00 |
| i2c_csr_rw | 4.250s | 2.246ms | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 2.000s | 111.757us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.190s | 65.151us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 1497 | 1842 | 81.27 | |||
| V2S | tl_intg_err | i2c_tl_intg_err | 2.440s | 152.946us | 20 | 20 | 100.00 |
| i2c_sec_cm | 1.120s | 686.327us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | i2c_tl_intg_err | 2.440s | 152.946us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | host_stress_all_with_rand_reset | i2c_host_stress_all_with_rand_reset | 7.414m | 6.262ms | 0 | 10 | 0.00 |
| V3 | target_stress_all_with_rand_reset | i2c_target_stress_all_with_rand_reset | 3.547m | 11.193ms | 0 | 10 | 0.00 |
| V3 | target_loopback | 0 | 0 | -- | |||
| V3 | TOTAL | 0 | 20 | 0.00 | |||
| TOTAL | 1677 | 2042 | 82.13 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 7 | 7 | 7 | 100.00 |
| V2 | 50 | 39 | 28 | 56.00 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 3 | 2 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 91.16 | 97.15 | 90.03 | 97.22 | 71.43 | 94.18 | 98.44 | 89.68 |
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 128 failures:
0.i2c_target_perf.44615992219630571974442862180264497355194953089426695181208554288218640918185
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_perf/latest/run.log
UVM_ERROR @ 74363201 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 0 [0x0])
UVM_INFO @ 74363201 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_perf.56529927041164746307890839153589786755900161327473734839006933660917507403164
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_perf/latest/run.log
UVM_ERROR @ 556733847 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 0 [0x0])
UVM_INFO @ 556733847 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 48 more failures.
0.i2c_target_stress_all.457335615746860687372026538049275194457720383667339761926501725772282440632
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 15370148121 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (234 [0xea] vs 196 [0xc4])
UVM_INFO @ 15370148121 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_stress_all.47936148697150774868508979374489536022154714663484216882292167629104295933390
Line 261, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 972055168 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (199 [0xc7] vs 94 [0x5e])
UVM_INFO @ 972055168 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 39 more failures.
1.i2c_target_stress_all_with_rand_reset.67320400538455168729054842841658337082814171318238907667146785185405933788435
Line 414, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 11193105918 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (183 [0xb7] vs 255 [0xff])
UVM_INFO @ 11193105918 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.i2c_target_stress_all_with_rand_reset.88912204332614880134404287640959554479062700424535010911838364718393166908872
Line 278, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 5511840211 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (56 [0x38] vs 53 [0x35])
UVM_INFO @ 5511840211 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
2.i2c_target_unexp_stop.39933917109953847238499970245856332863357303927106373909257207916860144928432
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 82301661 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 241 [0xf1])
UVM_INFO @ 82301661 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.i2c_target_unexp_stop.113270395692028870425076474522462922756354863346082257228542604484579888618060
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 176798130 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 232 [0xe8])
UVM_INFO @ 176798130 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 30 more failures.
UVM_ERROR (i2c_scoreboard.sv:714) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 74 failures:
0.i2c_host_stress_all.65491289482015283265872426995825576265943917444602008747064526227967452556407
Line 424, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 9306112496 ps: (i2c_scoreboard.sv:714) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @3002887
1.i2c_host_stress_all.6222057551305540043943276565245053283993881023343270837782543530270160984890
Line 300, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 68000611351 ps: (i2c_scoreboard.sv:714) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @651518
... and 22 more failures.
0.i2c_host_mode_toggle.68537864414800259096118040842156333789864619401820247012455228043347484785521
Line 255, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 1039288163 ps: (i2c_scoreboard.sv:714) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @87236
1.i2c_host_mode_toggle.99593568703532296518351194594364378107690384098099659036141528898621438683407
Line 255, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 12117986901 ps: (i2c_scoreboard.sv:714) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @196380
... and 48 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 33 failures:
0.i2c_target_nack_txstretch.39300431467494711204369732939329571621018090505349286697954791755965733554492
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_nack_txstretch/latest/run.log
UVM_FATAL @ 20000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 20000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 20000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_nack_txstretch.50966301553976948169499402107093238181614025627868801787587271654037400667569
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_nack_txstretch/latest/run.log
UVM_FATAL @ 20000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 20000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 20000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 31 more failures.
UVM_FATAL (i2c_monitor.sv:474) monitor [monitor] State at start of controller_collect_thread() is unexpected! has 26 failures:
0.i2c_target_hrst.14578330177193740670128823636569334123977630611063755401104823544408700399713
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log
UVM_FATAL @ 129130264 ps: (i2c_monitor.sv:474) uvm_test_top.env.m_i2c_agent.monitor [uvm_test_top.env.m_i2c_agent.monitor] State at start of controller_collect_thread() is unexpected!
UVM_INFO @ 129130264 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_hrst.27594767305023382452399916081811647636850452820869165841907818636671576488173
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_hrst/latest/run.log
UVM_FATAL @ 267356191 ps: (i2c_monitor.sv:474) uvm_test_top.env.m_i2c_agent.monitor [uvm_test_top.env.m_i2c_agent.monitor] State at start of controller_collect_thread() is unexpected!
UVM_INFO @ 267356191 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 24 more failures.
UVM_ERROR (i2c_base_vseq.sv:1473) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 19 failures:
0.i2c_target_unexp_stop.86403154463584752149695324840937546714090017644386256055713794568475634981512
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 186443437 ps: (i2c_base_vseq.sv:1473) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 186443437 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.i2c_target_unexp_stop.33122493595187000465635015526474588039272338119490738216630322208218117786496
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/4.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 365357951 ps: (i2c_base_vseq.sv:1473) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 365357951 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 13 more failures.
18.i2c_target_stress_all.58805331167339721597453495626385406844743605651311585610855844377073410719941
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/18.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 103388023 ps: (i2c_base_vseq.sv:1473) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 103388023 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
20.i2c_target_stress_all.39031090425128108462300437319293885002816808143682941603716439773612740819627
Line 254, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/20.i2c_target_stress_all/latest/run.log
UVM_ERROR @ 260948321 ps: (i2c_base_vseq.sv:1473) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 260948321 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 17 failures:
2.i2c_target_nack_txstretch.28250220170982165436744255686454043385257259268476562641742450451811559337639
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_nack_txstretch/latest/run.log
UVM_ERROR @ 170654054 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 170654054 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.i2c_target_nack_txstretch.95788707050545867922316718869442009094586461195239275217856274163758615819998
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_nack_txstretch/latest/run.log
UVM_ERROR @ 594679788 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 594679788 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 15 more failures.
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 14 failures:
2.i2c_target_hrst.41498131052759691696881353529839836666440398775404111305307207632305904552907
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_hrst/latest/run.log
UVM_FATAL @ 12275736874 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 12275736874 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.i2c_target_hrst.74939744080342242601233277598545246726683751208259937305483295189144931133151
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10105708227 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10105708227 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 12 more failures.
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 12 failures:
0.i2c_target_stress_all_with_rand_reset.54675802771231428339790962472594524899766825306472650521206379882308612520958
Line 314, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 7808041828 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 7808041828 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_stress_all_with_rand_reset.76186222242911847868786270712593275079882290834199601561904801992915817708047
Line 257, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 33362491 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 33362491 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
1.i2c_target_unexp_stop.22200377256653168710356155473220458628680846948671586836795365957372149230889
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 60707368 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 60707368 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
15.i2c_target_unexp_stop.99598256304738266966345478262162595981558148060978156598918847804230152990713
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/15.i2c_target_unexp_stop/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 173773904 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 173773904 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
3.i2c_target_stress_all.51515123770221916469167272443995008689349655530476820765597106262112925930237
Line 262, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 1854976415 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 1854976415 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
17.i2c_target_stress_all.21339630337345560331951729995664995105622815673844167648388798609241789253914
Line 262, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/17.i2c_target_stress_all/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 2702044627 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 2702044627 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
Job i2c-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 12 failures:
Test i2c_host_perf has 3 failures.
2.i2c_host_perf.38579441853818172250299021141909856661246741068158895529535625406347790846069
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_host_perf/latest/run.log
Job ID: smart:fb1d0673-7d67-4314-bc91-3086d85ce6fb
12.i2c_host_perf.37550573234384065387925887790114325275854888577973844168454340215533096564851
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/12.i2c_host_perf/latest/run.log
Job ID: smart:b612a77b-ee9d-4ce8-a734-d97eb4145348
... and 1 more failures.
Test i2c_host_stress_all_with_rand_reset has 2 failures.
3.i2c_host_stress_all_with_rand_reset.12952934774638681746652138251297308652318482603475038444578726696665788211653
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_host_stress_all_with_rand_reset/latest/run.log
Job ID: smart:b455d9b8-8e7b-4e92-9ccb-f954632c16ef
5.i2c_host_stress_all_with_rand_reset.115135285831057643615238482810541917258991549716445718181038131837235361277145
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/5.i2c_host_stress_all_with_rand_reset/latest/run.log
Job ID: smart:aca1787a-3399-44a8-be49-8d85395c0202
Test i2c_host_stress_all has 7 failures.
17.i2c_host_stress_all.15267896034020808051041168024520698770374307622757406750803974474859315339690
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/17.i2c_host_stress_all/latest/run.log
Job ID: smart:d86d75c2-d116-4266-a5ea-8d717b82c22a
18.i2c_host_stress_all.48025729164363027721963474791319153599442398386721605593454055435419407175442
Log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/18.i2c_host_stress_all/latest/run.log
Job ID: smart:cc50f010-3bf4-4927-9b79-a8e0bb01a540
... and 5 more failures.
UVM_FATAL (i2c_target_hrst_vseq.sv:384) [stop_interrupt_handler] wait timeout occurred! has 10 failures:
3.i2c_target_hrst.9477647529832142644574098163580829292916718446362007957067883217498784934363
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10004807223 ps: (i2c_target_hrst_vseq.sv:384) [stop_interrupt_handler] wait timeout occurred!
UVM_INFO @ 10004807223 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.i2c_target_hrst.14065751276465137628147639783551528945922335857788826549871301615820308957902
Line 251, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/8.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10002112437 ps: (i2c_target_hrst_vseq.sv:384) [stop_interrupt_handler] wait timeout occurred!
UVM_INFO @ 10002112437 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
UVM_ERROR (cip_base_vseq.sv:825) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 8 failures:
0.i2c_host_stress_all_with_rand_reset.52377924224675379833568305501955092412192502590875393235824076617905898059324
Line 324, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 5576974274 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 5576974274 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_host_stress_all_with_rand_reset.109552846636067697675132742457584838437382849127931434894901597421770801512983
Line 256, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 107973388 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 107973388 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred! has 6 failures:
2.i2c_target_stretch.82421472442450205411856359764185900660164074061904493192968129208703673707881
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/2.i2c_target_stretch/latest/run.log
UVM_FATAL @ 10047610059 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
UVM_INFO @ 10047610059 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
19.i2c_target_stretch.17749596043276444225663984062816075549035967006462648269688210504214625646896
Line 250, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/19.i2c_target_stretch/latest/run.log
UVM_FATAL @ 10023443326 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
UVM_INFO @ 10023443326 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
Error-[CNST-CIF] Constraints inconsistency failure has 3 failures:
Test i2c_target_tx_stretch_ctrl has 1 failures.
6.i2c_target_tx_stretch_ctrl.7017429031836037039535450097891982562692641456178840038041907576820645915643
Line 295, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/6.i2c_target_tx_stretch_ctrl/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 871
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
Test i2c_target_fifo_watermarks_tx has 2 failures.
31.i2c_target_fifo_watermarks_tx.13419016792997396501321138921023431582787879733764949113178936047018436519258
Line 292, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/31.i2c_target_fifo_watermarks_tx/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 844
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
37.i2c_target_fifo_watermarks_tx.72544782414428188950010393839327566714186621464414754276594433907519540303126
Line 292, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/37.i2c_target_fifo_watermarks_tx/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 844
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
UVM_ERROR (i2c_base_vseq.sv:760) [i2c_target_ack_stop_vseq] Check failed (cfg.m_i2c_agent_cfg.rcvd_rd_byte == *) has 1 failures:
3.i2c_target_stress_all_with_rand_reset.53981763130326087370632176054499436803952121695744445294944092598603942288789
Line 268, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 30834626 ps: (i2c_base_vseq.sv:760) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed (cfg.m_i2c_agent_cfg.rcvd_rd_byte == 0)
UVM_INFO @ 30834626 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:715) [scoreboard] controller_mode_wr_obs_fifo item uncompared: has 1 failures:
23.i2c_host_stress_all.112390672750540616050553571768049642132676941801841693348666746741753102920559
Line 296, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/23.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 30978244501 ps: (i2c_scoreboard.sv:715) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @2806371
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 1 failures:
32.i2c_host_stress_all.17379241636277864598024521810385652938126957522032942255505894434809043552106
Line 262, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/32.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 194780552 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------