| T1565 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/42.i2c_host_fifo_watermark.167759525 |
|
|
Sep 18 08:16:20 AM UTC 24 |
Sep 18 08:18:01 AM UTC 24 |
57462582033 ps |
| T1566 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/45.i2c_host_stretch_timeout.2199193199 |
|
|
Sep 18 08:17:52 AM UTC 24 |
Sep 18 08:18:03 AM UTC 24 |
2623129913 ps |
| T1567 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/40.i2c_host_fifo_overflow.1190797226 |
|
|
Sep 18 08:15:29 AM UTC 24 |
Sep 18 08:18:04 AM UTC 24 |
2680992706 ps |
| T1568 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/45.i2c_host_fifo_fmt_empty.3808872232 |
|
|
Sep 18 08:17:51 AM UTC 24 |
Sep 18 08:18:06 AM UTC 24 |
503670140 ps |
| T1569 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/47.i2c_host_error_intr.2304236990 |
|
|
Sep 18 08:19:14 AM UTC 24 |
Sep 18 08:19:22 AM UTC 24 |
122597603 ps |
| T1570 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/45.i2c_target_intr_smoke.3521990007 |
|
|
Sep 18 08:17:58 AM UTC 24 |
Sep 18 08:18:06 AM UTC 24 |
4650544374 ps |
| T1571 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/45.i2c_host_smoke.1118717688 |
|
|
Sep 18 08:17:48 AM UTC 24 |
Sep 18 08:18:07 AM UTC 24 |
2440101861 ps |
| T1572 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/45.i2c_host_perf_precise.1028316981 |
|
|
Sep 18 08:17:52 AM UTC 24 |
Sep 18 08:18:07 AM UTC 24 |
600972589 ps |
| T1573 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/47.i2c_host_perf.2711420973 |
|
|
Sep 18 08:19:11 AM UTC 24 |
Sep 18 08:19:25 AM UTC 24 |
2304999746 ps |
| T1574 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/45.i2c_target_fifo_reset_acq.2363714420 |
|
|
Sep 18 08:18:05 AM UTC 24 |
Sep 18 08:18:08 AM UTC 24 |
894703896 ps |
| T1575 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/45.i2c_target_stress_rd.131697275 |
|
|
Sep 18 08:17:55 AM UTC 24 |
Sep 18 08:18:08 AM UTC 24 |
9686513576 ps |
| T92 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/45.i2c_target_fifo_reset_tx.352376509 |
|
|
Sep 18 08:18:07 AM UTC 24 |
Sep 18 08:18:11 AM UTC 24 |
598030809 ps |
| T1576 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/45.i2c_target_timeout.37965878 |
|
|
Sep 18 08:18:02 AM UTC 24 |
Sep 18 08:18:11 AM UTC 24 |
10991308149 ps |
| T1577 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/45.i2c_host_mode_toggle.2169010757 |
|
|
Sep 18 08:18:08 AM UTC 24 |
Sep 18 08:18:11 AM UTC 24 |
1039605121 ps |
| T1578 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/44.i2c_host_fifo_full.446283550 |
|
|
Sep 18 08:17:20 AM UTC 24 |
Sep 18 08:18:13 AM UTC 24 |
1920527423 ps |
| T1579 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/45.i2c_target_perf.2195587531 |
|
|
Sep 18 08:18:07 AM UTC 24 |
Sep 18 08:18:13 AM UTC 24 |
4981418606 ps |
| T1580 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/45.i2c_target_fifo_watermarks_acq.2521746481 |
|
|
Sep 18 08:18:09 AM UTC 24 |
Sep 18 08:18:13 AM UTC 24 |
251411964 ps |
| T1581 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/43.i2c_host_smoke.302916829 |
|
|
Sep 18 08:16:44 AM UTC 24 |
Sep 18 08:18:14 AM UTC 24 |
6994381425 ps |
| T1582 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/45.i2c_target_fifo_watermarks_tx.3038453890 |
|
|
Sep 18 08:18:11 AM UTC 24 |
Sep 18 08:18:14 AM UTC 24 |
273028050 ps |
| T1583 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/45.i2c_target_bad_addr.3514884466 |
|
|
Sep 18 08:18:08 AM UTC 24 |
Sep 18 08:18:15 AM UTC 24 |
3609000368 ps |
| T1584 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/45.i2c_target_tx_stretch_ctrl.3674497666 |
|
|
Sep 18 08:18:12 AM UTC 24 |
Sep 18 08:18:15 AM UTC 24 |
114384652 ps |
| T1585 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/45.i2c_target_intr_stress_wr.184190623 |
|
|
Sep 18 08:17:59 AM UTC 24 |
Sep 18 08:18:17 AM UTC 24 |
3407414462 ps |
| T1586 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/45.i2c_target_stretch.1498494228 |
|
|
Sep 18 08:17:56 AM UTC 24 |
Sep 18 08:18:17 AM UTC 24 |
1845737755 ps |
| T1587 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/45.i2c_host_may_nack.842447753 |
|
|
Sep 18 08:18:08 AM UTC 24 |
Sep 18 08:18:17 AM UTC 24 |
463512600 ps |
| T1588 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/45.i2c_alert_test.1152956148 |
|
|
Sep 18 08:18:15 AM UTC 24 |
Sep 18 08:18:17 AM UTC 24 |
44045593 ps |
| T1589 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/45.i2c_target_nack_txstretch.3880484183 |
|
|
Sep 18 08:18:14 AM UTC 24 |
Sep 18 08:18:17 AM UTC 24 |
1094580775 ps |
| T1590 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/45.i2c_target_smbus_maxlen.2182402361 |
|
|
Sep 18 08:18:13 AM UTC 24 |
Sep 18 08:18:18 AM UTC 24 |
1681306004 ps |
| T1591 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/46.i2c_host_override.1914205176 |
|
|
Sep 18 08:18:16 AM UTC 24 |
Sep 18 08:18:18 AM UTC 24 |
27547433 ps |
| T1592 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/45.i2c_target_nack_acqfull.1861409497 |
|
|
Sep 18 08:18:14 AM UTC 24 |
Sep 18 08:18:18 AM UTC 24 |
3626580002 ps |
| T1593 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/45.i2c_target_nack_acqfull_addr.3033850131 |
|
|
Sep 18 08:18:14 AM UTC 24 |
Sep 18 08:18:18 AM UTC 24 |
1767669953 ps |
| T1594 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_reset_fmt.2271144721 |
|
|
Sep 18 08:18:17 AM UTC 24 |
Sep 18 08:18:19 AM UTC 24 |
485474676 ps |
| T1595 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/46.i2c_host_perf_precise.617797137 |
|
|
Sep 18 08:18:18 AM UTC 24 |
Sep 18 08:18:21 AM UTC 24 |
44101437 ps |
| T1596 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/46.i2c_host_error_intr.3757917388 |
|
|
Sep 18 08:18:20 AM UTC 24 |
Sep 18 08:18:23 AM UTC 24 |
372909627 ps |
| T1597 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_reset_rx.430476427 |
|
|
Sep 18 08:18:17 AM UTC 24 |
Sep 18 08:18:25 AM UTC 24 |
365321789 ps |
| T1598 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/45.i2c_host_fifo_overflow.24697520 |
|
|
Sep 18 08:17:50 AM UTC 24 |
Sep 18 08:18:30 AM UTC 24 |
2826142000 ps |
| T1599 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/46.i2c_target_stress_rd.900355198 |
|
|
Sep 18 08:18:24 AM UTC 24 |
Sep 18 08:18:31 AM UTC 24 |
1356451928 ps |
| T1600 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/45.i2c_target_smoke.3210022452 |
|
|
Sep 18 08:17:53 AM UTC 24 |
Sep 18 08:18:31 AM UTC 24 |
4797370285 ps |
| T1601 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_fmt_empty.2209803340 |
|
|
Sep 18 08:18:17 AM UTC 24 |
Sep 18 08:18:36 AM UTC 24 |
278153802 ps |
| T1602 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/43.i2c_target_stress_wr.2079315946 |
|
|
Sep 18 08:16:52 AM UTC 24 |
Sep 18 08:18:40 AM UTC 24 |
47517531788 ps |
| T1603 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/44.i2c_host_fifo_overflow.2957244405 |
|
|
Sep 18 08:17:20 AM UTC 24 |
Sep 18 08:18:41 AM UTC 24 |
14238707497 ps |
| T1604 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/46.i2c_target_timeout.4201079020 |
|
|
Sep 18 08:18:32 AM UTC 24 |
Sep 18 08:18:43 AM UTC 24 |
1457761718 ps |
| T1605 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/46.i2c_target_fifo_reset_acq.1339604410 |
|
|
Sep 18 08:18:40 AM UTC 24 |
Sep 18 08:18:43 AM UTC 24 |
283309574 ps |
| T1606 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/46.i2c_target_fifo_reset_tx.4083139091 |
|
|
Sep 18 08:18:41 AM UTC 24 |
Sep 18 08:18:44 AM UTC 24 |
367419630 ps |
| T1607 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/46.i2c_target_intr_smoke.868968797 |
|
|
Sep 18 08:18:31 AM UTC 24 |
Sep 18 08:18:45 AM UTC 24 |
1108390872 ps |
| T1608 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/46.i2c_host_mode_toggle.1989800769 |
|
|
Sep 18 08:18:46 AM UTC 24 |
Sep 18 08:18:49 AM UTC 24 |
834881583 ps |
| T1609 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/46.i2c_target_perf.3072803186 |
|
|
Sep 18 08:18:41 AM UTC 24 |
Sep 18 08:18:52 AM UTC 24 |
2085200392 ps |
| T1610 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/46.i2c_target_bad_addr.1030417099 |
|
|
Sep 18 08:18:44 AM UTC 24 |
Sep 18 08:18:53 AM UTC 24 |
878154735 ps |
| T1611 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/45.i2c_host_perf.2090612490 |
|
|
Sep 18 08:17:51 AM UTC 24 |
Sep 18 08:18:53 AM UTC 24 |
12332971634 ps |
| T1612 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/46.i2c_target_fifo_watermarks_tx.3186677917 |
|
|
Sep 18 08:18:54 AM UTC 24 |
Sep 18 08:18:57 AM UTC 24 |
208583180 ps |
| T1613 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/46.i2c_target_smoke.1929093613 |
|
|
Sep 18 08:18:21 AM UTC 24 |
Sep 18 08:18:59 AM UTC 24 |
1126618534 ps |
| T1614 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/46.i2c_target_fifo_watermarks_acq.1527165650 |
|
|
Sep 18 08:18:53 AM UTC 24 |
Sep 18 08:19:00 AM UTC 24 |
1009484779 ps |
| T1615 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/46.i2c_target_smbus_maxlen.2872776953 |
|
|
Sep 18 08:18:57 AM UTC 24 |
Sep 18 08:19:02 AM UTC 24 |
1499870910 ps |
| T1616 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/46.i2c_host_perf.2918536041 |
|
|
Sep 18 08:18:18 AM UTC 24 |
Sep 18 08:19:24 AM UTC 24 |
27223562554 ps |
| T1617 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/46.i2c_host_stretch_timeout.1885319257 |
|
|
Sep 18 08:18:20 AM UTC 24 |
Sep 18 08:19:03 AM UTC 24 |
5814070155 ps |
| T1618 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/46.i2c_alert_test.2464472347 |
|
|
Sep 18 08:19:03 AM UTC 24 |
Sep 18 08:19:05 AM UTC 24 |
17160542 ps |
| T1619 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/46.i2c_target_nack_txstretch.1833811280 |
|
|
Sep 18 08:19:02 AM UTC 24 |
Sep 18 08:19:06 AM UTC 24 |
516181375 ps |
| T1620 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/46.i2c_target_nack_acqfull.432570046 |
|
|
Sep 18 08:19:00 AM UTC 24 |
Sep 18 08:19:06 AM UTC 24 |
612608464 ps |
| T1621 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/46.i2c_target_nack_acqfull_addr.1615869732 |
|
|
Sep 18 08:19:00 AM UTC 24 |
Sep 18 08:19:07 AM UTC 24 |
519369859 ps |
| T258 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/46.i2c_host_may_nack.867112045 |
|
|
Sep 18 08:18:50 AM UTC 24 |
Sep 18 08:19:07 AM UTC 24 |
1518031063 ps |
| T1622 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/46.i2c_target_tx_stretch_ctrl.2063003251 |
|
|
Sep 18 08:18:54 AM UTC 24 |
Sep 18 08:19:08 AM UTC 24 |
604477443 ps |
| T1623 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/47.i2c_host_override.2762597599 |
|
|
Sep 18 08:19:07 AM UTC 24 |
Sep 18 08:19:09 AM UTC 24 |
83435939 ps |
| T1624 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/32.i2c_target_stress_wr.1071323131 |
|
|
Sep 18 08:10:21 AM UTC 24 |
Sep 18 08:19:10 AM UTC 24 |
48264360095 ps |
| T1625 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_reset_fmt.3683581726 |
|
|
Sep 18 08:19:08 AM UTC 24 |
Sep 18 08:19:11 AM UTC 24 |
178971153 ps |
| T1626 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/46.i2c_target_stretch.3837053808 |
|
|
Sep 18 08:18:26 AM UTC 24 |
Sep 18 08:19:12 AM UTC 24 |
2660185665 ps |
| T1627 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/42.i2c_host_perf_precise.1633760705 |
|
|
Sep 18 08:16:23 AM UTC 24 |
Sep 18 08:19:13 AM UTC 24 |
5788966956 ps |
| T1628 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_fmt_empty.2366356533 |
|
|
Sep 18 08:19:08 AM UTC 24 |
Sep 18 08:19:15 AM UTC 24 |
281579516 ps |
| T1629 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_reset_rx.848457746 |
|
|
Sep 18 08:19:09 AM UTC 24 |
Sep 18 08:19:16 AM UTC 24 |
164827778 ps |
| T1630 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/47.i2c_host_perf_precise.1294752913 |
|
|
Sep 18 08:19:11 AM UTC 24 |
Sep 18 08:19:16 AM UTC 24 |
115997720 ps |
| T1631 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/43.i2c_target_stress_all.3175944724 |
|
|
Sep 18 08:17:05 AM UTC 24 |
Sep 18 08:19:17 AM UTC 24 |
50759983902 ps |
| T1632 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/46.i2c_host_smoke.914712499 |
|
|
Sep 18 08:18:15 AM UTC 24 |
Sep 18 08:19:19 AM UTC 24 |
11388911605 ps |
| T1633 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/46.i2c_target_stress_wr.2150715882 |
|
|
Sep 18 08:18:22 AM UTC 24 |
Sep 18 08:19:20 AM UTC 24 |
38421260873 ps |
| T1634 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/47.i2c_target_fifo_reset_acq.2411612687 |
|
|
Sep 18 08:19:24 AM UTC 24 |
Sep 18 08:19:27 AM UTC 24 |
355080970 ps |
| T1635 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/47.i2c_target_fifo_reset_tx.2376271578 |
|
|
Sep 18 08:19:26 AM UTC 24 |
Sep 18 08:19:29 AM UTC 24 |
351858805 ps |
| T1636 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/47.i2c_target_intr_smoke.1217035078 |
|
|
Sep 18 08:19:20 AM UTC 24 |
Sep 18 08:19:31 AM UTC 24 |
1311368459 ps |
| T1637 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/45.i2c_host_fifo_full.370865594 |
|
|
Sep 18 08:17:51 AM UTC 24 |
Sep 18 08:19:31 AM UTC 24 |
3783609099 ps |
| T1638 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/47.i2c_target_bad_addr.2434451162 |
|
|
Sep 18 08:19:28 AM UTC 24 |
Sep 18 08:19:32 AM UTC 24 |
2559760374 ps |
| T1639 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/47.i2c_host_mode_toggle.85492052 |
|
|
Sep 18 08:19:31 AM UTC 24 |
Sep 18 08:19:34 AM UTC 24 |
236802879 ps |
| T1640 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/47.i2c_target_stress_wr.621995680 |
|
|
Sep 18 08:19:18 AM UTC 24 |
Sep 18 08:19:35 AM UTC 24 |
15495436461 ps |
| T1641 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/47.i2c_target_stress_rd.763274395 |
|
|
Sep 18 08:19:18 AM UTC 24 |
Sep 18 08:19:35 AM UTC 24 |
836831937 ps |
| T1642 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/47.i2c_target_timeout.1410816278 |
|
|
Sep 18 08:19:23 AM UTC 24 |
Sep 18 08:19:35 AM UTC 24 |
1333612781 ps |
| T1643 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/47.i2c_target_perf.1049814964 |
|
|
Sep 18 08:19:28 AM UTC 24 |
Sep 18 08:19:35 AM UTC 24 |
1654968817 ps |
| T1644 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/47.i2c_target_smoke.4009292703 |
|
|
Sep 18 08:19:16 AM UTC 24 |
Sep 18 08:19:36 AM UTC 24 |
1281975506 ps |
| T1645 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/47.i2c_target_fifo_watermarks_acq.710429833 |
|
|
Sep 18 08:19:34 AM UTC 24 |
Sep 18 08:19:38 AM UTC 24 |
486754073 ps |
| T1646 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/47.i2c_target_fifo_watermarks_tx.3721662417 |
|
|
Sep 18 08:19:36 AM UTC 24 |
Sep 18 08:19:38 AM UTC 24 |
244910329 ps |
| T1647 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/47.i2c_target_smbus_maxlen.3366468731 |
|
|
Sep 18 08:19:36 AM UTC 24 |
Sep 18 08:19:40 AM UTC 24 |
1414336412 ps |
| T1648 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/47.i2c_target_nack_txstretch.341438714 |
|
|
Sep 18 08:19:37 AM UTC 24 |
Sep 18 08:19:40 AM UTC 24 |
486424319 ps |
| T1649 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/47.i2c_host_may_nack.3671578565 |
|
|
Sep 18 08:19:32 AM UTC 24 |
Sep 18 08:19:40 AM UTC 24 |
489592432 ps |
| T1650 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_fmt_empty.30439204 |
|
|
Sep 18 08:20:17 AM UTC 24 |
Sep 18 08:20:47 AM UTC 24 |
1890839983 ps |
| T1651 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/47.i2c_target_tx_stretch_ctrl.3107696181 |
|
|
Sep 18 08:19:36 AM UTC 24 |
Sep 18 08:19:41 AM UTC 24 |
111165141 ps |
| T1652 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/47.i2c_alert_test.1394096906 |
|
|
Sep 18 08:19:39 AM UTC 24 |
Sep 18 08:19:41 AM UTC 24 |
54605696 ps |
| T1653 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/47.i2c_target_nack_acqfull.485990444 |
|
|
Sep 18 08:19:36 AM UTC 24 |
Sep 18 08:19:42 AM UTC 24 |
955389250 ps |
| T1654 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/48.i2c_host_override.21743610 |
|
|
Sep 18 08:19:40 AM UTC 24 |
Sep 18 08:19:42 AM UTC 24 |
51722116 ps |
| T1655 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/47.i2c_target_nack_acqfull_addr.2022300224 |
|
|
Sep 18 08:19:37 AM UTC 24 |
Sep 18 08:19:42 AM UTC 24 |
1872333971 ps |
| T1656 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_reset_fmt.2257024883 |
|
|
Sep 18 08:19:41 AM UTC 24 |
Sep 18 08:19:44 AM UTC 24 |
272249831 ps |
| T1657 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/47.i2c_target_intr_stress_wr.2685260429 |
|
|
Sep 18 08:19:21 AM UTC 24 |
Sep 18 08:19:44 AM UTC 24 |
14483308058 ps |
| T1658 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_reset_rx.2293379080 |
|
|
Sep 18 08:19:41 AM UTC 24 |
Sep 18 08:19:46 AM UTC 24 |
136037222 ps |
| T1659 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/48.i2c_host_perf_precise.1746440733 |
|
|
Sep 18 08:19:44 AM UTC 24 |
Sep 18 08:19:47 AM UTC 24 |
160044612 ps |
| T1660 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/47.i2c_host_smoke.3560201153 |
|
|
Sep 18 08:19:03 AM UTC 24 |
Sep 18 08:19:48 AM UTC 24 |
2021593549 ps |
| T1661 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/48.i2c_host_error_intr.3355314275 |
|
|
Sep 18 08:19:45 AM UTC 24 |
Sep 18 08:19:49 AM UTC 24 |
431782341 ps |
| T1662 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_overflow.2605885335 |
|
|
Sep 18 08:18:17 AM UTC 24 |
Sep 18 08:19:50 AM UTC 24 |
10779353476 ps |
| T1663 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/47.i2c_host_stretch_timeout.3037731503 |
|
|
Sep 18 08:19:13 AM UTC 24 |
Sep 18 08:19:50 AM UTC 24 |
641609552 ps |
| T1664 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_fmt_empty.2818793285 |
|
|
Sep 18 08:19:41 AM UTC 24 |
Sep 18 08:19:55 AM UTC 24 |
2040452373 ps |
| T1665 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/48.i2c_target_intr_stress_wr.2700552199 |
|
|
Sep 18 08:19:50 AM UTC 24 |
Sep 18 08:19:58 AM UTC 24 |
5582363321 ps |
| T1666 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/48.i2c_target_intr_smoke.837759739 |
|
|
Sep 18 08:19:50 AM UTC 24 |
Sep 18 08:19:59 AM UTC 24 |
658585906 ps |
| T1667 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/48.i2c_target_fifo_reset_tx.3762644420 |
|
|
Sep 18 08:19:59 AM UTC 24 |
Sep 18 08:20:01 AM UTC 24 |
232776349 ps |
| T1668 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/48.i2c_host_stretch_timeout.1139411330 |
|
|
Sep 18 08:19:44 AM UTC 24 |
Sep 18 08:20:01 AM UTC 24 |
762706415 ps |
| T1669 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/48.i2c_target_fifo_reset_acq.1787343698 |
|
|
Sep 18 08:19:58 AM UTC 24 |
Sep 18 08:20:02 AM UTC 24 |
238450030 ps |
| T1670 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/48.i2c_target_smoke.822739442 |
|
|
Sep 18 08:19:47 AM UTC 24 |
Sep 18 08:20:04 AM UTC 24 |
7085640140 ps |
| T1671 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/48.i2c_target_stretch.4096187011 |
|
|
Sep 18 08:19:50 AM UTC 24 |
Sep 18 08:20:07 AM UTC 24 |
3149601562 ps |
| T1672 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/48.i2c_target_bad_addr.3695585925 |
|
|
Sep 18 08:20:03 AM UTC 24 |
Sep 18 08:20:08 AM UTC 24 |
1245472893 ps |
| T1673 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/48.i2c_target_perf.2928099908 |
|
|
Sep 18 08:20:01 AM UTC 24 |
Sep 18 08:20:09 AM UTC 24 |
699502224 ps |
| T1674 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/48.i2c_target_timeout.3189149752 |
|
|
Sep 18 08:19:55 AM UTC 24 |
Sep 18 08:20:09 AM UTC 24 |
5561868663 ps |
| T263 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/48.i2c_host_mode_toggle.2790404141 |
|
|
Sep 18 08:20:05 AM UTC 24 |
Sep 18 08:20:09 AM UTC 24 |
174731808 ps |
| T1675 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_watermark.2958809695 |
|
|
Sep 18 08:18:16 AM UTC 24 |
Sep 18 08:20:10 AM UTC 24 |
5117497786 ps |
| T1676 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/43.i2c_host_fifo_watermark.1455152357 |
|
|
Sep 18 08:16:46 AM UTC 24 |
Sep 18 08:20:12 AM UTC 24 |
14471077477 ps |
| T1677 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/48.i2c_host_smoke.2497509820 |
|
|
Sep 18 08:19:39 AM UTC 24 |
Sep 18 08:20:12 AM UTC 24 |
1663572086 ps |
| T1678 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/48.i2c_target_fifo_watermarks_tx.1459667659 |
|
|
Sep 18 08:20:09 AM UTC 24 |
Sep 18 08:20:12 AM UTC 24 |
136482256 ps |
| T1679 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/48.i2c_target_fifo_watermarks_acq.2689891561 |
|
|
Sep 18 08:20:09 AM UTC 24 |
Sep 18 08:20:13 AM UTC 24 |
556802870 ps |
| T1680 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/40.i2c_target_stress_all.1709250262 |
|
|
Sep 18 08:15:46 AM UTC 24 |
Sep 18 08:20:13 AM UTC 24 |
46277188393 ps |
| T1681 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/48.i2c_host_may_nack.1092551017 |
|
|
Sep 18 08:20:08 AM UTC 24 |
Sep 18 08:20:14 AM UTC 24 |
215261697 ps |
| T1682 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/48.i2c_target_smbus_maxlen.1401100702 |
|
|
Sep 18 08:20:10 AM UTC 24 |
Sep 18 08:20:14 AM UTC 24 |
1640741451 ps |
| T1683 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/48.i2c_alert_test.3243693400 |
|
|
Sep 18 08:20:14 AM UTC 24 |
Sep 18 08:20:16 AM UTC 24 |
18435205 ps |
| T1684 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/49.i2c_host_override.3504054556 |
|
|
Sep 18 08:20:14 AM UTC 24 |
Sep 18 08:20:16 AM UTC 24 |
101780728 ps |
| T1685 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/48.i2c_target_nack_acqfull_addr.1986155763 |
|
|
Sep 18 08:20:12 AM UTC 24 |
Sep 18 08:20:17 AM UTC 24 |
1947062815 ps |
| T1686 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/48.i2c_target_nack_acqfull.833364833 |
|
|
Sep 18 08:20:10 AM UTC 24 |
Sep 18 08:20:17 AM UTC 24 |
2552908484 ps |
| T1687 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/44.i2c_host_fifo_watermark.879685603 |
|
|
Sep 18 08:17:20 AM UTC 24 |
Sep 18 08:20:19 AM UTC 24 |
7872313388 ps |
| T1688 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/48.i2c_target_tx_stretch_ctrl.3554581187 |
|
|
Sep 18 08:20:10 AM UTC 24 |
Sep 18 08:20:19 AM UTC 24 |
312947842 ps |
| T1689 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_reset_fmt.2418570022 |
|
|
Sep 18 08:20:16 AM UTC 24 |
Sep 18 08:20:19 AM UTC 24 |
548758839 ps |
| T1690 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/45.i2c_target_stress_all.3316202628 |
|
|
Sep 18 08:18:07 AM UTC 24 |
Sep 18 08:20:21 AM UTC 24 |
17641618352 ps |
| T1691 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_reset_rx.30598343 |
|
|
Sep 18 08:20:17 AM UTC 24 |
Sep 18 08:20:22 AM UTC 24 |
158280561 ps |
| T1692 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/49.i2c_host_perf_precise.115920117 |
|
|
Sep 18 08:20:19 AM UTC 24 |
Sep 18 08:20:23 AM UTC 24 |
97060394 ps |
| T1693 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/49.i2c_host_perf.2867893641 |
|
|
Sep 18 08:20:18 AM UTC 24 |
Sep 18 08:20:23 AM UTC 24 |
280949714 ps |
| T1694 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/49.i2c_host_error_intr.57367475 |
|
|
Sep 18 08:20:20 AM UTC 24 |
Sep 18 08:20:24 AM UTC 24 |
458828140 ps |
| T1695 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/49.i2c_target_stretch.3600109826 |
|
|
Sep 18 08:20:24 AM UTC 24 |
Sep 18 08:20:28 AM UTC 24 |
683480807 ps |
| T1696 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_full.4225294326 |
|
|
Sep 18 08:18:18 AM UTC 24 |
Sep 18 08:20:30 AM UTC 24 |
9224343971 ps |
| T1697 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/48.i2c_target_stress_rd.1355529494 |
|
|
Sep 18 08:19:49 AM UTC 24 |
Sep 18 08:20:31 AM UTC 24 |
1981545094 ps |
| T1698 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_overflow.773260878 |
|
|
Sep 18 08:19:07 AM UTC 24 |
Sep 18 08:20:33 AM UTC 24 |
10523382259 ps |
| T1699 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/49.i2c_target_intr_smoke.2830151976 |
|
|
Sep 18 08:20:25 AM UTC 24 |
Sep 18 08:20:35 AM UTC 24 |
2101567531 ps |
| T1700 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/48.i2c_target_stress_wr.1108755646 |
|
|
Sep 18 08:19:48 AM UTC 24 |
Sep 18 08:20:35 AM UTC 24 |
15834850627 ps |
| T1701 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/49.i2c_target_fifo_reset_acq.637702669 |
|
|
Sep 18 08:20:34 AM UTC 24 |
Sep 18 08:20:36 AM UTC 24 |
154648509 ps |
| T1702 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/49.i2c_target_fifo_reset_tx.1511693860 |
|
|
Sep 18 08:20:34 AM UTC 24 |
Sep 18 08:20:37 AM UTC 24 |
320444395 ps |
| T1703 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/49.i2c_target_timeout.4050783989 |
|
|
Sep 18 08:20:31 AM UTC 24 |
Sep 18 08:20:42 AM UTC 24 |
1932092120 ps |
| T1704 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/49.i2c_target_smoke.2996480002 |
|
|
Sep 18 08:20:22 AM UTC 24 |
Sep 18 08:20:42 AM UTC 24 |
1274795421 ps |
| T1705 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/44.i2c_host_perf.173334136 |
|
|
Sep 18 08:17:21 AM UTC 24 |
Sep 18 08:20:42 AM UTC 24 |
6155744561 ps |
| T1706 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/46.i2c_target_intr_stress_wr.2421983031 |
|
|
Sep 18 08:18:32 AM UTC 24 |
Sep 18 08:20:43 AM UTC 24 |
20816004023 ps |
| T1707 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_overflow.3170945909 |
|
|
Sep 18 08:19:41 AM UTC 24 |
Sep 18 08:20:44 AM UTC 24 |
1940453760 ps |
| T1708 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/49.i2c_target_intr_stress_wr.669975460 |
|
|
Sep 18 08:20:28 AM UTC 24 |
Sep 18 08:20:44 AM UTC 24 |
4071498777 ps |
| T1709 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/49.i2c_host_mode_toggle.2041296793 |
|
|
Sep 18 08:20:43 AM UTC 24 |
Sep 18 08:20:45 AM UTC 24 |
261726866 ps |
| T1710 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/49.i2c_target_perf.2110505491 |
|
|
Sep 18 08:20:35 AM UTC 24 |
Sep 18 08:20:46 AM UTC 24 |
3114942774 ps |
| T1711 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/49.i2c_target_fifo_watermarks_acq.809411385 |
|
|
Sep 18 08:20:44 AM UTC 24 |
Sep 18 08:20:47 AM UTC 24 |
833883035 ps |
| T1712 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/49.i2c_target_fifo_watermarks_tx.171853926 |
|
|
Sep 18 08:20:44 AM UTC 24 |
Sep 18 08:20:47 AM UTC 24 |
154558091 ps |
| T1713 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/49.i2c_target_tx_stretch_ctrl.1188011848 |
|
|
Sep 18 08:20:45 AM UTC 24 |
Sep 18 08:20:47 AM UTC 24 |
53530793 ps |
| T1714 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/49.i2c_target_bad_addr.2505146434 |
|
|
Sep 18 08:20:37 AM UTC 24 |
Sep 18 08:20:47 AM UTC 24 |
4204194271 ps |
| T1715 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/49.i2c_target_smbus_maxlen.1271273931 |
|
|
Sep 18 08:20:45 AM UTC 24 |
Sep 18 08:20:49 AM UTC 24 |
851250612 ps |
| T1716 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/49.i2c_target_nack_acqfull_addr.1678430564 |
|
|
Sep 18 08:20:46 AM UTC 24 |
Sep 18 08:20:50 AM UTC 24 |
2188745506 ps |
| T1717 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/49.i2c_alert_test.3021758723 |
|
|
Sep 18 08:20:48 AM UTC 24 |
Sep 18 08:20:50 AM UTC 24 |
32969536 ps |
| T1718 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/28.i2c_target_stress_wr.3843712798 |
|
|
Sep 18 08:08:01 AM UTC 24 |
Sep 18 08:20:51 AM UTC 24 |
51256771284 ps |
| T1719 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/49.i2c_target_nack_txstretch.4195320409 |
|
|
Sep 18 08:20:47 AM UTC 24 |
Sep 18 08:20:51 AM UTC 24 |
571267323 ps |
| T1720 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/49.i2c_target_nack_acqfull.3732767364 |
|
|
Sep 18 08:20:46 AM UTC 24 |
Sep 18 08:20:51 AM UTC 24 |
1860651206 ps |
| T1721 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/49.i2c_host_may_nack.3529926816 |
|
|
Sep 18 08:20:43 AM UTC 24 |
Sep 18 08:20:54 AM UTC 24 |
282221530 ps |
| T1722 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_watermark.1926846812 |
|
|
Sep 18 08:19:07 AM UTC 24 |
Sep 18 08:20:56 AM UTC 24 |
7403996784 ps |
| T1723 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_overflow.3075600065 |
|
|
Sep 18 08:20:15 AM UTC 24 |
Sep 18 08:21:10 AM UTC 24 |
9430856118 ps |
| T1724 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/49.i2c_host_stretch_timeout.1250720707 |
|
|
Sep 18 08:20:20 AM UTC 24 |
Sep 18 08:21:12 AM UTC 24 |
2024711236 ps |
| T1725 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_full.1158493179 |
|
|
Sep 18 08:19:43 AM UTC 24 |
Sep 18 08:21:25 AM UTC 24 |
3215679239 ps |
| T1726 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/49.i2c_target_stress_all.515628950 |
|
|
Sep 18 08:20:36 AM UTC 24 |
Sep 18 08:21:25 AM UTC 24 |
5945594586 ps |
| T21 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/28.i2c_host_stress_all.681200065 |
|
|
Sep 18 08:07:59 AM UTC 24 |
Sep 18 08:21:27 AM UTC 24 |
22493597110 ps |
| T1727 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/49.i2c_target_stress_rd.796272165 |
|
|
Sep 18 08:20:24 AM UTC 24 |
Sep 18 08:21:36 AM UTC 24 |
7898697024 ps |
| T1728 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/47.i2c_target_stress_all.3419612986 |
|
|
Sep 18 08:19:28 AM UTC 24 |
Sep 18 08:21:37 AM UTC 24 |
52903309311 ps |
| T1729 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/49.i2c_host_smoke.630617414 |
|
|
Sep 18 08:20:14 AM UTC 24 |
Sep 18 08:21:39 AM UTC 24 |
33287083435 ps |
| T1730 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_watermark.3553745853 |
|
|
Sep 18 08:20:15 AM UTC 24 |
Sep 18 08:21:44 AM UTC 24 |
44760693887 ps |
| T1731 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/45.i2c_host_fifo_watermark.1631855415 |
|
|
Sep 18 08:17:50 AM UTC 24 |
Sep 18 08:21:50 AM UTC 24 |
17432997095 ps |
| T1732 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_full.2548904966 |
|
|
Sep 18 08:19:10 AM UTC 24 |
Sep 18 08:21:58 AM UTC 24 |
3091459481 ps |
| T1733 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/45.i2c_target_stress_wr.3432389568 |
|
|
Sep 18 08:17:54 AM UTC 24 |
Sep 18 08:22:11 AM UTC 24 |
33317332906 ps |
| T1734 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/46.i2c_target_stress_all.3643739455 |
|
|
Sep 18 08:18:44 AM UTC 24 |
Sep 18 08:22:40 AM UTC 24 |
48545634934 ps |
| T1735 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/31.i2c_target_stress_all.3461868276 |
|
|
Sep 18 08:10:01 AM UTC 24 |
Sep 18 08:22:42 AM UTC 24 |
39440607787 ps |
| T1736 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_watermark.2936971573 |
|
|
Sep 18 08:19:40 AM UTC 24 |
Sep 18 08:22:58 AM UTC 24 |
3640145481 ps |
| T1737 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_full.2956806246 |
|
|
Sep 18 08:20:18 AM UTC 24 |
Sep 18 08:23:03 AM UTC 24 |
2992021195 ps |
| T1738 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/43.i2c_host_perf.191454671 |
|
|
Sep 18 08:16:49 AM UTC 24 |
Sep 18 08:23:04 AM UTC 24 |
26707453494 ps |
| T1739 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/31.i2c_target_stress_wr.961018796 |
|
|
Sep 18 08:09:39 AM UTC 24 |
Sep 18 08:23:13 AM UTC 24 |
51609812809 ps |
| T1740 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/41.i2c_target_stress_all.2343984100 |
|
|
Sep 18 08:16:10 AM UTC 24 |
Sep 18 08:23:14 AM UTC 24 |
35085812246 ps |
| T1741 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/44.i2c_target_stress_all.2371839913 |
|
|
Sep 18 08:17:38 AM UTC 24 |
Sep 18 08:23:19 AM UTC 24 |
66322905557 ps |
| T1742 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/38.i2c_target_stress_wr.2168739630 |
|
|
Sep 18 08:14:22 AM UTC 24 |
Sep 18 08:25:36 AM UTC 24 |
50516197416 ps |
| T1743 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/44.i2c_target_stress_wr.3309264111 |
|
|
Sep 18 08:17:26 AM UTC 24 |
Sep 18 08:26:06 AM UTC 24 |
43948929555 ps |
| T1744 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/48.i2c_host_perf.1290652133 |
|
|
Sep 18 08:19:43 AM UTC 24 |
Sep 18 08:26:08 AM UTC 24 |
74009986666 ps |
| T1745 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/6.i2c_host_stress_all.2302394373 |
|
|
Sep 18 07:56:21 AM UTC 24 |
Sep 18 08:26:33 AM UTC 24 |
71712380868 ps |
| T1746 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/48.i2c_target_stress_all.3752618790 |
|
|
Sep 18 08:20:02 AM UTC 24 |
Sep 18 08:26:43 AM UTC 24 |
53118493518 ps |
| T1747 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/19.i2c_target_stress_wr.42959561 |
|
|
Sep 18 08:02:36 AM UTC 24 |
Sep 18 08:28:48 AM UTC 24 |
70462859483 ps |
| T1748 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/41.i2c_target_stress_wr.3699020648 |
|
|
Sep 18 08:16:00 AM UTC 24 |
Sep 18 08:32:10 AM UTC 24 |
54570495367 ps |
| T1749 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/37.i2c_host_perf.3733184155 |
|
|
Sep 18 08:13:32 AM UTC 24 |
Sep 18 08:33:23 AM UTC 24 |
28002875277 ps |
| T1750 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/18.i2c_host_perf.1235984694 |
|
|
Sep 18 08:02:05 AM UTC 24 |
Sep 18 08:39:26 AM UTC 24 |
26423932371 ps |
| T1751 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/49.i2c_target_stress_wr.4130205241 |
|
|
Sep 18 08:20:23 AM UTC 24 |
Sep 18 08:39:40 AM UTC 24 |
59396498893 ps |
| T280 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/16.i2c_host_stress_all.4176006001 |
|
|
Sep 18 08:01:10 AM UTC 24 |
Sep 18 08:59:41 AM UTC 24 |
35993510803 ps |
| T200 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_tl_errors.2000744926 |
|
|
Sep 18 09:37:42 AM UTC 24 |
Sep 18 09:37:45 AM UTC 24 |
148014809 ps |
| T278 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_intr_test.407647626 |
|
|
Sep 18 09:37:46 AM UTC 24 |
Sep 18 09:37:48 AM UTC 24 |
23253411 ps |
| T108 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_tl_intg_err.4289869095 |
|
|
Sep 18 09:37:45 AM UTC 24 |
Sep 18 09:37:48 AM UTC 24 |
147661106 ps |
| T217 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_hw_reset.406661115 |
|
|
Sep 18 09:37:48 AM UTC 24 |
Sep 18 09:37:50 AM UTC 24 |
45459421 ps |
| T218 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_rw.699200084 |
|
|
Sep 18 09:37:49 AM UTC 24 |
Sep 18 09:37:51 AM UTC 24 |
50681975 ps |
| T224 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_aliasing.2614343588 |
|
|
Sep 18 09:37:49 AM UTC 24 |
Sep 18 09:37:53 AM UTC 24 |
480668133 ps |
| T109 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.270371012 |
|
|
Sep 18 09:37:52 AM UTC 24 |
Sep 18 09:37:54 AM UTC 24 |
31665390 ps |
| T110 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_same_csr_outstanding.625380007 |
|
|
Sep 18 09:37:52 AM UTC 24 |
Sep 18 09:37:54 AM UTC 24 |
138069158 ps |
| T111 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_bit_bash.4265161439 |
|
|
Sep 18 09:37:49 AM UTC 24 |
Sep 18 09:37:55 AM UTC 24 |
239748931 ps |
| T136 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_intr_test.1278410346 |
|
|
Sep 18 09:37:55 AM UTC 24 |
Sep 18 09:37:57 AM UTC 24 |
20372946 ps |
| T112 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_tl_intg_err.2177144004 |
|
|
Sep 18 09:37:55 AM UTC 24 |
Sep 18 09:37:58 AM UTC 24 |
178587746 ps |
| T203 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_tl_errors.3253078590 |
|
|
Sep 18 09:37:54 AM UTC 24 |
Sep 18 09:37:58 AM UTC 24 |
416205849 ps |
| T225 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_hw_reset.2700254575 |
|
|
Sep 18 09:37:56 AM UTC 24 |
Sep 18 09:37:58 AM UTC 24 |
63219810 ps |
| T237 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_rw.1938682403 |
|
|
Sep 18 09:37:57 AM UTC 24 |
Sep 18 09:37:59 AM UTC 24 |
43923505 ps |
| T205 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.3427049641 |
|
|
Sep 18 09:37:59 AM UTC 24 |
Sep 18 09:38:02 AM UTC 24 |
106930221 ps |
| T113 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_same_csr_outstanding.1309689515 |
|
|
Sep 18 09:37:59 AM UTC 24 |
Sep 18 09:38:02 AM UTC 24 |
58562853 ps |
| T226 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_aliasing.1582859793 |
|
|
Sep 18 09:37:59 AM UTC 24 |
Sep 18 09:38:02 AM UTC 24 |
54445157 ps |
| T1752 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_bit_bash.1747711741 |
|
|
Sep 18 09:37:58 AM UTC 24 |
Sep 18 09:38:03 AM UTC 24 |
194933643 ps |
| T281 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_intr_test.408465389 |
|
|
Sep 18 09:38:03 AM UTC 24 |
Sep 18 09:38:05 AM UTC 24 |
51852906 ps |
| T114 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_rw.1131179410 |
|
|
Sep 18 09:38:03 AM UTC 24 |
Sep 18 09:38:05 AM UTC 24 |
24658478 ps |
| T1753 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_hw_reset.338948267 |
|
|
Sep 18 09:38:03 AM UTC 24 |
Sep 18 09:38:05 AM UTC 24 |
64929684 ps |
| T115 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_tl_errors.666009013 |
|
|
Sep 18 09:38:00 AM UTC 24 |
Sep 18 09:38:06 AM UTC 24 |
1547001606 ps |
| T116 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_tl_intg_err.635247746 |
|
|
Sep 18 09:38:03 AM UTC 24 |
Sep 18 09:38:07 AM UTC 24 |
563242175 ps |
| T117 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_same_csr_outstanding.980585614 |
|
|
Sep 18 09:38:06 AM UTC 24 |
Sep 18 09:38:09 AM UTC 24 |
190307701 ps |
| T134 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.3122938141 |
|
|
Sep 18 09:38:06 AM UTC 24 |
Sep 18 09:38:09 AM UTC 24 |
128284180 ps |
| T227 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_aliasing.3231016354 |
|
|
Sep 18 09:38:06 AM UTC 24 |
Sep 18 09:38:09 AM UTC 24 |
43574974 ps |
| T206 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_tl_errors.3587638567 |
|
|
Sep 18 09:38:07 AM UTC 24 |
Sep 18 09:38:11 AM UTC 24 |
392074215 ps |
| T1754 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_hw_reset.2526796503 |
|
|
Sep 18 09:38:09 AM UTC 24 |
Sep 18 09:38:11 AM UTC 24 |
34001886 ps |
| T275 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_intr_test.4001417485 |
|
|
Sep 18 09:38:09 AM UTC 24 |
Sep 18 09:38:11 AM UTC 24 |
46119562 ps |
| T212 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_tl_intg_err.508961270 |
|
|
Sep 18 09:38:07 AM UTC 24 |
Sep 18 09:38:11 AM UTC 24 |
645441478 ps |
| T228 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_bit_bash.340760600 |
|
|
Sep 18 09:38:04 AM UTC 24 |
Sep 18 09:38:12 AM UTC 24 |
2063315912 ps |
| T229 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_rw.3964672852 |
|
|
Sep 18 09:38:11 AM UTC 24 |
Sep 18 09:38:12 AM UTC 24 |
20062411 ps |
| T1755 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_aliasing.3875315053 |
|
|
Sep 18 09:38:12 AM UTC 24 |
Sep 18 09:38:14 AM UTC 24 |
48337152 ps |
| T238 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_same_csr_outstanding.111870310 |
|
|
Sep 18 09:38:12 AM UTC 24 |
Sep 18 09:38:15 AM UTC 24 |
62108708 ps |
| T279 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_intr_test.1335024744 |
|
|
Sep 18 09:38:13 AM UTC 24 |
Sep 18 09:38:15 AM UTC 24 |
33311813 ps |
| T222 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.628920278 |
|
|
Sep 18 09:38:13 AM UTC 24 |
Sep 18 09:38:16 AM UTC 24 |
112254861 ps |
| T204 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_tl_intg_err.1989395172 |
|
|
Sep 18 09:38:13 AM UTC 24 |
Sep 18 09:38:16 AM UTC 24 |
79475461 ps |
| T1756 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_tl_errors.3379153328 |
|
|
Sep 18 09:38:13 AM UTC 24 |
Sep 18 09:38:16 AM UTC 24 |
257308472 ps |
| T1757 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_bit_bash.3781735852 |
|
|
Sep 18 09:38:12 AM UTC 24 |
Sep 18 09:38:17 AM UTC 24 |
2489786529 ps |
| T230 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_hw_reset.2719587880 |
|
|
Sep 18 09:38:15 AM UTC 24 |
Sep 18 09:38:17 AM UTC 24 |
81192063 ps |
| T231 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_rw.466204911 |
|
|
Sep 18 09:38:15 AM UTC 24 |
Sep 18 09:38:17 AM UTC 24 |
25609964 ps |
| T239 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_same_csr_outstanding.2794711327 |
|
|
Sep 18 09:38:17 AM UTC 24 |
Sep 18 09:38:19 AM UTC 24 |
111787116 ps |
| T1758 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.3234334931 |
|
|
Sep 18 09:38:17 AM UTC 24 |
Sep 18 09:38:19 AM UTC 24 |
26454306 ps |
| T277 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_intr_test.3741808142 |
|
|
Sep 18 09:38:18 AM UTC 24 |
Sep 18 09:38:20 AM UTC 24 |
22481019 ps |
| T232 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_aliasing.26988286 |
|
|
Sep 18 09:38:17 AM UTC 24 |
Sep 18 09:38:20 AM UTC 24 |
954022248 ps |
| T233 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_csr_rw.2621681974 |
|
|
Sep 18 09:38:18 AM UTC 24 |
Sep 18 09:38:20 AM UTC 24 |
173448613 ps |
| T1759 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_tl_errors.2972830843 |
|
|
Sep 18 09:38:17 AM UTC 24 |
Sep 18 09:38:20 AM UTC 24 |
88452507 ps |
| T207 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_tl_intg_err.1465657394 |
|
|
Sep 18 09:38:18 AM UTC 24 |
Sep 18 09:38:22 AM UTC 24 |
299969782 ps |
| T1760 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_same_csr_outstanding.1051094004 |
|
|
Sep 18 09:38:20 AM UTC 24 |
Sep 18 09:38:23 AM UTC 24 |
93428820 ps |
| T1761 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.4153521597 |
|
|
Sep 18 09:38:20 AM UTC 24 |
Sep 18 09:38:23 AM UTC 24 |
48107878 ps |
| T1762 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_bit_bash.3808437928 |
|
|
Sep 18 09:38:15 AM UTC 24 |
Sep 18 09:38:24 AM UTC 24 |
531848641 ps |
| T276 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_intr_test.1836047639 |
|
|
Sep 18 09:38:22 AM UTC 24 |
Sep 18 09:38:24 AM UTC 24 |
20417215 ps |
| T234 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_csr_rw.3149974708 |
|
|
Sep 18 09:38:22 AM UTC 24 |
Sep 18 09:38:24 AM UTC 24 |
52054256 ps |
| T1763 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_same_csr_outstanding.2850983694 |
|
|
Sep 18 09:38:22 AM UTC 24 |
Sep 18 09:38:24 AM UTC 24 |
43188734 ps |
| T208 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_tl_intg_err.2425251684 |
|
|
Sep 18 09:38:22 AM UTC 24 |
Sep 18 09:38:25 AM UTC 24 |
73410810 ps |
| T1764 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_tl_errors.4163992613 |
|
|
Sep 18 09:38:22 AM UTC 24 |
Sep 18 09:38:25 AM UTC 24 |
112703322 ps |
| T1765 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.693837460 |
|
|
Sep 18 09:38:23 AM UTC 24 |
Sep 18 09:38:26 AM UTC 24 |
24320021 ps |
| T1766 |
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_tl_errors.1703554209 |
|
|
Sep 18 09:38:23 AM UTC 24 |
Sep 18 09:38:26 AM UTC 24 |
58798297 ps |