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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
91.26 97.20 89.46 97.22 72.02 94.23 98.47 90.21


Total test records in report: 1857
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T1767 /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_csr_rw.1425001354 Sep 18 09:38:25 AM UTC 24 Sep 18 09:38:27 AM UTC 24 28103562 ps
T1768 /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_intr_test.1460804327 Sep 18 09:38:25 AM UTC 24 Sep 18 09:38:27 AM UTC 24 18393646 ps
T1769 /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_same_csr_outstanding.2180757441 Sep 18 09:38:25 AM UTC 24 Sep 18 09:38:27 AM UTC 24 117160199 ps
T1770 /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.1864932634 Sep 18 09:38:25 AM UTC 24 Sep 18 09:38:27 AM UTC 24 85142623 ps
T284 /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_intr_test.3832951330 Sep 18 09:38:26 AM UTC 24 Sep 18 09:38:28 AM UTC 24 50494212 ps
T210 /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_tl_intg_err.3398314832 Sep 18 09:38:24 AM UTC 24 Sep 18 09:38:28 AM UTC 24 116847226 ps
T216 /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_tl_intg_err.1277656199 Sep 18 09:38:26 AM UTC 24 Sep 18 09:38:29 AM UTC 24 87533666 ps
T1771 /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_csr_rw.2128255127 Sep 18 09:38:27 AM UTC 24 Sep 18 09:38:30 AM UTC 24 18272544 ps
T1772 /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_same_csr_outstanding.1092425987 Sep 18 09:38:28 AM UTC 24 Sep 18 09:38:30 AM UTC 24 68664478 ps
T1773 /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.3528839950 Sep 18 09:38:28 AM UTC 24 Sep 18 09:38:30 AM UTC 24 22641147 ps
T1774 /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_tl_errors.3367916159 Sep 18 09:38:26 AM UTC 24 Sep 18 09:38:30 AM UTC 24 101642881 ps
T215 /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/9.i2c_tl_intg_err.3689771471 Sep 18 09:38:28 AM UTC 24 Sep 18 09:38:31 AM UTC 24 124499843 ps
T286 /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/9.i2c_intr_test.4010718120 Sep 18 09:38:29 AM UTC 24 Sep 18 09:38:31 AM UTC 24 15407833 ps
T235 /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/9.i2c_csr_rw.2497768975 Sep 18 09:38:29 AM UTC 24 Sep 18 09:38:31 AM UTC 24 29214251 ps
T1775 /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/9.i2c_tl_errors.367538181 Sep 18 09:38:28 AM UTC 24 Sep 18 09:38:31 AM UTC 24 512699518 ps
T1776 /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.2150489274 Sep 18 09:38:30 AM UTC 24 Sep 18 09:38:33 AM UTC 24 70013229 ps
T1777 /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/9.i2c_same_csr_outstanding.3834507347 Sep 18 09:38:30 AM UTC 24 Sep 18 09:38:33 AM UTC 24 59935990 ps
T1778 /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_intr_test.1007498402 Sep 18 09:38:32 AM UTC 24 Sep 18 09:38:34 AM UTC 24 15571611 ps
T1779 /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_csr_rw.3789486774 Sep 18 09:38:32 AM UTC 24 Sep 18 09:38:34 AM UTC 24 22942969 ps
T1780 /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_tl_errors.1887024365 Sep 18 09:38:30 AM UTC 24 Sep 18 09:38:34 AM UTC 24 278590375 ps
T1781 /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.1271061657 Sep 18 09:38:32 AM UTC 24 Sep 18 09:38:34 AM UTC 24 111239548 ps
T1782 /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_same_csr_outstanding.1503941736 Sep 18 09:38:32 AM UTC 24 Sep 18 09:38:34 AM UTC 24 136338204 ps
T214 /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_tl_intg_err.1565777410 Sep 18 09:38:32 AM UTC 24 Sep 18 09:38:35 AM UTC 24 292139291 ps
T1783 /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_tl_errors.435432290 Sep 18 09:38:32 AM UTC 24 Sep 18 09:38:36 AM UTC 24 1480498688 ps
T264 /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_tl_intg_err.2205018273 Sep 18 09:38:33 AM UTC 24 Sep 18 09:38:36 AM UTC 24 394873063 ps
T1784 /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_intr_test.3097856483 Sep 18 09:38:35 AM UTC 24 Sep 18 09:38:36 AM UTC 24 24334539 ps
T1785 /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_csr_rw.3496509525 Sep 18 09:38:35 AM UTC 24 Sep 18 09:38:37 AM UTC 24 96506688 ps
T1786 /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_same_csr_outstanding.2036644485 Sep 18 09:38:35 AM UTC 24 Sep 18 09:38:37 AM UTC 24 47460216 ps
T1787 /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.2786584135 Sep 18 09:38:35 AM UTC 24 Sep 18 09:38:37 AM UTC 24 67563631 ps
T1788 /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_csr_rw.1536325455 Sep 18 09:38:37 AM UTC 24 Sep 18 09:38:39 AM UTC 24 20269088 ps
T1789 /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_intr_test.3804000656 Sep 18 09:38:36 AM UTC 24 Sep 18 09:38:38 AM UTC 24 41551536 ps
T1790 /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_same_csr_outstanding.4125227638 Sep 18 09:38:37 AM UTC 24 Sep 18 09:38:39 AM UTC 24 35693375 ps
T1791 /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.1652601265 Sep 18 09:38:37 AM UTC 24 Sep 18 09:38:39 AM UTC 24 32792376 ps
T211 /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_tl_intg_err.3692519374 Sep 18 09:38:36 AM UTC 24 Sep 18 09:38:39 AM UTC 24 87770631 ps
T1792 /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_tl_errors.2054411135 Sep 18 09:38:36 AM UTC 24 Sep 18 09:38:40 AM UTC 24 148953234 ps
T285 /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_intr_test.1358548240 Sep 18 09:38:38 AM UTC 24 Sep 18 09:38:40 AM UTC 24 44441351 ps
T1793 /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_csr_rw.1132417133 Sep 18 09:38:38 AM UTC 24 Sep 18 09:38:40 AM UTC 24 22721566 ps
T1794 /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_tl_intg_err.3187155873 Sep 18 09:38:38 AM UTC 24 Sep 18 09:38:41 AM UTC 24 84346510 ps
T1795 /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_tl_errors.498790098 Sep 18 09:38:38 AM UTC 24 Sep 18 09:38:41 AM UTC 24 212435080 ps
T1796 /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.605804954 Sep 18 09:38:40 AM UTC 24 Sep 18 09:38:42 AM UTC 24 47366355 ps
T1797 /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_same_csr_outstanding.20863986 Sep 18 09:38:40 AM UTC 24 Sep 18 09:38:42 AM UTC 24 59604208 ps
T1798 /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_tl_errors.3513892251 Sep 18 09:38:40 AM UTC 24 Sep 18 09:38:43 AM UTC 24 83281579 ps
T1799 /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_intr_test.117638903 Sep 18 09:38:41 AM UTC 24 Sep 18 09:38:43 AM UTC 24 17155910 ps
T1800 /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_csr_rw.1739134111 Sep 18 09:38:42 AM UTC 24 Sep 18 09:38:44 AM UTC 24 25815449 ps
T1801 /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_same_csr_outstanding.4293038532 Sep 18 09:38:42 AM UTC 24 Sep 18 09:38:44 AM UTC 24 32200249 ps
T1802 /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_tl_intg_err.1417182934 Sep 18 09:38:40 AM UTC 24 Sep 18 09:38:44 AM UTC 24 89068007 ps
T1803 /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.3794900458 Sep 18 09:38:42 AM UTC 24 Sep 18 09:38:44 AM UTC 24 84396828 ps
T1804 /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/15.i2c_intr_test.450501836 Sep 18 09:38:43 AM UTC 24 Sep 18 09:38:45 AM UTC 24 67083506 ps
T1805 /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/15.i2c_csr_rw.1329575591 Sep 18 09:38:43 AM UTC 24 Sep 18 09:38:45 AM UTC 24 97224832 ps
T1806 /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/15.i2c_tl_errors.3421598402 Sep 18 09:38:43 AM UTC 24 Sep 18 09:38:46 AM UTC 24 47482905 ps
T1807 /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/15.i2c_tl_intg_err.3876139864 Sep 18 09:38:43 AM UTC 24 Sep 18 09:38:46 AM UTC 24 146216240 ps
T1808 /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/15.i2c_same_csr_outstanding.2583398406 Sep 18 09:38:45 AM UTC 24 Sep 18 09:38:47 AM UTC 24 32254149 ps
T282 /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/16.i2c_intr_test.2132442866 Sep 18 09:38:45 AM UTC 24 Sep 18 09:38:47 AM UTC 24 19379598 ps
T236 /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/16.i2c_csr_rw.846675509 Sep 18 09:38:45 AM UTC 24 Sep 18 09:38:48 AM UTC 24 43150211 ps
T1809 /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.244931538 Sep 18 09:38:45 AM UTC 24 Sep 18 09:38:48 AM UTC 24 172401675 ps
T1810 /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/16.i2c_tl_intg_err.4281082454 Sep 18 09:38:45 AM UTC 24 Sep 18 09:38:48 AM UTC 24 313927561 ps
T1811 /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/16.i2c_tl_errors.3699399433 Sep 18 09:38:45 AM UTC 24 Sep 18 09:38:49 AM UTC 24 267877137 ps
T1812 /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.1294986094 Sep 18 09:38:47 AM UTC 24 Sep 18 09:38:49 AM UTC 24 20724424 ps
T1813 /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/16.i2c_same_csr_outstanding.1447209538 Sep 18 09:38:47 AM UTC 24 Sep 18 09:38:49 AM UTC 24 38154000 ps
T209 /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/17.i2c_tl_intg_err.3777696936 Sep 18 09:38:47 AM UTC 24 Sep 18 09:38:50 AM UTC 24 645547925 ps
T1814 /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/17.i2c_csr_rw.3993426421 Sep 18 09:38:49 AM UTC 24 Sep 18 09:38:51 AM UTC 24 59331029 ps
T1815 /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/17.i2c_intr_test.1799816364 Sep 18 09:38:49 AM UTC 24 Sep 18 09:38:51 AM UTC 24 16286152 ps
T1816 /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/17.i2c_same_csr_outstanding.1120116414 Sep 18 09:38:49 AM UTC 24 Sep 18 09:38:51 AM UTC 24 56433310 ps
T1817 /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/17.i2c_tl_errors.2010513755 Sep 18 09:38:47 AM UTC 24 Sep 18 09:38:52 AM UTC 24 50593715 ps
T1818 /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/18.i2c_intr_test.3605307940 Sep 18 09:38:51 AM UTC 24 Sep 18 09:38:53 AM UTC 24 18346699 ps
T1819 /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/18.i2c_csr_rw.1462296088 Sep 18 09:38:51 AM UTC 24 Sep 18 09:38:53 AM UTC 24 17116336 ps
T1820 /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.2235928964 Sep 18 09:38:51 AM UTC 24 Sep 18 09:38:54 AM UTC 24 25652967 ps
T1821 /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.3672991140 Sep 18 09:38:51 AM UTC 24 Sep 18 09:38:54 AM UTC 24 639091239 ps
T259 /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/18.i2c_same_csr_outstanding.3432734695 Sep 18 09:38:51 AM UTC 24 Sep 18 09:38:54 AM UTC 24 26364693 ps
T213 /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/18.i2c_tl_intg_err.1101502244 Sep 18 09:38:51 AM UTC 24 Sep 18 09:38:54 AM UTC 24 505869337 ps
T1822 /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/19.i2c_intr_test.3505474394 Sep 18 09:38:53 AM UTC 24 Sep 18 09:38:55 AM UTC 24 43231457 ps
T1823 /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/18.i2c_tl_errors.2859102508 Sep 18 09:38:51 AM UTC 24 Sep 18 09:38:55 AM UTC 24 303453052 ps
T1824 /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/19.i2c_tl_errors.2101421533 Sep 18 09:38:53 AM UTC 24 Sep 18 09:38:56 AM UTC 24 29255421 ps
T1825 /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/19.i2c_csr_rw.493014622 Sep 18 09:38:54 AM UTC 24 Sep 18 09:38:57 AM UTC 24 27943390 ps
T1826 /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/19.i2c_tl_intg_err.1703051765 Sep 18 09:38:53 AM UTC 24 Sep 18 09:38:57 AM UTC 24 784807905 ps
T1827 /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/19.i2c_same_csr_outstanding.4266606339 Sep 18 09:38:54 AM UTC 24 Sep 18 09:38:57 AM UTC 24 75850169 ps
T283 /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/20.i2c_intr_test.2808037778 Sep 18 09:38:55 AM UTC 24 Sep 18 09:38:57 AM UTC 24 16303105 ps
T1828 /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/21.i2c_intr_test.1525347469 Sep 18 09:38:55 AM UTC 24 Sep 18 09:38:57 AM UTC 24 97721924 ps
T1829 /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.2900686933 Sep 18 09:38:55 AM UTC 24 Sep 18 09:38:57 AM UTC 24 36078746 ps
T1830 /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/22.i2c_intr_test.3288929450 Sep 18 09:38:56 AM UTC 24 Sep 18 09:38:58 AM UTC 24 43046931 ps
T1831 /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/24.i2c_intr_test.2967078211 Sep 18 09:38:56 AM UTC 24 Sep 18 09:38:58 AM UTC 24 40629413 ps
T1832 /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/25.i2c_intr_test.4131537628 Sep 18 09:38:57 AM UTC 24 Sep 18 09:38:58 AM UTC 24 52043417 ps
T1833 /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/23.i2c_intr_test.4140917366 Sep 18 09:38:56 AM UTC 24 Sep 18 09:38:58 AM UTC 24 16627336 ps
T1834 /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/26.i2c_intr_test.4126168594 Sep 18 09:39:00 AM UTC 24 Sep 18 09:39:02 AM UTC 24 151311600 ps
T1835 /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/28.i2c_intr_test.85251187 Sep 18 09:39:00 AM UTC 24 Sep 18 09:39:02 AM UTC 24 17158440 ps
T1836 /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/27.i2c_intr_test.2087179250 Sep 18 09:39:00 AM UTC 24 Sep 18 09:39:02 AM UTC 24 33602134 ps
T1837 /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/29.i2c_intr_test.336801811 Sep 18 09:39:00 AM UTC 24 Sep 18 09:39:02 AM UTC 24 19191677 ps
T1838 /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/30.i2c_intr_test.72519359 Sep 18 09:39:00 AM UTC 24 Sep 18 09:39:02 AM UTC 24 42871212 ps
T1839 /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/32.i2c_intr_test.4029800440 Sep 18 09:39:00 AM UTC 24 Sep 18 09:39:02 AM UTC 24 20156486 ps
T1840 /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/31.i2c_intr_test.2652230607 Sep 18 09:39:00 AM UTC 24 Sep 18 09:39:02 AM UTC 24 54418370 ps
T1841 /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/33.i2c_intr_test.148561959 Sep 18 09:39:00 AM UTC 24 Sep 18 09:39:02 AM UTC 24 41448831 ps
T1842 /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/34.i2c_intr_test.2540098618 Sep 18 09:39:00 AM UTC 24 Sep 18 09:39:02 AM UTC 24 20573928 ps
T1843 /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/35.i2c_intr_test.246877624 Sep 18 09:39:00 AM UTC 24 Sep 18 09:39:02 AM UTC 24 38030373 ps
T1844 /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/36.i2c_intr_test.2558733766 Sep 18 09:39:00 AM UTC 24 Sep 18 09:39:02 AM UTC 24 19313711 ps
T1845 /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/39.i2c_intr_test.3802402774 Sep 18 09:39:05 AM UTC 24 Sep 18 09:39:08 AM UTC 24 20124578 ps
T1846 /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/38.i2c_intr_test.2905260790 Sep 18 09:39:05 AM UTC 24 Sep 18 09:39:08 AM UTC 24 19044101 ps
T1847 /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/37.i2c_intr_test.3561210481 Sep 18 09:39:05 AM UTC 24 Sep 18 09:39:08 AM UTC 24 17953597 ps
T1848 /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/43.i2c_intr_test.3032845966 Sep 18 09:39:05 AM UTC 24 Sep 18 09:39:08 AM UTC 24 37956221 ps
T1849 /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/44.i2c_intr_test.977884000 Sep 18 09:39:05 AM UTC 24 Sep 18 09:39:08 AM UTC 24 20392365 ps
T1850 /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/46.i2c_intr_test.551160679 Sep 18 09:39:05 AM UTC 24 Sep 18 09:39:08 AM UTC 24 22422024 ps
T1851 /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/40.i2c_intr_test.4128177048 Sep 18 09:39:05 AM UTC 24 Sep 18 09:39:08 AM UTC 24 16337203 ps
T1852 /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/41.i2c_intr_test.1943255792 Sep 18 09:39:05 AM UTC 24 Sep 18 09:39:08 AM UTC 24 52770651 ps
T1853 /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/45.i2c_intr_test.1867389738 Sep 18 09:39:05 AM UTC 24 Sep 18 09:39:08 AM UTC 24 50835903 ps
T1854 /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/47.i2c_intr_test.3313882764 Sep 18 09:39:05 AM UTC 24 Sep 18 09:39:08 AM UTC 24 19168978 ps
T1855 /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/42.i2c_intr_test.3982102732 Sep 18 09:39:05 AM UTC 24 Sep 18 09:39:08 AM UTC 24 47566867 ps
T1856 /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/48.i2c_intr_test.13041209 Sep 18 09:39:12 AM UTC 24 Sep 18 09:39:14 AM UTC 24 24405448 ps
T1857 /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/49.i2c_intr_test.2854648929 Sep 18 09:39:12 AM UTC 24 Sep 18 09:39:14 AM UTC 24 57442901 ps

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/0.i2c_target_bad_addr.1315844273
Short name T10
Test name
Test status
Simulation time 3006427045 ps
CPU time 4.01 seconds
Started Sep 18 07:54:31 AM UTC 24
Finished Sep 18 07:54:37 AM UTC 24
Peak memory 227812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=1315844273 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_bad_addr.1315844273
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/0.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/0.i2c_host_error_intr.3356454540
Short name T5
Test name
Test status
Simulation time 583486187 ps
CPU time 2.49 seconds
Started Sep 18 07:54:28 AM UTC 24
Finished Sep 18 07:54:31 AM UTC 24
Peak memory 225572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3356454540 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 0.i2c_host_error_intr.3356454540
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/0.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/0.i2c_target_glitch.4154229393
Short name T50
Test name
Test status
Simulation time 7730602819 ps
CPU time 14.21 seconds
Started Sep 18 07:54:28 AM UTC 24
Finished Sep 18 07:54:43 AM UTC 24
Peak memory 226204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4154229393 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_glitch.4154229393
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/0.i2c_target_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/9.i2c_host_stress_all.4205530150
Short name T122
Test name
Test status
Simulation time 10476982276 ps
CPU time 256.02 seconds
Started Sep 18 07:57:32 AM UTC 24
Finished Sep 18 08:01:52 AM UTC 24
Peak memory 2237312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4205530150 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 9.i2c_host_stress_all.4205530150
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/9.i2c_host_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_tl_errors.666009013
Short name T115
Test name
Test status
Simulation time 1547001606 ps
CPU time 4.22 seconds
Started Sep 18 09:38:00 AM UTC 24
Finished Sep 18 09:38:06 AM UTC 24
Peak memory 215484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=666009013 -assert nopostproc +UVM_TESTNAME=i2c_base_tes
t +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_errors.666009013
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/2.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/1.i2c_host_may_nack.1476585788
Short name T12
Test name
Test status
Simulation time 2426543530 ps
CPU time 9.48 seconds
Started Sep 18 07:54:47 AM UTC 24
Finished Sep 18 07:54:58 AM UTC 24
Peak memory 215324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1476585788 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.i2c_host_may_nack.1476585788
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/1.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/1.i2c_host_fifo_reset_rx.3572447005
Short name T43
Test name
Test status
Simulation time 155761539 ps
CPU time 5.69 seconds
Started Sep 18 07:54:40 AM UTC 24
Finished Sep 18 07:54:46 AM UTC 24
Peak memory 240420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3572447005 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_rx.3572447005
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/1.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/1.i2c_target_nack_txstretch.652261736
Short name T58
Test name
Test status
Simulation time 318931288 ps
CPU time 2.16 seconds
Started Sep 18 07:54:50 AM UTC 24
Finished Sep 18 07:54:54 AM UTC 24
Peak memory 232352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6522617
36 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_nack_txstretch.652261736
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/1.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/1.i2c_host_override.355039104
Short name T81
Test name
Test status
Simulation time 26288877 ps
CPU time 1.05 seconds
Started Sep 18 07:54:37 AM UTC 24
Finished Sep 18 07:54:39 AM UTC 24
Peak memory 214112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=355039104 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 1.i2c_host_override.355039104
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/1.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/0.i2c_target_timeout.1451892035
Short name T72
Test name
Test status
Simulation time 1367327225 ps
CPU time 8.39 seconds
Started Sep 18 07:54:30 AM UTC 24
Finished Sep 18 07:54:40 AM UTC 24
Peak memory 232424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1451892
035 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_timeout.1451892035
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/0.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/0.i2c_sec_cm.3670837925
Short name T75
Test name
Test status
Simulation time 41043559 ps
CPU time 1.22 seconds
Started Sep 18 07:54:36 AM UTC 24
Finished Sep 18 07:54:39 AM UTC 24
Peak memory 244508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3670837925 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_sec_cm.3670837925
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/0.i2c_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/1.i2c_target_nack_acqfull_addr.3750607455
Short name T47
Test name
Test status
Simulation time 512544564 ps
CPU time 4.71 seconds
Started Sep 18 07:54:50 AM UTC 24
Finished Sep 18 07:54:56 AM UTC 24
Peak memory 215264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3750607
455 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_nack_acqfull_addr.3750607455
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/1.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/0.i2c_host_fifo_watermark.757968334
Short name T32
Test name
Test status
Simulation time 20936795938 ps
CPU time 86.63 seconds
Started Sep 18 07:54:24 AM UTC 24
Finished Sep 18 07:55:53 AM UTC 24
Peak memory 1303320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=757968334 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_watermark.757968334
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/0.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/26.i2c_host_stress_all.2165981377
Short name T20
Test name
Test status
Simulation time 12068909230 ps
CPU time 267.92 seconds
Started Sep 18 08:06:44 AM UTC 24
Finished Sep 18 08:11:16 AM UTC 24
Peak memory 1401796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2165981377 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 26.i2c_host_stress_all.2165981377
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/26.i2c_host_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_rw.466204911
Short name T231
Test name
Test status
Simulation time 25609964 ps
CPU time 1.11 seconds
Started Sep 18 09:38:15 AM UTC 24
Finished Sep 18 09:38:17 AM UTC 24
Peak memory 214800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=466204911 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_rw.466204911
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/4.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/2.i2c_target_stress_all.3965907601
Short name T56
Test name
Test status
Simulation time 69794446610 ps
CPU time 185.77 seconds
Started Sep 18 07:55:06 AM UTC 24
Finished Sep 18 07:58:14 AM UTC 24
Peak memory 2216808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=396590
7601 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_stress_all.3965907601
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/2.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/0.i2c_target_nack_acqfull.3356697180
Short name T61
Test name
Test status
Simulation time 2161240635 ps
CPU time 3.5 seconds
Started Sep 18 07:54:35 AM UTC 24
Finished Sep 18 07:54:40 AM UTC 24
Peak memory 225304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3356697
180 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_nack_acqfull.3356697180
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/0.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_tl_intg_err.1465657394
Short name T207
Test name
Test status
Simulation time 299969782 ps
CPU time 2.9 seconds
Started Sep 18 09:38:18 AM UTC 24
Finished Sep 18 09:38:22 AM UTC 24
Peak memory 215336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1465657394 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_intg_err.1465657394
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/5.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/3.i2c_host_fifo_reset_fmt.2809916113
Short name T35
Test name
Test status
Simulation time 506378693 ps
CPU time 1.79 seconds
Started Sep 18 07:55:13 AM UTC 24
Finished Sep 18 07:55:15 AM UTC 24
Peak memory 214904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2809916113 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_fmt.2809916113
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/3.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/3.i2c_host_perf.2431468622
Short name T601
Test name
Test status
Simulation time 47465380579 ps
CPU time 331.66 seconds
Started Sep 18 07:55:14 AM UTC 24
Finished Sep 18 08:00:50 AM UTC 24
Peak memory 225756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2431468622 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 3.i2c_host_perf.2431468622
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/3.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/12.i2c_target_nack_acqfull.2212727026
Short name T53
Test name
Test status
Simulation time 5594620754 ps
CPU time 4.72 seconds
Started Sep 18 07:59:20 AM UTC 24
Finished Sep 18 07:59:26 AM UTC 24
Peak memory 225624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2212727
026 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_nack_acqfull.2212727026
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/12.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/24.i2c_host_stress_all.3419553869
Short name T78
Test name
Test status
Simulation time 18297617657 ps
CPU time 100.96 seconds
Started Sep 18 08:05:41 AM UTC 24
Finished Sep 18 08:07:24 AM UTC 24
Peak memory 590624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3419553869 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 24.i2c_host_stress_all.3419553869
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/24.i2c_host_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/0.i2c_host_fifo_full.2735204493
Short name T28
Test name
Test status
Simulation time 23524053780 ps
CPU time 114.16 seconds
Started Sep 18 07:54:25 AM UTC 24
Finished Sep 18 07:56:22 AM UTC 24
Peak memory 844508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2735204493 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_full.2735204493
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/0.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/0.i2c_host_fifo_overflow.3708929231
Short name T94
Test name
Test status
Simulation time 15991884861 ps
CPU time 142.95 seconds
Started Sep 18 07:54:25 AM UTC 24
Finished Sep 18 07:56:51 AM UTC 24
Peak memory 791260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3708929231 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_overflow.3708929231
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/0.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/0.i2c_target_fifo_watermarks_acq.749965590
Short name T45
Test name
Test status
Simulation time 487140362 ps
CPU time 3.75 seconds
Started Sep 18 07:54:33 AM UTC 24
Finished Sep 18 07:54:38 AM UTC 24
Peak memory 215256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7499655
90 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_fifo_watermarks
_acq.749965590
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/0.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/0.i2c_alert_test.1091198021
Short name T74
Test name
Test status
Simulation time 39875292 ps
CPU time 0.92 seconds
Started Sep 18 07:54:36 AM UTC 24
Finished Sep 18 07:54:38 AM UTC 24
Peak memory 214840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1091198021 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_alert_test.1091198021
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/0.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/45.i2c_target_fifo_reset_tx.352376509
Short name T92
Test name
Test status
Simulation time 598030809 ps
CPU time 2.73 seconds
Started Sep 18 08:18:07 AM UTC 24
Finished Sep 18 08:18:11 AM UTC 24
Peak memory 215384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3523765
09 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_fifo_reset_tx.352376509
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/45.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_intr_test.407647626
Short name T278
Test name
Test status
Simulation time 23253411 ps
CPU time 1.08 seconds
Started Sep 18 09:37:46 AM UTC 24
Finished Sep 18 09:37:48 AM UTC 24
Peak memory 214616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=407647626 -assert nopostproc +UVM_TESTNAME=i2c_base_tes
t +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_intr_test.407647626
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/0.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/2.i2c_host_fifo_fmt_empty.683545389
Short name T42
Test name
Test status
Simulation time 3877721549 ps
CPU time 14.07 seconds
Started Sep 18 07:54:55 AM UTC 24
Finished Sep 18 07:55:10 AM UTC 24
Peak memory 262876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=683545389 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_fmt_empty.683545389
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/2.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/16.i2c_target_stress_all.3807274553
Short name T291
Test name
Test status
Simulation time 188135496649 ps
CPU time 81.95 seconds
Started Sep 18 08:01:24 AM UTC 24
Finished Sep 18 08:02:48 AM UTC 24
Peak memory 343072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=380727
4553 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_stress_all.3807274553
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/16.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/18.i2c_same_csr_outstanding.3432734695
Short name T259
Test name
Test status
Simulation time 26364693 ps
CPU time 1.56 seconds
Started Sep 18 09:38:51 AM UTC 24
Finished Sep 18 09:38:54 AM UTC 24
Peak memory 214748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3432734695 -assert nopostproc +UVM
_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_same_csr_outstanding.3432734695
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/18.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/7.i2c_host_may_nack.32991224
Short name T247
Test name
Test status
Simulation time 2664379140 ps
CPU time 10.39 seconds
Started Sep 18 07:56:58 AM UTC 24
Finished Sep 18 07:57:10 AM UTC 24
Peak memory 215516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=32991224 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ho
st_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 7.i2c_host_may_nack.32991224
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/7.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_tl_intg_err.3692519374
Short name T211
Test name
Test status
Simulation time 87770631 ps
CPU time 2.03 seconds
Started Sep 18 09:38:36 AM UTC 24
Finished Sep 18 09:38:39 AM UTC 24
Peak memory 215392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3692519374 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_intg_err.3692519374
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/12.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/0.i2c_target_stress_rd.2547388313
Short name T223
Test name
Test status
Simulation time 1610523121 ps
CPU time 32.98 seconds
Started Sep 18 07:54:28 AM UTC 24
Finished Sep 18 07:55:02 AM UTC 24
Peak memory 242408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2547388313 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_stress_rd.2547388313
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/0.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/10.i2c_host_override.4158755674
Short name T149
Test name
Test status
Simulation time 20376266 ps
CPU time 0.96 seconds
Started Sep 18 07:57:55 AM UTC 24
Finished Sep 18 07:57:57 AM UTC 24
Peak memory 214112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4158755674 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.i2c_host_override.4158755674
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/10.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_intr_test.1007498402
Short name T1778
Test name
Test status
Simulation time 15571611 ps
CPU time 0.92 seconds
Started Sep 18 09:38:32 AM UTC 24
Finished Sep 18 09:38:34 AM UTC 24
Peak memory 214612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1007498402 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_intr_test.1007498402
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/10.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/21.i2c_host_stress_all.493500050
Short name T243
Test name
Test status
Simulation time 59534661452 ps
CPU time 670.4 seconds
Started Sep 18 08:03:50 AM UTC 24
Finished Sep 18 08:15:09 AM UTC 24
Peak memory 3259172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=493500050 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 21.i2c_host_stress_all.493500050
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/21.i2c_host_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/31.i2c_host_fifo_reset_fmt.3237732931
Short name T245
Test name
Test status
Simulation time 519335565 ps
CPU time 1.88 seconds
Started Sep 18 08:09:34 AM UTC 24
Finished Sep 18 08:09:37 AM UTC 24
Peak memory 214900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3237732931 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_fmt.3237732931
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/31.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/4.i2c_host_may_nack.3110006177
Short name T249
Test name
Test status
Simulation time 632531510 ps
CPU time 8.77 seconds
Started Sep 18 07:55:51 AM UTC 24
Finished Sep 18 07:56:01 AM UTC 24
Peak memory 215192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3110006177 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.i2c_host_may_nack.3110006177
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/4.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/14.i2c_host_mode_toggle.2961774068
Short name T79
Test name
Test status
Simulation time 562931097 ps
CPU time 2.61 seconds
Started Sep 18 08:00:09 AM UTC 24
Finished Sep 18 08:00:13 AM UTC 24
Peak memory 232108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2961774068 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_mode_toggle.2961774068
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/14.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_tl_intg_err.4289869095
Short name T108
Test name
Test status
Simulation time 147661106 ps
CPU time 2.2 seconds
Started Sep 18 09:37:45 AM UTC 24
Finished Sep 18 09:37:48 AM UTC 24
Peak memory 215336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4289869095 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_intg_err.4289869095
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/0.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/0.i2c_target_fifo_reset_acq.2544927750
Short name T6
Test name
Test status
Simulation time 579474256 ps
CPU time 1.14 seconds
Started Sep 18 07:54:30 AM UTC 24
Finished Sep 18 07:54:34 AM UTC 24
Peak memory 214784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2544927
750 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_fifo_reset_acq.2544927750
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/0.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/1.i2c_target_glitch.3398551322
Short name T51
Test name
Test status
Simulation time 8459729439 ps
CPU time 17.44 seconds
Started Sep 18 07:54:41 AM UTC 24
Finished Sep 18 07:55:00 AM UTC 24
Peak memory 226076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3398551322 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_glitch.3398551322
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/1.i2c_target_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/18.i2c_host_stress_all.3857860474
Short name T37
Test name
Test status
Simulation time 58943949884 ps
CPU time 317.22 seconds
Started Sep 18 08:02:06 AM UTC 24
Finished Sep 18 08:07:27 AM UTC 24
Peak memory 2018252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3857860474 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 18.i2c_host_stress_all.3857860474
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/18.i2c_host_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/0.i2c_host_may_nack.1512854048
Short name T11
Test name
Test status
Simulation time 453524196 ps
CPU time 15.14 seconds
Started Sep 18 07:54:33 AM UTC 24
Finished Sep 18 07:54:50 AM UTC 24
Peak memory 215260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1512854048 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.i2c_host_may_nack.1512854048
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/0.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/0.i2c_host_stretch_timeout.3280210972
Short name T40
Test name
Test status
Simulation time 1603640679 ps
CPU time 30.24 seconds
Started Sep 18 07:54:27 AM UTC 24
Finished Sep 18 07:54:58 AM UTC 24
Peak memory 225688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3280210972 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_stretch_timeout.3280210972
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/0.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/0.i2c_target_tx_stretch_ctrl.4289987363
Short name T67
Test name
Test status
Simulation time 188400680 ps
CPU time 4.68 seconds
Started Sep 18 07:54:34 AM UTC 24
Finished Sep 18 07:54:40 AM UTC 24
Peak memory 215216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4289987
363 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_tx_stretch_ctrl.4289987363
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/0.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/10.i2c_target_stress_wr.2468236944
Short name T629
Test name
Test status
Simulation time 68022435510 ps
CPU time 194.24 seconds
Started Sep 18 07:58:00 AM UTC 24
Finished Sep 18 08:01:17 AM UTC 24
Peak memory 2911000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2468236944 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_stress_wr.2468236944
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/10.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/32.i2c_host_may_nack.3200222842
Short name T251
Test name
Test status
Simulation time 231954569 ps
CPU time 4.07 seconds
Started Sep 18 08:10:40 AM UTC 24
Finished Sep 18 08:10:45 AM UTC 24
Peak memory 215264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3200222842 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.i2c_host_may_nack.3200222842
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/32.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/37.i2c_host_mode_toggle.3286933926
Short name T260
Test name
Test status
Simulation time 97967107 ps
CPU time 3.75 seconds
Started Sep 18 08:13:57 AM UTC 24
Finished Sep 18 08:14:02 AM UTC 24
Peak memory 225572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3286933926 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_mode_toggle.3286933926
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/37.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/39.i2c_host_override.1982613914
Short name T261
Test name
Test status
Simulation time 18555942 ps
CPU time 1.07 seconds
Started Sep 18 08:14:55 AM UTC 24
Finished Sep 18 08:14:57 AM UTC 24
Peak memory 214108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1982613914 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.i2c_host_override.1982613914
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/39.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_tl_errors.2000744926
Short name T200
Test name
Test status
Simulation time 148014809 ps
CPU time 2.51 seconds
Started Sep 18 09:37:42 AM UTC 24
Finished Sep 18 09:37:45 AM UTC 24
Peak memory 215352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2000744926 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_errors.2000744926
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/0.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_tl_intg_err.1277656199
Short name T216
Test name
Test status
Simulation time 87533666 ps
CPU time 2.33 seconds
Started Sep 18 09:38:26 AM UTC 24
Finished Sep 18 09:38:29 AM UTC 24
Peak memory 215072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1277656199 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_intg_err.1277656199
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/8.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/17.i2c_tl_intg_err.3777696936
Short name T209
Test name
Test status
Simulation time 645547925 ps
CPU time 1.91 seconds
Started Sep 18 09:38:47 AM UTC 24
Finished Sep 18 09:38:50 AM UTC 24
Peak memory 214696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3777696936 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_intg_err.3777696936
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/17.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_aliasing.2614343588
Short name T224
Test name
Test status
Simulation time 480668133 ps
CPU time 2.31 seconds
Started Sep 18 09:37:49 AM UTC 24
Finished Sep 18 09:37:53 AM UTC 24
Peak memory 215268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2614343588 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_aliasing.2614343588
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/0.i2c_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_bit_bash.4265161439
Short name T111
Test name
Test status
Simulation time 239748931 ps
CPU time 4.39 seconds
Started Sep 18 09:37:49 AM UTC 24
Finished Sep 18 09:37:55 AM UTC 24
Peak memory 215208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4265161439 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_bit_bash.4265161439
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/0.i2c_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_hw_reset.406661115
Short name T217
Test name
Test status
Simulation time 45459421 ps
CPU time 1.18 seconds
Started Sep 18 09:37:48 AM UTC 24
Finished Sep 18 09:37:50 AM UTC 24
Peak memory 214616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=406661115 -assert nopostproc +UVM_TESTNAME=i2c
_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i
2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_hw_reset.406661115
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/0.i2c_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.270371012
Short name T109
Test name
Test status
Simulation time 31665390 ps
CPU time 1.17 seconds
Started Sep 18 09:37:52 AM UTC 24
Finished Sep 18 09:37:54 AM UTC 24
Peak memory 214740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=270371012 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_mem_rw_with_rand_reset.270371012
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/0.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_rw.699200084
Short name T218
Test name
Test status
Simulation time 50681975 ps
CPU time 0.9 seconds
Started Sep 18 09:37:49 AM UTC 24
Finished Sep 18 09:37:51 AM UTC 24
Peak memory 214800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=699200084 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_rw.699200084
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/0.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_same_csr_outstanding.625380007
Short name T110
Test name
Test status
Simulation time 138069158 ps
CPU time 1.25 seconds
Started Sep 18 09:37:52 AM UTC 24
Finished Sep 18 09:37:54 AM UTC 24
Peak memory 214740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=625380007 -assert nopostproc +UVM_
TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_same_csr_outstanding.625380007
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/0.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_aliasing.1582859793
Short name T226
Test name
Test status
Simulation time 54445157 ps
CPU time 1.77 seconds
Started Sep 18 09:37:59 AM UTC 24
Finished Sep 18 09:38:02 AM UTC 24
Peak memory 214748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1582859793 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_aliasing.1582859793
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/1.i2c_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_bit_bash.1747711741
Short name T1752
Test name
Test status
Simulation time 194933643 ps
CPU time 3.63 seconds
Started Sep 18 09:37:58 AM UTC 24
Finished Sep 18 09:38:03 AM UTC 24
Peak memory 215196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1747711741 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_bit_bash.1747711741
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/1.i2c_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_hw_reset.2700254575
Short name T225
Test name
Test status
Simulation time 63219810 ps
CPU time 0.98 seconds
Started Sep 18 09:37:56 AM UTC 24
Finished Sep 18 09:37:58 AM UTC 24
Peak memory 214676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2700254575 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_hw_reset.2700254575
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/1.i2c_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.3427049641
Short name T205
Test name
Test status
Simulation time 106930221 ps
CPU time 1.48 seconds
Started Sep 18 09:37:59 AM UTC 24
Finished Sep 18 09:38:02 AM UTC 24
Peak memory 214572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3427049641 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_mem_rw_with_rand_reset.3427049641
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/1.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_rw.1938682403
Short name T237
Test name
Test status
Simulation time 43923505 ps
CPU time 0.99 seconds
Started Sep 18 09:37:57 AM UTC 24
Finished Sep 18 09:37:59 AM UTC 24
Peak memory 214740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1938682403 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_rw.1938682403
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/1.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_intr_test.1278410346
Short name T136
Test name
Test status
Simulation time 20372946 ps
CPU time 0.86 seconds
Started Sep 18 09:37:55 AM UTC 24
Finished Sep 18 09:37:57 AM UTC 24
Peak memory 214612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1278410346 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_intr_test.1278410346
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/1.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_same_csr_outstanding.1309689515
Short name T113
Test name
Test status
Simulation time 58562853 ps
CPU time 1.57 seconds
Started Sep 18 09:37:59 AM UTC 24
Finished Sep 18 09:38:02 AM UTC 24
Peak memory 214692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1309689515 -assert nopostproc +UVM
_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_same_csr_outstanding.1309689515
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/1.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_tl_errors.3253078590
Short name T203
Test name
Test status
Simulation time 416205849 ps
CPU time 3.15 seconds
Started Sep 18 09:37:54 AM UTC 24
Finished Sep 18 09:37:58 AM UTC 24
Peak memory 215480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3253078590 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_errors.3253078590
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/1.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_tl_intg_err.2177144004
Short name T112
Test name
Test status
Simulation time 178587746 ps
CPU time 1.98 seconds
Started Sep 18 09:37:55 AM UTC 24
Finished Sep 18 09:37:58 AM UTC 24
Peak memory 214780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2177144004 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_intg_err.2177144004
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/1.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.1271061657
Short name T1781
Test name
Test status
Simulation time 111239548 ps
CPU time 1.28 seconds
Started Sep 18 09:38:32 AM UTC 24
Finished Sep 18 09:38:34 AM UTC 24
Peak memory 214744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=1271061657 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_csr_mem_rw_with_rand_reset.1271061657
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/10.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_csr_rw.3789486774
Short name T1779
Test name
Test status
Simulation time 22942969 ps
CPU time 1.06 seconds
Started Sep 18 09:38:32 AM UTC 24
Finished Sep 18 09:38:34 AM UTC 24
Peak memory 214744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3789486774 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_csr_rw.3789486774
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/10.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_same_csr_outstanding.1503941736
Short name T1782
Test name
Test status
Simulation time 136338204 ps
CPU time 1.37 seconds
Started Sep 18 09:38:32 AM UTC 24
Finished Sep 18 09:38:34 AM UTC 24
Peak memory 214804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1503941736 -assert nopostproc +UVM
_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_same_csr_outstanding.1503941736
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/10.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_tl_errors.1887024365
Short name T1780
Test name
Test status
Simulation time 278590375 ps
CPU time 2.74 seconds
Started Sep 18 09:38:30 AM UTC 24
Finished Sep 18 09:38:34 AM UTC 24
Peak memory 215456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1887024365 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_errors.1887024365
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/10.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_tl_intg_err.1565777410
Short name T214
Test name
Test status
Simulation time 292139291 ps
CPU time 2.1 seconds
Started Sep 18 09:38:32 AM UTC 24
Finished Sep 18 09:38:35 AM UTC 24
Peak memory 215268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1565777410 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_intg_err.1565777410
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/10.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.2786584135
Short name T1787
Test name
Test status
Simulation time 67563631 ps
CPU time 1.5 seconds
Started Sep 18 09:38:35 AM UTC 24
Finished Sep 18 09:38:37 AM UTC 24
Peak memory 214804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=2786584135 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_csr_mem_rw_with_rand_reset.2786584135
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/11.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_csr_rw.3496509525
Short name T1785
Test name
Test status
Simulation time 96506688 ps
CPU time 1.12 seconds
Started Sep 18 09:38:35 AM UTC 24
Finished Sep 18 09:38:37 AM UTC 24
Peak memory 214744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3496509525 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_csr_rw.3496509525
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/11.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_intr_test.3097856483
Short name T1784
Test name
Test status
Simulation time 24334539 ps
CPU time 0.99 seconds
Started Sep 18 09:38:35 AM UTC 24
Finished Sep 18 09:38:36 AM UTC 24
Peak memory 214612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3097856483 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_intr_test.3097856483
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/11.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_same_csr_outstanding.2036644485
Short name T1786
Test name
Test status
Simulation time 47460216 ps
CPU time 1.49 seconds
Started Sep 18 09:38:35 AM UTC 24
Finished Sep 18 09:38:37 AM UTC 24
Peak memory 214748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2036644485 -assert nopostproc +UVM
_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_same_csr_outstanding.2036644485
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/11.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_tl_errors.435432290
Short name T1783
Test name
Test status
Simulation time 1480498688 ps
CPU time 2.52 seconds
Started Sep 18 09:38:32 AM UTC 24
Finished Sep 18 09:38:36 AM UTC 24
Peak memory 215296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=435432290 -assert nopostproc +UVM_TESTNAME=i2c_base_tes
t +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_errors.435432290
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/11.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_tl_intg_err.2205018273
Short name T264
Test name
Test status
Simulation time 394873063 ps
CPU time 1.63 seconds
Started Sep 18 09:38:33 AM UTC 24
Finished Sep 18 09:38:36 AM UTC 24
Peak memory 214740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2205018273 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_intg_err.2205018273
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/11.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.1652601265
Short name T1791
Test name
Test status
Simulation time 32792376 ps
CPU time 1.43 seconds
Started Sep 18 09:38:37 AM UTC 24
Finished Sep 18 09:38:39 AM UTC 24
Peak memory 214744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=1652601265 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_csr_mem_rw_with_rand_reset.1652601265
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/12.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_csr_rw.1536325455
Short name T1788
Test name
Test status
Simulation time 20269088 ps
CPU time 1.03 seconds
Started Sep 18 09:38:37 AM UTC 24
Finished Sep 18 09:38:39 AM UTC 24
Peak memory 214744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1536325455 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_csr_rw.1536325455
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/12.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_intr_test.3804000656
Short name T1789
Test name
Test status
Simulation time 41551536 ps
CPU time 0.91 seconds
Started Sep 18 09:38:36 AM UTC 24
Finished Sep 18 09:38:38 AM UTC 24
Peak memory 214340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3804000656 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_intr_test.3804000656
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/12.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_same_csr_outstanding.4125227638
Short name T1790
Test name
Test status
Simulation time 35693375 ps
CPU time 1.36 seconds
Started Sep 18 09:38:37 AM UTC 24
Finished Sep 18 09:38:39 AM UTC 24
Peak memory 214740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4125227638 -assert nopostproc +UVM
_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_same_csr_outstanding.4125227638
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/12.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_tl_errors.2054411135
Short name T1792
Test name
Test status
Simulation time 148953234 ps
CPU time 2.71 seconds
Started Sep 18 09:38:36 AM UTC 24
Finished Sep 18 09:38:40 AM UTC 24
Peak memory 215260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2054411135 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_errors.2054411135
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/12.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.605804954
Short name T1796
Test name
Test status
Simulation time 47366355 ps
CPU time 1.14 seconds
Started Sep 18 09:38:40 AM UTC 24
Finished Sep 18 09:38:42 AM UTC 24
Peak memory 214740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=605804954 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_csr_mem_rw_with_rand_reset.605804954
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/13.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_csr_rw.1132417133
Short name T1793
Test name
Test status
Simulation time 22721566 ps
CPU time 0.99 seconds
Started Sep 18 09:38:38 AM UTC 24
Finished Sep 18 09:38:40 AM UTC 24
Peak memory 214744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1132417133 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_csr_rw.1132417133
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/13.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_intr_test.1358548240
Short name T285
Test name
Test status
Simulation time 44441351 ps
CPU time 1.01 seconds
Started Sep 18 09:38:38 AM UTC 24
Finished Sep 18 09:38:40 AM UTC 24
Peak memory 214612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1358548240 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_intr_test.1358548240
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/13.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_same_csr_outstanding.20863986
Short name T1797
Test name
Test status
Simulation time 59604208 ps
CPU time 1.44 seconds
Started Sep 18 09:38:40 AM UTC 24
Finished Sep 18 09:38:42 AM UTC 24
Peak memory 214628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=20863986 -assert nopostproc +UVM_T
ESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_same_csr_outstanding.20863986
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/13.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_tl_errors.498790098
Short name T1795
Test name
Test status
Simulation time 212435080 ps
CPU time 2.08 seconds
Started Sep 18 09:38:38 AM UTC 24
Finished Sep 18 09:38:41 AM UTC 24
Peak memory 215460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=498790098 -assert nopostproc +UVM_TESTNAME=i2c_base_tes
t +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_errors.498790098
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/13.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_tl_intg_err.3187155873
Short name T1794
Test name
Test status
Simulation time 84346510 ps
CPU time 1.92 seconds
Started Sep 18 09:38:38 AM UTC 24
Finished Sep 18 09:38:41 AM UTC 24
Peak memory 214648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3187155873 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_intg_err.3187155873
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/13.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.3794900458
Short name T1803
Test name
Test status
Simulation time 84396828 ps
CPU time 1.75 seconds
Started Sep 18 09:38:42 AM UTC 24
Finished Sep 18 09:38:44 AM UTC 24
Peak memory 214760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3794900458 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_csr_mem_rw_with_rand_reset.3794900458
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/14.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_csr_rw.1739134111
Short name T1800
Test name
Test status
Simulation time 25815449 ps
CPU time 1.06 seconds
Started Sep 18 09:38:42 AM UTC 24
Finished Sep 18 09:38:44 AM UTC 24
Peak memory 214744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1739134111 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_csr_rw.1739134111
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/14.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_intr_test.117638903
Short name T1799
Test name
Test status
Simulation time 17155910 ps
CPU time 0.93 seconds
Started Sep 18 09:38:41 AM UTC 24
Finished Sep 18 09:38:43 AM UTC 24
Peak memory 214616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=117638903 -assert nopostproc +UVM_TESTNAME=i2c_base_tes
t +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_intr_test.117638903
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/14.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_same_csr_outstanding.4293038532
Short name T1801
Test name
Test status
Simulation time 32200249 ps
CPU time 1.3 seconds
Started Sep 18 09:38:42 AM UTC 24
Finished Sep 18 09:38:44 AM UTC 24
Peak memory 214740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4293038532 -assert nopostproc +UVM
_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_same_csr_outstanding.4293038532
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/14.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_tl_errors.3513892251
Short name T1798
Test name
Test status
Simulation time 83281579 ps
CPU time 2.02 seconds
Started Sep 18 09:38:40 AM UTC 24
Finished Sep 18 09:38:43 AM UTC 24
Peak memory 215396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3513892251 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_errors.3513892251
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/14.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_tl_intg_err.1417182934
Short name T1802
Test name
Test status
Simulation time 89068007 ps
CPU time 2.86 seconds
Started Sep 18 09:38:40 AM UTC 24
Finished Sep 18 09:38:44 AM UTC 24
Peak memory 215292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1417182934 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_intg_err.1417182934
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/14.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.244931538
Short name T1809
Test name
Test status
Simulation time 172401675 ps
CPU time 2.02 seconds
Started Sep 18 09:38:45 AM UTC 24
Finished Sep 18 09:38:48 AM UTC 24
Peak memory 225700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=244931538 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_csr_mem_rw_with_rand_reset.244931538
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/15.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/15.i2c_csr_rw.1329575591
Short name T1805
Test name
Test status
Simulation time 97224832 ps
CPU time 1.14 seconds
Started Sep 18 09:38:43 AM UTC 24
Finished Sep 18 09:38:45 AM UTC 24
Peak memory 214744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1329575591 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_csr_rw.1329575591
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/15.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/15.i2c_intr_test.450501836
Short name T1804
Test name
Test status
Simulation time 67083506 ps
CPU time 0.96 seconds
Started Sep 18 09:38:43 AM UTC 24
Finished Sep 18 09:38:45 AM UTC 24
Peak memory 214616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=450501836 -assert nopostproc +UVM_TESTNAME=i2c_base_tes
t +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_intr_test.450501836
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/15.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/15.i2c_same_csr_outstanding.2583398406
Short name T1808
Test name
Test status
Simulation time 32254149 ps
CPU time 1.15 seconds
Started Sep 18 09:38:45 AM UTC 24
Finished Sep 18 09:38:47 AM UTC 24
Peak memory 214740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2583398406 -assert nopostproc +UVM
_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_same_csr_outstanding.2583398406
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/15.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/15.i2c_tl_errors.3421598402
Short name T1806
Test name
Test status
Simulation time 47482905 ps
CPU time 1.7 seconds
Started Sep 18 09:38:43 AM UTC 24
Finished Sep 18 09:38:46 AM UTC 24
Peak memory 214684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3421598402 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_errors.3421598402
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/15.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/15.i2c_tl_intg_err.3876139864
Short name T1807
Test name
Test status
Simulation time 146216240 ps
CPU time 1.91 seconds
Started Sep 18 09:38:43 AM UTC 24
Finished Sep 18 09:38:46 AM UTC 24
Peak memory 214716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3876139864 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_intg_err.3876139864
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/15.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.1294986094
Short name T1812
Test name
Test status
Simulation time 20724424 ps
CPU time 1.28 seconds
Started Sep 18 09:38:47 AM UTC 24
Finished Sep 18 09:38:49 AM UTC 24
Peak memory 214744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=1294986094 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_csr_mem_rw_with_rand_reset.1294986094
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/16.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/16.i2c_csr_rw.846675509
Short name T236
Test name
Test status
Simulation time 43150211 ps
CPU time 1.07 seconds
Started Sep 18 09:38:45 AM UTC 24
Finished Sep 18 09:38:48 AM UTC 24
Peak memory 214800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=846675509 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_csr_rw.846675509
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/16.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/16.i2c_intr_test.2132442866
Short name T282
Test name
Test status
Simulation time 19379598 ps
CPU time 0.99 seconds
Started Sep 18 09:38:45 AM UTC 24
Finished Sep 18 09:38:47 AM UTC 24
Peak memory 214612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2132442866 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_intr_test.2132442866
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/16.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/16.i2c_same_csr_outstanding.1447209538
Short name T1813
Test name
Test status
Simulation time 38154000 ps
CPU time 1.25 seconds
Started Sep 18 09:38:47 AM UTC 24
Finished Sep 18 09:38:49 AM UTC 24
Peak memory 214740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1447209538 -assert nopostproc +UVM
_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_same_csr_outstanding.1447209538
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/16.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/16.i2c_tl_errors.3699399433
Short name T1811
Test name
Test status
Simulation time 267877137 ps
CPU time 2.74 seconds
Started Sep 18 09:38:45 AM UTC 24
Finished Sep 18 09:38:49 AM UTC 24
Peak memory 215204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3699399433 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_errors.3699399433
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/16.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/16.i2c_tl_intg_err.4281082454
Short name T1810
Test name
Test status
Simulation time 313927561 ps
CPU time 1.98 seconds
Started Sep 18 09:38:45 AM UTC 24
Finished Sep 18 09:38:48 AM UTC 24
Peak memory 214732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4281082454 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_intg_err.4281082454
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/16.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.2235928964
Short name T1820
Test name
Test status
Simulation time 25652967 ps
CPU time 1.56 seconds
Started Sep 18 09:38:51 AM UTC 24
Finished Sep 18 09:38:54 AM UTC 24
Peak memory 214752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=2235928964 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_csr_mem_rw_with_rand_reset.2235928964
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/17.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/17.i2c_csr_rw.3993426421
Short name T1814
Test name
Test status
Simulation time 59331029 ps
CPU time 0.93 seconds
Started Sep 18 09:38:49 AM UTC 24
Finished Sep 18 09:38:51 AM UTC 24
Peak memory 214376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3993426421 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_csr_rw.3993426421
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/17.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/17.i2c_intr_test.1799816364
Short name T1815
Test name
Test status
Simulation time 16286152 ps
CPU time 1.04 seconds
Started Sep 18 09:38:49 AM UTC 24
Finished Sep 18 09:38:51 AM UTC 24
Peak memory 214612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1799816364 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_intr_test.1799816364
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/17.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/17.i2c_same_csr_outstanding.1120116414
Short name T1816
Test name
Test status
Simulation time 56433310 ps
CPU time 1.16 seconds
Started Sep 18 09:38:49 AM UTC 24
Finished Sep 18 09:38:51 AM UTC 24
Peak memory 214740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1120116414 -assert nopostproc +UVM
_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_same_csr_outstanding.1120116414
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/17.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/17.i2c_tl_errors.2010513755
Short name T1817
Test name
Test status
Simulation time 50593715 ps
CPU time 3.94 seconds
Started Sep 18 09:38:47 AM UTC 24
Finished Sep 18 09:38:52 AM UTC 24
Peak memory 215456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2010513755 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_errors.2010513755
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/17.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.3672991140
Short name T1821
Test name
Test status
Simulation time 639091239 ps
CPU time 1.33 seconds
Started Sep 18 09:38:51 AM UTC 24
Finished Sep 18 09:38:54 AM UTC 24
Peak memory 214744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3672991140 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_csr_mem_rw_with_rand_reset.3672991140
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/18.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/18.i2c_csr_rw.1462296088
Short name T1819
Test name
Test status
Simulation time 17116336 ps
CPU time 1.03 seconds
Started Sep 18 09:38:51 AM UTC 24
Finished Sep 18 09:38:53 AM UTC 24
Peak memory 214744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1462296088 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_csr_rw.1462296088
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/18.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/18.i2c_intr_test.3605307940
Short name T1818
Test name
Test status
Simulation time 18346699 ps
CPU time 1.06 seconds
Started Sep 18 09:38:51 AM UTC 24
Finished Sep 18 09:38:53 AM UTC 24
Peak memory 214612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3605307940 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_intr_test.3605307940
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/18.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/18.i2c_tl_errors.2859102508
Short name T1823
Test name
Test status
Simulation time 303453052 ps
CPU time 2.94 seconds
Started Sep 18 09:38:51 AM UTC 24
Finished Sep 18 09:38:55 AM UTC 24
Peak memory 215516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2859102508 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_errors.2859102508
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/18.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/18.i2c_tl_intg_err.1101502244
Short name T213
Test name
Test status
Simulation time 505869337 ps
CPU time 1.98 seconds
Started Sep 18 09:38:51 AM UTC 24
Finished Sep 18 09:38:54 AM UTC 24
Peak memory 214696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1101502244 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_intg_err.1101502244
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/18.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.2900686933
Short name T1829
Test name
Test status
Simulation time 36078746 ps
CPU time 1.44 seconds
Started Sep 18 09:38:55 AM UTC 24
Finished Sep 18 09:38:57 AM UTC 24
Peak memory 214744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=2900686933 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_csr_mem_rw_with_rand_reset.2900686933
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/19.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/19.i2c_csr_rw.493014622
Short name T1825
Test name
Test status
Simulation time 27943390 ps
CPU time 1.2 seconds
Started Sep 18 09:38:54 AM UTC 24
Finished Sep 18 09:38:57 AM UTC 24
Peak memory 214800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=493014622 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_csr_rw.493014622
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/19.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/19.i2c_intr_test.3505474394
Short name T1822
Test name
Test status
Simulation time 43231457 ps
CPU time 0.97 seconds
Started Sep 18 09:38:53 AM UTC 24
Finished Sep 18 09:38:55 AM UTC 24
Peak memory 214612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3505474394 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_intr_test.3505474394
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/19.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/19.i2c_same_csr_outstanding.4266606339
Short name T1827
Test name
Test status
Simulation time 75850169 ps
CPU time 1.23 seconds
Started Sep 18 09:38:54 AM UTC 24
Finished Sep 18 09:38:57 AM UTC 24
Peak memory 214740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4266606339 -assert nopostproc +UVM
_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_same_csr_outstanding.4266606339
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/19.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/19.i2c_tl_errors.2101421533
Short name T1824
Test name
Test status
Simulation time 29255421 ps
CPU time 2.22 seconds
Started Sep 18 09:38:53 AM UTC 24
Finished Sep 18 09:38:56 AM UTC 24
Peak memory 215520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2101421533 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_errors.2101421533
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/19.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/19.i2c_tl_intg_err.1703051765
Short name T1826
Test name
Test status
Simulation time 784807905 ps
CPU time 2.93 seconds
Started Sep 18 09:38:53 AM UTC 24
Finished Sep 18 09:38:57 AM UTC 24
Peak memory 215420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1703051765 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_intg_err.1703051765
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/19.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_aliasing.3231016354
Short name T227
Test name
Test status
Simulation time 43574974 ps
CPU time 2.37 seconds
Started Sep 18 09:38:06 AM UTC 24
Finished Sep 18 09:38:09 AM UTC 24
Peak memory 215204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3231016354 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_aliasing.3231016354
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/2.i2c_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_bit_bash.340760600
Short name T228
Test name
Test status
Simulation time 2063315912 ps
CPU time 7.13 seconds
Started Sep 18 09:38:04 AM UTC 24
Finished Sep 18 09:38:12 AM UTC 24
Peak memory 215264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=340760600 -assert nopostproc +UVM_TESTNAME=i2c
_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i
2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_bit_bash.340760600
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/2.i2c_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_hw_reset.338948267
Short name T1753
Test name
Test status
Simulation time 64929684 ps
CPU time 1.19 seconds
Started Sep 18 09:38:03 AM UTC 24
Finished Sep 18 09:38:05 AM UTC 24
Peak memory 214616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=338948267 -assert nopostproc +UVM_TESTNAME=i2c
_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i
2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_hw_reset.338948267
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/2.i2c_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.3122938141
Short name T134
Test name
Test status
Simulation time 128284180 ps
CPU time 1.48 seconds
Started Sep 18 09:38:06 AM UTC 24
Finished Sep 18 09:38:09 AM UTC 24
Peak memory 214572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3122938141 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_mem_rw_with_rand_reset.3122938141
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/2.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_rw.1131179410
Short name T114
Test name
Test status
Simulation time 24658478 ps
CPU time 1.01 seconds
Started Sep 18 09:38:03 AM UTC 24
Finished Sep 18 09:38:05 AM UTC 24
Peak memory 214680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1131179410 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_rw.1131179410
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/2.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_intr_test.408465389
Short name T281
Test name
Test status
Simulation time 51852906 ps
CPU time 1.05 seconds
Started Sep 18 09:38:03 AM UTC 24
Finished Sep 18 09:38:05 AM UTC 24
Peak memory 214616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=408465389 -assert nopostproc +UVM_TESTNAME=i2c_base_tes
t +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_intr_test.408465389
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/2.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_same_csr_outstanding.980585614
Short name T117
Test name
Test status
Simulation time 190307701 ps
CPU time 1.59 seconds
Started Sep 18 09:38:06 AM UTC 24
Finished Sep 18 09:38:09 AM UTC 24
Peak memory 214708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=980585614 -assert nopostproc +UVM_
TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_same_csr_outstanding.980585614
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/2.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_tl_intg_err.635247746
Short name T116
Test name
Test status
Simulation time 563242175 ps
CPU time 3.01 seconds
Started Sep 18 09:38:03 AM UTC 24
Finished Sep 18 09:38:07 AM UTC 24
Peak memory 215168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=635247746 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_intg_err.635247746
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/2.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/20.i2c_intr_test.2808037778
Short name T283
Test name
Test status
Simulation time 16303105 ps
CPU time 1.07 seconds
Started Sep 18 09:38:55 AM UTC 24
Finished Sep 18 09:38:57 AM UTC 24
Peak memory 214612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2808037778 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.i2c_intr_test.2808037778
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/20.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/21.i2c_intr_test.1525347469
Short name T1828
Test name
Test status
Simulation time 97721924 ps
CPU time 0.99 seconds
Started Sep 18 09:38:55 AM UTC 24
Finished Sep 18 09:38:57 AM UTC 24
Peak memory 214612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1525347469 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.i2c_intr_test.1525347469
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/21.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/22.i2c_intr_test.3288929450
Short name T1830
Test name
Test status
Simulation time 43046931 ps
CPU time 0.96 seconds
Started Sep 18 09:38:56 AM UTC 24
Finished Sep 18 09:38:58 AM UTC 24
Peak memory 214616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3288929450 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.i2c_intr_test.3288929450
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/22.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/23.i2c_intr_test.4140917366
Short name T1833
Test name
Test status
Simulation time 16627336 ps
CPU time 1.09 seconds
Started Sep 18 09:38:56 AM UTC 24
Finished Sep 18 09:38:58 AM UTC 24
Peak memory 214612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4140917366 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.i2c_intr_test.4140917366
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/23.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/24.i2c_intr_test.2967078211
Short name T1831
Test name
Test status
Simulation time 40629413 ps
CPU time 0.99 seconds
Started Sep 18 09:38:56 AM UTC 24
Finished Sep 18 09:38:58 AM UTC 24
Peak memory 214612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2967078211 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.i2c_intr_test.2967078211
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/24.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/25.i2c_intr_test.4131537628
Short name T1832
Test name
Test status
Simulation time 52043417 ps
CPU time 0.98 seconds
Started Sep 18 09:38:57 AM UTC 24
Finished Sep 18 09:38:58 AM UTC 24
Peak memory 214612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4131537628 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.i2c_intr_test.4131537628
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/25.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/26.i2c_intr_test.4126168594
Short name T1834
Test name
Test status
Simulation time 151311600 ps
CPU time 1.03 seconds
Started Sep 18 09:39:00 AM UTC 24
Finished Sep 18 09:39:02 AM UTC 24
Peak memory 214612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4126168594 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.i2c_intr_test.4126168594
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/26.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/27.i2c_intr_test.2087179250
Short name T1836
Test name
Test status
Simulation time 33602134 ps
CPU time 1.07 seconds
Started Sep 18 09:39:00 AM UTC 24
Finished Sep 18 09:39:02 AM UTC 24
Peak memory 214616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2087179250 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.i2c_intr_test.2087179250
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/27.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/28.i2c_intr_test.85251187
Short name T1835
Test name
Test status
Simulation time 17158440 ps
CPU time 0.93 seconds
Started Sep 18 09:39:00 AM UTC 24
Finished Sep 18 09:39:02 AM UTC 24
Peak memory 214680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=85251187 -assert nopostproc +UVM_TESTNAME=i2c_base_test
+UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.i2c_intr_test.85251187
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/28.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/29.i2c_intr_test.336801811
Short name T1837
Test name
Test status
Simulation time 19191677 ps
CPU time 0.94 seconds
Started Sep 18 09:39:00 AM UTC 24
Finished Sep 18 09:39:02 AM UTC 24
Peak memory 214128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=336801811 -assert nopostproc +UVM_TESTNAME=i2c_base_tes
t +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.i2c_intr_test.336801811
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/29.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_aliasing.3875315053
Short name T1755
Test name
Test status
Simulation time 48337152 ps
CPU time 1.58 seconds
Started Sep 18 09:38:12 AM UTC 24
Finished Sep 18 09:38:14 AM UTC 24
Peak memory 214748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3875315053 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_aliasing.3875315053
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/3.i2c_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_bit_bash.3781735852
Short name T1757
Test name
Test status
Simulation time 2489786529 ps
CPU time 3.86 seconds
Started Sep 18 09:38:12 AM UTC 24
Finished Sep 18 09:38:17 AM UTC 24
Peak memory 215460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3781735852 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_bit_bash.3781735852
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/3.i2c_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_hw_reset.2526796503
Short name T1754
Test name
Test status
Simulation time 34001886 ps
CPU time 0.87 seconds
Started Sep 18 09:38:09 AM UTC 24
Finished Sep 18 09:38:11 AM UTC 24
Peak memory 214800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2526796503 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_hw_reset.2526796503
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/3.i2c_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.628920278
Short name T222
Test name
Test status
Simulation time 112254861 ps
CPU time 1.86 seconds
Started Sep 18 09:38:13 AM UTC 24
Finished Sep 18 09:38:16 AM UTC 24
Peak memory 224756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=628920278 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_mem_rw_with_rand_reset.628920278
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/3.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_rw.3964672852
Short name T229
Test name
Test status
Simulation time 20062411 ps
CPU time 0.93 seconds
Started Sep 18 09:38:11 AM UTC 24
Finished Sep 18 09:38:12 AM UTC 24
Peak memory 214740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3964672852 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_rw.3964672852
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/3.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_intr_test.4001417485
Short name T275
Test name
Test status
Simulation time 46119562 ps
CPU time 0.99 seconds
Started Sep 18 09:38:09 AM UTC 24
Finished Sep 18 09:38:11 AM UTC 24
Peak memory 214612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4001417485 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_intr_test.4001417485
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/3.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_same_csr_outstanding.111870310
Short name T238
Test name
Test status
Simulation time 62108708 ps
CPU time 1.76 seconds
Started Sep 18 09:38:12 AM UTC 24
Finished Sep 18 09:38:15 AM UTC 24
Peak memory 214716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=111870310 -assert nopostproc +UVM_
TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_same_csr_outstanding.111870310
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/3.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_tl_errors.3587638567
Short name T206
Test name
Test status
Simulation time 392074215 ps
CPU time 2.61 seconds
Started Sep 18 09:38:07 AM UTC 24
Finished Sep 18 09:38:11 AM UTC 24
Peak memory 225400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3587638567 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_errors.3587638567
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/3.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_tl_intg_err.508961270
Short name T212
Test name
Test status
Simulation time 645441478 ps
CPU time 3.08 seconds
Started Sep 18 09:38:07 AM UTC 24
Finished Sep 18 09:38:11 AM UTC 24
Peak memory 215264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=508961270 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_intg_err.508961270
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/3.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/30.i2c_intr_test.72519359
Short name T1838
Test name
Test status
Simulation time 42871212 ps
CPU time 0.99 seconds
Started Sep 18 09:39:00 AM UTC 24
Finished Sep 18 09:39:02 AM UTC 24
Peak memory 214680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=72519359 -assert nopostproc +UVM_TESTNAME=i2c_base_test
+UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.i2c_intr_test.72519359
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/30.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/31.i2c_intr_test.2652230607
Short name T1840
Test name
Test status
Simulation time 54418370 ps
CPU time 0.99 seconds
Started Sep 18 09:39:00 AM UTC 24
Finished Sep 18 09:39:02 AM UTC 24
Peak memory 214288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2652230607 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.i2c_intr_test.2652230607
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/31.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/32.i2c_intr_test.4029800440
Short name T1839
Test name
Test status
Simulation time 20156486 ps
CPU time 0.96 seconds
Started Sep 18 09:39:00 AM UTC 24
Finished Sep 18 09:39:02 AM UTC 24
Peak memory 214464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4029800440 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.i2c_intr_test.4029800440
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/32.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/33.i2c_intr_test.148561959
Short name T1841
Test name
Test status
Simulation time 41448831 ps
CPU time 1.03 seconds
Started Sep 18 09:39:00 AM UTC 24
Finished Sep 18 09:39:02 AM UTC 24
Peak memory 213828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=148561959 -assert nopostproc +UVM_TESTNAME=i2c_base_tes
t +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.i2c_intr_test.148561959
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/33.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/34.i2c_intr_test.2540098618
Short name T1842
Test name
Test status
Simulation time 20573928 ps
CPU time 1.04 seconds
Started Sep 18 09:39:00 AM UTC 24
Finished Sep 18 09:39:02 AM UTC 24
Peak memory 214600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2540098618 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.i2c_intr_test.2540098618
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/34.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/35.i2c_intr_test.246877624
Short name T1843
Test name
Test status
Simulation time 38030373 ps
CPU time 1.04 seconds
Started Sep 18 09:39:00 AM UTC 24
Finished Sep 18 09:39:02 AM UTC 24
Peak memory 214604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=246877624 -assert nopostproc +UVM_TESTNAME=i2c_base_tes
t +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.i2c_intr_test.246877624
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/35.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/36.i2c_intr_test.2558733766
Short name T1844
Test name
Test status
Simulation time 19313711 ps
CPU time 1.13 seconds
Started Sep 18 09:39:00 AM UTC 24
Finished Sep 18 09:39:02 AM UTC 24
Peak memory 214604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2558733766 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.i2c_intr_test.2558733766
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/36.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/37.i2c_intr_test.3561210481
Short name T1847
Test name
Test status
Simulation time 17953597 ps
CPU time 1.06 seconds
Started Sep 18 09:39:05 AM UTC 24
Finished Sep 18 09:39:08 AM UTC 24
Peak memory 214612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3561210481 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.i2c_intr_test.3561210481
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/37.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/38.i2c_intr_test.2905260790
Short name T1846
Test name
Test status
Simulation time 19044101 ps
CPU time 1.06 seconds
Started Sep 18 09:39:05 AM UTC 24
Finished Sep 18 09:39:08 AM UTC 24
Peak memory 214612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2905260790 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.i2c_intr_test.2905260790
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/38.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/39.i2c_intr_test.3802402774
Short name T1845
Test name
Test status
Simulation time 20124578 ps
CPU time 0.99 seconds
Started Sep 18 09:39:05 AM UTC 24
Finished Sep 18 09:39:08 AM UTC 24
Peak memory 214736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3802402774 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.i2c_intr_test.3802402774
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/39.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_aliasing.26988286
Short name T232
Test name
Test status
Simulation time 954022248 ps
CPU time 2.46 seconds
Started Sep 18 09:38:17 AM UTC 24
Finished Sep 18 09:38:20 AM UTC 24
Peak memory 215200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=26988286 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_aliasing.26988286
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/4.i2c_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_bit_bash.3808437928
Short name T1762
Test name
Test status
Simulation time 531848641 ps
CPU time 7.03 seconds
Started Sep 18 09:38:15 AM UTC 24
Finished Sep 18 09:38:24 AM UTC 24
Peak memory 215396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3808437928 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_bit_bash.3808437928
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/4.i2c_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_hw_reset.2719587880
Short name T230
Test name
Test status
Simulation time 81192063 ps
CPU time 1.03 seconds
Started Sep 18 09:38:15 AM UTC 24
Finished Sep 18 09:38:17 AM UTC 24
Peak memory 214800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2719587880 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_hw_reset.2719587880
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/4.i2c_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.3234334931
Short name T1758
Test name
Test status
Simulation time 26454306 ps
CPU time 1.59 seconds
Started Sep 18 09:38:17 AM UTC 24
Finished Sep 18 09:38:19 AM UTC 24
Peak memory 224620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3234334931 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_mem_rw_with_rand_reset.3234334931
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/4.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_intr_test.1335024744
Short name T279
Test name
Test status
Simulation time 33311813 ps
CPU time 0.89 seconds
Started Sep 18 09:38:13 AM UTC 24
Finished Sep 18 09:38:15 AM UTC 24
Peak memory 214612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1335024744 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_intr_test.1335024744
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/4.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_same_csr_outstanding.2794711327
Short name T239
Test name
Test status
Simulation time 111787116 ps
CPU time 1.36 seconds
Started Sep 18 09:38:17 AM UTC 24
Finished Sep 18 09:38:19 AM UTC 24
Peak memory 214692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2794711327 -assert nopostproc +UVM
_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_same_csr_outstanding.2794711327
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/4.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_tl_errors.3379153328
Short name T1756
Test name
Test status
Simulation time 257308472 ps
CPU time 2.08 seconds
Started Sep 18 09:38:13 AM UTC 24
Finished Sep 18 09:38:16 AM UTC 24
Peak memory 215288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3379153328 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_errors.3379153328
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/4.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_tl_intg_err.1989395172
Short name T204
Test name
Test status
Simulation time 79475461 ps
CPU time 2.03 seconds
Started Sep 18 09:38:13 AM UTC 24
Finished Sep 18 09:38:16 AM UTC 24
Peak memory 215420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1989395172 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_intg_err.1989395172
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/4.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/40.i2c_intr_test.4128177048
Short name T1851
Test name
Test status
Simulation time 16337203 ps
CPU time 0.98 seconds
Started Sep 18 09:39:05 AM UTC 24
Finished Sep 18 09:39:08 AM UTC 24
Peak memory 214552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4128177048 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.i2c_intr_test.4128177048
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/40.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/41.i2c_intr_test.1943255792
Short name T1852
Test name
Test status
Simulation time 52770651 ps
CPU time 1 seconds
Started Sep 18 09:39:05 AM UTC 24
Finished Sep 18 09:39:08 AM UTC 24
Peak memory 212796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1943255792 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.i2c_intr_test.1943255792
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/41.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/42.i2c_intr_test.3982102732
Short name T1855
Test name
Test status
Simulation time 47566867 ps
CPU time 1 seconds
Started Sep 18 09:39:05 AM UTC 24
Finished Sep 18 09:39:08 AM UTC 24
Peak memory 214612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3982102732 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.i2c_intr_test.3982102732
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/42.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/43.i2c_intr_test.3032845966
Short name T1848
Test name
Test status
Simulation time 37956221 ps
CPU time 0.91 seconds
Started Sep 18 09:39:05 AM UTC 24
Finished Sep 18 09:39:08 AM UTC 24
Peak memory 214612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3032845966 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.i2c_intr_test.3032845966
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/43.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/44.i2c_intr_test.977884000
Short name T1849
Test name
Test status
Simulation time 20392365 ps
CPU time 0.93 seconds
Started Sep 18 09:39:05 AM UTC 24
Finished Sep 18 09:39:08 AM UTC 24
Peak memory 212876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=977884000 -assert nopostproc +UVM_TESTNAME=i2c_base_tes
t +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.i2c_intr_test.977884000
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/44.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/45.i2c_intr_test.1867389738
Short name T1853
Test name
Test status
Simulation time 50835903 ps
CPU time 0.95 seconds
Started Sep 18 09:39:05 AM UTC 24
Finished Sep 18 09:39:08 AM UTC 24
Peak memory 214544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1867389738 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.i2c_intr_test.1867389738
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/45.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/46.i2c_intr_test.551160679
Short name T1850
Test name
Test status
Simulation time 22422024 ps
CPU time 0.88 seconds
Started Sep 18 09:39:05 AM UTC 24
Finished Sep 18 09:39:08 AM UTC 24
Peak memory 214616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=551160679 -assert nopostproc +UVM_TESTNAME=i2c_base_tes
t +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.i2c_intr_test.551160679
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/46.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/47.i2c_intr_test.3313882764
Short name T1854
Test name
Test status
Simulation time 19168978 ps
CPU time 0.98 seconds
Started Sep 18 09:39:05 AM UTC 24
Finished Sep 18 09:39:08 AM UTC 24
Peak memory 214608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3313882764 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.i2c_intr_test.3313882764
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/47.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/48.i2c_intr_test.13041209
Short name T1856
Test name
Test status
Simulation time 24405448 ps
CPU time 0.93 seconds
Started Sep 18 09:39:12 AM UTC 24
Finished Sep 18 09:39:14 AM UTC 24
Peak memory 214540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=13041209 -assert nopostproc +UVM_TESTNAME=i2c_base_test
+UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.i2c_intr_test.13041209
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/48.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/49.i2c_intr_test.2854648929
Short name T1857
Test name
Test status
Simulation time 57442901 ps
CPU time 0.97 seconds
Started Sep 18 09:39:12 AM UTC 24
Finished Sep 18 09:39:14 AM UTC 24
Peak memory 214508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2854648929 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.i2c_intr_test.2854648929
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/49.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.4153521597
Short name T1761
Test name
Test status
Simulation time 48107878 ps
CPU time 1.7 seconds
Started Sep 18 09:38:20 AM UTC 24
Finished Sep 18 09:38:23 AM UTC 24
Peak memory 214488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=4153521597 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_csr_mem_rw_with_rand_reset.4153521597
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/5.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_csr_rw.2621681974
Short name T233
Test name
Test status
Simulation time 173448613 ps
CPU time 1.04 seconds
Started Sep 18 09:38:18 AM UTC 24
Finished Sep 18 09:38:20 AM UTC 24
Peak memory 214680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2621681974 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_csr_rw.2621681974
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/5.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_intr_test.3741808142
Short name T277
Test name
Test status
Simulation time 22481019 ps
CPU time 0.99 seconds
Started Sep 18 09:38:18 AM UTC 24
Finished Sep 18 09:38:20 AM UTC 24
Peak memory 214612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3741808142 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_intr_test.3741808142
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/5.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_same_csr_outstanding.1051094004
Short name T1760
Test name
Test status
Simulation time 93428820 ps
CPU time 1.41 seconds
Started Sep 18 09:38:20 AM UTC 24
Finished Sep 18 09:38:23 AM UTC 24
Peak memory 214692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1051094004 -assert nopostproc +UVM
_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_same_csr_outstanding.1051094004
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/5.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_tl_errors.2972830843
Short name T1759
Test name
Test status
Simulation time 88452507 ps
CPU time 2.42 seconds
Started Sep 18 09:38:17 AM UTC 24
Finished Sep 18 09:38:20 AM UTC 24
Peak memory 215288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2972830843 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_errors.2972830843
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/5.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.693837460
Short name T1765
Test name
Test status
Simulation time 24320021 ps
CPU time 1.53 seconds
Started Sep 18 09:38:23 AM UTC 24
Finished Sep 18 09:38:26 AM UTC 24
Peak memory 214808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=693837460 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_csr_mem_rw_with_rand_reset.693837460
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/6.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_csr_rw.3149974708
Short name T234
Test name
Test status
Simulation time 52054256 ps
CPU time 1.05 seconds
Started Sep 18 09:38:22 AM UTC 24
Finished Sep 18 09:38:24 AM UTC 24
Peak memory 214740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3149974708 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_csr_rw.3149974708
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/6.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_intr_test.1836047639
Short name T276
Test name
Test status
Simulation time 20417215 ps
CPU time 0.91 seconds
Started Sep 18 09:38:22 AM UTC 24
Finished Sep 18 09:38:24 AM UTC 24
Peak memory 214612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1836047639 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_intr_test.1836047639
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/6.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_same_csr_outstanding.2850983694
Short name T1763
Test name
Test status
Simulation time 43188734 ps
CPU time 1.01 seconds
Started Sep 18 09:38:22 AM UTC 24
Finished Sep 18 09:38:24 AM UTC 24
Peak memory 214676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2850983694 -assert nopostproc +UVM
_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_same_csr_outstanding.2850983694
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/6.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_tl_errors.4163992613
Short name T1764
Test name
Test status
Simulation time 112703322 ps
CPU time 2.72 seconds
Started Sep 18 09:38:22 AM UTC 24
Finished Sep 18 09:38:25 AM UTC 24
Peak memory 215440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4163992613 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_errors.4163992613
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/6.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_tl_intg_err.2425251684
Short name T208
Test name
Test status
Simulation time 73410810 ps
CPU time 2.15 seconds
Started Sep 18 09:38:22 AM UTC 24
Finished Sep 18 09:38:25 AM UTC 24
Peak memory 215292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2425251684 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_intg_err.2425251684
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/6.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.1864932634
Short name T1770
Test name
Test status
Simulation time 85142623 ps
CPU time 1.21 seconds
Started Sep 18 09:38:25 AM UTC 24
Finished Sep 18 09:38:27 AM UTC 24
Peak memory 214572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=1864932634 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_csr_mem_rw_with_rand_reset.1864932634
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/7.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_csr_rw.1425001354
Short name T1767
Test name
Test status
Simulation time 28103562 ps
CPU time 1 seconds
Started Sep 18 09:38:25 AM UTC 24
Finished Sep 18 09:38:27 AM UTC 24
Peak memory 214740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1425001354 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_csr_rw.1425001354
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/7.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_intr_test.1460804327
Short name T1768
Test name
Test status
Simulation time 18393646 ps
CPU time 1.09 seconds
Started Sep 18 09:38:25 AM UTC 24
Finished Sep 18 09:38:27 AM UTC 24
Peak memory 214612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1460804327 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_intr_test.1460804327
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/7.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_same_csr_outstanding.2180757441
Short name T1769
Test name
Test status
Simulation time 117160199 ps
CPU time 1.18 seconds
Started Sep 18 09:38:25 AM UTC 24
Finished Sep 18 09:38:27 AM UTC 24
Peak memory 214676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2180757441 -assert nopostproc +UVM
_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_same_csr_outstanding.2180757441
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/7.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_tl_errors.1703554209
Short name T1766
Test name
Test status
Simulation time 58798297 ps
CPU time 2.14 seconds
Started Sep 18 09:38:23 AM UTC 24
Finished Sep 18 09:38:26 AM UTC 24
Peak memory 215480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1703554209 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_errors.1703554209
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/7.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_tl_intg_err.3398314832
Short name T210
Test name
Test status
Simulation time 116847226 ps
CPU time 2.92 seconds
Started Sep 18 09:38:24 AM UTC 24
Finished Sep 18 09:38:28 AM UTC 24
Peak memory 215224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3398314832 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_intg_err.3398314832
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/7.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.3528839950
Short name T1773
Test name
Test status
Simulation time 22641147 ps
CPU time 1.48 seconds
Started Sep 18 09:38:28 AM UTC 24
Finished Sep 18 09:38:30 AM UTC 24
Peak memory 214572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3528839950 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_csr_mem_rw_with_rand_reset.3528839950
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/8.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_csr_rw.2128255127
Short name T1771
Test name
Test status
Simulation time 18272544 ps
CPU time 1.06 seconds
Started Sep 18 09:38:27 AM UTC 24
Finished Sep 18 09:38:30 AM UTC 24
Peak memory 214740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2128255127 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_csr_rw.2128255127
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/8.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_intr_test.3832951330
Short name T284
Test name
Test status
Simulation time 50494212 ps
CPU time 1.01 seconds
Started Sep 18 09:38:26 AM UTC 24
Finished Sep 18 09:38:28 AM UTC 24
Peak memory 214612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3832951330 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_intr_test.3832951330
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/8.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_same_csr_outstanding.1092425987
Short name T1772
Test name
Test status
Simulation time 68664478 ps
CPU time 1.19 seconds
Started Sep 18 09:38:28 AM UTC 24
Finished Sep 18 09:38:30 AM UTC 24
Peak memory 214676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1092425987 -assert nopostproc +UVM
_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_same_csr_outstanding.1092425987
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/8.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_tl_errors.3367916159
Short name T1774
Test name
Test status
Simulation time 101642881 ps
CPU time 3.37 seconds
Started Sep 18 09:38:26 AM UTC 24
Finished Sep 18 09:38:30 AM UTC 24
Peak memory 215264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3367916159 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_errors.3367916159
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/8.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.2150489274
Short name T1776
Test name
Test status
Simulation time 70013229 ps
CPU time 1.31 seconds
Started Sep 18 09:38:30 AM UTC 24
Finished Sep 18 09:38:33 AM UTC 24
Peak memory 214572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=2150489274 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_csr_mem_rw_with_rand_reset.2150489274
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/9.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/9.i2c_csr_rw.2497768975
Short name T235
Test name
Test status
Simulation time 29214251 ps
CPU time 1.15 seconds
Started Sep 18 09:38:29 AM UTC 24
Finished Sep 18 09:38:31 AM UTC 24
Peak memory 214740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2497768975 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_csr_rw.2497768975
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/9.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/9.i2c_intr_test.4010718120
Short name T286
Test name
Test status
Simulation time 15407833 ps
CPU time 1.03 seconds
Started Sep 18 09:38:29 AM UTC 24
Finished Sep 18 09:38:31 AM UTC 24
Peak memory 214612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4010718120 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_intr_test.4010718120
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/9.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/9.i2c_same_csr_outstanding.3834507347
Short name T1777
Test name
Test status
Simulation time 59935990 ps
CPU time 1.68 seconds
Started Sep 18 09:38:30 AM UTC 24
Finished Sep 18 09:38:33 AM UTC 24
Peak memory 214684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3834507347 -assert nopostproc +UVM
_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_same_csr_outstanding.3834507347
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/9.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/9.i2c_tl_errors.367538181
Short name T1775
Test name
Test status
Simulation time 512699518 ps
CPU time 2.6 seconds
Started Sep 18 09:38:28 AM UTC 24
Finished Sep 18 09:38:31 AM UTC 24
Peak memory 215232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=367538181 -assert nopostproc +UVM_TESTNAME=i2c_base_tes
t +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_errors.367538181
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/9.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/cover_reg_top/9.i2c_tl_intg_err.3689771471
Short name T215
Test name
Test status
Simulation time 124499843 ps
CPU time 2.17 seconds
Started Sep 18 09:38:28 AM UTC 24
Finished Sep 18 09:38:31 AM UTC 24
Peak memory 215200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3689771471 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_intg_err.3689771471
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/9.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/0.i2c_host_fifo_fmt_empty.407501791
Short name T29
Test name
Test status
Simulation time 1377993250 ps
CPU time 17.69 seconds
Started Sep 18 07:54:25 AM UTC 24
Finished Sep 18 07:54:45 AM UTC 24
Peak memory 283424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=407501791 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_fmt_empty.407501791
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/0.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/0.i2c_host_fifo_reset_fmt.161199759
Short name T2
Test name
Test status
Simulation time 390695253 ps
CPU time 1.56 seconds
Started Sep 18 07:54:25 AM UTC 24
Finished Sep 18 07:54:28 AM UTC 24
Peak memory 215028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=161199759 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_fmt.161199759
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/0.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/0.i2c_host_fifo_reset_rx.3059859891
Short name T3
Test name
Test status
Simulation time 626151814 ps
CPU time 3.52 seconds
Started Sep 18 07:54:25 AM UTC 24
Finished Sep 18 07:54:30 AM UTC 24
Peak memory 215324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3059859891 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_rx.3059859891
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/0.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/0.i2c_host_override.910016387
Short name T1
Test name
Test status
Simulation time 17345417 ps
CPU time 1 seconds
Started Sep 18 07:54:24 AM UTC 24
Finished Sep 18 07:54:26 AM UTC 24
Peak memory 214260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=910016387 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 0.i2c_host_override.910016387
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/0.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/0.i2c_host_perf.3221923112
Short name T1259
Test name
Test status
Simulation time 49858809512 ps
CPU time 1103.54 seconds
Started Sep 18 07:54:26 AM UTC 24
Finished Sep 18 08:13:01 AM UTC 24
Peak memory 2917820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3221923112 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 0.i2c_host_perf.3221923112
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/0.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/0.i2c_host_perf_precise.477862720
Short name T4
Test name
Test status
Simulation time 236226092 ps
CPU time 2.83 seconds
Started Sep 18 07:54:27 AM UTC 24
Finished Sep 18 07:54:30 AM UTC 24
Peak memory 215196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=477862720 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_perf_precise.477862720
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/0.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/0.i2c_host_smoke.64808611
Short name T331
Test name
Test status
Simulation time 1827355889 ps
CPU time 75.31 seconds
Started Sep 18 07:54:24 AM UTC 24
Finished Sep 18 07:55:41 AM UTC 24
Peak memory 346976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=64808611 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ho
st_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 0.i2c_host_smoke.64808611
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/0.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/0.i2c_target_fifo_reset_tx.3685334432
Short name T7
Test name
Test status
Simulation time 202875131 ps
CPU time 1.21 seconds
Started Sep 18 07:54:30 AM UTC 24
Finished Sep 18 07:54:34 AM UTC 24
Peak memory 214780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3685334
432 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_fifo_reset_tx.3685334432
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/0.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/0.i2c_target_fifo_watermarks_tx.3841026398
Short name T9
Test name
Test status
Simulation time 126309030 ps
CPU time 1.87 seconds
Started Sep 18 07:54:34 AM UTC 24
Finished Sep 18 07:54:37 AM UTC 24
Peak memory 214852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3841026
398 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_fifo_watermarks
_tx.3841026398
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/0.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/0.i2c_target_hrst.3944242018
Short name T8
Test name
Test status
Simulation time 266223915 ps
CPU time 2.84 seconds
Started Sep 18 07:54:32 AM UTC 24
Finished Sep 18 07:54:36 AM UTC 24
Peak memory 225620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3944242
018 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_hrst.3944242018
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/0.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/0.i2c_target_intr_smoke.2083353444
Short name T46
Test name
Test status
Simulation time 1389264216 ps
CPU time 7.38 seconds
Started Sep 18 07:54:29 AM UTC 24
Finished Sep 18 07:54:38 AM UTC 24
Peak memory 242476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=208335
3444 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_intr_smoke.2083353444
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/0.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/0.i2c_target_intr_stress_wr.1967171093
Short name T303
Test name
Test status
Simulation time 15897648928 ps
CPU time 33.26 seconds
Started Sep 18 07:54:29 AM UTC 24
Finished Sep 18 07:55:04 AM UTC 24
Peak memory 998180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1967171093 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_intr_stress
_wr.1967171093
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/0.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/0.i2c_target_nack_acqfull_addr.445959127
Short name T62
Test name
Test status
Simulation time 631808194 ps
CPU time 4.31 seconds
Started Sep 18 07:54:35 AM UTC 24
Finished Sep 18 07:54:40 AM UTC 24
Peak memory 215256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4459591
27 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_nack_acqfull_addr.445959127
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/0.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/0.i2c_target_perf.2329597100
Short name T71
Test name
Test status
Simulation time 2541098981 ps
CPU time 6.32 seconds
Started Sep 18 07:54:31 AM UTC 24
Finished Sep 18 07:54:40 AM UTC 24
Peak memory 231760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2329597
100 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_perf.2329597100
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/0.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/0.i2c_target_smbus_maxlen.1981103313
Short name T76
Test name
Test status
Simulation time 886764567 ps
CPU time 3.65 seconds
Started Sep 18 07:54:34 AM UTC 24
Finished Sep 18 07:54:39 AM UTC 24
Peak memory 215092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1981103
313 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_smbus_maxlen.1981103313
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/0.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/0.i2c_target_smoke.578806601
Short name T70
Test name
Test status
Simulation time 4702261949 ps
CPU time 10.4 seconds
Started Sep 18 07:54:28 AM UTC 24
Finished Sep 18 07:54:39 AM UTC 24
Peak memory 225652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=578806601 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_smoke.578806601
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/0.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/0.i2c_target_stress_all.2361289959
Short name T479
Test name
Test status
Simulation time 28829022578 ps
CPU time 236.19 seconds
Started Sep 18 07:54:31 AM UTC 24
Finished Sep 18 07:58:32 AM UTC 24
Peak memory 3336996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=236128
9959 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_stress_all.2361289959
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/0.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/0.i2c_target_stress_wr.2095220052
Short name T301
Test name
Test status
Simulation time 10749951274 ps
CPU time 34.73 seconds
Started Sep 18 07:54:28 AM UTC 24
Finished Sep 18 07:55:04 AM UTC 24
Peak memory 215428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2095220052 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_stress_wr.2095220052
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/0.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/0.i2c_target_stretch.2610453825
Short name T189
Test name
Test status
Simulation time 3932461944 ps
CPU time 26.44 seconds
Started Sep 18 07:54:28 AM UTC 24
Finished Sep 18 07:54:56 AM UTC 24
Peak memory 676704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2610453825 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_stretch.2610453825
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/0.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/1.i2c_alert_test.1660809632
Short name T102
Test name
Test status
Simulation time 27029148 ps
CPU time 0.94 seconds
Started Sep 18 07:54:51 AM UTC 24
Finished Sep 18 07:54:53 AM UTC 24
Peak memory 214840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1660809632 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_alert_test.1660809632
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/1.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/1.i2c_host_error_intr.923803234
Short name T14
Test name
Test status
Simulation time 276260731 ps
CPU time 5.07 seconds
Started Sep 18 07:54:40 AM UTC 24
Finished Sep 18 07:54:46 AM UTC 24
Peak memory 242640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=923803234 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 1.i2c_host_error_intr.923803234
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/1.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/1.i2c_host_fifo_fmt_empty.31046924
Short name T41
Test name
Test status
Simulation time 211174743 ps
CPU time 12.61 seconds
Started Sep 18 07:54:40 AM UTC 24
Finished Sep 18 07:54:53 AM UTC 24
Peak memory 238428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31046924 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_fmt_empty.31046924
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/1.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/1.i2c_host_fifo_full.998119052
Short name T27
Test name
Test status
Simulation time 3487056230 ps
CPU time 84.66 seconds
Started Sep 18 07:54:40 AM UTC 24
Finished Sep 18 07:56:06 AM UTC 24
Peak memory 596900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=998119052 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_full.998119052
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/1.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/1.i2c_host_fifo_overflow.3723538807
Short name T101
Test name
Test status
Simulation time 9562781115 ps
CPU time 134.95 seconds
Started Sep 18 07:54:38 AM UTC 24
Finished Sep 18 07:56:56 AM UTC 24
Peak memory 801636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3723538807 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_overflow.3723538807
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/1.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/1.i2c_host_fifo_reset_fmt.3877540113
Short name T34
Test name
Test status
Simulation time 141758082 ps
CPU time 1.11 seconds
Started Sep 18 07:54:38 AM UTC 24
Finished Sep 18 07:54:40 AM UTC 24
Peak memory 214900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3877540113 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_fmt.3877540113
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/1.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/1.i2c_host_fifo_watermark.4096920953
Short name T83
Test name
Test status
Simulation time 18694740272 ps
CPU time 96.27 seconds
Started Sep 18 07:54:38 AM UTC 24
Finished Sep 18 07:56:17 AM UTC 24
Peak memory 1536780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4096920953 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_watermark.4096920953
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/1.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/1.i2c_host_perf.3183030289
Short name T15
Test name
Test status
Simulation time 7862201393 ps
CPU time 26.59 seconds
Started Sep 18 07:54:40 AM UTC 24
Finished Sep 18 07:55:07 AM UTC 24
Peak memory 246448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3183030289 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 1.i2c_host_perf.3183030289
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/1.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/1.i2c_host_perf_precise.201890176
Short name T22
Test name
Test status
Simulation time 511235347 ps
CPU time 3.18 seconds
Started Sep 18 07:54:40 AM UTC 24
Finished Sep 18 07:54:44 AM UTC 24
Peak memory 215196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=201890176 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_perf_precise.201890176
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/1.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/1.i2c_host_smoke.3250129063
Short name T336
Test name
Test status
Simulation time 3107731188 ps
CPU time 69.24 seconds
Started Sep 18 07:54:37 AM UTC 24
Finished Sep 18 07:55:48 AM UTC 24
Peak memory 312288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3250129063 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.i2c_host_smoke.3250129063
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/1.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/1.i2c_host_stretch_timeout.1234384013
Short name T288
Test name
Test status
Simulation time 2034722158 ps
CPU time 28.66 seconds
Started Sep 18 07:54:40 AM UTC 24
Finished Sep 18 07:55:10 AM UTC 24
Peak memory 225504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1234384013 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_stretch_timeout.1234384013
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/1.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/1.i2c_sec_cm.1157988299
Short name T188
Test name
Test status
Simulation time 801128393 ps
CPU time 1.63 seconds
Started Sep 18 07:54:51 AM UTC 24
Finished Sep 18 07:54:54 AM UTC 24
Peak memory 244508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1157988299 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_sec_cm.1157988299
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/1.i2c_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/1.i2c_target_bad_addr.1348704414
Short name T64
Test name
Test status
Simulation time 2894839009 ps
CPU time 7.27 seconds
Started Sep 18 07:54:46 AM UTC 24
Finished Sep 18 07:54:54 AM UTC 24
Peak memory 219476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=1348704414 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_bad_addr.1348704414
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/1.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/1.i2c_target_fifo_reset_acq.3081440835
Short name T73
Test name
Test status
Simulation time 167993991 ps
CPU time 1.96 seconds
Started Sep 18 07:54:41 AM UTC 24
Finished Sep 18 07:54:44 AM UTC 24
Peak memory 214784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3081440
835 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_fifo_reset_acq.3081440835
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/1.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/1.i2c_target_fifo_reset_tx.2169217953
Short name T297
Test name
Test status
Simulation time 248385262 ps
CPU time 1.41 seconds
Started Sep 18 07:54:44 AM UTC 24
Finished Sep 18 07:54:47 AM UTC 24
Peak memory 214776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2169217
953 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_fifo_reset_tx.2169217953
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/1.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/1.i2c_target_fifo_watermarks_acq.624460133
Short name T271
Test name
Test status
Simulation time 2444673587 ps
CPU time 2.97 seconds
Started Sep 18 07:54:47 AM UTC 24
Finished Sep 18 07:54:51 AM UTC 24
Peak memory 215396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6244601
33 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_fifo_watermarks
_acq.624460133
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/1.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/1.i2c_target_fifo_watermarks_tx.1795014705
Short name T290
Test name
Test status
Simulation time 163355421 ps
CPU time 2.5 seconds
Started Sep 18 07:54:48 AM UTC 24
Finished Sep 18 07:54:51 AM UTC 24
Peak memory 215048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1795014
705 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_fifo_watermarks
_tx.1795014705
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/1.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/1.i2c_target_intr_smoke.89813111
Short name T220
Test name
Test status
Simulation time 960885623 ps
CPU time 6.48 seconds
Started Sep 18 07:54:41 AM UTC 24
Finished Sep 18 07:54:49 AM UTC 24
Peak memory 232232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=898131
11 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_intr_smoke.89813111
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/1.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/1.i2c_target_intr_stress_wr.3274765523
Short name T390
Test name
Test status
Simulation time 21902888754 ps
CPU time 142.11 seconds
Started Sep 18 07:54:41 AM UTC 24
Finished Sep 18 07:57:06 AM UTC 24
Peak memory 2734944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3274765523 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_intr_stress
_wr.3274765523
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/1.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/1.i2c_target_nack_acqfull.3960869000
Short name T63
Test name
Test status
Simulation time 2468734329 ps
CPU time 6.02 seconds
Started Sep 18 07:54:50 AM UTC 24
Finished Sep 18 07:54:57 AM UTC 24
Peak memory 225736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3960869
000 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_nack_acqfull.3960869000
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/1.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/1.i2c_target_perf.2376463412
Short name T298
Test name
Test status
Simulation time 627620665 ps
CPU time 4.64 seconds
Started Sep 18 07:54:44 AM UTC 24
Finished Sep 18 07:54:50 AM UTC 24
Peak memory 227680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2376463
412 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_perf.2376463412
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/1.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/1.i2c_target_smbus_maxlen.2877876867
Short name T299
Test name
Test status
Simulation time 792375373 ps
CPU time 2.53 seconds
Started Sep 18 07:54:48 AM UTC 24
Finished Sep 18 07:54:52 AM UTC 24
Peak memory 215004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2877876
867 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_smbus_maxlen.2877876867
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/1.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/1.i2c_target_smoke.3743735638
Short name T322
Test name
Test status
Simulation time 12207705317 ps
CPU time 50.26 seconds
Started Sep 18 07:54:41 AM UTC 24
Finished Sep 18 07:55:33 AM UTC 24
Peak memory 225896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3743735638 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_smoke.3743735638
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/1.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/1.i2c_target_stress_all.3332625598
Short name T266
Test name
Test status
Simulation time 23426407328 ps
CPU time 210.74 seconds
Started Sep 18 07:54:44 AM UTC 24
Finished Sep 18 07:58:18 AM UTC 24
Peak memory 2583320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=333262
5598 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_stress_all.3332625598
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/1.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/1.i2c_target_stress_rd.671485253
Short name T312
Test name
Test status
Simulation time 722351521 ps
CPU time 36.4 seconds
Started Sep 18 07:54:41 AM UTC 24
Finished Sep 18 07:55:19 AM UTC 24
Peak memory 225496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=671485253 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_stress_rd.671485253
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/1.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/1.i2c_target_stress_wr.2236371302
Short name T295
Test name
Test status
Simulation time 25970940377 ps
CPU time 41.77 seconds
Started Sep 18 07:54:41 AM UTC 24
Finished Sep 18 07:55:24 AM UTC 24
Peak memory 889584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2236371302 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_stress_wr.2236371302
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/1.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/1.i2c_target_stretch.2400651838
Short name T163
Test name
Test status
Simulation time 4169024032 ps
CPU time 4.16 seconds
Started Sep 18 07:54:41 AM UTC 24
Finished Sep 18 07:54:46 AM UTC 24
Peak memory 271140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2400651838 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_stretch.2400651838
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/1.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/1.i2c_target_timeout.3420221954
Short name T77
Test name
Test status
Simulation time 4232637978 ps
CPU time 9.16 seconds
Started Sep 18 07:54:41 AM UTC 24
Finished Sep 18 07:54:52 AM UTC 24
Peak memory 225688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3420221
954 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_timeout.3420221954
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/1.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/1.i2c_target_tx_stretch_ctrl.2302893334
Short name T68
Test name
Test status
Simulation time 1096736464 ps
CPU time 19.14 seconds
Started Sep 18 07:54:48 AM UTC 24
Finished Sep 18 07:55:08 AM UTC 24
Peak memory 217492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2302893
334 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_tx_stretch_ctrl.2302893334
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/1.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/10.i2c_alert_test.2267632009
Short name T460
Test name
Test status
Simulation time 26522405 ps
CPU time 0.8 seconds
Started Sep 18 07:58:18 AM UTC 24
Finished Sep 18 07:58:20 AM UTC 24
Peak memory 214900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2267632009 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_alert_test.2267632009
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/10.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/10.i2c_host_error_intr.2424807712
Short name T452
Test name
Test status
Simulation time 598448481 ps
CPU time 1.84 seconds
Started Sep 18 07:57:59 AM UTC 24
Finished Sep 18 07:58:01 AM UTC 24
Peak memory 231556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2424807712 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 10.i2c_host_error_intr.2424807712
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/10.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/10.i2c_host_fifo_fmt_empty.3058093817
Short name T454
Test name
Test status
Simulation time 425826435 ps
CPU time 7.22 seconds
Started Sep 18 07:57:56 AM UTC 24
Finished Sep 18 07:58:05 AM UTC 24
Peak memory 271060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3058093817 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_fmt_empty.3058093817
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/10.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/10.i2c_host_fifo_full.321383127
Short name T544
Test name
Test status
Simulation time 14192220120 ps
CPU time 102.67 seconds
Started Sep 18 07:57:57 AM UTC 24
Finished Sep 18 07:59:42 AM UTC 24
Peak memory 594732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=321383127 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_full.321383127
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/10.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/10.i2c_host_fifo_overflow.1339289709
Short name T490
Test name
Test status
Simulation time 1516904014 ps
CPU time 46.7 seconds
Started Sep 18 07:57:56 AM UTC 24
Finished Sep 18 07:58:44 AM UTC 24
Peak memory 598744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1339289709 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_overflow.1339289709
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/10.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/10.i2c_host_fifo_reset_fmt.3474239242
Short name T449
Test name
Test status
Simulation time 1221233383 ps
CPU time 1.43 seconds
Started Sep 18 07:57:56 AM UTC 24
Finished Sep 18 07:57:59 AM UTC 24
Peak memory 214900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3474239242 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_fmt.3474239242
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/10.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/10.i2c_host_fifo_reset_rx.3068849544
Short name T445
Test name
Test status
Simulation time 161453454 ps
CPU time 9.83 seconds
Started Sep 18 07:57:57 AM UTC 24
Finished Sep 18 07:58:08 AM UTC 24
Peak memory 215324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3068849544 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_rx.3068849544
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/10.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/10.i2c_host_fifo_watermark.3968989087
Short name T539
Test name
Test status
Simulation time 9741883072 ps
CPU time 101.28 seconds
Started Sep 18 07:57:56 AM UTC 24
Finished Sep 18 07:59:39 AM UTC 24
Peak memory 1235932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3968989087 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_watermark.3968989087
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/10.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/10.i2c_host_may_nack.2395488818
Short name T473
Test name
Test status
Simulation time 1023076184 ps
CPU time 12.46 seconds
Started Sep 18 07:58:14 AM UTC 24
Finished Sep 18 07:58:27 AM UTC 24
Peak memory 215324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2395488818 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.i2c_host_may_nack.2395488818
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/10.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/10.i2c_host_perf.2134873152
Short name T504
Test name
Test status
Simulation time 12593381013 ps
CPU time 87.19 seconds
Started Sep 18 07:57:58 AM UTC 24
Finished Sep 18 07:59:27 AM UTC 24
Peak memory 215248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2134873152 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 10.i2c_host_perf.2134873152
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/10.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/10.i2c_host_perf_precise.2102170556
Short name T469
Test name
Test status
Simulation time 2647296710 ps
CPU time 27.04 seconds
Started Sep 18 07:57:58 AM UTC 24
Finished Sep 18 07:58:26 AM UTC 24
Peak memory 482008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2102170556 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_perf_precise.2102170556
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/10.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/10.i2c_host_smoke.3847652812
Short name T476
Test name
Test status
Simulation time 3194440758 ps
CPU time 32.24 seconds
Started Sep 18 07:57:55 AM UTC 24
Finished Sep 18 07:58:29 AM UTC 24
Peak memory 355108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3847652812 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 10.i2c_host_smoke.3847652812
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/10.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/10.i2c_host_stretch_timeout.2241984407
Short name T486
Test name
Test status
Simulation time 3804081423 ps
CPU time 40.59 seconds
Started Sep 18 07:57:59 AM UTC 24
Finished Sep 18 07:58:41 AM UTC 24
Peak memory 227684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2241984407 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_stretch_timeout.2241984407
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/10.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/10.i2c_target_bad_addr.2630646006
Short name T457
Test name
Test status
Simulation time 1073670200 ps
CPU time 7.3 seconds
Started Sep 18 07:58:10 AM UTC 24
Finished Sep 18 07:58:18 AM UTC 24
Peak memory 225496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=2630646006 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_bad_ad
dr.2630646006
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/10.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/10.i2c_target_fifo_reset_acq.3996997649
Short name T186
Test name
Test status
Simulation time 248920918 ps
CPU time 2.24 seconds
Started Sep 18 07:58:06 AM UTC 24
Finished Sep 18 07:58:10 AM UTC 24
Peak memory 215312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3996997
649 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_fifo_reset_acq.3996997649
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/10.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/10.i2c_target_fifo_reset_tx.1344560008
Short name T455
Test name
Test status
Simulation time 262891708 ps
CPU time 1.43 seconds
Started Sep 18 07:58:07 AM UTC 24
Finished Sep 18 07:58:10 AM UTC 24
Peak memory 214904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1344560
008 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_fifo_reset_tx.1344560008
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/10.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/10.i2c_target_fifo_watermarks_acq.373517034
Short name T458
Test name
Test status
Simulation time 835386787 ps
CPU time 3.88 seconds
Started Sep 18 07:58:14 AM UTC 24
Finished Sep 18 07:58:19 AM UTC 24
Peak memory 215320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3735170
34 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_fifo_watermark
s_acq.373517034
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/10.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/10.i2c_target_fifo_watermarks_tx.2423861252
Short name T456
Test name
Test status
Simulation time 55819404 ps
CPU time 1.36 seconds
Started Sep 18 07:58:15 AM UTC 24
Finished Sep 18 07:58:17 AM UTC 24
Peak memory 215092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2423861
252 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_fifo_watermark
s_tx.2423861252
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/10.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/10.i2c_target_hrst.1136258340
Short name T425
Test name
Test status
Simulation time 363583720 ps
CPU time 4.31 seconds
Started Sep 18 07:58:11 AM UTC 24
Finished Sep 18 07:58:16 AM UTC 24
Peak memory 231712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1136258
340 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_hrst.1136258340
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/10.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/10.i2c_target_intr_smoke.3588580542
Short name T404
Test name
Test status
Simulation time 2992608766 ps
CPU time 12.16 seconds
Started Sep 18 07:58:02 AM UTC 24
Finished Sep 18 07:58:15 AM UTC 24
Peak memory 242460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=358858
0542 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_intr_smoke.3588580542
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/10.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/10.i2c_target_intr_stress_wr.2025229947
Short name T470
Test name
Test status
Simulation time 19199908976 ps
CPU time 20.85 seconds
Started Sep 18 07:58:04 AM UTC 24
Finished Sep 18 07:58:26 AM UTC 24
Peak memory 398340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2025229947 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_intr_stres
s_wr.2025229947
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/10.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/10.i2c_target_nack_acqfull.3416286253
Short name T464
Test name
Test status
Simulation time 2893528294 ps
CPU time 3.95 seconds
Started Sep 18 07:58:17 AM UTC 24
Finished Sep 18 07:58:22 AM UTC 24
Peak memory 225772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3416286
253 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_nack_acqfull.3416286253
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/10.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/10.i2c_target_nack_acqfull_addr.555664401
Short name T466
Test name
Test status
Simulation time 2599681894 ps
CPU time 3.75 seconds
Started Sep 18 07:58:18 AM UTC 24
Finished Sep 18 07:58:23 AM UTC 24
Peak memory 215404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5556644
01 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_nack_acqfull_addr.555664401
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/10.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/10.i2c_target_nack_txstretch.3789919555
Short name T187
Test name
Test status
Simulation time 635959426 ps
CPU time 2.24 seconds
Started Sep 18 07:58:18 AM UTC 24
Finished Sep 18 07:58:21 AM UTC 24
Peak memory 232348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3789919
555 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_nack_txstretch.3789919555
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/10.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/10.i2c_target_perf.296673198
Short name T443
Test name
Test status
Simulation time 713904655 ps
CPU time 7.43 seconds
Started Sep 18 07:58:08 AM UTC 24
Finished Sep 18 07:58:17 AM UTC 24
Peak memory 225504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2966731
98 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_perf.296673198
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/10.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/10.i2c_target_smbus_maxlen.1238993417
Short name T461
Test name
Test status
Simulation time 529594616 ps
CPU time 3.48 seconds
Started Sep 18 07:58:16 AM UTC 24
Finished Sep 18 07:58:20 AM UTC 24
Peak memory 215088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1238993
417 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_smbus_maxlen.1238993417
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/10.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/10.i2c_target_smoke.1035304676
Short name T477
Test name
Test status
Simulation time 3740085100 ps
CPU time 28.67 seconds
Started Sep 18 07:57:59 AM UTC 24
Finished Sep 18 07:58:29 AM UTC 24
Peak memory 225828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1035304676 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_smoke.1035304676
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/10.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/10.i2c_target_stress_all.3076111564
Short name T509
Test name
Test status
Simulation time 13446433519 ps
CPU time 54.18 seconds
Started Sep 18 07:58:10 AM UTC 24
Finished Sep 18 07:59:05 AM UTC 24
Peak memory 277344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=307611
1564 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_stress_all.3076111564
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/10.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/10.i2c_target_stress_rd.4193368564
Short name T498
Test name
Test status
Simulation time 3462374124 ps
CPU time 46.23 seconds
Started Sep 18 07:58:01 AM UTC 24
Finished Sep 18 07:58:49 AM UTC 24
Peak memory 225628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4193368564 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_stress_rd.4193368564
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/10.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/10.i2c_target_stretch.2047572377
Short name T531
Test name
Test status
Simulation time 4115367126 ps
CPU time 84.63 seconds
Started Sep 18 07:58:01 AM UTC 24
Finished Sep 18 07:59:27 AM UTC 24
Peak memory 1213408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2047572377 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_stretch.2047572377
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/10.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/10.i2c_target_timeout.272335006
Short name T459
Test name
Test status
Simulation time 6848591192 ps
CPU time 12.67 seconds
Started Sep 18 07:58:05 AM UTC 24
Finished Sep 18 07:58:19 AM UTC 24
Peak memory 227672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2723350
06 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_timeout.272335006
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/10.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/10.i2c_target_tx_stretch_ctrl.3255841463
Short name T462
Test name
Test status
Simulation time 103554238 ps
CPU time 3.52 seconds
Started Sep 18 07:58:16 AM UTC 24
Finished Sep 18 07:58:21 AM UTC 24
Peak memory 214984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3255841
463 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_tx_stretch_ctrl.3255841463
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/10.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/11.i2c_alert_test.707092424
Short name T496
Test name
Test status
Simulation time 55128688 ps
CPU time 0.98 seconds
Started Sep 18 07:58:47 AM UTC 24
Finished Sep 18 07:58:49 AM UTC 24
Peak memory 214668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=707092424 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_alert_test.707092424
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/11.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/11.i2c_host_error_intr.3122625378
Short name T474
Test name
Test status
Simulation time 423442622 ps
CPU time 2.24 seconds
Started Sep 18 07:58:25 AM UTC 24
Finished Sep 18 07:58:28 AM UTC 24
Peak memory 215528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3122625378 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 11.i2c_host_error_intr.3122625378
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/11.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/11.i2c_host_fifo_fmt_empty.2155383244
Short name T475
Test name
Test status
Simulation time 244218031 ps
CPU time 5.69 seconds
Started Sep 18 07:58:22 AM UTC 24
Finished Sep 18 07:58:28 AM UTC 24
Peak memory 265112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2155383244 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_fmt_empty.2155383244
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/11.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/11.i2c_host_fifo_full.1207691303
Short name T684
Test name
Test status
Simulation time 8683679377 ps
CPU time 226.88 seconds
Started Sep 18 07:58:23 AM UTC 24
Finished Sep 18 08:02:13 AM UTC 24
Peak memory 529248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1207691303 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_full.1207691303
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/11.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/11.i2c_host_fifo_overflow.3025712953
Short name T569
Test name
Test status
Simulation time 5600375583 ps
CPU time 98.44 seconds
Started Sep 18 07:58:21 AM UTC 24
Finished Sep 18 08:00:01 AM UTC 24
Peak memory 887576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3025712953 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_overflow.3025712953
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/11.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/11.i2c_host_fifo_reset_fmt.1253309041
Short name T467
Test name
Test status
Simulation time 582478628 ps
CPU time 1.63 seconds
Started Sep 18 07:58:22 AM UTC 24
Finished Sep 18 07:58:24 AM UTC 24
Peak memory 214900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1253309041 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_fmt.1253309041
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/11.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/11.i2c_host_fifo_reset_rx.3558224301
Short name T472
Test name
Test status
Simulation time 162106706 ps
CPU time 3.25 seconds
Started Sep 18 07:58:23 AM UTC 24
Finished Sep 18 07:58:27 AM UTC 24
Peak memory 215324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3558224301 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_rx.3558224301
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/11.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/11.i2c_host_fifo_watermark.693502993
Short name T120
Test name
Test status
Simulation time 19710872679 ps
CPU time 75.79 seconds
Started Sep 18 07:58:19 AM UTC 24
Finished Sep 18 07:59:37 AM UTC 24
Peak memory 1172388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=693502993 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_watermark.693502993
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/11.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/11.i2c_host_may_nack.812452795
Short name T255
Test name
Test status
Simulation time 351232326 ps
CPU time 13.32 seconds
Started Sep 18 07:58:39 AM UTC 24
Finished Sep 18 07:58:54 AM UTC 24
Peak memory 215380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=812452795 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 11.i2c_host_may_nack.812452795
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/11.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/11.i2c_host_override.1852005693
Short name T463
Test name
Test status
Simulation time 87045865 ps
CPU time 0.87 seconds
Started Sep 18 07:58:19 AM UTC 24
Finished Sep 18 07:58:21 AM UTC 24
Peak memory 214112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1852005693 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.i2c_host_override.1852005693
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/11.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/11.i2c_host_perf.2936923371
Short name T518
Test name
Test status
Simulation time 8515087169 ps
CPU time 53.37 seconds
Started Sep 18 07:58:23 AM UTC 24
Finished Sep 18 07:59:18 AM UTC 24
Peak memory 752488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2936923371 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 11.i2c_host_perf.2936923371
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/11.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/11.i2c_host_perf_precise.4229889862
Short name T471
Test name
Test status
Simulation time 63314070 ps
CPU time 1.31 seconds
Started Sep 18 07:58:24 AM UTC 24
Finished Sep 18 07:58:26 AM UTC 24
Peak memory 236972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4229889862 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_perf_precise.4229889862
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/11.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/11.i2c_host_smoke.2688310964
Short name T501
Test name
Test status
Simulation time 6428485009 ps
CPU time 30.14 seconds
Started Sep 18 07:58:19 AM UTC 24
Finished Sep 18 07:58:51 AM UTC 24
Peak memory 369628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2688310964 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.i2c_host_smoke.2688310964
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/11.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/11.i2c_host_stretch_timeout.30214503
Short name T482
Test name
Test status
Simulation time 2047608470 ps
CPU time 9.59 seconds
Started Sep 18 07:58:24 AM UTC 24
Finished Sep 18 07:58:35 AM UTC 24
Peak memory 227744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=30214503 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ho
st_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_stretch_timeout.30214503
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/11.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/11.i2c_target_bad_addr.2280277976
Short name T487
Test name
Test status
Simulation time 8473330467 ps
CPU time 7.73 seconds
Started Sep 18 07:58:34 AM UTC 24
Finished Sep 18 07:58:43 AM UTC 24
Peak memory 217372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=2280277976 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_bad_ad
dr.2280277976
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/11.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/11.i2c_target_fifo_reset_acq.771553032
Short name T480
Test name
Test status
Simulation time 202830087 ps
CPU time 2.33 seconds
Started Sep 18 07:58:30 AM UTC 24
Finished Sep 18 07:58:33 AM UTC 24
Peak memory 215040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7715530
32 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_fifo_reset_acq.771553032
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/11.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/11.i2c_target_fifo_reset_tx.2167474076
Short name T481
Test name
Test status
Simulation time 239240166 ps
CPU time 1.38 seconds
Started Sep 18 07:58:32 AM UTC 24
Finished Sep 18 07:58:34 AM UTC 24
Peak memory 214904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2167474
076 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_fifo_reset_tx.2167474076
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/11.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/11.i2c_target_fifo_watermarks_acq.1258243023
Short name T491
Test name
Test status
Simulation time 1279252641 ps
CPU time 2.98 seconds
Started Sep 18 07:58:40 AM UTC 24
Finished Sep 18 07:58:44 AM UTC 24
Peak memory 215340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1258243
023 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_fifo_watermar
ks_acq.1258243023
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/11.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/11.i2c_target_fifo_watermarks_tx.864940950
Short name T489
Test name
Test status
Simulation time 476345714 ps
CPU time 2.41 seconds
Started Sep 18 07:58:40 AM UTC 24
Finished Sep 18 07:58:44 AM UTC 24
Peak memory 215040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8649409
50 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_fifo_watermarks
_tx.864940950
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/11.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/11.i2c_target_intr_smoke.1840254677
Short name T484
Test name
Test status
Simulation time 1003591170 ps
CPU time 9.49 seconds
Started Sep 18 07:58:28 AM UTC 24
Finished Sep 18 07:58:39 AM UTC 24
Peak memory 227544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=184025
4677 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_intr_smoke.1840254677
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/11.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/11.i2c_target_intr_stress_wr.1318435417
Short name T510
Test name
Test status
Simulation time 16124981774 ps
CPU time 35.15 seconds
Started Sep 18 07:58:29 AM UTC 24
Finished Sep 18 07:59:06 AM UTC 24
Peak memory 983828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1318435417 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_intr_stres
s_wr.1318435417
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/11.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/11.i2c_target_nack_acqfull.1741411155
Short name T503
Test name
Test status
Simulation time 521487921 ps
CPU time 5.69 seconds
Started Sep 18 07:58:43 AM UTC 24
Finished Sep 18 07:58:51 AM UTC 24
Peak memory 225488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1741411
155 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_nack_acqfull.1741411155
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/11.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/11.i2c_target_nack_acqfull_addr.1935045915
Short name T500
Test name
Test status
Simulation time 2188366563 ps
CPU time 4.67 seconds
Started Sep 18 07:58:43 AM UTC 24
Finished Sep 18 07:58:50 AM UTC 24
Peak memory 215336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1935045
915 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_nack_acqfull_ad
dr.1935045915
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/11.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/11.i2c_target_perf.2518131743
Short name T488
Test name
Test status
Simulation time 3033088579 ps
CPU time 9.15 seconds
Started Sep 18 07:58:33 AM UTC 24
Finished Sep 18 07:58:43 AM UTC 24
Peak memory 231832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2518131
743 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_perf.2518131743
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/11.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/11.i2c_target_smbus_maxlen.3693777244
Short name T494
Test name
Test status
Simulation time 1007780264 ps
CPU time 4.06 seconds
Started Sep 18 07:58:41 AM UTC 24
Finished Sep 18 07:58:46 AM UTC 24
Peak memory 215076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3693777
244 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_smbus_maxlen.3693777244
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/11.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/11.i2c_target_smoke.383627963
Short name T88
Test name
Test status
Simulation time 1579320620 ps
CPU time 58.74 seconds
Started Sep 18 07:58:27 AM UTC 24
Finished Sep 18 07:59:27 AM UTC 24
Peak memory 225624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=383627963 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_smoke.383627963
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/11.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/11.i2c_target_stress_all.2524654215
Short name T655
Test name
Test status
Simulation time 72911958370 ps
CPU time 183.73 seconds
Started Sep 18 07:58:34 AM UTC 24
Finished Sep 18 08:01:40 AM UTC 24
Peak memory 1559392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=252465
4215 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_stress_all.2524654215
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/11.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/11.i2c_target_stress_rd.4125588077
Short name T499
Test name
Test status
Simulation time 5184105778 ps
CPU time 21.56 seconds
Started Sep 18 07:58:27 AM UTC 24
Finished Sep 18 07:58:50 AM UTC 24
Peak memory 248868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4125588077 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_stress_rd.4125588077
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/11.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/11.i2c_target_stress_wr.665507131
Short name T613
Test name
Test status
Simulation time 29617572545 ps
CPU time 155.18 seconds
Started Sep 18 07:58:27 AM UTC 24
Finished Sep 18 08:01:05 AM UTC 24
Peak memory 2601732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=665507131 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_stress_wr.665507131
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/11.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/11.i2c_target_stretch.2129006340
Short name T478
Test name
Test status
Simulation time 1800970535 ps
CPU time 2.09 seconds
Started Sep 18 07:58:28 AM UTC 24
Finished Sep 18 07:58:31 AM UTC 24
Peak memory 225624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2129006340 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_stretch.2129006340
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/11.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/11.i2c_target_timeout.217996928
Short name T483
Test name
Test status
Simulation time 1451706879 ps
CPU time 7.32 seconds
Started Sep 18 07:58:30 AM UTC 24
Finished Sep 18 07:58:38 AM UTC 24
Peak memory 242532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2179969
28 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_timeout.217996928
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/11.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/11.i2c_target_tx_stretch_ctrl.1316647633
Short name T492
Test name
Test status
Simulation time 82883825 ps
CPU time 2.43 seconds
Started Sep 18 07:58:41 AM UTC 24
Finished Sep 18 07:58:45 AM UTC 24
Peak memory 215324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1316647
633 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_tx_stretch_ctrl.1316647633
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/11.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/12.i2c_alert_test.1175812286
Short name T526
Test name
Test status
Simulation time 19070977 ps
CPU time 1 seconds
Started Sep 18 07:59:22 AM UTC 24
Finished Sep 18 07:59:24 AM UTC 24
Peak memory 214840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1175812286 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_alert_test.1175812286
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/12.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/12.i2c_host_error_intr.3208300613
Short name T505
Test name
Test status
Simulation time 1490956672 ps
CPU time 3.39 seconds
Started Sep 18 07:58:52 AM UTC 24
Finished Sep 18 07:58:57 AM UTC 24
Peak memory 231976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3208300613 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 12.i2c_host_error_intr.3208300613
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/12.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/12.i2c_host_fifo_fmt_empty.304682739
Short name T506
Test name
Test status
Simulation time 930805530 ps
CPU time 7.94 seconds
Started Sep 18 07:58:49 AM UTC 24
Finished Sep 18 07:58:58 AM UTC 24
Peak memory 273256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=304682739 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_fmt_empty.304682739
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/12.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/12.i2c_host_fifo_full.3384722618
Short name T679
Test name
Test status
Simulation time 6228609808 ps
CPU time 193.73 seconds
Started Sep 18 07:58:50 AM UTC 24
Finished Sep 18 08:02:08 AM UTC 24
Peak memory 621336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3384722618 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_full.3384722618
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/12.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/12.i2c_host_fifo_overflow.1744164288
Short name T573
Test name
Test status
Simulation time 8533343062 ps
CPU time 77.69 seconds
Started Sep 18 07:58:48 AM UTC 24
Finished Sep 18 08:00:07 AM UTC 24
Peak memory 644004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1744164288 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_overflow.1744164288
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/12.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/12.i2c_host_fifo_reset_fmt.4001265182
Short name T502
Test name
Test status
Simulation time 100883229 ps
CPU time 1.58 seconds
Started Sep 18 07:58:49 AM UTC 24
Finished Sep 18 07:58:51 AM UTC 24
Peak memory 214900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4001265182 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_fmt.4001265182
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/12.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/12.i2c_host_fifo_reset_rx.314201456
Short name T513
Test name
Test status
Simulation time 494391522 ps
CPU time 18.98 seconds
Started Sep 18 07:58:49 AM UTC 24
Finished Sep 18 07:59:09 AM UTC 24
Peak memory 266964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=314201456 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_rx.314201456
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/12.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/12.i2c_host_fifo_watermark.1943273559
Short name T641
Test name
Test status
Simulation time 3026100960 ps
CPU time 160.08 seconds
Started Sep 18 07:58:47 AM UTC 24
Finished Sep 18 08:01:29 AM UTC 24
Peak memory 902036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1943273559 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_watermark.1943273559
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/12.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/12.i2c_host_may_nack.1262965427
Short name T253
Test name
Test status
Simulation time 381258701 ps
CPU time 6.69 seconds
Started Sep 18 07:59:13 AM UTC 24
Finished Sep 18 07:59:21 AM UTC 24
Peak memory 215252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1262965427 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.i2c_host_may_nack.1262965427
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/12.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/12.i2c_host_override.2864460875
Short name T497
Test name
Test status
Simulation time 16767582 ps
CPU time 0.99 seconds
Started Sep 18 07:58:47 AM UTC 24
Finished Sep 18 07:58:49 AM UTC 24
Peak memory 214112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2864460875 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.i2c_host_override.2864460875
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/12.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/12.i2c_host_perf.1588115656
Short name T745
Test name
Test status
Simulation time 73739982605 ps
CPU time 258.2 seconds
Started Sep 18 07:58:51 AM UTC 24
Finished Sep 18 08:03:14 AM UTC 24
Peak memory 215508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1588115656 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 12.i2c_host_perf.1588115656
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/12.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/12.i2c_host_perf_precise.2492623867
Short name T241
Test name
Test status
Simulation time 1764598561 ps
CPU time 40.57 seconds
Started Sep 18 07:58:51 AM UTC 24
Finished Sep 18 07:59:34 AM UTC 24
Peak memory 322208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2492623867 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_perf_precise.2492623867
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/12.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/12.i2c_host_smoke.4143591220
Short name T546
Test name
Test status
Simulation time 1427068968 ps
CPU time 56.31 seconds
Started Sep 18 07:58:47 AM UTC 24
Finished Sep 18 07:59:44 AM UTC 24
Peak memory 307840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4143591220 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.i2c_host_smoke.4143591220
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/12.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/12.i2c_host_stretch_timeout.2314940465
Short name T508
Test name
Test status
Simulation time 308925074 ps
CPU time 7.32 seconds
Started Sep 18 07:58:52 AM UTC 24
Finished Sep 18 07:59:01 AM UTC 24
Peak memory 225632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2314940465 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_stretch_timeout.2314940465
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/12.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/12.i2c_target_bad_addr.1607362179
Short name T525
Test name
Test status
Simulation time 1244364960 ps
CPU time 10.62 seconds
Started Sep 18 07:59:11 AM UTC 24
Finished Sep 18 07:59:23 AM UTC 24
Peak memory 225572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=1607362179 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_bad_ad
dr.1607362179
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/12.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/12.i2c_target_fifo_reset_acq.3427760174
Short name T515
Test name
Test status
Simulation time 127391929 ps
CPU time 1.22 seconds
Started Sep 18 07:59:09 AM UTC 24
Finished Sep 18 07:59:11 AM UTC 24
Peak memory 214784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3427760
174 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_fifo_reset_acq.3427760174
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/12.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/12.i2c_target_fifo_reset_tx.203846817
Short name T516
Test name
Test status
Simulation time 418269005 ps
CPU time 1.78 seconds
Started Sep 18 07:59:10 AM UTC 24
Finished Sep 18 07:59:13 AM UTC 24
Peak memory 214100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2038468
17 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_fifo_reset_tx.203846817
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/12.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/12.i2c_target_fifo_watermarks_acq.3936479538
Short name T523
Test name
Test status
Simulation time 611992412 ps
CPU time 3.85 seconds
Started Sep 18 07:59:17 AM UTC 24
Finished Sep 18 07:59:21 AM UTC 24
Peak memory 215264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3936479
538 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_fifo_watermar
ks_acq.3936479538
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/12.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/12.i2c_target_fifo_watermarks_tx.1326099149
Short name T521
Test name
Test status
Simulation time 165137423 ps
CPU time 2.12 seconds
Started Sep 18 07:59:18 AM UTC 24
Finished Sep 18 07:59:21 AM UTC 24
Peak memory 215044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1326099
149 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_fifo_watermark
s_tx.1326099149
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/12.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/12.i2c_target_hrst.3636305272
Short name T517
Test name
Test status
Simulation time 451376235 ps
CPU time 3.57 seconds
Started Sep 18 07:59:12 AM UTC 24
Finished Sep 18 07:59:17 AM UTC 24
Peak memory 225544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3636305
272 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_hrst.3636305272
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/12.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/12.i2c_target_intr_smoke.3687746935
Short name T511
Test name
Test status
Simulation time 1208335956 ps
CPU time 6.14 seconds
Started Sep 18 07:59:01 AM UTC 24
Finished Sep 18 07:59:08 AM UTC 24
Peak memory 232144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=368774
6935 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_intr_smoke.3687746935
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/12.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/12.i2c_target_intr_stress_wr.4055758361
Short name T522
Test name
Test status
Simulation time 5018663263 ps
CPU time 17.78 seconds
Started Sep 18 07:59:02 AM UTC 24
Finished Sep 18 07:59:21 AM UTC 24
Peak memory 215396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=4055758361 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_intr_stres
s_wr.4055758361
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/12.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/12.i2c_target_nack_acqfull_addr.1933894200
Short name T529
Test name
Test status
Simulation time 452278511 ps
CPU time 4.05 seconds
Started Sep 18 07:59:21 AM UTC 24
Finished Sep 18 07:59:26 AM UTC 24
Peak memory 215336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1933894
200 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_nack_acqfull_ad
dr.1933894200
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/12.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/12.i2c_target_perf.3094458200
Short name T269
Test name
Test status
Simulation time 636135537 ps
CPU time 8.12 seconds
Started Sep 18 07:59:10 AM UTC 24
Finished Sep 18 07:59:19 AM UTC 24
Peak memory 225568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3094458
200 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_perf.3094458200
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/12.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/12.i2c_target_smbus_maxlen.3094871180
Short name T495
Test name
Test status
Simulation time 420017992 ps
CPU time 3.26 seconds
Started Sep 18 07:59:20 AM UTC 24
Finished Sep 18 07:59:24 AM UTC 24
Peak memory 215092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3094871
180 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_smbus_maxlen.3094871180
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/12.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/12.i2c_target_smoke.1104540804
Short name T87
Test name
Test status
Simulation time 2050229363 ps
CPU time 29.19 seconds
Started Sep 18 07:58:54 AM UTC 24
Finished Sep 18 07:59:25 AM UTC 24
Peak memory 225492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1104540804 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_smoke.1104540804
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/12.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/12.i2c_target_stress_all.2173272343
Short name T825
Test name
Test status
Simulation time 49810153434 ps
CPU time 398.97 seconds
Started Sep 18 07:59:11 AM UTC 24
Finished Sep 18 08:05:55 AM UTC 24
Peak memory 3459940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=217327
2343 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_stress_all.2173272343
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/12.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/12.i2c_target_stress_rd.1154477857
Short name T524
Test name
Test status
Simulation time 3873645905 ps
CPU time 23.87 seconds
Started Sep 18 07:58:58 AM UTC 24
Finished Sep 18 07:59:23 AM UTC 24
Peak memory 242528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1154477857 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_stress_rd.1154477857
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/12.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/12.i2c_target_stress_wr.2147546536
Short name T512
Test name
Test status
Simulation time 16054959136 ps
CPU time 10.39 seconds
Started Sep 18 07:58:57 AM UTC 24
Finished Sep 18 07:59:09 AM UTC 24
Peak memory 215636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2147546536 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_stress_wr.2147546536
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/12.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/12.i2c_target_timeout.3278957279
Short name T519
Test name
Test status
Simulation time 2586965250 ps
CPU time 11.26 seconds
Started Sep 18 07:59:06 AM UTC 24
Finished Sep 18 07:59:18 AM UTC 24
Peak memory 231788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3278957
279 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_timeout.3278957279
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/12.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/12.i2c_target_tx_stretch_ctrl.1255915604
Short name T527
Test name
Test status
Simulation time 361463996 ps
CPU time 5.09 seconds
Started Sep 18 07:59:19 AM UTC 24
Finished Sep 18 07:59:25 AM UTC 24
Peak memory 215324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1255915
604 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_tx_stretch_ctrl.1255915604
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/12.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/13.i2c_alert_test.2982607664
Short name T555
Test name
Test status
Simulation time 193643909 ps
CPU time 1 seconds
Started Sep 18 07:59:46 AM UTC 24
Finished Sep 18 07:59:48 AM UTC 24
Peak memory 214840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2982607664 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_alert_test.2982607664
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/13.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/13.i2c_host_error_intr.3168514873
Short name T533
Test name
Test status
Simulation time 92566684 ps
CPU time 4.32 seconds
Started Sep 18 07:59:27 AM UTC 24
Finished Sep 18 07:59:32 AM UTC 24
Peak memory 229812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3168514873 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 13.i2c_host_error_intr.3168514873
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/13.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/13.i2c_host_fifo_fmt_empty.3256439735
Short name T534
Test name
Test status
Simulation time 1129873449 ps
CPU time 6.76 seconds
Started Sep 18 07:59:24 AM UTC 24
Finished Sep 18 07:59:32 AM UTC 24
Peak memory 287376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3256439735 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_fmt_empty.3256439735
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/13.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/13.i2c_host_fifo_full.1503865801
Short name T587
Test name
Test status
Simulation time 7129834021 ps
CPU time 49.92 seconds
Started Sep 18 07:59:26 AM UTC 24
Finished Sep 18 08:00:17 AM UTC 24
Peak memory 510752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1503865801 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_full.1503865801
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/13.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/13.i2c_host_fifo_overflow.1677149103
Short name T576
Test name
Test status
Simulation time 1327839529 ps
CPU time 42.43 seconds
Started Sep 18 07:59:24 AM UTC 24
Finished Sep 18 08:00:08 AM UTC 24
Peak memory 547616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1677149103 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_overflow.1677149103
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/13.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/13.i2c_host_fifo_reset_fmt.993583450
Short name T530
Test name
Test status
Simulation time 112199829 ps
CPU time 1.47 seconds
Started Sep 18 07:59:24 AM UTC 24
Finished Sep 18 07:59:27 AM UTC 24
Peak memory 214904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=993583450 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_fmt.993583450
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/13.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/13.i2c_host_fifo_reset_rx.1325505590
Short name T532
Test name
Test status
Simulation time 245778002 ps
CPU time 5.4 seconds
Started Sep 18 07:59:24 AM UTC 24
Finished Sep 18 07:59:31 AM UTC 24
Peak memory 233900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1325505590 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_rx.1325505590
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/13.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/13.i2c_host_fifo_watermark.3725919127
Short name T121
Test name
Test status
Simulation time 3331561068 ps
CPU time 68.31 seconds
Started Sep 18 07:59:23 AM UTC 24
Finished Sep 18 08:00:33 AM UTC 24
Peak memory 1032920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3725919127 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_watermark.3725919127
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/13.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/13.i2c_host_may_nack.3784534244
Short name T559
Test name
Test status
Simulation time 1252510086 ps
CPU time 8.67 seconds
Started Sep 18 07:59:41 AM UTC 24
Finished Sep 18 07:59:51 AM UTC 24
Peak memory 215392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3784534244 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.i2c_host_may_nack.3784534244
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/13.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/13.i2c_host_mode_toggle.2424305726
Short name T25
Test name
Test status
Simulation time 143674888 ps
CPU time 7.1 seconds
Started Sep 18 07:59:41 AM UTC 24
Finished Sep 18 07:59:49 AM UTC 24
Peak memory 236420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2424305726 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_mode_toggle.2424305726
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/13.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/13.i2c_host_override.139132001
Short name T485
Test name
Test status
Simulation time 21087310 ps
CPU time 1.03 seconds
Started Sep 18 07:59:22 AM UTC 24
Finished Sep 18 07:59:24 AM UTC 24
Peak memory 214108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=139132001 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 13.i2c_host_override.139132001
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/13.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/13.i2c_host_perf.1234975079
Short name T799
Test name
Test status
Simulation time 18838433603 ps
CPU time 289.7 seconds
Started Sep 18 07:59:26 AM UTC 24
Finished Sep 18 08:04:19 AM UTC 24
Peak memory 1338068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1234975079 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 13.i2c_host_perf.1234975079
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/13.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/13.i2c_host_perf_precise.1649531542
Short name T536
Test name
Test status
Simulation time 264144733 ps
CPU time 11.61 seconds
Started Sep 18 07:59:26 AM UTC 24
Finished Sep 18 07:59:38 AM UTC 24
Peak memory 260840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1649531542 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_perf_precise.1649531542
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/13.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/13.i2c_host_smoke.1947505229
Short name T579
Test name
Test status
Simulation time 22507456660 ps
CPU time 49.84 seconds
Started Sep 18 07:59:22 AM UTC 24
Finished Sep 18 08:00:13 AM UTC 24
Peak memory 269144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1947505229 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.i2c_host_smoke.1947505229
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/13.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/13.i2c_host_stress_all.2912377960
Short name T1000
Test name
Test status
Simulation time 39621579718 ps
CPU time 508 seconds
Started Sep 18 07:59:27 AM UTC 24
Finished Sep 18 08:08:01 AM UTC 24
Peak memory 1940452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2912377960 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 13.i2c_host_stress_all.2912377960
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/13.i2c_host_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/13.i2c_host_stretch_timeout.1331749684
Short name T538
Test name
Test status
Simulation time 526967581 ps
CPU time 12.43 seconds
Started Sep 18 07:59:26 AM UTC 24
Finished Sep 18 07:59:39 AM UTC 24
Peak memory 231716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1331749684 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_stretch_timeout.1331749684
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/13.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/13.i2c_target_bad_addr.674599422
Short name T554
Test name
Test status
Simulation time 787452710 ps
CPU time 7.15 seconds
Started Sep 18 07:59:40 AM UTC 24
Finished Sep 18 07:59:48 AM UTC 24
Peak memory 229668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=674599422 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_bad_addr.674599422
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/13.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/13.i2c_target_fifo_reset_acq.3203873669
Short name T542
Test name
Test status
Simulation time 301274096 ps
CPU time 2.29 seconds
Started Sep 18 07:59:37 AM UTC 24
Finished Sep 18 07:59:41 AM UTC 24
Peak memory 215456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3203873
669 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_fifo_reset_acq.3203873669
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/13.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/13.i2c_target_fifo_reset_tx.2242170049
Short name T540
Test name
Test status
Simulation time 301165881 ps
CPU time 1.22 seconds
Started Sep 18 07:59:38 AM UTC 24
Finished Sep 18 07:59:40 AM UTC 24
Peak memory 214904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2242170
049 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_fifo_reset_tx.2242170049
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/13.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/13.i2c_target_fifo_watermarks_acq.2816785345
Short name T549
Test name
Test status
Simulation time 175160654 ps
CPU time 2.18 seconds
Started Sep 18 07:59:42 AM UTC 24
Finished Sep 18 07:59:45 AM UTC 24
Peak memory 215100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2816785
345 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_fifo_watermar
ks_acq.2816785345
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/13.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/13.i2c_target_fifo_watermarks_tx.1220126970
Short name T550
Test name
Test status
Simulation time 174093354 ps
CPU time 1.94 seconds
Started Sep 18 07:59:43 AM UTC 24
Finished Sep 18 07:59:46 AM UTC 24
Peak memory 214972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1220126
970 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_fifo_watermark
s_tx.1220126970
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/13.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/13.i2c_target_hrst.2945914538
Short name T547
Test name
Test status
Simulation time 512440452 ps
CPU time 3.27 seconds
Started Sep 18 07:59:41 AM UTC 24
Finished Sep 18 07:59:45 AM UTC 24
Peak memory 225436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2945914
538 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_hrst.2945914538
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/13.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/13.i2c_target_intr_smoke.2274257726
Short name T541
Test name
Test status
Simulation time 4384041085 ps
CPU time 8 seconds
Started Sep 18 07:59:31 AM UTC 24
Finished Sep 18 07:59:40 AM UTC 24
Peak memory 232228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=227425
7726 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_intr_smoke.2274257726
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/13.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/13.i2c_target_intr_stress_wr.1844029513
Short name T545
Test name
Test status
Simulation time 8125552629 ps
CPU time 9.46 seconds
Started Sep 18 07:59:33 AM UTC 24
Finished Sep 18 07:59:44 AM UTC 24
Peak memory 430880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1844029513 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_intr_stres
s_wr.1844029513
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/13.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/13.i2c_target_nack_acqfull.872524840
Short name T562
Test name
Test status
Simulation time 1591140113 ps
CPU time 5.1 seconds
Started Sep 18 07:59:45 AM UTC 24
Finished Sep 18 07:59:51 AM UTC 24
Peak memory 225300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8725248
40 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_nack_acqfull.872524840
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/13.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/13.i2c_target_nack_acqfull_addr.3042470509
Short name T560
Test name
Test status
Simulation time 1738558039 ps
CPU time 3.89 seconds
Started Sep 18 07:59:46 AM UTC 24
Finished Sep 18 07:59:51 AM UTC 24
Peak memory 215248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3042470
509 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_nack_acqfull_ad
dr.3042470509
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/13.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/13.i2c_target_nack_txstretch.3040582081
Short name T556
Test name
Test status
Simulation time 526936149 ps
CPU time 1.79 seconds
Started Sep 18 07:59:46 AM UTC 24
Finished Sep 18 07:59:49 AM UTC 24
Peak memory 231564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3040582
081 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_nack_txstretch.3040582081
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/13.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/13.i2c_target_perf.3235479710
Short name T551
Test name
Test status
Simulation time 678441424 ps
CPU time 6.75 seconds
Started Sep 18 07:59:39 AM UTC 24
Finished Sep 18 07:59:46 AM UTC 24
Peak memory 232476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3235479
710 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_perf.3235479710
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/13.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/13.i2c_target_smbus_maxlen.4200884662
Short name T553
Test name
Test status
Simulation time 790511098 ps
CPU time 2.64 seconds
Started Sep 18 07:59:44 AM UTC 24
Finished Sep 18 07:59:48 AM UTC 24
Peak memory 215096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4200884
662 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_smbus_maxlen.4200884662
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/13.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/13.i2c_target_smoke.3507797917
Short name T558
Test name
Test status
Simulation time 1074129835 ps
CPU time 20.73 seconds
Started Sep 18 07:59:28 AM UTC 24
Finished Sep 18 07:59:50 AM UTC 24
Peak memory 225624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3507797917 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_smoke.3507797917
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/13.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/13.i2c_target_stress_all.3636338657
Short name T752
Test name
Test status
Simulation time 40121711900 ps
CPU time 227.75 seconds
Started Sep 18 07:59:40 AM UTC 24
Finished Sep 18 08:03:30 AM UTC 24
Peak memory 2483120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=363633
8657 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_stress_all.3636338657
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/13.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/13.i2c_target_stress_rd.1649520563
Short name T528
Test name
Test status
Simulation time 4908531548 ps
CPU time 64.23 seconds
Started Sep 18 07:59:28 AM UTC 24
Finished Sep 18 08:00:34 AM UTC 24
Peak memory 229708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1649520563 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_stress_rd.1649520563
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/13.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/13.i2c_target_stress_wr.3488668117
Short name T537
Test name
Test status
Simulation time 10211593226 ps
CPU time 10.16 seconds
Started Sep 18 07:59:28 AM UTC 24
Finished Sep 18 07:59:39 AM UTC 24
Peak memory 215388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3488668117 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_stress_wr.3488668117
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/13.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/13.i2c_target_stretch.2807253393
Short name T726
Test name
Test status
Simulation time 5875707235 ps
CPU time 204.45 seconds
Started Sep 18 07:59:28 AM UTC 24
Finished Sep 18 08:02:56 AM UTC 24
Peak memory 1534876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2807253393 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_stretch.2807253393
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/13.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/13.i2c_target_timeout.895306156
Short name T548
Test name
Test status
Simulation time 1163834865 ps
CPU time 10.63 seconds
Started Sep 18 07:59:33 AM UTC 24
Finished Sep 18 07:59:45 AM UTC 24
Peak memory 229664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8953061
56 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_timeout.895306156
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/13.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/13.i2c_target_tx_stretch_ctrl.2329101955
Short name T563
Test name
Test status
Simulation time 416290705 ps
CPU time 7.49 seconds
Started Sep 18 07:59:43 AM UTC 24
Finished Sep 18 07:59:52 AM UTC 24
Peak memory 215324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2329101
955 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_tx_stretch_ctrl.2329101955
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/13.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/14.i2c_alert_test.1156799722
Short name T585
Test name
Test status
Simulation time 20560224 ps
CPU time 0.87 seconds
Started Sep 18 08:00:15 AM UTC 24
Finished Sep 18 08:00:17 AM UTC 24
Peak memory 214840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1156799722 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_alert_test.1156799722
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/14.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/14.i2c_host_error_intr.3520671837
Short name T567
Test name
Test status
Simulation time 216091763 ps
CPU time 4.44 seconds
Started Sep 18 07:59:52 AM UTC 24
Finished Sep 18 07:59:58 AM UTC 24
Peak memory 225576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3520671837 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 14.i2c_host_error_intr.3520671837
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/14.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/14.i2c_host_fifo_fmt_empty.1520102800
Short name T565
Test name
Test status
Simulation time 216245994 ps
CPU time 5.88 seconds
Started Sep 18 07:59:50 AM UTC 24
Finished Sep 18 07:59:57 AM UTC 24
Peak memory 254688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1520102800 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_fmt_empty.1520102800
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/14.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/14.i2c_host_fifo_full.180764338
Short name T732
Test name
Test status
Simulation time 3534318732 ps
CPU time 187.28 seconds
Started Sep 18 07:59:50 AM UTC 24
Finished Sep 18 08:03:00 AM UTC 24
Peak memory 396272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=180764338 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_full.180764338
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/14.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/14.i2c_host_fifo_overflow.372071321
Short name T598
Test name
Test status
Simulation time 3430625915 ps
CPU time 54.51 seconds
Started Sep 18 07:59:49 AM UTC 24
Finished Sep 18 08:00:45 AM UTC 24
Peak memory 592676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=372071321 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_overflow.372071321
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/14.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/14.i2c_host_fifo_reset_fmt.1775733833
Short name T561
Test name
Test status
Simulation time 1026946710 ps
CPU time 1.59 seconds
Started Sep 18 07:59:49 AM UTC 24
Finished Sep 18 07:59:51 AM UTC 24
Peak memory 215080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1775733833 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_fmt.1775733833
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/14.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/14.i2c_host_fifo_reset_rx.1873922431
Short name T566
Test name
Test status
Simulation time 629506887 ps
CPU time 6.63 seconds
Started Sep 18 07:59:50 AM UTC 24
Finished Sep 18 07:59:57 AM UTC 24
Peak memory 244580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1873922431 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_rx.1873922431
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/14.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/14.i2c_host_fifo_watermark.2693094317
Short name T615
Test name
Test status
Simulation time 13047258820 ps
CPU time 75.54 seconds
Started Sep 18 07:59:49 AM UTC 24
Finished Sep 18 08:01:06 AM UTC 24
Peak memory 1014616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2693094317 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_watermark.2693094317
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/14.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/14.i2c_host_may_nack.1166961946
Short name T584
Test name
Test status
Simulation time 3789584313 ps
CPU time 5.99 seconds
Started Sep 18 08:00:09 AM UTC 24
Finished Sep 18 08:00:16 AM UTC 24
Peak memory 215380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1166961946 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.i2c_host_may_nack.1166961946
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/14.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/14.i2c_host_override.4097559255
Short name T557
Test name
Test status
Simulation time 30066922 ps
CPU time 1.08 seconds
Started Sep 18 07:59:47 AM UTC 24
Finished Sep 18 07:59:49 AM UTC 24
Peak memory 214112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4097559255 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.i2c_host_override.4097559255
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/14.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/14.i2c_host_perf.681776847
Short name T568
Test name
Test status
Simulation time 495241290 ps
CPU time 7.47 seconds
Started Sep 18 07:59:51 AM UTC 24
Finished Sep 18 08:00:00 AM UTC 24
Peak memory 271080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=681776847 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 14.i2c_host_perf.681776847
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/14.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/14.i2c_host_perf_precise.2484254947
Short name T603
Test name
Test status
Simulation time 6419367013 ps
CPU time 60.85 seconds
Started Sep 18 07:59:51 AM UTC 24
Finished Sep 18 08:00:54 AM UTC 24
Peak memory 215388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2484254947 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_perf_precise.2484254947
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/14.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/14.i2c_host_smoke.1468008071
Short name T535
Test name
Test status
Simulation time 4851759381 ps
CPU time 50.71 seconds
Started Sep 18 07:59:46 AM UTC 24
Finished Sep 18 08:00:39 AM UTC 24
Peak memory 379880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1468008071 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 14.i2c_host_smoke.1468008071
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/14.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/14.i2c_host_stretch_timeout.3209289401
Short name T575
Test name
Test status
Simulation time 633767177 ps
CPU time 15.54 seconds
Started Sep 18 07:59:51 AM UTC 24
Finished Sep 18 08:00:08 AM UTC 24
Peak memory 229784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3209289401 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_stretch_timeout.3209289401
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/14.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/14.i2c_target_bad_addr.1873472075
Short name T583
Test name
Test status
Simulation time 1203477761 ps
CPU time 5.57 seconds
Started Sep 18 08:00:09 AM UTC 24
Finished Sep 18 08:00:16 AM UTC 24
Peak memory 227520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=1873472075 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_bad_ad
dr.1873472075
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/14.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/14.i2c_target_fifo_reset_acq.4048278113
Short name T89
Test name
Test status
Simulation time 452729631 ps
CPU time 2.47 seconds
Started Sep 18 08:00:03 AM UTC 24
Finished Sep 18 08:00:09 AM UTC 24
Peak memory 215456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4048278
113 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_fifo_reset_acq.4048278113
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/14.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/14.i2c_target_fifo_reset_tx.2325960336
Short name T577
Test name
Test status
Simulation time 463552886 ps
CPU time 1.81 seconds
Started Sep 18 08:00:07 AM UTC 24
Finished Sep 18 08:00:10 AM UTC 24
Peak memory 214784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2325960
336 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_fifo_reset_tx.2325960336
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/14.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/14.i2c_target_fifo_watermarks_acq.3510552485
Short name T586
Test name
Test status
Simulation time 1087406531 ps
CPU time 5.22 seconds
Started Sep 18 08:00:10 AM UTC 24
Finished Sep 18 08:00:17 AM UTC 24
Peak memory 215276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3510552
485 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_fifo_watermar
ks_acq.3510552485
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/14.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/14.i2c_target_fifo_watermarks_tx.1266519077
Short name T581
Test name
Test status
Simulation time 624503936 ps
CPU time 2.32 seconds
Started Sep 18 08:00:10 AM UTC 24
Finished Sep 18 08:00:14 AM UTC 24
Peak memory 215112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1266519
077 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_fifo_watermark
s_tx.1266519077
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/14.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/14.i2c_target_hrst.2937529065
Short name T578
Test name
Test status
Simulation time 933429401 ps
CPU time 2.9 seconds
Started Sep 18 08:00:09 AM UTC 24
Finished Sep 18 08:00:13 AM UTC 24
Peak memory 215392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2937529
065 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_hrst.2937529065
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/14.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/14.i2c_target_intr_smoke.84706625
Short name T574
Test name
Test status
Simulation time 1565275346 ps
CPU time 8.26 seconds
Started Sep 18 07:59:59 AM UTC 24
Finished Sep 18 08:00:08 AM UTC 24
Peak memory 229732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=847066
25 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_intr_smoke.84706625
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/14.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/14.i2c_target_intr_stress_wr.2776443033
Short name T843
Test name
Test status
Simulation time 20274380542 ps
CPU time 316.21 seconds
Started Sep 18 07:59:59 AM UTC 24
Finished Sep 18 08:05:19 AM UTC 24
Peak memory 5018464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2776443033 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_intr_stres
s_wr.2776443033
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/14.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/14.i2c_target_nack_acqfull.494653594
Short name T589
Test name
Test status
Simulation time 1005785996 ps
CPU time 3.88 seconds
Started Sep 18 08:00:14 AM UTC 24
Finished Sep 18 08:00:18 AM UTC 24
Peak memory 225508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4946535
94 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_nack_acqfull.494653594
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/14.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/14.i2c_target_nack_acqfull_addr.2565620215
Short name T593
Test name
Test status
Simulation time 465541718 ps
CPU time 4.43 seconds
Started Sep 18 08:00:15 AM UTC 24
Finished Sep 18 08:00:20 AM UTC 24
Peak memory 215336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2565620
215 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_nack_acqfull_ad
dr.2565620215
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/14.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/14.i2c_target_nack_txstretch.2717303484
Short name T588
Test name
Test status
Simulation time 607218223 ps
CPU time 2.32 seconds
Started Sep 18 08:00:15 AM UTC 24
Finished Sep 18 08:00:18 AM UTC 24
Peak memory 232152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2717303
484 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_nack_txstretch.2717303484
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/14.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/14.i2c_target_perf.3172545760
Short name T591
Test name
Test status
Simulation time 969739671 ps
CPU time 10.99 seconds
Started Sep 18 08:00:07 AM UTC 24
Finished Sep 18 08:00:19 AM UTC 24
Peak memory 242604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3172545
760 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_perf.3172545760
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/14.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/14.i2c_target_smbus_maxlen.371652330
Short name T592
Test name
Test status
Simulation time 922380192 ps
CPU time 4.61 seconds
Started Sep 18 08:00:14 AM UTC 24
Finished Sep 18 08:00:19 AM UTC 24
Peak memory 215100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3716523
30 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_smbus_maxlen.371652330
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/14.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/14.i2c_target_smoke.4213069947
Short name T570
Test name
Test status
Simulation time 1980718579 ps
CPU time 8.47 seconds
Started Sep 18 07:59:52 AM UTC 24
Finished Sep 18 08:00:02 AM UTC 24
Peak memory 225696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4213069947 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_smoke.4213069947
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/14.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/14.i2c_target_stress_all.1917342934
Short name T1127
Test name
Test status
Simulation time 39501251603 ps
CPU time 600.44 seconds
Started Sep 18 08:00:08 AM UTC 24
Finished Sep 18 08:10:15 AM UTC 24
Peak memory 6675288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=191734
2934 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_stress_all.1917342934
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/14.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/14.i2c_target_stress_rd.1645685471
Short name T621
Test name
Test status
Simulation time 1628939985 ps
CPU time 70.6 seconds
Started Sep 18 07:59:55 AM UTC 24
Finished Sep 18 08:01:08 AM UTC 24
Peak memory 229588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1645685471 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_stress_rd.1645685471
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/14.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/14.i2c_target_stress_wr.195194579
Short name T878
Test name
Test status
Simulation time 39417512771 ps
CPU time 362.68 seconds
Started Sep 18 07:59:52 AM UTC 24
Finished Sep 18 08:05:59 AM UTC 24
Peak memory 5090068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=195194579 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_stress_wr.195194579
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/14.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/14.i2c_target_stretch.3529266946
Short name T607
Test name
Test status
Simulation time 4716818184 ps
CPU time 59.06 seconds
Started Sep 18 07:59:57 AM UTC 24
Finished Sep 18 08:00:58 AM UTC 24
Peak memory 906084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3529266946 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_stretch.3529266946
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/14.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/14.i2c_target_timeout.1496273864
Short name T580
Test name
Test status
Simulation time 4897737434 ps
CPU time 7.79 seconds
Started Sep 18 08:00:01 AM UTC 24
Finished Sep 18 08:00:14 AM UTC 24
Peak memory 232368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1496273
864 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_timeout.1496273864
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/14.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/14.i2c_target_tx_stretch_ctrl.4290034588
Short name T582
Test name
Test status
Simulation time 113258083 ps
CPU time 2.97 seconds
Started Sep 18 08:00:10 AM UTC 24
Finished Sep 18 08:00:14 AM UTC 24
Peak memory 215260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4290034
588 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_tx_stretch_ctrl.4290034588
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/14.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/15.i2c_alert_test.2491585293
Short name T619
Test name
Test status
Simulation time 45320626 ps
CPU time 0.98 seconds
Started Sep 18 08:01:04 AM UTC 24
Finished Sep 18 08:01:06 AM UTC 24
Peak memory 214900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2491585293 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_alert_test.2491585293
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/15.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/15.i2c_host_error_intr.2284509502
Short name T595
Test name
Test status
Simulation time 645693025 ps
CPU time 3.83 seconds
Started Sep 18 08:00:21 AM UTC 24
Finished Sep 18 08:00:25 AM UTC 24
Peak memory 246648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2284509502 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 15.i2c_host_error_intr.2284509502
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/15.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/15.i2c_host_fifo_fmt_empty.2652528242
Short name T596
Test name
Test status
Simulation time 314094745 ps
CPU time 6.98 seconds
Started Sep 18 08:00:18 AM UTC 24
Finished Sep 18 08:00:26 AM UTC 24
Peak memory 275232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2652528242 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_fmt_empty.2652528242
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/15.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/15.i2c_host_fifo_full.482481108
Short name T142
Test name
Test status
Simulation time 3057186462 ps
CPU time 95.96 seconds
Started Sep 18 08:00:19 AM UTC 24
Finished Sep 18 08:01:57 AM UTC 24
Peak memory 750392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=482481108 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_full.482481108
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/15.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/15.i2c_host_fifo_overflow.685673687
Short name T145
Test name
Test status
Simulation time 3728903810 ps
CPU time 100.78 seconds
Started Sep 18 08:00:17 AM UTC 24
Finished Sep 18 08:02:00 AM UTC 24
Peak memory 598948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=685673687 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_overflow.685673687
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/15.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/15.i2c_host_fifo_reset_fmt.1482374456
Short name T594
Test name
Test status
Simulation time 93754271 ps
CPU time 1.67 seconds
Started Sep 18 08:00:18 AM UTC 24
Finished Sep 18 08:00:21 AM UTC 24
Peak memory 214900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1482374456 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_fmt.1482374456
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/15.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/15.i2c_host_fifo_reset_rx.3577090054
Short name T597
Test name
Test status
Simulation time 564764081 ps
CPU time 8.09 seconds
Started Sep 18 08:00:19 AM UTC 24
Finished Sep 18 08:00:28 AM UTC 24
Peak memory 215192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3577090054 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_rx.3577090054
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/15.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/15.i2c_host_fifo_watermark.1884576721
Short name T123
Test name
Test status
Simulation time 4878712230 ps
CPU time 106.48 seconds
Started Sep 18 08:00:17 AM UTC 24
Finished Sep 18 08:02:06 AM UTC 24
Peak memory 1364752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1884576721 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_watermark.1884576721
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/15.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/15.i2c_host_may_nack.1107196295
Short name T614
Test name
Test status
Simulation time 564255321 ps
CPU time 7.73 seconds
Started Sep 18 08:00:57 AM UTC 24
Finished Sep 18 08:01:06 AM UTC 24
Peak memory 215264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1107196295 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.i2c_host_may_nack.1107196295
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/15.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/15.i2c_host_override.3672641744
Short name T590
Test name
Test status
Simulation time 15760961 ps
CPU time 1.06 seconds
Started Sep 18 08:00:17 AM UTC 24
Finished Sep 18 08:00:19 AM UTC 24
Peak memory 214112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3672641744 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.i2c_host_override.3672641744
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/15.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/15.i2c_host_perf.2520156274
Short name T628
Test name
Test status
Simulation time 2636192588 ps
CPU time 55.01 seconds
Started Sep 18 08:00:19 AM UTC 24
Finished Sep 18 08:01:16 AM UTC 24
Peak memory 750432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2520156274 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 15.i2c_host_perf.2520156274
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/15.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/15.i2c_host_perf_precise.493139412
Short name T660
Test name
Test status
Simulation time 6310644034 ps
CPU time 82.06 seconds
Started Sep 18 08:00:21 AM UTC 24
Finished Sep 18 08:01:44 AM UTC 24
Peak memory 674456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=493139412 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_perf_precise.493139412
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/15.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/15.i2c_host_smoke.224562226
Short name T638
Test name
Test status
Simulation time 2135236025 ps
CPU time 69.29 seconds
Started Sep 18 08:00:16 AM UTC 24
Finished Sep 18 08:01:27 AM UTC 24
Peak memory 330464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=224562226 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 15.i2c_host_smoke.224562226
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/15.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/15.i2c_host_stretch_timeout.40853781
Short name T609
Test name
Test status
Simulation time 728817108 ps
CPU time 39.13 seconds
Started Sep 18 08:00:21 AM UTC 24
Finished Sep 18 08:01:01 AM UTC 24
Peak memory 225424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=40853781 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ho
st_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_stretch_timeout.40853781
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/15.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/15.i2c_target_bad_addr.1224140367
Short name T611
Test name
Test status
Simulation time 1400823788 ps
CPU time 6.62 seconds
Started Sep 18 08:00:55 AM UTC 24
Finished Sep 18 08:01:03 AM UTC 24
Peak memory 229592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=1224140367 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_bad_ad
dr.1224140367
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/15.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/15.i2c_target_fifo_reset_acq.1887357341
Short name T602
Test name
Test status
Simulation time 661870370 ps
CPU time 2.07 seconds
Started Sep 18 08:00:49 AM UTC 24
Finished Sep 18 08:00:53 AM UTC 24
Peak memory 214976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1887357
341 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_fifo_reset_acq.1887357341
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/15.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/15.i2c_target_fifo_reset_tx.1386722177
Short name T604
Test name
Test status
Simulation time 179877895 ps
CPU time 1.89 seconds
Started Sep 18 08:00:50 AM UTC 24
Finished Sep 18 08:00:54 AM UTC 24
Peak memory 215024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1386722
177 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_fifo_reset_tx.1386722177
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/15.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/15.i2c_target_fifo_watermarks_acq.2270156198
Short name T612
Test name
Test status
Simulation time 432744865 ps
CPU time 4.61 seconds
Started Sep 18 08:00:58 AM UTC 24
Finished Sep 18 08:01:04 AM UTC 24
Peak memory 215340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2270156
198 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_fifo_watermar
ks_acq.2270156198
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/15.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/15.i2c_target_fifo_watermarks_tx.1321470478
Short name T610
Test name
Test status
Simulation time 633603449 ps
CPU time 2.45 seconds
Started Sep 18 08:00:59 AM UTC 24
Finished Sep 18 08:01:02 AM UTC 24
Peak memory 215244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1321470
478 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_fifo_watermark
s_tx.1321470478
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/15.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/15.i2c_target_intr_smoke.1542719512
Short name T599
Test name
Test status
Simulation time 4073065147 ps
CPU time 12 seconds
Started Sep 18 08:00:35 AM UTC 24
Finished Sep 18 08:00:48 AM UTC 24
Peak memory 225556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=154271
9512 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_intr_smoke.1542719512
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/15.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/15.i2c_target_intr_stress_wr.1418036436
Short name T738
Test name
Test status
Simulation time 21404673537 ps
CPU time 142.84 seconds
Started Sep 18 08:00:39 AM UTC 24
Finished Sep 18 08:03:05 AM UTC 24
Peak memory 2128728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1418036436 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_intr_stres
s_wr.1418036436
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/15.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/15.i2c_target_nack_acqfull.895674016
Short name T620
Test name
Test status
Simulation time 473416002 ps
CPU time 3.87 seconds
Started Sep 18 08:01:02 AM UTC 24
Finished Sep 18 08:01:07 AM UTC 24
Peak memory 225636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8956740
16 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_nack_acqfull.895674016
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/15.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/15.i2c_target_nack_acqfull_addr.2466813897
Short name T623
Test name
Test status
Simulation time 2958446478 ps
CPU time 5.29 seconds
Started Sep 18 08:01:03 AM UTC 24
Finished Sep 18 08:01:10 AM UTC 24
Peak memory 215400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2466813
897 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_nack_acqfull_ad
dr.2466813897
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/15.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/15.i2c_target_nack_txstretch.2069430709
Short name T617
Test name
Test status
Simulation time 128107165 ps
CPU time 1.79 seconds
Started Sep 18 08:01:03 AM UTC 24
Finished Sep 18 08:01:06 AM UTC 24
Peak memory 231504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2069430
709 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_nack_txstretch.2069430709
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/15.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/15.i2c_target_perf.2585423003
Short name T608
Test name
Test status
Simulation time 2553085639 ps
CPU time 5.37 seconds
Started Sep 18 08:00:54 AM UTC 24
Finished Sep 18 08:01:00 AM UTC 24
Peak memory 225632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2585423
003 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_perf.2585423003
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/15.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/15.i2c_target_smbus_maxlen.3482619633
Short name T616
Test name
Test status
Simulation time 3180988306 ps
CPU time 3.94 seconds
Started Sep 18 08:01:01 AM UTC 24
Finished Sep 18 08:01:06 AM UTC 24
Peak memory 215096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3482619
633 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_smbus_maxlen.3482619633
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/15.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/15.i2c_target_smoke.4109082583
Short name T606
Test name
Test status
Simulation time 3442085213 ps
CPU time 30.03 seconds
Started Sep 18 08:00:26 AM UTC 24
Finished Sep 18 08:00:57 AM UTC 24
Peak memory 225688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4109082583 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_smoke.4109082583
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/15.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/15.i2c_target_stress_all.2562955108
Short name T699
Test name
Test status
Simulation time 17988585519 ps
CPU time 90.87 seconds
Started Sep 18 08:00:54 AM UTC 24
Finished Sep 18 08:02:26 AM UTC 24
Peak memory 1547248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=256295
5108 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_stress_all.2562955108
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/15.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/15.i2c_target_stress_rd.561288683
Short name T626
Test name
Test status
Simulation time 2374667517 ps
CPU time 42.94 seconds
Started Sep 18 08:00:29 AM UTC 24
Finished Sep 18 08:01:13 AM UTC 24
Peak memory 225628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=561288683 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_stress_rd.561288683
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/15.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/15.i2c_target_stress_wr.516345474
Short name T634
Test name
Test status
Simulation time 24688046513 ps
CPU time 55.46 seconds
Started Sep 18 08:00:27 AM UTC 24
Finished Sep 18 08:01:24 AM UTC 24
Peak memory 674784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=516345474 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_stress_wr.516345474
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/15.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/15.i2c_target_stretch.1681005338
Short name T600
Test name
Test status
Simulation time 1091585725 ps
CPU time 13.49 seconds
Started Sep 18 08:00:34 AM UTC 24
Finished Sep 18 08:00:49 AM UTC 24
Peak memory 258776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1681005338 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_stretch.1681005338
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/15.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/15.i2c_target_timeout.2885724295
Short name T605
Test name
Test status
Simulation time 5590621708 ps
CPU time 9.47 seconds
Started Sep 18 08:00:45 AM UTC 24
Finished Sep 18 08:00:56 AM UTC 24
Peak memory 232256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2885724
295 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_timeout.2885724295
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/15.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/15.i2c_target_tx_stretch_ctrl.1073227020
Short name T618
Test name
Test status
Simulation time 162043211 ps
CPU time 4.19 seconds
Started Sep 18 08:01:01 AM UTC 24
Finished Sep 18 08:01:06 AM UTC 24
Peak memory 215452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1073227
020 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_tx_stretch_ctrl.1073227020
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/15.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/16.i2c_alert_test.67466926
Short name T649
Test name
Test status
Simulation time 26128665 ps
CPU time 0.97 seconds
Started Sep 18 08:01:34 AM UTC 24
Finished Sep 18 08:01:36 AM UTC 24
Peak memory 214844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=67466926 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_alert_test.67466926
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/16.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/16.i2c_host_error_intr.422487433
Short name T627
Test name
Test status
Simulation time 112685804 ps
CPU time 4.55 seconds
Started Sep 18 08:01:10 AM UTC 24
Finished Sep 18 08:01:16 AM UTC 24
Peak memory 229608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=422487433 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 16.i2c_host_error_intr.422487433
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/16.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/16.i2c_host_fifo_fmt_empty.2850681288
Short name T633
Test name
Test status
Simulation time 1386118646 ps
CPU time 13.03 seconds
Started Sep 18 08:01:07 AM UTC 24
Finished Sep 18 08:01:21 AM UTC 24
Peak memory 254676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2850681288 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_fmt_empty.2850681288
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/16.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/16.i2c_host_fifo_full.1901151379
Short name T715
Test name
Test status
Simulation time 3003406436 ps
CPU time 90.91 seconds
Started Sep 18 08:01:08 AM UTC 24
Finished Sep 18 08:02:41 AM UTC 24
Peak memory 592740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1901151379 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_full.1901151379
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/16.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/16.i2c_host_fifo_overflow.1046894850
Short name T664
Test name
Test status
Simulation time 1705979612 ps
CPU time 42.42 seconds
Started Sep 18 08:01:07 AM UTC 24
Finished Sep 18 08:01:50 AM UTC 24
Peak memory 551604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1046894850 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_overflow.1046894850
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/16.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/16.i2c_host_fifo_reset_fmt.2052539715
Short name T622
Test name
Test status
Simulation time 399143010 ps
CPU time 1.52 seconds
Started Sep 18 08:01:07 AM UTC 24
Finished Sep 18 08:01:09 AM UTC 24
Peak memory 214868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2052539715 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_fmt.2052539715
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/16.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/16.i2c_host_fifo_reset_rx.3840856640
Short name T632
Test name
Test status
Simulation time 172952840 ps
CPU time 11.71 seconds
Started Sep 18 08:01:08 AM UTC 24
Finished Sep 18 08:01:21 AM UTC 24
Peak memory 215192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3840856640 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_rx.3840856640
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/16.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/16.i2c_host_fifo_watermark.3424248891
Short name T750
Test name
Test status
Simulation time 15512547703 ps
CPU time 140.2 seconds
Started Sep 18 08:01:07 AM UTC 24
Finished Sep 18 08:03:29 AM UTC 24
Peak memory 830360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3424248891 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_watermark.3424248891
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/16.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/16.i2c_host_may_nack.943032598
Short name T250
Test name
Test status
Simulation time 2241678146 ps
CPU time 18.53 seconds
Started Sep 18 08:01:26 AM UTC 24
Finished Sep 18 08:01:46 AM UTC 24
Peak memory 215520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=943032598 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 16.i2c_host_may_nack.943032598
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/16.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/16.i2c_host_override.1519470445
Short name T150
Test name
Test status
Simulation time 47707779 ps
CPU time 1.02 seconds
Started Sep 18 08:01:07 AM UTC 24
Finished Sep 18 08:01:08 AM UTC 24
Peak memory 214112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1519470445 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.i2c_host_override.1519470445
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/16.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/16.i2c_host_perf.2862881297
Short name T661
Test name
Test status
Simulation time 2718459551 ps
CPU time 34.75 seconds
Started Sep 18 08:01:09 AM UTC 24
Finished Sep 18 08:01:45 AM UTC 24
Peak memory 239824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2862881297 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 16.i2c_host_perf.2862881297
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/16.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/16.i2c_host_perf_precise.116779791
Short name T625
Test name
Test status
Simulation time 89192305 ps
CPU time 2.63 seconds
Started Sep 18 08:01:09 AM UTC 24
Finished Sep 18 08:01:13 AM UTC 24
Peak memory 215252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=116779791 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_perf_precise.116779791
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/16.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/16.i2c_host_smoke.2759220593
Short name T143
Test name
Test status
Simulation time 4039662791 ps
CPU time 51.42 seconds
Started Sep 18 08:01:05 AM UTC 24
Finished Sep 18 08:01:58 AM UTC 24
Peak memory 291548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2759220593 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.i2c_host_smoke.2759220593
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/16.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/16.i2c_host_stress_all.4176006001
Short name T280
Test name
Test status
Simulation time 35993510803 ps
CPU time 3476.99 seconds
Started Sep 18 08:01:10 AM UTC 24
Finished Sep 18 08:59:41 AM UTC 24
Peak memory 5212904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4176006001 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 16.i2c_host_stress_all.4176006001
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/16.i2c_host_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/16.i2c_host_stretch_timeout.2662010877
Short name T631
Test name
Test status
Simulation time 508711534 ps
CPU time 9.3 seconds
Started Sep 18 08:01:10 AM UTC 24
Finished Sep 18 08:01:20 AM UTC 24
Peak memory 225632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2662010877 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_stretch_timeout.2662010877
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/16.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/16.i2c_target_bad_addr.1189378989
Short name T652
Test name
Test status
Simulation time 2163643525 ps
CPU time 11.06 seconds
Started Sep 18 08:01:25 AM UTC 24
Finished Sep 18 08:01:37 AM UTC 24
Peak memory 227624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=1189378989 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_bad_ad
dr.1189378989
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/16.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/16.i2c_target_fifo_reset_acq.1754551273
Short name T637
Test name
Test status
Simulation time 216070207 ps
CPU time 2.41 seconds
Started Sep 18 08:01:22 AM UTC 24
Finished Sep 18 08:01:25 AM UTC 24
Peak memory 215256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1754551
273 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_fifo_reset_acq.1754551273
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/16.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/16.i2c_target_fifo_reset_tx.3674048180
Short name T636
Test name
Test status
Simulation time 2412221664 ps
CPU time 2.03 seconds
Started Sep 18 08:01:22 AM UTC 24
Finished Sep 18 08:01:25 AM UTC 24
Peak memory 215292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3674048
180 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_fifo_reset_tx.3674048180
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/16.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/16.i2c_target_fifo_watermarks_acq.1431176612
Short name T645
Test name
Test status
Simulation time 674891475 ps
CPU time 3.55 seconds
Started Sep 18 08:01:28 AM UTC 24
Finished Sep 18 08:01:33 AM UTC 24
Peak memory 215240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1431176
612 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_fifo_watermar
ks_acq.1431176612
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/16.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/16.i2c_target_fifo_watermarks_tx.443722273
Short name T643
Test name
Test status
Simulation time 152959433 ps
CPU time 2.45 seconds
Started Sep 18 08:01:29 AM UTC 24
Finished Sep 18 08:01:32 AM UTC 24
Peak memory 215120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4437222
73 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_fifo_watermarks
_tx.443722273
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/16.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/16.i2c_target_intr_smoke.1236038140
Short name T635
Test name
Test status
Simulation time 3971511919 ps
CPU time 7.09 seconds
Started Sep 18 08:01:17 AM UTC 24
Finished Sep 18 08:01:25 AM UTC 24
Peak memory 232260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=123603
8140 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_intr_smoke.1236038140
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/16.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/16.i2c_target_intr_stress_wr.1581210407
Short name T657
Test name
Test status
Simulation time 10996264831 ps
CPU time 25.52 seconds
Started Sep 18 08:01:17 AM UTC 24
Finished Sep 18 08:01:43 AM UTC 24
Peak memory 625632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1581210407 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_intr_stres
s_wr.1581210407
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/16.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/16.i2c_target_nack_acqfull.1724770408
Short name T650
Test name
Test status
Simulation time 2356447664 ps
CPU time 5.25 seconds
Started Sep 18 08:01:31 AM UTC 24
Finished Sep 18 08:01:37 AM UTC 24
Peak memory 225612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1724770
408 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_nack_acqfull.1724770408
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/16.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/16.i2c_target_nack_acqfull_addr.3754804135
Short name T653
Test name
Test status
Simulation time 1807357590 ps
CPU time 4.62 seconds
Started Sep 18 08:01:33 AM UTC 24
Finished Sep 18 08:01:38 AM UTC 24
Peak memory 215260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3754804
135 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_nack_acqfull_ad
dr.3754804135
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/16.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/16.i2c_target_nack_txstretch.32033979
Short name T648
Test name
Test status
Simulation time 275724091 ps
CPU time 1.9 seconds
Started Sep 18 08:01:33 AM UTC 24
Finished Sep 18 08:01:36 AM UTC 24
Peak memory 231568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3203397
9 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_nack_txstretch.32033979
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/16.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/16.i2c_target_perf.1030949375
Short name T646
Test name
Test status
Simulation time 3486455967 ps
CPU time 10.46 seconds
Started Sep 18 08:01:22 AM UTC 24
Finished Sep 18 08:01:34 AM UTC 24
Peak memory 242536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1030949
375 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_perf.1030949375
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/16.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/16.i2c_target_smbus_maxlen.439476369
Short name T647
Test name
Test status
Simulation time 462091839 ps
CPU time 4.33 seconds
Started Sep 18 08:01:30 AM UTC 24
Finished Sep 18 08:01:35 AM UTC 24
Peak memory 215096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4394763
69 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_smbus_maxlen.439476369
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/16.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/16.i2c_target_smoke.2262029298
Short name T639
Test name
Test status
Simulation time 462013642 ps
CPU time 14.75 seconds
Started Sep 18 08:01:11 AM UTC 24
Finished Sep 18 08:01:27 AM UTC 24
Peak memory 225548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2262029298 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_smoke.2262029298
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/16.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/16.i2c_target_stress_rd.79147483
Short name T642
Test name
Test status
Simulation time 2775414799 ps
CPU time 16.06 seconds
Started Sep 18 08:01:14 AM UTC 24
Finished Sep 18 08:01:32 AM UTC 24
Peak memory 215396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=79147483 -assert nopostpro
c +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_stress_rd.79147483
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/16.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/16.i2c_target_stress_wr.1625060612
Short name T880
Test name
Test status
Simulation time 54574769540 ps
CPU time 283.64 seconds
Started Sep 18 08:01:13 AM UTC 24
Finished Sep 18 08:06:00 AM UTC 24
Peak memory 4107024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1625060612 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_stress_wr.1625060612
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/16.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/16.i2c_target_stretch.3926203653
Short name T630
Test name
Test status
Simulation time 1952944277 ps
CPU time 2.57 seconds
Started Sep 18 08:01:17 AM UTC 24
Finished Sep 18 08:01:20 AM UTC 24
Peak memory 215040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3926203653 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_stretch.3926203653
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/16.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/16.i2c_target_timeout.80545906
Short name T640
Test name
Test status
Simulation time 16211254566 ps
CPU time 8.73 seconds
Started Sep 18 08:01:18 AM UTC 24
Finished Sep 18 08:01:27 AM UTC 24
Peak memory 242800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8054590
6 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_timeout.80545906
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/16.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/16.i2c_target_tx_stretch_ctrl.31601006
Short name T644
Test name
Test status
Simulation time 196721141 ps
CPU time 3.43 seconds
Started Sep 18 08:01:29 AM UTC 24
Finished Sep 18 08:01:33 AM UTC 24
Peak memory 215248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3160100
6 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_tx_stretch_ctrl.31601006
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/16.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/17.i2c_alert_test.453341247
Short name T670
Test name
Test status
Simulation time 143331137 ps
CPU time 0.83 seconds
Started Sep 18 08:02:01 AM UTC 24
Finished Sep 18 08:02:03 AM UTC 24
Peak memory 214668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=453341247 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_alert_test.453341247
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/17.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/17.i2c_host_error_intr.876866264
Short name T659
Test name
Test status
Simulation time 208225290 ps
CPU time 2.42 seconds
Started Sep 18 08:01:41 AM UTC 24
Finished Sep 18 08:01:44 AM UTC 24
Peak memory 229616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=876866264 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 17.i2c_host_error_intr.876866264
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/17.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/17.i2c_host_fifo_fmt_empty.2291125067
Short name T656
Test name
Test status
Simulation time 1223636027 ps
CPU time 5.66 seconds
Started Sep 18 08:01:36 AM UTC 24
Finished Sep 18 08:01:43 AM UTC 24
Peak memory 281308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2291125067 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_fmt_empty.2291125067
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/17.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/17.i2c_host_fifo_full.849003559
Short name T844
Test name
Test status
Simulation time 3412843373 ps
CPU time 217.2 seconds
Started Sep 18 08:01:39 AM UTC 24
Finished Sep 18 08:05:19 AM UTC 24
Peak memory 865260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=849003559 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_full.849003559
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/17.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/17.i2c_host_fifo_overflow.1512051743
Short name T779
Test name
Test status
Simulation time 19912204058 ps
CPU time 145.6 seconds
Started Sep 18 08:01:36 AM UTC 24
Finished Sep 18 08:04:04 AM UTC 24
Peak memory 772912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1512051743 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_overflow.1512051743
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/17.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/17.i2c_host_fifo_reset_fmt.3838571833
Short name T654
Test name
Test status
Simulation time 461462017 ps
CPU time 1.76 seconds
Started Sep 18 08:01:36 AM UTC 24
Finished Sep 18 08:01:39 AM UTC 24
Peak memory 215020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3838571833 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_fmt.3838571833
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/17.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/17.i2c_host_fifo_reset_rx.4280627926
Short name T663
Test name
Test status
Simulation time 195376615 ps
CPU time 7.19 seconds
Started Sep 18 08:01:37 AM UTC 24
Finished Sep 18 08:01:46 AM UTC 24
Peak memory 248620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4280627926 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_rx.4280627926
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/17.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/17.i2c_host_fifo_watermark.4237436526
Short name T778
Test name
Test status
Simulation time 22951655574 ps
CPU time 143.86 seconds
Started Sep 18 08:01:36 AM UTC 24
Finished Sep 18 08:04:03 AM UTC 24
Peak memory 1682276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4237436526 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_watermark.4237436526
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/17.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/17.i2c_host_may_nack.3917588000
Short name T674
Test name
Test status
Simulation time 483066075 ps
CPU time 7.56 seconds
Started Sep 18 08:01:56 AM UTC 24
Finished Sep 18 08:02:04 AM UTC 24
Peak memory 215392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3917588000 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.i2c_host_may_nack.3917588000
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/17.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/17.i2c_host_mode_toggle.4131492142
Short name T80
Test name
Test status
Simulation time 133909942 ps
CPU time 4.95 seconds
Started Sep 18 08:01:56 AM UTC 24
Finished Sep 18 08:02:02 AM UTC 24
Peak memory 225640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4131492142 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_mode_toggle.4131492142
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/17.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/17.i2c_host_override.3079130585
Short name T651
Test name
Test status
Simulation time 48186457 ps
CPU time 1.14 seconds
Started Sep 18 08:01:35 AM UTC 24
Finished Sep 18 08:01:37 AM UTC 24
Peak memory 214112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3079130585 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.i2c_host_override.3079130585
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/17.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/17.i2c_host_perf.487145516
Short name T1068
Test name
Test status
Simulation time 51312778623 ps
CPU time 449.7 seconds
Started Sep 18 08:01:39 AM UTC 24
Finished Sep 18 08:09:14 AM UTC 24
Peak memory 225640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=487145516 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 17.i2c_host_perf.487145516
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/17.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/17.i2c_host_perf_precise.653635195
Short name T658
Test name
Test status
Simulation time 71492480 ps
CPU time 3.14 seconds
Started Sep 18 08:01:40 AM UTC 24
Finished Sep 18 08:01:44 AM UTC 24
Peak memory 225636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=653635195 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_perf_precise.653635195
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/17.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/17.i2c_host_smoke.2696381971
Short name T665
Test name
Test status
Simulation time 4945927788 ps
CPU time 25.69 seconds
Started Sep 18 08:01:34 AM UTC 24
Finished Sep 18 08:02:01 AM UTC 24
Peak memory 330660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2696381971 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 17.i2c_host_smoke.2696381971
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/17.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/17.i2c_host_stress_all.3407960903
Short name T840
Test name
Test status
Simulation time 12489787693 ps
CPU time 210.14 seconds
Started Sep 18 08:01:44 AM UTC 24
Finished Sep 18 08:05:17 AM UTC 24
Peak memory 1106784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3407960903 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 17.i2c_host_stress_all.3407960903
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/17.i2c_host_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/17.i2c_host_stretch_timeout.3533791466
Short name T138
Test name
Test status
Simulation time 755205118 ps
CPU time 13.97 seconds
Started Sep 18 08:01:40 AM UTC 24
Finished Sep 18 08:01:55 AM UTC 24
Peak memory 232204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3533791466 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_stretch_timeout.3533791466
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/17.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/17.i2c_target_bad_addr.1663379039
Short name T672
Test name
Test status
Simulation time 3226734637 ps
CPU time 8.17 seconds
Started Sep 18 08:01:55 AM UTC 24
Finished Sep 18 08:02:04 AM UTC 24
Peak memory 229800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=1663379039 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_bad_ad
dr.1663379039
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/17.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/17.i2c_target_fifo_reset_acq.3672154045
Short name T164
Test name
Test status
Simulation time 740284461 ps
CPU time 1.81 seconds
Started Sep 18 08:01:51 AM UTC 24
Finished Sep 18 08:01:54 AM UTC 24
Peak memory 214784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3672154
045 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_fifo_reset_acq.3672154045
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/17.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/17.i2c_target_fifo_reset_tx.3832275799
Short name T140
Test name
Test status
Simulation time 250649940 ps
CPU time 2.52 seconds
Started Sep 18 08:01:53 AM UTC 24
Finished Sep 18 08:01:56 AM UTC 24
Peak memory 217356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3832275
799 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_fifo_reset_tx.3832275799
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/17.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/17.i2c_target_fifo_watermarks_acq.3028710613
Short name T668
Test name
Test status
Simulation time 538238560 ps
CPU time 3.71 seconds
Started Sep 18 08:01:57 AM UTC 24
Finished Sep 18 08:02:02 AM UTC 24
Peak memory 215520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3028710
613 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_fifo_watermar
ks_acq.3028710613
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/17.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/17.i2c_target_fifo_watermarks_tx.3104122166
Short name T666
Test name
Test status
Simulation time 539387817 ps
CPU time 2.2 seconds
Started Sep 18 08:01:58 AM UTC 24
Finished Sep 18 08:02:01 AM UTC 24
Peak memory 215244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3104122
166 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_fifo_watermark
s_tx.3104122166
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/17.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/17.i2c_target_hrst.1205752084
Short name T144
Test name
Test status
Simulation time 378463911 ps
CPU time 4.01 seconds
Started Sep 18 08:01:55 AM UTC 24
Finished Sep 18 08:02:00 AM UTC 24
Peak memory 225556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1205752
084 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_hrst.1205752084
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/17.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/17.i2c_target_intr_smoke.2613724011
Short name T137
Test name
Test status
Simulation time 1498145991 ps
CPU time 6.42 seconds
Started Sep 18 08:01:46 AM UTC 24
Finished Sep 18 08:01:54 AM UTC 24
Peak memory 225580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=261372
4011 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_intr_smoke.2613724011
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/17.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/17.i2c_target_intr_stress_wr.1889013314
Short name T693
Test name
Test status
Simulation time 27458252861 ps
CPU time 37.47 seconds
Started Sep 18 08:01:46 AM UTC 24
Finished Sep 18 08:02:25 AM UTC 24
Peak memory 828388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1889013314 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_intr_stres
s_wr.1889013314
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/17.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/17.i2c_target_nack_acqfull.2915660387
Short name T676
Test name
Test status
Simulation time 1897927818 ps
CPU time 4.72 seconds
Started Sep 18 08:02:00 AM UTC 24
Finished Sep 18 08:02:06 AM UTC 24
Peak memory 225484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2915660
387 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_nack_acqfull.2915660387
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/17.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/17.i2c_target_nack_acqfull_addr.2920318751
Short name T673
Test name
Test status
Simulation time 492961220 ps
CPU time 3.27 seconds
Started Sep 18 08:02:00 AM UTC 24
Finished Sep 18 08:02:04 AM UTC 24
Peak memory 215260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2920318
751 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_nack_acqfull_ad
dr.2920318751
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/17.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/17.i2c_target_perf.2006000615
Short name T669
Test name
Test status
Simulation time 1055888724 ps
CPU time 9.28 seconds
Started Sep 18 08:01:53 AM UTC 24
Finished Sep 18 08:02:03 AM UTC 24
Peak memory 234288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2006000
615 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_perf.2006000615
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/17.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/17.i2c_target_smbus_maxlen.1701413096
Short name T671
Test name
Test status
Simulation time 1432096958 ps
CPU time 3.55 seconds
Started Sep 18 08:01:59 AM UTC 24
Finished Sep 18 08:02:04 AM UTC 24
Peak memory 215096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1701413
096 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_smbus_maxlen.1701413096
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/17.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/17.i2c_target_smoke.2248845955
Short name T139
Test name
Test status
Simulation time 648711507 ps
CPU time 10.06 seconds
Started Sep 18 08:01:44 AM UTC 24
Finished Sep 18 08:01:55 AM UTC 24
Peak memory 225504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2248845955 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_smoke.2248845955
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/17.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/17.i2c_target_stress_all.2176817698
Short name T713
Test name
Test status
Simulation time 72874167553 ps
CPU time 44 seconds
Started Sep 18 08:01:53 AM UTC 24
Finished Sep 18 08:02:38 AM UTC 24
Peak memory 537444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=217681
7698 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_stress_all.2176817698
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/17.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/17.i2c_target_stress_rd.3612897622
Short name T675
Test name
Test status
Simulation time 854838756 ps
CPU time 19.35 seconds
Started Sep 18 08:01:45 AM UTC 24
Finished Sep 18 08:02:06 AM UTC 24
Peak memory 232100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3612897622 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_stress_rd.3612897622
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/17.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/17.i2c_target_stress_wr.2127230546
Short name T836
Test name
Test status
Simulation time 34094673681 ps
CPU time 207.08 seconds
Started Sep 18 08:01:45 AM UTC 24
Finished Sep 18 08:05:15 AM UTC 24
Peak memory 3533792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2127230546 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_stress_wr.2127230546
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/17.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/17.i2c_target_stretch.9418539
Short name T681
Test name
Test status
Simulation time 5708561275 ps
CPU time 23.58 seconds
Started Sep 18 08:01:45 AM UTC 24
Finished Sep 18 08:02:10 AM UTC 24
Peak memory 533404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9418539 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_stretch.9418539
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/17.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/17.i2c_target_timeout.333245260
Short name T141
Test name
Test status
Simulation time 1145829756 ps
CPU time 9.66 seconds
Started Sep 18 08:01:46 AM UTC 24
Finished Sep 18 08:01:57 AM UTC 24
Peak memory 225624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3332452
60 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_timeout.333245260
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/17.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/17.i2c_target_tx_stretch_ctrl.4141511494
Short name T667
Test name
Test status
Simulation time 130832460 ps
CPU time 2.37 seconds
Started Sep 18 08:01:58 AM UTC 24
Finished Sep 18 08:02:01 AM UTC 24
Peak memory 225568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4141511
494 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_tx_stretch_ctrl.4141511494
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/17.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/18.i2c_alert_test.3194135791
Short name T702
Test name
Test status
Simulation time 43640901 ps
CPU time 0.98 seconds
Started Sep 18 08:02:27 AM UTC 24
Finished Sep 18 08:02:29 AM UTC 24
Peak memory 214900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3194135791 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_alert_test.3194135791
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/18.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/18.i2c_host_error_intr.2346242107
Short name T682
Test name
Test status
Simulation time 170652087 ps
CPU time 4.06 seconds
Started Sep 18 08:02:05 AM UTC 24
Finished Sep 18 08:02:10 AM UTC 24
Peak memory 242476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2346242107 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 18.i2c_host_error_intr.2346242107
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/18.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/18.i2c_host_fifo_fmt_empty.3487756572
Short name T688
Test name
Test status
Simulation time 620058522 ps
CPU time 13.64 seconds
Started Sep 18 08:02:04 AM UTC 24
Finished Sep 18 08:02:18 AM UTC 24
Peak memory 273244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3487756572 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_fmt_empty.3487756572
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/18.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/18.i2c_host_fifo_full.130471172
Short name T917
Test name
Test status
Simulation time 15541838453 ps
CPU time 263.54 seconds
Started Sep 18 08:02:05 AM UTC 24
Finished Sep 18 08:06:32 AM UTC 24
Peak memory 944992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=130471172 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_full.130471172
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/18.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/18.i2c_host_fifo_overflow.2926384643
Short name T768
Test name
Test status
Simulation time 2821700706 ps
CPU time 102.37 seconds
Started Sep 18 08:02:03 AM UTC 24
Finished Sep 18 08:03:47 AM UTC 24
Peak memory 861156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2926384643 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_overflow.2926384643
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/18.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/18.i2c_host_fifo_reset_fmt.914146747
Short name T677
Test name
Test status
Simulation time 136111352 ps
CPU time 1.62 seconds
Started Sep 18 08:02:04 AM UTC 24
Finished Sep 18 08:02:06 AM UTC 24
Peak memory 214904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=914146747 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_fmt.914146747
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/18.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/18.i2c_host_fifo_reset_rx.3632618149
Short name T680
Test name
Test status
Simulation time 158592084 ps
CPU time 4.77 seconds
Started Sep 18 08:02:04 AM UTC 24
Finished Sep 18 08:02:09 AM UTC 24
Peak memory 244448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3632618149 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_rx.3632618149
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/18.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/18.i2c_host_fifo_watermark.1946014185
Short name T819
Test name
Test status
Simulation time 19631702214 ps
CPU time 162.91 seconds
Started Sep 18 08:02:03 AM UTC 24
Finished Sep 18 08:04:48 AM UTC 24
Peak memory 1508036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1946014185 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_watermark.1946014185
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/18.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/18.i2c_host_may_nack.3033589087
Short name T694
Test name
Test status
Simulation time 1622470148 ps
CPU time 4.55 seconds
Started Sep 18 08:02:19 AM UTC 24
Finished Sep 18 08:02:25 AM UTC 24
Peak memory 215196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3033589087 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.i2c_host_may_nack.3033589087
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/18.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/18.i2c_host_mode_toggle.3567867677
Short name T690
Test name
Test status
Simulation time 84116342 ps
CPU time 2.04 seconds
Started Sep 18 08:02:18 AM UTC 24
Finished Sep 18 08:02:22 AM UTC 24
Peak memory 225656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3567867677 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_mode_toggle.3567867677
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/18.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/18.i2c_host_override.2771340675
Short name T151
Test name
Test status
Simulation time 31628816 ps
CPU time 0.95 seconds
Started Sep 18 08:02:02 AM UTC 24
Finished Sep 18 08:02:04 AM UTC 24
Peak memory 214916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2771340675 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.i2c_host_override.2771340675
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/18.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/18.i2c_host_perf.1235984694
Short name T1750
Test name
Test status
Simulation time 26423932371 ps
CPU time 2219.35 seconds
Started Sep 18 08:02:05 AM UTC 24
Finished Sep 18 08:39:26 AM UTC 24
Peak memory 3802020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1235984694 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 18.i2c_host_perf.1235984694
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/18.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/18.i2c_host_perf_precise.998238489
Short name T683
Test name
Test status
Simulation time 337108714 ps
CPU time 4.53 seconds
Started Sep 18 08:02:05 AM UTC 24
Finished Sep 18 08:02:10 AM UTC 24
Peak memory 215252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=998238489 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_perf_precise.998238489
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/18.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/18.i2c_host_smoke.2927039283
Short name T716
Test name
Test status
Simulation time 6466765776 ps
CPU time 40.58 seconds
Started Sep 18 08:02:02 AM UTC 24
Finished Sep 18 08:02:44 AM UTC 24
Peak memory 443172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2927039283 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.i2c_host_smoke.2927039283
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/18.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/18.i2c_host_stretch_timeout.209877415
Short name T714
Test name
Test status
Simulation time 774374392 ps
CPU time 33.11 seconds
Started Sep 18 08:02:05 AM UTC 24
Finished Sep 18 08:02:39 AM UTC 24
Peak memory 225512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=209877415 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_stretch_timeout.209877415
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/18.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/18.i2c_target_bad_addr.1385253668
Short name T698
Test name
Test status
Simulation time 1122051499 ps
CPU time 8.48 seconds
Started Sep 18 08:02:16 AM UTC 24
Finished Sep 18 08:02:26 AM UTC 24
Peak memory 225756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=1385253668 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_bad_ad
dr.1385253668
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/18.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/18.i2c_target_fifo_reset_acq.4051395142
Short name T686
Test name
Test status
Simulation time 656414422 ps
CPU time 2.17 seconds
Started Sep 18 08:02:12 AM UTC 24
Finished Sep 18 08:02:15 AM UTC 24
Peak memory 215040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4051395
142 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_fifo_reset_acq.4051395142
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/18.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/18.i2c_target_fifo_reset_tx.2277693299
Short name T687
Test name
Test status
Simulation time 187042397 ps
CPU time 2.08 seconds
Started Sep 18 08:02:14 AM UTC 24
Finished Sep 18 08:02:17 AM UTC 24
Peak memory 215236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2277693
299 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_fifo_reset_tx.2277693299
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/18.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/18.i2c_target_fifo_watermarks_acq.2864666954
Short name T697
Test name
Test status
Simulation time 1668825067 ps
CPU time 3.67 seconds
Started Sep 18 08:02:21 AM UTC 24
Finished Sep 18 08:02:26 AM UTC 24
Peak memory 215384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2864666
954 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_fifo_watermar
ks_acq.2864666954
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/18.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/18.i2c_target_fifo_watermarks_tx.1243460965
Short name T695
Test name
Test status
Simulation time 575972703 ps
CPU time 1.87 seconds
Started Sep 18 08:02:22 AM UTC 24
Finished Sep 18 08:02:25 AM UTC 24
Peak memory 215032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1243460
965 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_fifo_watermark
s_tx.1243460965
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/18.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/18.i2c_target_hrst.497940849
Short name T691
Test name
Test status
Simulation time 3892106676 ps
CPU time 3.26 seconds
Started Sep 18 08:02:17 AM UTC 24
Finished Sep 18 08:02:22 AM UTC 24
Peak memory 229916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4979408
49 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_hrst.497940849
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/18.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/18.i2c_target_intr_smoke.511145785
Short name T689
Test name
Test status
Simulation time 4805925537 ps
CPU time 11.44 seconds
Started Sep 18 08:02:08 AM UTC 24
Finished Sep 18 08:02:21 AM UTC 24
Peak memory 227864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=511145
785 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_intr_smoke.511145785
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/18.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/18.i2c_target_intr_stress_wr.3123386147
Short name T221
Test name
Test status
Simulation time 5104325365 ps
CPU time 4.42 seconds
Started Sep 18 08:02:10 AM UTC 24
Finished Sep 18 08:02:16 AM UTC 24
Peak memory 215440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3123386147 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_intr_stres
s_wr.3123386147
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/18.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/18.i2c_target_nack_acqfull.1275928431
Short name T705
Test name
Test status
Simulation time 466182691 ps
CPU time 3.7 seconds
Started Sep 18 08:02:25 AM UTC 24
Finished Sep 18 08:02:30 AM UTC 24
Peak memory 225632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1275928
431 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_nack_acqfull.1275928431
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/18.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/18.i2c_target_nack_acqfull_addr.3327709101
Short name T707
Test name
Test status
Simulation time 2235740415 ps
CPU time 4.88 seconds
Started Sep 18 08:02:26 AM UTC 24
Finished Sep 18 08:02:32 AM UTC 24
Peak memory 215400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3327709
101 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_nack_acqfull_ad
dr.3327709101
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/18.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/18.i2c_target_nack_txstretch.999075221
Short name T704
Test name
Test status
Simulation time 147754682 ps
CPU time 2.48 seconds
Started Sep 18 08:02:27 AM UTC 24
Finished Sep 18 08:02:30 AM UTC 24
Peak memory 232228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9990752
21 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_nack_txstretch.999075221
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/18.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/18.i2c_target_perf.3934102277
Short name T692
Test name
Test status
Simulation time 726104588 ps
CPU time 7.97 seconds
Started Sep 18 08:02:15 AM UTC 24
Finished Sep 18 08:02:24 AM UTC 24
Peak memory 232216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3934102
277 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_perf.3934102277
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/18.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/18.i2c_target_smbus_maxlen.2379760005
Short name T701
Test name
Test status
Simulation time 433165966 ps
CPU time 3.12 seconds
Started Sep 18 08:02:24 AM UTC 24
Finished Sep 18 08:02:28 AM UTC 24
Peak memory 215096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2379760
005 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_smbus_maxlen.2379760005
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/18.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/18.i2c_target_smoke.1304270221
Short name T712
Test name
Test status
Simulation time 5248549493 ps
CPU time 30.2 seconds
Started Sep 18 08:02:06 AM UTC 24
Finished Sep 18 08:02:38 AM UTC 24
Peak memory 225616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1304270221 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_smoke.1304270221
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/18.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/18.i2c_target_stress_all.3087959272
Short name T292
Test name
Test status
Simulation time 81086042005 ps
CPU time 166.41 seconds
Started Sep 18 08:02:15 AM UTC 24
Finished Sep 18 08:05:04 AM UTC 24
Peak memory 1762076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=308795
9272 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_stress_all.3087959272
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/18.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/18.i2c_target_stress_rd.2055289734
Short name T739
Test name
Test status
Simulation time 3063430069 ps
CPU time 56.19 seconds
Started Sep 18 08:02:07 AM UTC 24
Finished Sep 18 08:03:05 AM UTC 24
Peak memory 227460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2055289734 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_stress_rd.2055289734
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/18.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/18.i2c_target_stress_wr.2815407714
Short name T1280
Test name
Test status
Simulation time 48075274140 ps
CPU time 672.18 seconds
Started Sep 18 08:02:07 AM UTC 24
Finished Sep 18 08:13:26 AM UTC 24
Peak memory 7418776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2815407714 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_stress_wr.2815407714
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/18.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/18.i2c_target_stretch.1250223293
Short name T685
Test name
Test status
Simulation time 1429044719 ps
CPU time 5.29 seconds
Started Sep 18 08:02:07 AM UTC 24
Finished Sep 18 08:02:14 AM UTC 24
Peak memory 274960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1250223293 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_stretch.1250223293
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/18.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/18.i2c_target_timeout.3543851949
Short name T696
Test name
Test status
Simulation time 1486901467 ps
CPU time 13.68 seconds
Started Sep 18 08:02:10 AM UTC 24
Finished Sep 18 08:02:25 AM UTC 24
Peak memory 232160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3543851
949 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_timeout.3543851949
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/18.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/18.i2c_target_tx_stretch_ctrl.2996400588
Short name T700
Test name
Test status
Simulation time 107335267 ps
CPU time 3.69 seconds
Started Sep 18 08:02:23 AM UTC 24
Finished Sep 18 08:02:28 AM UTC 24
Peak memory 215324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2996400
588 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_tx_stretch_ctrl.2996400588
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/18.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/19.i2c_alert_test.3092225364
Short name T727
Test name
Test status
Simulation time 18293621 ps
CPU time 0.92 seconds
Started Sep 18 08:02:58 AM UTC 24
Finished Sep 18 08:03:00 AM UTC 24
Peak memory 214900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3092225364 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_alert_test.3092225364
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/19.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/19.i2c_host_error_intr.427628641
Short name T711
Test name
Test status
Simulation time 175066595 ps
CPU time 2.2 seconds
Started Sep 18 08:02:33 AM UTC 24
Finished Sep 18 08:02:37 AM UTC 24
Peak memory 215344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=427628641 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 19.i2c_host_error_intr.427628641
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/19.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/19.i2c_host_fifo_fmt_empty.654131608
Short name T709
Test name
Test status
Simulation time 411926805 ps
CPU time 5.76 seconds
Started Sep 18 08:02:29 AM UTC 24
Finished Sep 18 08:02:36 AM UTC 24
Peak memory 256672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=654131608 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_fmt_empty.654131608
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/19.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/19.i2c_host_fifo_full.2779557613
Short name T821
Test name
Test status
Simulation time 19651360329 ps
CPU time 138.76 seconds
Started Sep 18 08:02:31 AM UTC 24
Finished Sep 18 08:04:53 AM UTC 24
Peak memory 586548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2779557613 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_full.2779557613
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/19.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/19.i2c_host_fifo_overflow.4095405554
Short name T787
Test name
Test status
Simulation time 6016216963 ps
CPU time 102.66 seconds
Started Sep 18 08:02:29 AM UTC 24
Finished Sep 18 08:04:14 AM UTC 24
Peak memory 543536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4095405554 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_overflow.4095405554
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/19.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/19.i2c_host_fifo_reset_fmt.4048112092
Short name T706
Test name
Test status
Simulation time 82254954 ps
CPU time 1.67 seconds
Started Sep 18 08:02:29 AM UTC 24
Finished Sep 18 08:02:32 AM UTC 24
Peak memory 214900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4048112092 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_fmt.4048112092
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/19.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/19.i2c_host_fifo_reset_rx.2719537504
Short name T710
Test name
Test status
Simulation time 168545261 ps
CPU time 4.95 seconds
Started Sep 18 08:02:30 AM UTC 24
Finished Sep 18 08:02:36 AM UTC 24
Peak memory 215388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2719537504 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_rx.2719537504
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/19.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/19.i2c_host_fifo_watermark.2760788269
Short name T124
Test name
Test status
Simulation time 10737376372 ps
CPU time 59.12 seconds
Started Sep 18 08:02:28 AM UTC 24
Finished Sep 18 08:03:28 AM UTC 24
Peak memory 1039264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2760788269 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_watermark.2760788269
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/19.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/19.i2c_host_may_nack.3772117705
Short name T256
Test name
Test status
Simulation time 711626893 ps
CPU time 25.26 seconds
Started Sep 18 08:02:49 AM UTC 24
Finished Sep 18 08:03:16 AM UTC 24
Peak memory 215268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3772117705 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.i2c_host_may_nack.3772117705
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/19.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/19.i2c_host_mode_toggle.3018403103
Short name T723
Test name
Test status
Simulation time 190739507 ps
CPU time 3.63 seconds
Started Sep 18 08:02:48 AM UTC 24
Finished Sep 18 08:02:53 AM UTC 24
Peak memory 231720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3018403103 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_mode_toggle.3018403103
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/19.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/19.i2c_host_override.3171319837
Short name T703
Test name
Test status
Simulation time 89222143 ps
CPU time 1.01 seconds
Started Sep 18 08:02:28 AM UTC 24
Finished Sep 18 08:02:30 AM UTC 24
Peak memory 214916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3171319837 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.i2c_host_override.3171319837
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/19.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/19.i2c_host_perf.1531151999
Short name T1468
Test name
Test status
Simulation time 19027797776 ps
CPU time 832.93 seconds
Started Sep 18 08:02:31 AM UTC 24
Finished Sep 18 08:16:34 AM UTC 24
Peak memory 1639272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1531151999 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 19.i2c_host_perf.1531151999
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/19.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/19.i2c_host_perf_precise.1006576677
Short name T708
Test name
Test status
Simulation time 140078426 ps
CPU time 2.57 seconds
Started Sep 18 08:02:31 AM UTC 24
Finished Sep 18 08:02:35 AM UTC 24
Peak memory 229468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1006576677 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_perf_precise.1006576677
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/19.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/19.i2c_host_smoke.1421744152
Short name T773
Test name
Test status
Simulation time 18215803437 ps
CPU time 84.83 seconds
Started Sep 18 08:02:27 AM UTC 24
Finished Sep 18 08:03:54 AM UTC 24
Peak memory 365476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1421744152 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.i2c_host_smoke.1421744152
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/19.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/19.i2c_host_stretch_timeout.3798550172
Short name T721
Test name
Test status
Simulation time 530472305 ps
CPU time 13.98 seconds
Started Sep 18 08:02:32 AM UTC 24
Finished Sep 18 08:02:48 AM UTC 24
Peak memory 231772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3798550172 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_stretch_timeout.3798550172
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/19.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/19.i2c_target_bad_addr.3615846330
Short name T729
Test name
Test status
Simulation time 3211369689 ps
CPU time 6.93 seconds
Started Sep 18 08:02:48 AM UTC 24
Finished Sep 18 08:02:56 AM UTC 24
Peak memory 217572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=3615846330 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_bad_ad
dr.3615846330
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/19.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/19.i2c_target_fifo_reset_acq.3924706071
Short name T719
Test name
Test status
Simulation time 280699767 ps
CPU time 1.45 seconds
Started Sep 18 08:02:45 AM UTC 24
Finished Sep 18 08:02:47 AM UTC 24
Peak memory 214784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3924706
071 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_fifo_reset_acq.3924706071
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/19.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/19.i2c_target_fifo_reset_tx.526161075
Short name T717
Test name
Test status
Simulation time 223818139 ps
CPU time 1.28 seconds
Started Sep 18 08:02:45 AM UTC 24
Finished Sep 18 08:02:47 AM UTC 24
Peak memory 214844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5261610
75 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_fifo_reset_tx.526161075
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/19.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/19.i2c_target_fifo_watermarks_acq.3655423973
Short name T730
Test name
Test status
Simulation time 1053869852 ps
CPU time 4.81 seconds
Started Sep 18 08:02:52 AM UTC 24
Finished Sep 18 08:02:58 AM UTC 24
Peak memory 215368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3655423
973 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_fifo_watermar
ks_acq.3655423973
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/19.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/19.i2c_target_fifo_watermarks_tx.4089942381
Short name T728
Test name
Test status
Simulation time 135477803 ps
CPU time 1.62 seconds
Started Sep 18 08:02:53 AM UTC 24
Finished Sep 18 08:02:56 AM UTC 24
Peak memory 215032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4089942
381 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_fifo_watermark
s_tx.4089942381
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/19.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/19.i2c_target_hrst.2491762261
Short name T724
Test name
Test status
Simulation time 359700740 ps
CPU time 4.7 seconds
Started Sep 18 08:02:48 AM UTC 24
Finished Sep 18 08:02:54 AM UTC 24
Peak memory 225496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2491762
261 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_hrst.2491762261
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/19.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/19.i2c_target_intr_smoke.3555009247
Short name T718
Test name
Test status
Simulation time 3035819087 ps
CPU time 7.44 seconds
Started Sep 18 08:02:39 AM UTC 24
Finished Sep 18 08:02:47 AM UTC 24
Peak memory 225556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=355500
9247 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_intr_smoke.3555009247
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/19.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/19.i2c_target_intr_stress_wr.3342748879
Short name T906
Test name
Test status
Simulation time 17737021635 ps
CPU time 220.64 seconds
Started Sep 18 08:02:39 AM UTC 24
Finished Sep 18 08:06:22 AM UTC 24
Peak memory 2730780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3342748879 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_intr_stres
s_wr.3342748879
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/19.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/19.i2c_target_nack_acqfull.3867352773
Short name T734
Test name
Test status
Simulation time 1655865760 ps
CPU time 3.2 seconds
Started Sep 18 08:02:57 AM UTC 24
Finished Sep 18 08:03:01 AM UTC 24
Peak memory 225624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3867352
773 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_nack_acqfull.3867352773
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/19.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/19.i2c_target_nack_acqfull_addr.801518358
Short name T736
Test name
Test status
Simulation time 582367375 ps
CPU time 5.1 seconds
Started Sep 18 08:02:57 AM UTC 24
Finished Sep 18 08:03:03 AM UTC 24
Peak memory 215264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8015183
58 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_nack_acqfull_addr.801518358
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/19.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/19.i2c_target_nack_txstretch.1900018307
Short name T731
Test name
Test status
Simulation time 190405616 ps
CPU time 2.3 seconds
Started Sep 18 08:02:57 AM UTC 24
Finished Sep 18 08:03:00 AM UTC 24
Peak memory 232356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1900018
307 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_nack_txstretch.1900018307
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/19.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/19.i2c_target_perf.3293445864
Short name T725
Test name
Test status
Simulation time 558758396 ps
CPU time 6.48 seconds
Started Sep 18 08:02:48 AM UTC 24
Finished Sep 18 08:02:55 AM UTC 24
Peak memory 225508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3293445
864 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_perf.3293445864
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/19.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/19.i2c_target_smbus_maxlen.3663082010
Short name T733
Test name
Test status
Simulation time 887729188 ps
CPU time 2.92 seconds
Started Sep 18 08:02:57 AM UTC 24
Finished Sep 18 08:03:00 AM UTC 24
Peak memory 215220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3663082
010 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_smbus_maxlen.3663082010
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/19.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/19.i2c_target_smoke.2319382228
Short name T740
Test name
Test status
Simulation time 1428483159 ps
CPU time 27.8 seconds
Started Sep 18 08:02:36 AM UTC 24
Finished Sep 18 08:03:06 AM UTC 24
Peak memory 225696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2319382228 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_smoke.2319382228
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/19.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/19.i2c_target_stress_all.306170089
Short name T842
Test name
Test status
Simulation time 48672883116 ps
CPU time 147.96 seconds
Started Sep 18 08:02:48 AM UTC 24
Finished Sep 18 08:05:19 AM UTC 24
Peak memory 1035044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=306170
089 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_stress_all.306170089
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/19.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/19.i2c_target_stress_rd.132093180
Short name T735
Test name
Test status
Simulation time 685992327 ps
CPU time 23.91 seconds
Started Sep 18 08:02:36 AM UTC 24
Finished Sep 18 08:03:02 AM UTC 24
Peak memory 225564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=132093180 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_stress_rd.132093180
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/19.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/19.i2c_target_stress_wr.42959561
Short name T1747
Test name
Test status
Simulation time 70462859483 ps
CPU time 1557.74 seconds
Started Sep 18 08:02:36 AM UTC 24
Finished Sep 18 08:28:48 AM UTC 24
Peak memory 12563228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=42959561 -assert nopostpro
c +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_stress_wr.42959561
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/19.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/19.i2c_target_stretch.3136150257
Short name T722
Test name
Test status
Simulation time 2122541344 ps
CPU time 12.84 seconds
Started Sep 18 08:02:38 AM UTC 24
Finished Sep 18 08:02:52 AM UTC 24
Peak memory 695212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3136150257 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_stretch.3136150257
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/19.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/19.i2c_target_timeout.2174035843
Short name T720
Test name
Test status
Simulation time 4861834216 ps
CPU time 6.6 seconds
Started Sep 18 08:02:40 AM UTC 24
Finished Sep 18 08:02:47 AM UTC 24
Peak memory 225628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2174035
843 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_timeout.2174035843
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/19.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/2.i2c_alert_test.3107564203
Short name T103
Test name
Test status
Simulation time 17065056 ps
CPU time 0.96 seconds
Started Sep 18 07:55:10 AM UTC 24
Finished Sep 18 07:55:12 AM UTC 24
Peak memory 214840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3107564203 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_alert_test.3107564203
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/2.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/2.i2c_host_error_intr.3097272151
Short name T18
Test name
Test status
Simulation time 313379381 ps
CPU time 6.64 seconds
Started Sep 18 07:54:57 AM UTC 24
Finished Sep 18 07:55:05 AM UTC 24
Peak memory 248632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3097272151 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 2.i2c_host_error_intr.3097272151
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/2.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/2.i2c_host_fifo_full.2481909440
Short name T439
Test name
Test status
Simulation time 9411121651 ps
CPU time 177.89 seconds
Started Sep 18 07:54:55 AM UTC 24
Finished Sep 18 07:57:55 AM UTC 24
Peak memory 326356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2481909440 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_full.2481909440
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/2.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/2.i2c_host_fifo_overflow.815948287
Short name T105
Test name
Test status
Simulation time 11129337618 ps
CPU time 56.1 seconds
Started Sep 18 07:54:52 AM UTC 24
Finished Sep 18 07:55:50 AM UTC 24
Peak memory 656172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=815948287 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_overflow.815948287
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/2.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/2.i2c_host_fifo_reset_fmt.3875062021
Short name T190
Test name
Test status
Simulation time 83021174 ps
CPU time 1.36 seconds
Started Sep 18 07:54:55 AM UTC 24
Finished Sep 18 07:54:57 AM UTC 24
Peak memory 215144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3875062021 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_fmt.3875062021
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/2.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/2.i2c_host_fifo_reset_rx.2516769751
Short name T82
Test name
Test status
Simulation time 554023725 ps
CPU time 4.51 seconds
Started Sep 18 07:54:55 AM UTC 24
Finished Sep 18 07:55:00 AM UTC 24
Peak memory 215324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2516769751 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_rx.2516769751
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/2.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/2.i2c_host_fifo_watermark.575725604
Short name T388
Test name
Test status
Simulation time 20974177650 ps
CPU time 129.18 seconds
Started Sep 18 07:54:52 AM UTC 24
Finished Sep 18 07:57:04 AM UTC 24
Peak memory 1438496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=575725604 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_watermark.575725604
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/2.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/2.i2c_host_may_nack.747601771
Short name T13
Test name
Test status
Simulation time 2030059361 ps
CPU time 3.48 seconds
Started Sep 18 07:55:07 AM UTC 24
Finished Sep 18 07:55:11 AM UTC 24
Peak memory 215264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=747601771 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 2.i2c_host_may_nack.747601771
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/2.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/2.i2c_host_override.879107208
Short name T104
Test name
Test status
Simulation time 35008255 ps
CPU time 0.97 seconds
Started Sep 18 07:54:52 AM UTC 24
Finished Sep 18 07:54:54 AM UTC 24
Peak memory 214080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=879107208 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 2.i2c_host_override.879107208
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/2.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/2.i2c_host_perf.2628472947
Short name T36
Test name
Test status
Simulation time 13033767935 ps
CPU time 356.1 seconds
Started Sep 18 07:54:56 AM UTC 24
Finished Sep 18 08:00:56 AM UTC 24
Peak memory 1792820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2628472947 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 2.i2c_host_perf.2628472947
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/2.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/2.i2c_host_perf_precise.2518977103
Short name T179
Test name
Test status
Simulation time 352303999 ps
CPU time 4.87 seconds
Started Sep 18 07:54:56 AM UTC 24
Finished Sep 18 07:55:02 AM UTC 24
Peak memory 233876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2518977103 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_perf_precise.2518977103
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/2.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/2.i2c_host_smoke.3875895278
Short name T289
Test name
Test status
Simulation time 4426967625 ps
CPU time 22.96 seconds
Started Sep 18 07:54:52 AM UTC 24
Finished Sep 18 07:55:17 AM UTC 24
Peak memory 310208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3875895278 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.i2c_host_smoke.3875895278
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/2.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/2.i2c_host_stress_all.1562351333
Short name T199
Test name
Test status
Simulation time 51202920197 ps
CPU time 444.34 seconds
Started Sep 18 07:54:58 AM UTC 24
Finished Sep 18 08:02:28 AM UTC 24
Peak memory 2519776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1562351333 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 2.i2c_host_stress_all.1562351333
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/2.i2c_host_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/2.i2c_host_stretch_timeout.1152084476
Short name T196
Test name
Test status
Simulation time 7444832685 ps
CPU time 44.38 seconds
Started Sep 18 07:54:57 AM UTC 24
Finished Sep 18 07:55:43 AM UTC 24
Peak memory 225816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1152084476 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_stretch_timeout.1152084476
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/2.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/2.i2c_sec_cm.3943776509
Short name T201
Test name
Test status
Simulation time 130265759 ps
CPU time 1.44 seconds
Started Sep 18 07:55:10 AM UTC 24
Finished Sep 18 07:55:13 AM UTC 24
Peak memory 244508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3943776509 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_sec_cm.3943776509
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/2.i2c_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/2.i2c_target_bad_addr.3288702271
Short name T65
Test name
Test status
Simulation time 605328918 ps
CPU time 3.33 seconds
Started Sep 18 07:55:06 AM UTC 24
Finished Sep 18 07:55:10 AM UTC 24
Peak memory 225572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=3288702271 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_bad_addr.3288702271
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/2.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/2.i2c_target_fifo_reset_acq.4010968779
Short name T304
Test name
Test status
Simulation time 121278736 ps
CPU time 1.49 seconds
Started Sep 18 07:55:03 AM UTC 24
Finished Sep 18 07:55:06 AM UTC 24
Peak memory 214784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4010968
779 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_fifo_reset_acq.4010968779
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/2.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/2.i2c_target_fifo_reset_tx.2720646187
Short name T306
Test name
Test status
Simulation time 210166990 ps
CPU time 2.22 seconds
Started Sep 18 07:55:03 AM UTC 24
Finished Sep 18 07:55:07 AM UTC 24
Peak memory 215456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2720646
187 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_fifo_reset_tx.2720646187
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/2.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/2.i2c_target_fifo_watermarks_acq.171977732
Short name T272
Test name
Test status
Simulation time 2286204762 ps
CPU time 4.78 seconds
Started Sep 18 07:55:07 AM UTC 24
Finished Sep 18 07:55:13 AM UTC 24
Peak memory 215460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1719777
32 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_fifo_watermarks
_acq.171977732
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/2.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/2.i2c_target_fifo_watermarks_tx.3177704221
Short name T308
Test name
Test status
Simulation time 1179792401 ps
CPU time 1.6 seconds
Started Sep 18 07:55:08 AM UTC 24
Finished Sep 18 07:55:11 AM UTC 24
Peak memory 215036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3177704
221 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_fifo_watermarks
_tx.3177704221
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/2.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/2.i2c_target_intr_smoke.3544794903
Short name T307
Test name
Test status
Simulation time 1291892245 ps
CPU time 7.76 seconds
Started Sep 18 07:55:00 AM UTC 24
Finished Sep 18 07:55:09 AM UTC 24
Peak memory 225568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=354479
4903 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_intr_smoke.3544794903
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/2.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/2.i2c_target_intr_stress_wr.724356325
Short name T52
Test name
Test status
Simulation time 9686054453 ps
CPU time 17.98 seconds
Started Sep 18 07:55:01 AM UTC 24
Finished Sep 18 07:55:20 AM UTC 24
Peak memory 396128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=724356325 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_intr_stress_wr.724356325
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/2.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/2.i2c_target_nack_acqfull.1950852530
Short name T165
Test name
Test status
Simulation time 4383354275 ps
CPU time 5.32 seconds
Started Sep 18 07:55:09 AM UTC 24
Finished Sep 18 07:55:15 AM UTC 24
Peak memory 225552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1950852
530 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_nack_acqfull.1950852530
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/2.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/2.i2c_target_nack_acqfull_addr.466849356
Short name T66
Test name
Test status
Simulation time 2578663806 ps
CPU time 5.45 seconds
Started Sep 18 07:55:09 AM UTC 24
Finished Sep 18 07:55:16 AM UTC 24
Peak memory 215192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4668493
56 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_nack_acqfull_addr.466849356
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/2.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/2.i2c_target_nack_txstretch.1724151307
Short name T59
Test name
Test status
Simulation time 136022971 ps
CPU time 2.41 seconds
Started Sep 18 07:55:10 AM UTC 24
Finished Sep 18 07:55:14 AM UTC 24
Peak memory 232164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1724151
307 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_nack_txstretch.1724151307
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/2.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/2.i2c_target_perf.995759379
Short name T302
Test name
Test status
Simulation time 1622730839 ps
CPU time 3.05 seconds
Started Sep 18 07:55:05 AM UTC 24
Finished Sep 18 07:55:09 AM UTC 24
Peak memory 225704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9957593
79 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_perf.995759379
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/2.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/2.i2c_target_smbus_maxlen.4176003265
Short name T309
Test name
Test status
Simulation time 2011595014 ps
CPU time 2.5 seconds
Started Sep 18 07:55:09 AM UTC 24
Finished Sep 18 07:55:13 AM UTC 24
Peak memory 215224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4176003
265 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_smbus_maxlen.4176003265
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/2.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/2.i2c_target_smoke.1218623069
Short name T315
Test name
Test status
Simulation time 732085628 ps
CPU time 24.57 seconds
Started Sep 18 07:54:58 AM UTC 24
Finished Sep 18 07:55:24 AM UTC 24
Peak memory 217380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1218623069 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_smoke.1218623069
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/2.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/2.i2c_target_stress_rd.1594545068
Short name T305
Test name
Test status
Simulation time 400023023 ps
CPU time 6.32 seconds
Started Sep 18 07:54:59 AM UTC 24
Finished Sep 18 07:55:06 AM UTC 24
Peak memory 215380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1594545068 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_stress_rd.1594545068
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/2.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/2.i2c_target_stress_wr.3715542541
Short name T300
Test name
Test status
Simulation time 16145434806 ps
CPU time 3.71 seconds
Started Sep 18 07:54:58 AM UTC 24
Finished Sep 18 07:55:03 AM UTC 24
Peak memory 217340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3715542541 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_stress_wr.3715542541
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/2.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/2.i2c_target_stretch.2630069140
Short name T399
Test name
Test status
Simulation time 4415112512 ps
CPU time 134.88 seconds
Started Sep 18 07:55:00 AM UTC 24
Finished Sep 18 07:57:17 AM UTC 24
Peak memory 986020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2630069140 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_stretch.2630069140
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/2.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/2.i2c_target_timeout.758132703
Short name T69
Test name
Test status
Simulation time 6200694506 ps
CPU time 11.2 seconds
Started Sep 18 07:55:01 AM UTC 24
Finished Sep 18 07:55:14 AM UTC 24
Peak memory 231772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7581327
03 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_timeout.758132703
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/2.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/2.i2c_target_tx_stretch_ctrl.3314298288
Short name T294
Test name
Test status
Simulation time 75715758 ps
CPU time 2.84 seconds
Started Sep 18 07:55:08 AM UTC 24
Finished Sep 18 07:55:12 AM UTC 24
Peak memory 215316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3314298
288 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_tx_stretch_ctrl.3314298288
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/2.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/20.i2c_alert_test.869546913
Short name T765
Test name
Test status
Simulation time 40812093 ps
CPU time 0.95 seconds
Started Sep 18 08:03:41 AM UTC 24
Finished Sep 18 08:03:43 AM UTC 24
Peak memory 214608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=869546913 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_alert_test.869546913
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/20.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/20.i2c_host_error_intr.3401724034
Short name T741
Test name
Test status
Simulation time 78550530 ps
CPU time 1.75 seconds
Started Sep 18 08:03:06 AM UTC 24
Finished Sep 18 08:03:08 AM UTC 24
Peak memory 224728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3401724034 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 20.i2c_host_error_intr.3401724034
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/20.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/20.i2c_host_fifo_fmt_empty.3889101978
Short name T743
Test name
Test status
Simulation time 1136083101 ps
CPU time 6.34 seconds
Started Sep 18 08:03:02 AM UTC 24
Finished Sep 18 08:03:10 AM UTC 24
Peak memory 277140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3889101978 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_fmt_empty.3889101978
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/20.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/20.i2c_host_fifo_full.991056801
Short name T784
Test name
Test status
Simulation time 1951182022 ps
CPU time 63.38 seconds
Started Sep 18 08:03:02 AM UTC 24
Finished Sep 18 08:04:07 AM UTC 24
Peak memory 439012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=991056801 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_full.991056801
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/20.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/20.i2c_host_fifo_overflow.208124515
Short name T808
Test name
Test status
Simulation time 15768899849 ps
CPU time 85.7 seconds
Started Sep 18 08:03:01 AM UTC 24
Finished Sep 18 08:04:29 AM UTC 24
Peak memory 797532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=208124515 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_overflow.208124515
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/20.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/20.i2c_host_fifo_reset_fmt.148895328
Short name T737
Test name
Test status
Simulation time 1196479248 ps
CPU time 1.61 seconds
Started Sep 18 08:03:01 AM UTC 24
Finished Sep 18 08:03:04 AM UTC 24
Peak memory 214900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=148895328 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_fmt.148895328
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/20.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/20.i2c_host_fifo_reset_rx.1871898034
Short name T744
Test name
Test status
Simulation time 383015710 ps
CPU time 10.06 seconds
Started Sep 18 08:03:02 AM UTC 24
Finished Sep 18 08:03:13 AM UTC 24
Peak memory 250604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1871898034 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_rx.1871898034
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/20.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/20.i2c_host_fifo_watermark.3993529455
Short name T812
Test name
Test status
Simulation time 58927278766 ps
CPU time 94.78 seconds
Started Sep 18 08:03:01 AM UTC 24
Finished Sep 18 08:04:38 AM UTC 24
Peak memory 1086216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3993529455 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_watermark.3993529455
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/20.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/20.i2c_host_may_nack.304686467
Short name T254
Test name
Test status
Simulation time 397799309 ps
CPU time 7.84 seconds
Started Sep 18 08:03:32 AM UTC 24
Finished Sep 18 08:03:41 AM UTC 24
Peak memory 215424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=304686467 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 20.i2c_host_may_nack.304686467
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/20.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/20.i2c_host_override.4094163056
Short name T152
Test name
Test status
Simulation time 51295296 ps
CPU time 1.03 seconds
Started Sep 18 08:03:00 AM UTC 24
Finished Sep 18 08:03:02 AM UTC 24
Peak memory 214108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4094163056 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.i2c_host_override.4094163056
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/20.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/20.i2c_host_perf.3603058982
Short name T772
Test name
Test status
Simulation time 12763462010 ps
CPU time 46.74 seconds
Started Sep 18 08:03:03 AM UTC 24
Finished Sep 18 08:03:52 AM UTC 24
Peak memory 543592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3603058982 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 20.i2c_host_perf.3603058982
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/20.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/20.i2c_host_perf_precise.3092740608
Short name T742
Test name
Test status
Simulation time 216493588 ps
CPU time 3.82 seconds
Started Sep 18 08:03:04 AM UTC 24
Finished Sep 18 08:03:09 AM UTC 24
Peak memory 215380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3092740608 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_perf_precise.3092740608
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/20.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/20.i2c_host_smoke.3910226384
Short name T754
Test name
Test status
Simulation time 1467319786 ps
CPU time 31.13 seconds
Started Sep 18 08:02:59 AM UTC 24
Finished Sep 18 08:03:31 AM UTC 24
Peak memory 346860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3910226384 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 20.i2c_host_smoke.3910226384
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/20.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/20.i2c_host_stretch_timeout.791694260
Short name T746
Test name
Test status
Simulation time 1529676218 ps
CPU time 18.05 seconds
Started Sep 18 08:03:06 AM UTC 24
Finished Sep 18 08:03:25 AM UTC 24
Peak memory 232284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=791694260 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_stretch_timeout.791694260
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/20.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/20.i2c_target_bad_addr.3316054034
Short name T760
Test name
Test status
Simulation time 1168755985 ps
CPU time 10.76 seconds
Started Sep 18 08:03:31 AM UTC 24
Finished Sep 18 08:03:43 AM UTC 24
Peak memory 229916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=3316054034 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_bad_ad
dr.3316054034
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/20.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/20.i2c_target_fifo_reset_acq.2368002456
Short name T751
Test name
Test status
Simulation time 191483611 ps
CPU time 1.54 seconds
Started Sep 18 08:03:27 AM UTC 24
Finished Sep 18 08:03:30 AM UTC 24
Peak memory 215024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2368002
456 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_fifo_reset_acq.2368002456
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/20.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/20.i2c_target_fifo_reset_tx.99229261
Short name T753
Test name
Test status
Simulation time 375660371 ps
CPU time 1.44 seconds
Started Sep 18 08:03:28 AM UTC 24
Finished Sep 18 08:03:31 AM UTC 24
Peak memory 224844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9922926
1 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_fifo_reset_tx.99229261
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/20.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/20.i2c_target_fifo_watermarks_acq.2164441211
Short name T756
Test name
Test status
Simulation time 1681018551 ps
CPU time 2.85 seconds
Started Sep 18 08:03:32 AM UTC 24
Finished Sep 18 08:03:36 AM UTC 24
Peak memory 215340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2164441
211 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_fifo_watermar
ks_acq.2164441211
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/20.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/20.i2c_target_fifo_watermarks_tx.3691679846
Short name T758
Test name
Test status
Simulation time 563910737 ps
CPU time 2.26 seconds
Started Sep 18 08:03:35 AM UTC 24
Finished Sep 18 08:03:38 AM UTC 24
Peak memory 215116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3691679
846 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_fifo_watermark
s_tx.3691679846
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/20.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/20.i2c_target_intr_smoke.3896350877
Short name T748
Test name
Test status
Simulation time 961195547 ps
CPU time 9.88 seconds
Started Sep 18 08:03:15 AM UTC 24
Finished Sep 18 08:03:26 AM UTC 24
Peak memory 232484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=389635
0877 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_intr_smoke.3896350877
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/20.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/20.i2c_target_intr_stress_wr.1310035679
Short name T747
Test name
Test status
Simulation time 5545909675 ps
CPU time 8.67 seconds
Started Sep 18 08:03:16 AM UTC 24
Finished Sep 18 08:03:26 AM UTC 24
Peak memory 215440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1310035679 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_intr_stres
s_wr.1310035679
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/20.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/20.i2c_target_nack_acqfull.967606952
Short name T763
Test name
Test status
Simulation time 9625523618 ps
CPU time 4.95 seconds
Started Sep 18 08:03:37 AM UTC 24
Finished Sep 18 08:03:43 AM UTC 24
Peak memory 225636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9676069
52 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_nack_acqfull.967606952
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/20.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/20.i2c_target_nack_acqfull_addr.3880195959
Short name T764
Test name
Test status
Simulation time 2007542260 ps
CPU time 2.87 seconds
Started Sep 18 08:03:39 AM UTC 24
Finished Sep 18 08:03:43 AM UTC 24
Peak memory 215464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3880195
959 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_nack_acqfull_ad
dr.3880195959
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/20.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/20.i2c_target_nack_txstretch.3921928016
Short name T761
Test name
Test status
Simulation time 585324875 ps
CPU time 2.36 seconds
Started Sep 18 08:03:39 AM UTC 24
Finished Sep 18 08:03:43 AM UTC 24
Peak memory 232140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3921928
016 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_nack_txstretch.3921928016
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/20.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/20.i2c_target_perf.3983897021
Short name T757
Test name
Test status
Simulation time 3753262177 ps
CPU time 7.32 seconds
Started Sep 18 08:03:29 AM UTC 24
Finished Sep 18 08:03:38 AM UTC 24
Peak memory 227808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3983897
021 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_perf.3983897021
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/20.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/20.i2c_target_smbus_maxlen.2936134788
Short name T762
Test name
Test status
Simulation time 2423984619 ps
CPU time 4.67 seconds
Started Sep 18 08:03:37 AM UTC 24
Finished Sep 18 08:03:43 AM UTC 24
Peak memory 215088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2936134
788 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_smbus_maxlen.2936134788
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/20.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/20.i2c_target_smoke.2235352331
Short name T749
Test name
Test status
Simulation time 2199325886 ps
CPU time 17.89 seconds
Started Sep 18 08:03:09 AM UTC 24
Finished Sep 18 08:03:28 AM UTC 24
Peak memory 225560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2235352331 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_smoke.2235352331
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/20.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/20.i2c_target_stress_all.3286959447
Short name T293
Test name
Test status
Simulation time 109830009260 ps
CPU time 103.4 seconds
Started Sep 18 08:03:30 AM UTC 24
Finished Sep 18 08:05:15 AM UTC 24
Peak memory 838488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=328695
9447 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_stress_all.3286959447
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/20.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/20.i2c_target_stress_rd.3646421091
Short name T804
Test name
Test status
Simulation time 8672305056 ps
CPU time 71.21 seconds
Started Sep 18 08:03:11 AM UTC 24
Finished Sep 18 08:04:24 AM UTC 24
Peak memory 227604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3646421091 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_stress_rd.3646421091
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/20.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/20.i2c_target_stress_wr.1029022312
Short name T759
Test name
Test status
Simulation time 37877206982 ps
CPU time 29.97 seconds
Started Sep 18 08:03:10 AM UTC 24
Finished Sep 18 08:03:41 AM UTC 24
Peak memory 588568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1029022312 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_stress_wr.1029022312
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/20.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/20.i2c_target_timeout.2817988744
Short name T755
Test name
Test status
Simulation time 1254887405 ps
CPU time 9.68 seconds
Started Sep 18 08:03:25 AM UTC 24
Finished Sep 18 08:03:36 AM UTC 24
Peak memory 232356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2817988
744 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_timeout.2817988744
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/20.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/20.i2c_target_tx_stretch_ctrl.2191443913
Short name T766
Test name
Test status
Simulation time 321288806 ps
CPU time 8.41 seconds
Started Sep 18 08:03:36 AM UTC 24
Finished Sep 18 08:03:45 AM UTC 24
Peak memory 217300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2191443
913 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_tx_stretch_ctrl.2191443913
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/20.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/21.i2c_alert_test.2962979620
Short name T794
Test name
Test status
Simulation time 26575004 ps
CPU time 0.92 seconds
Started Sep 18 08:04:16 AM UTC 24
Finished Sep 18 08:04:18 AM UTC 24
Peak memory 214840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2962979620 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_alert_test.2962979620
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/21.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/21.i2c_host_error_intr.1073422339
Short name T774
Test name
Test status
Simulation time 1028233319 ps
CPU time 4.91 seconds
Started Sep 18 08:03:49 AM UTC 24
Finished Sep 18 08:03:55 AM UTC 24
Peak memory 225648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1073422339 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 21.i2c_host_error_intr.1073422339
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/21.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/21.i2c_host_fifo_fmt_empty.2711492662
Short name T771
Test name
Test status
Simulation time 1358282161 ps
CPU time 5.38 seconds
Started Sep 18 08:03:45 AM UTC 24
Finished Sep 18 08:03:51 AM UTC 24
Peak memory 258968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2711492662 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_fmt_empty.2711492662
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/21.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/21.i2c_host_fifo_full.3197507654
Short name T827
Test name
Test status
Simulation time 34581451638 ps
CPU time 75.11 seconds
Started Sep 18 08:03:46 AM UTC 24
Finished Sep 18 08:05:03 AM UTC 24
Peak memory 520996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3197507654 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_full.3197507654
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/21.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/21.i2c_host_fifo_overflow.4197401741
Short name T837
Test name
Test status
Simulation time 5638463835 ps
CPU time 89.42 seconds
Started Sep 18 08:03:44 AM UTC 24
Finished Sep 18 08:05:15 AM UTC 24
Peak memory 490280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4197401741 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_overflow.4197401741
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/21.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/21.i2c_host_fifo_reset_fmt.2188865911
Short name T769
Test name
Test status
Simulation time 233195255 ps
CPU time 1.89 seconds
Started Sep 18 08:03:45 AM UTC 24
Finished Sep 18 08:03:48 AM UTC 24
Peak memory 214900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2188865911 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_fmt.2188865911
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/21.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/21.i2c_host_fifo_reset_rx.2244421377
Short name T776
Test name
Test status
Simulation time 228127391 ps
CPU time 15.17 seconds
Started Sep 18 08:03:45 AM UTC 24
Finished Sep 18 08:04:01 AM UTC 24
Peak memory 215172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2244421377 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_rx.2244421377
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/21.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/21.i2c_host_fifo_watermark.3659802751
Short name T856
Test name
Test status
Simulation time 4708806367 ps
CPU time 107.06 seconds
Started Sep 18 08:03:44 AM UTC 24
Finished Sep 18 08:05:33 AM UTC 24
Peak memory 1380704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3659802751 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_watermark.3659802751
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/21.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/21.i2c_host_may_nack.4177714038
Short name T805
Test name
Test status
Simulation time 1152817760 ps
CPU time 14.38 seconds
Started Sep 18 08:04:08 AM UTC 24
Finished Sep 18 08:04:24 AM UTC 24
Peak memory 215336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4177714038 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.i2c_host_may_nack.4177714038
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/21.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/21.i2c_host_override.710354079
Short name T767
Test name
Test status
Simulation time 49156121 ps
CPU time 1.16 seconds
Started Sep 18 08:03:43 AM UTC 24
Finished Sep 18 08:03:46 AM UTC 24
Peak memory 214108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=710354079 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 21.i2c_host_override.710354079
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/21.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/21.i2c_host_perf.2072254464
Short name T873
Test name
Test status
Simulation time 8106787417 ps
CPU time 114.04 seconds
Started Sep 18 08:03:46 AM UTC 24
Finished Sep 18 08:05:42 AM UTC 24
Peak memory 215332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2072254464 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 21.i2c_host_perf.2072254464
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/21.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/21.i2c_host_perf_precise.1720446335
Short name T770
Test name
Test status
Simulation time 63498008 ps
CPU time 2.48 seconds
Started Sep 18 08:03:46 AM UTC 24
Finished Sep 18 08:03:50 AM UTC 24
Peak memory 225612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1720446335 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_perf_precise.1720446335
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/21.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/21.i2c_host_smoke.2976392663
Short name T777
Test name
Test status
Simulation time 1263594585 ps
CPU time 19.6 seconds
Started Sep 18 08:03:41 AM UTC 24
Finished Sep 18 08:04:02 AM UTC 24
Peak memory 308012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2976392663 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 21.i2c_host_smoke.2976392663
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/21.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/21.i2c_host_stretch_timeout.3576323907
Short name T775
Test name
Test status
Simulation time 402488145 ps
CPU time 10.15 seconds
Started Sep 18 08:03:48 AM UTC 24
Finished Sep 18 08:04:00 AM UTC 24
Peak memory 225632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3576323907 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_stretch_timeout.3576323907
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/21.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/21.i2c_target_bad_addr.531301200
Short name T801
Test name
Test status
Simulation time 3414009626 ps
CPU time 12.69 seconds
Started Sep 18 08:04:07 AM UTC 24
Finished Sep 18 08:04:21 AM UTC 24
Peak memory 232244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=531301200 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_bad_addr.531301200
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/21.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/21.i2c_target_fifo_reset_acq.1699832623
Short name T783
Test name
Test status
Simulation time 211760710 ps
CPU time 2.52 seconds
Started Sep 18 08:04:04 AM UTC 24
Finished Sep 18 08:04:07 AM UTC 24
Peak memory 225696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1699832
623 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_fifo_reset_acq.1699832623
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/21.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/21.i2c_target_fifo_reset_tx.4272730537
Short name T785
Test name
Test status
Simulation time 276255124 ps
CPU time 2.41 seconds
Started Sep 18 08:04:05 AM UTC 24
Finished Sep 18 08:04:08 AM UTC 24
Peak memory 221468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4272730
537 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_fifo_reset_tx.4272730537
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/21.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/21.i2c_target_fifo_watermarks_acq.1313228707
Short name T791
Test name
Test status
Simulation time 429493440 ps
CPU time 4.46 seconds
Started Sep 18 08:04:09 AM UTC 24
Finished Sep 18 08:04:15 AM UTC 24
Peak memory 215312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1313228
707 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_fifo_watermar
ks_acq.1313228707
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/21.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/21.i2c_target_fifo_watermarks_tx.3507853472
Short name T792
Test name
Test status
Simulation time 219709277 ps
CPU time 1.65 seconds
Started Sep 18 08:04:12 AM UTC 24
Finished Sep 18 08:04:15 AM UTC 24
Peak memory 214848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3507853
472 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_fifo_watermark
s_tx.3507853472
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/21.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/21.i2c_target_hrst.2026011571
Short name T786
Test name
Test status
Simulation time 1007960679 ps
CPU time 2.6 seconds
Started Sep 18 08:04:08 AM UTC 24
Finished Sep 18 08:04:12 AM UTC 24
Peak memory 225624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2026011
571 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_hrst.2026011571
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/21.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/21.i2c_target_intr_smoke.4074397959
Short name T780
Test name
Test status
Simulation time 3836123933 ps
CPU time 7.31 seconds
Started Sep 18 08:03:57 AM UTC 24
Finished Sep 18 08:04:05 AM UTC 24
Peak memory 229784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=407439
7959 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_intr_smoke.4074397959
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/21.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/21.i2c_target_intr_stress_wr.2264346312
Short name T893
Test name
Test status
Simulation time 10066035316 ps
CPU time 125.61 seconds
Started Sep 18 08:04:01 AM UTC 24
Finished Sep 18 08:06:09 AM UTC 24
Peak memory 2577176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2264346312 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_intr_stres
s_wr.2264346312
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/21.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/21.i2c_target_nack_acqfull.1601458767
Short name T798
Test name
Test status
Simulation time 2077258032 ps
CPU time 3.85 seconds
Started Sep 18 08:04:15 AM UTC 24
Finished Sep 18 08:04:19 AM UTC 24
Peak memory 225504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1601458
767 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_nack_acqfull.1601458767
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/21.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/21.i2c_target_nack_acqfull_addr.2146898680
Short name T800
Test name
Test status
Simulation time 2132794219 ps
CPU time 4.17 seconds
Started Sep 18 08:04:16 AM UTC 24
Finished Sep 18 08:04:21 AM UTC 24
Peak memory 215248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2146898
680 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_nack_acqfull_ad
dr.2146898680
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/21.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/21.i2c_target_nack_txstretch.1436762420
Short name T796
Test name
Test status
Simulation time 1151672820 ps
CPU time 2.39 seconds
Started Sep 18 08:04:16 AM UTC 24
Finished Sep 18 08:04:19 AM UTC 24
Peak memory 232352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1436762
420 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_nack_txstretch.1436762420
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/21.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/21.i2c_target_perf.1806112106
Short name T790
Test name
Test status
Simulation time 11044816028 ps
CPU time 7.47 seconds
Started Sep 18 08:04:06 AM UTC 24
Finished Sep 18 08:04:15 AM UTC 24
Peak memory 244592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1806112
106 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_perf.1806112106
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/21.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/21.i2c_target_smbus_maxlen.696145495
Short name T797
Test name
Test status
Simulation time 467146488 ps
CPU time 3.73 seconds
Started Sep 18 08:04:14 AM UTC 24
Finished Sep 18 08:04:19 AM UTC 24
Peak memory 215164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6961454
95 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_smbus_maxlen.696145495
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/21.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/21.i2c_target_smoke.998629427
Short name T781
Test name
Test status
Simulation time 3121221804 ps
CPU time 13.54 seconds
Started Sep 18 08:03:50 AM UTC 24
Finished Sep 18 08:04:05 AM UTC 24
Peak memory 225624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=998629427 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_smoke.998629427
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/21.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/21.i2c_target_stress_rd.2070948284
Short name T789
Test name
Test status
Simulation time 1174777982 ps
CPU time 20.8 seconds
Started Sep 18 08:03:52 AM UTC 24
Finished Sep 18 08:04:14 AM UTC 24
Peak memory 242660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2070948284 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_stress_rd.2070948284
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/21.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/21.i2c_target_stress_wr.780699615
Short name T803
Test name
Test status
Simulation time 28175718218 ps
CPU time 29.53 seconds
Started Sep 18 08:03:52 AM UTC 24
Finished Sep 18 08:04:23 AM UTC 24
Peak memory 631772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=780699615 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_stress_wr.780699615
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/21.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/21.i2c_target_stretch.3899071431
Short name T782
Test name
Test status
Simulation time 1516345017 ps
CPU time 11.25 seconds
Started Sep 18 08:03:54 AM UTC 24
Finished Sep 18 08:04:07 AM UTC 24
Peak memory 267100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3899071431 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_stretch.3899071431
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/21.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/21.i2c_target_timeout.106674696
Short name T788
Test name
Test status
Simulation time 7155682159 ps
CPU time 10.08 seconds
Started Sep 18 08:04:03 AM UTC 24
Finished Sep 18 08:04:14 AM UTC 24
Peak memory 232300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1066746
96 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_timeout.106674696
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/21.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/21.i2c_target_tx_stretch_ctrl.3948234761
Short name T793
Test name
Test status
Simulation time 86628730 ps
CPU time 3.25 seconds
Started Sep 18 08:04:12 AM UTC 24
Finished Sep 18 08:04:17 AM UTC 24
Peak memory 215320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3948234
761 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_tx_stretch_ctrl.3948234761
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/21.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/22.i2c_alert_test.2591376538
Short name T831
Test name
Test status
Simulation time 18418808 ps
CPU time 1.04 seconds
Started Sep 18 08:05:04 AM UTC 24
Finished Sep 18 08:05:07 AM UTC 24
Peak memory 214900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2591376538 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_alert_test.2591376538
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/22.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/22.i2c_host_error_intr.93984666
Short name T807
Test name
Test status
Simulation time 95485938 ps
CPU time 2.32 seconds
Started Sep 18 08:04:25 AM UTC 24
Finished Sep 18 08:04:28 AM UTC 24
Peak memory 225516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=93984666 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ho
st_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.i2c_host_error_intr.93984666
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/22.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/22.i2c_host_fifo_fmt_empty.431864736
Short name T810
Test name
Test status
Simulation time 447208089 ps
CPU time 11.26 seconds
Started Sep 18 08:04:20 AM UTC 24
Finished Sep 18 08:04:32 AM UTC 24
Peak memory 262940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=431864736 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_fmt_empty.431864736
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/22.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/22.i2c_host_fifo_full.1048984183
Short name T857
Test name
Test status
Simulation time 2945555816 ps
CPU time 70.98 seconds
Started Sep 18 08:04:20 AM UTC 24
Finished Sep 18 08:05:33 AM UTC 24
Peak memory 574416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1048984183 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_full.1048984183
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/22.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/22.i2c_host_fifo_overflow.2149444345
Short name T845
Test name
Test status
Simulation time 2971074057 ps
CPU time 57.68 seconds
Started Sep 18 08:04:20 AM UTC 24
Finished Sep 18 08:05:19 AM UTC 24
Peak memory 617260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2149444345 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_overflow.2149444345
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/22.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/22.i2c_host_fifo_reset_fmt.3705375430
Short name T802
Test name
Test status
Simulation time 1208963949 ps
CPU time 1.82 seconds
Started Sep 18 08:04:20 AM UTC 24
Finished Sep 18 08:04:23 AM UTC 24
Peak memory 214920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3705375430 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_fmt.3705375430
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/22.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/22.i2c_host_fifo_reset_rx.3694244625
Short name T809
Test name
Test status
Simulation time 332914214 ps
CPU time 9.54 seconds
Started Sep 18 08:04:20 AM UTC 24
Finished Sep 18 08:04:31 AM UTC 24
Peak memory 215268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3694244625 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_rx.3694244625
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/22.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/22.i2c_host_fifo_watermark.3235065856
Short name T1004
Test name
Test status
Simulation time 3595303685 ps
CPU time 222.4 seconds
Started Sep 18 08:04:18 AM UTC 24
Finished Sep 18 08:08:04 AM UTC 24
Peak memory 1104660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3235065856 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_watermark.3235065856
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/22.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/22.i2c_host_may_nack.2490298096
Short name T257
Test name
Test status
Simulation time 2496272990 ps
CPU time 14.24 seconds
Started Sep 18 08:04:54 AM UTC 24
Finished Sep 18 08:05:09 AM UTC 24
Peak memory 215144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2490298096 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.i2c_host_may_nack.2490298096
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/22.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/22.i2c_host_mode_toggle.2507360207
Short name T823
Test name
Test status
Simulation time 87216227 ps
CPU time 3.27 seconds
Started Sep 18 08:04:49 AM UTC 24
Finished Sep 18 08:04:53 AM UTC 24
Peak memory 225512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2507360207 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_mode_toggle.2507360207
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/22.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/22.i2c_host_override.2075322123
Short name T795
Test name
Test status
Simulation time 28674689 ps
CPU time 0.96 seconds
Started Sep 18 08:04:17 AM UTC 24
Finished Sep 18 08:04:19 AM UTC 24
Peak memory 214112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2075322123 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.i2c_host_override.2075322123
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/22.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/22.i2c_host_perf.693754293
Short name T1237
Test name
Test status
Simulation time 50716481024 ps
CPU time 488.75 seconds
Started Sep 18 08:04:21 AM UTC 24
Finished Sep 18 08:12:36 AM UTC 24
Peak memory 225632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=693754293 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 22.i2c_host_perf.693754293
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/22.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/22.i2c_host_perf_precise.4014761857
Short name T806
Test name
Test status
Simulation time 55053524 ps
CPU time 1.68 seconds
Started Sep 18 08:04:21 AM UTC 24
Finished Sep 18 08:04:24 AM UTC 24
Peak memory 234804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4014761857 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_perf_precise.4014761857
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/22.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/22.i2c_host_smoke.415269674
Short name T870
Test name
Test status
Simulation time 1591727902 ps
CPU time 82.02 seconds
Started Sep 18 08:04:16 AM UTC 24
Finished Sep 18 08:05:40 AM UTC 24
Peak memory 361192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=415269674 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 22.i2c_host_smoke.415269674
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/22.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/22.i2c_host_stress_all.1276497085
Short name T240
Test name
Test status
Simulation time 10574092352 ps
CPU time 268.79 seconds
Started Sep 18 08:04:25 AM UTC 24
Finished Sep 18 08:08:57 AM UTC 24
Peak memory 1246072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1276497085 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 22.i2c_host_stress_all.1276497085
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/22.i2c_host_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/22.i2c_host_stretch_timeout.1948043656
Short name T833
Test name
Test status
Simulation time 9697122600 ps
CPU time 44.8 seconds
Started Sep 18 08:04:23 AM UTC 24
Finished Sep 18 08:05:10 AM UTC 24
Peak memory 225624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1948043656 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_stretch_timeout.1948043656
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/22.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/22.i2c_target_bad_addr.1324765070
Short name T822
Test name
Test status
Simulation time 1421976961 ps
CPU time 5.36 seconds
Started Sep 18 08:04:47 AM UTC 24
Finished Sep 18 08:04:53 AM UTC 24
Peak memory 219492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=1324765070 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_bad_ad
dr.1324765070
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/22.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/22.i2c_target_fifo_reset_acq.569957045
Short name T817
Test name
Test status
Simulation time 532832843 ps
CPU time 1.77 seconds
Started Sep 18 08:04:43 AM UTC 24
Finished Sep 18 08:04:46 AM UTC 24
Peak memory 224904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5699570
45 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_fifo_reset_acq.569957045
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/22.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/22.i2c_target_fifo_reset_tx.3944520571
Short name T818
Test name
Test status
Simulation time 507442548 ps
CPU time 1.8 seconds
Started Sep 18 08:04:43 AM UTC 24
Finished Sep 18 08:04:46 AM UTC 24
Peak memory 214864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3944520
571 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_fifo_reset_tx.3944520571
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/22.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/22.i2c_target_fifo_watermarks_acq.1105798398
Short name T826
Test name
Test status
Simulation time 312445334 ps
CPU time 3.43 seconds
Started Sep 18 08:04:54 AM UTC 24
Finished Sep 18 08:04:58 AM UTC 24
Peak memory 215240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1105798
398 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_fifo_watermar
ks_acq.1105798398
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/22.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/22.i2c_target_fifo_watermarks_tx.709114900
Short name T824
Test name
Test status
Simulation time 142415127 ps
CPU time 2.39 seconds
Started Sep 18 08:04:54 AM UTC 24
Finished Sep 18 08:04:57 AM UTC 24
Peak memory 215120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7091149
00 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_fifo_watermarks
_tx.709114900
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/22.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/22.i2c_target_intr_smoke.155723327
Short name T814
Test name
Test status
Simulation time 3929678558 ps
CPU time 9.84 seconds
Started Sep 18 08:04:32 AM UTC 24
Finished Sep 18 08:04:43 AM UTC 24
Peak memory 232492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=155723
327 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_intr_smoke.155723327
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/22.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/22.i2c_target_intr_stress_wr.2653709944
Short name T909
Test name
Test status
Simulation time 14696867344 ps
CPU time 112.11 seconds
Started Sep 18 08:04:33 AM UTC 24
Finished Sep 18 08:06:27 AM UTC 24
Peak memory 2155288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2653709944 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_intr_stres
s_wr.2653709944
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/22.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/22.i2c_target_nack_acqfull.3519187067
Short name T830
Test name
Test status
Simulation time 640919219 ps
CPU time 5.32 seconds
Started Sep 18 08:04:59 AM UTC 24
Finished Sep 18 08:05:05 AM UTC 24
Peak memory 225484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3519187
067 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_nack_acqfull.3519187067
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/22.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/22.i2c_target_nack_acqfull_addr.2718497835
Short name T829
Test name
Test status
Simulation time 1010261445 ps
CPU time 4.55 seconds
Started Sep 18 08:04:59 AM UTC 24
Finished Sep 18 08:05:05 AM UTC 24
Peak memory 215340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2718497
835 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_nack_acqfull_ad
dr.2718497835
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/22.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/22.i2c_target_nack_txstretch.626256636
Short name T832
Test name
Test status
Simulation time 144816414 ps
CPU time 2.11 seconds
Started Sep 18 08:05:04 AM UTC 24
Finished Sep 18 08:05:07 AM UTC 24
Peak memory 232224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6262566
36 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_nack_txstretch.626256636
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/22.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/22.i2c_target_perf.1506894564
Short name T820
Test name
Test status
Simulation time 2508502309 ps
CPU time 7.4 seconds
Started Sep 18 08:04:44 AM UTC 24
Finished Sep 18 08:04:53 AM UTC 24
Peak memory 232304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1506894
564 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_perf.1506894564
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/22.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/22.i2c_target_smbus_maxlen.317679992
Short name T828
Test name
Test status
Simulation time 1104250553 ps
CPU time 4.25 seconds
Started Sep 18 08:04:58 AM UTC 24
Finished Sep 18 08:05:03 AM UTC 24
Peak memory 215272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3176799
92 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_smbus_maxlen.317679992
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/22.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/22.i2c_target_smoke.2466647589
Short name T816
Test name
Test status
Simulation time 934699417 ps
CPU time 18.36 seconds
Started Sep 18 08:04:25 AM UTC 24
Finished Sep 18 08:04:44 AM UTC 24
Peak memory 225540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2466647589 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_smoke.2466647589
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/22.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/22.i2c_target_stress_all.1380039182
Short name T1073
Test name
Test status
Simulation time 36690207123 ps
CPU time 271.72 seconds
Started Sep 18 08:04:45 AM UTC 24
Finished Sep 18 08:09:21 AM UTC 24
Peak memory 2423576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=138003
9182 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_stress_all.1380039182
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/22.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/22.i2c_target_stress_rd.3647755130
Short name T867
Test name
Test status
Simulation time 6180857441 ps
CPU time 79.07 seconds
Started Sep 18 08:04:29 AM UTC 24
Finished Sep 18 08:05:50 AM UTC 24
Peak memory 229708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3647755130 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_stress_rd.3647755130
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/22.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/22.i2c_target_stress_wr.3283929572
Short name T905
Test name
Test status
Simulation time 46650946856 ps
CPU time 114.14 seconds
Started Sep 18 08:04:25 AM UTC 24
Finished Sep 18 08:06:21 AM UTC 24
Peak memory 1704708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3283929572 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_stress_wr.3283929572
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/22.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/22.i2c_target_stretch.984266596
Short name T811
Test name
Test status
Simulation time 1785746334 ps
CPU time 3.19 seconds
Started Sep 18 08:04:30 AM UTC 24
Finished Sep 18 08:04:34 AM UTC 24
Peak memory 225636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=984266596 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_stretch.984266596
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/22.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/22.i2c_target_timeout.2361842999
Short name T815
Test name
Test status
Simulation time 1158680074 ps
CPU time 7.01 seconds
Started Sep 18 08:04:35 AM UTC 24
Finished Sep 18 08:04:43 AM UTC 24
Peak memory 225552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2361842
999 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_timeout.2361842999
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/22.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/22.i2c_target_tx_stretch_ctrl.1865362738
Short name T834
Test name
Test status
Simulation time 740937582 ps
CPU time 14.86 seconds
Started Sep 18 08:04:54 AM UTC 24
Finished Sep 18 08:05:10 AM UTC 24
Peak memory 215252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1865362
738 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_tx_stretch_ctrl.1865362738
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/22.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/23.i2c_alert_test.1771345473
Short name T864
Test name
Test status
Simulation time 59587393 ps
CPU time 0.95 seconds
Started Sep 18 08:05:36 AM UTC 24
Finished Sep 18 08:05:38 AM UTC 24
Peak memory 214840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1771345473 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_alert_test.1771345473
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/23.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/23.i2c_host_error_intr.1865963153
Short name T846
Test name
Test status
Simulation time 148335013 ps
CPU time 4.07 seconds
Started Sep 18 08:05:15 AM UTC 24
Finished Sep 18 08:05:21 AM UTC 24
Peak memory 225604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1865963153 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 23.i2c_host_error_intr.1865963153
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/23.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/23.i2c_host_fifo_fmt_empty.3385496274
Short name T841
Test name
Test status
Simulation time 405505047 ps
CPU time 8.15 seconds
Started Sep 18 08:05:09 AM UTC 24
Finished Sep 18 08:05:18 AM UTC 24
Peak memory 303836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3385496274 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_fmt_empty.3385496274
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/23.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/23.i2c_host_fifo_full.2474893153
Short name T901
Test name
Test status
Simulation time 5948952944 ps
CPU time 60.15 seconds
Started Sep 18 08:05:11 AM UTC 24
Finished Sep 18 08:06:13 AM UTC 24
Peak memory 703412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2474893153 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_full.2474893153
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/23.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/23.i2c_host_fifo_overflow.1159338078
Short name T964
Test name
Test status
Simulation time 8373623120 ps
CPU time 136.69 seconds
Started Sep 18 08:05:08 AM UTC 24
Finished Sep 18 08:07:27 AM UTC 24
Peak memory 748320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1159338078 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_overflow.1159338078
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/23.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/23.i2c_host_fifo_reset_fmt.2279620956
Short name T835
Test name
Test status
Simulation time 471834207 ps
CPU time 1.56 seconds
Started Sep 18 08:05:09 AM UTC 24
Finished Sep 18 08:05:12 AM UTC 24
Peak memory 215020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2279620956 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_fmt.2279620956
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/23.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/23.i2c_host_fifo_reset_rx.366127893
Short name T839
Test name
Test status
Simulation time 139945824 ps
CPU time 5.21 seconds
Started Sep 18 08:05:10 AM UTC 24
Finished Sep 18 08:05:17 AM UTC 24
Peak memory 215320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=366127893 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_rx.366127893
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/23.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/23.i2c_host_fifo_watermark.1735342519
Short name T915
Test name
Test status
Simulation time 7050747472 ps
CPU time 83.05 seconds
Started Sep 18 08:05:07 AM UTC 24
Finished Sep 18 08:06:31 AM UTC 24
Peak memory 1151776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1735342519 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_watermark.1735342519
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/23.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/23.i2c_host_may_nack.844113952
Short name T248
Test name
Test status
Simulation time 1179369310 ps
CPU time 5.32 seconds
Started Sep 18 08:05:29 AM UTC 24
Finished Sep 18 08:05:36 AM UTC 24
Peak memory 215456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=844113952 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 23.i2c_host_may_nack.844113952
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/23.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/23.i2c_host_mode_toggle.2140763714
Short name T854
Test name
Test status
Simulation time 62087392 ps
CPU time 1.69 seconds
Started Sep 18 08:05:28 AM UTC 24
Finished Sep 18 08:05:31 AM UTC 24
Peak memory 215032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2140763714 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_mode_toggle.2140763714
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/23.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/23.i2c_host_override.1478212813
Short name T153
Test name
Test status
Simulation time 20204393 ps
CPU time 1.03 seconds
Started Sep 18 08:05:06 AM UTC 24
Finished Sep 18 08:05:08 AM UTC 24
Peak memory 214112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1478212813 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.i2c_host_override.1478212813
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/23.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/23.i2c_host_perf.1558730402
Short name T960
Test name
Test status
Simulation time 5439517243 ps
CPU time 129.68 seconds
Started Sep 18 08:05:11 AM UTC 24
Finished Sep 18 08:07:23 AM UTC 24
Peak memory 1151832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1558730402 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 23.i2c_host_perf.1558730402
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/23.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/23.i2c_host_perf_precise.4024104321
Short name T838
Test name
Test status
Simulation time 75717739 ps
CPU time 1.7 seconds
Started Sep 18 08:05:13 AM UTC 24
Finished Sep 18 08:05:16 AM UTC 24
Peak memory 214852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4024104321 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_perf_precise.4024104321
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/23.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/23.i2c_host_smoke.682562737
Short name T876
Test name
Test status
Simulation time 1905277964 ps
CPU time 45.92 seconds
Started Sep 18 08:05:04 AM UTC 24
Finished Sep 18 08:05:52 AM UTC 24
Peak memory 365292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=682562737 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 23.i2c_host_smoke.682562737
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/23.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/23.i2c_host_stretch_timeout.3767199983
Short name T848
Test name
Test status
Simulation time 3645654070 ps
CPU time 9.3 seconds
Started Sep 18 08:05:13 AM UTC 24
Finished Sep 18 08:05:24 AM UTC 24
Peak memory 227612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3767199983 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_stretch_timeout.3767199983
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/23.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/23.i2c_target_bad_addr.855528066
Short name T862
Test name
Test status
Simulation time 2331320202 ps
CPU time 10.01 seconds
Started Sep 18 08:05:25 AM UTC 24
Finished Sep 18 08:05:36 AM UTC 24
Peak memory 225692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=855528066 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_bad_addr.855528066
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/23.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/23.i2c_target_fifo_reset_acq.1692184205
Short name T847
Test name
Test status
Simulation time 218808601 ps
CPU time 2.31 seconds
Started Sep 18 08:05:20 AM UTC 24
Finished Sep 18 08:05:23 AM UTC 24
Peak memory 215040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1692184
205 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_fifo_reset_acq.1692184205
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/23.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/23.i2c_target_fifo_reset_tx.2780105082
Short name T849
Test name
Test status
Simulation time 276075754 ps
CPU time 2.9 seconds
Started Sep 18 08:05:21 AM UTC 24
Finished Sep 18 08:05:25 AM UTC 24
Peak memory 215324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2780105
082 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_fifo_reset_tx.2780105082
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/23.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/23.i2c_target_fifo_watermarks_acq.1800376084
Short name T860
Test name
Test status
Simulation time 1524536233 ps
CPU time 3.72 seconds
Started Sep 18 08:05:31 AM UTC 24
Finished Sep 18 08:05:35 AM UTC 24
Peak memory 215328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1800376
084 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_fifo_watermar
ks_acq.1800376084
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/23.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/23.i2c_target_fifo_watermarks_tx.1041364609
Short name T858
Test name
Test status
Simulation time 222674364 ps
CPU time 1.66 seconds
Started Sep 18 08:05:32 AM UTC 24
Finished Sep 18 08:05:34 AM UTC 24
Peak memory 214848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1041364
609 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_fifo_watermark
s_tx.1041364609
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/23.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/23.i2c_target_hrst.1958099441
Short name T855
Test name
Test status
Simulation time 1364755920 ps
CPU time 4.13 seconds
Started Sep 18 08:05:26 AM UTC 24
Finished Sep 18 08:05:32 AM UTC 24
Peak memory 225632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1958099
441 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_hrst.1958099441
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/23.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/23.i2c_target_intr_smoke.2299444134
Short name T852
Test name
Test status
Simulation time 3637300782 ps
CPU time 9.74 seconds
Started Sep 18 08:05:19 AM UTC 24
Finished Sep 18 08:05:30 AM UTC 24
Peak memory 225560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=229944
4134 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_intr_smoke.2299444134
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/23.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/23.i2c_target_intr_stress_wr.425856305
Short name T872
Test name
Test status
Simulation time 14123526456 ps
CPU time 19.41 seconds
Started Sep 18 08:05:20 AM UTC 24
Finished Sep 18 08:05:40 AM UTC 24
Peak memory 498452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=425856305 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_intr_stress
_wr.425856305
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/23.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/23.i2c_target_nack_acqfull.4068699716
Short name T868
Test name
Test status
Simulation time 921788789 ps
CPU time 4.27 seconds
Started Sep 18 08:05:34 AM UTC 24
Finished Sep 18 08:05:39 AM UTC 24
Peak memory 225580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4068699
716 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_nack_acqfull.4068699716
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/23.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/23.i2c_target_nack_acqfull_addr.853005689
Short name T866
Test name
Test status
Simulation time 570691716 ps
CPU time 3.62 seconds
Started Sep 18 08:05:34 AM UTC 24
Finished Sep 18 08:05:39 AM UTC 24
Peak memory 215132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8530056
89 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_nack_acqfull_addr.853005689
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/23.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/23.i2c_target_perf.1681416534
Short name T859
Test name
Test status
Simulation time 938632706 ps
CPU time 9.84 seconds
Started Sep 18 08:05:24 AM UTC 24
Finished Sep 18 08:05:35 AM UTC 24
Peak memory 231712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1681416
534 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_perf.1681416534
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/23.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/23.i2c_target_smbus_maxlen.3130732657
Short name T865
Test name
Test status
Simulation time 962811441 ps
CPU time 4.29 seconds
Started Sep 18 08:05:33 AM UTC 24
Finished Sep 18 08:05:38 AM UTC 24
Peak memory 215020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3130732
657 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_smbus_maxlen.3130732657
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/23.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/23.i2c_target_smoke.1926561560
Short name T853
Test name
Test status
Simulation time 943243902 ps
CPU time 12.83 seconds
Started Sep 18 08:05:16 AM UTC 24
Finished Sep 18 08:05:30 AM UTC 24
Peak memory 225696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1926561560 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_smoke.1926561560
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/23.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/23.i2c_target_stress_all.2555186111
Short name T907
Test name
Test status
Simulation time 38800269175 ps
CPU time 56.81 seconds
Started Sep 18 08:05:25 AM UTC 24
Finished Sep 18 08:06:24 AM UTC 24
Peak memory 799512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=255518
6111 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_stress_all.2555186111
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/23.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/23.i2c_target_stress_rd.1697379604
Short name T861
Test name
Test status
Simulation time 1100384235 ps
CPU time 17.15 seconds
Started Sep 18 08:05:18 AM UTC 24
Finished Sep 18 08:05:36 AM UTC 24
Peak memory 248728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1697379604 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_stress_rd.1697379604
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/23.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/23.i2c_target_stress_wr.3354796009
Short name T1070
Test name
Test status
Simulation time 68290139924 ps
CPU time 236.5 seconds
Started Sep 18 08:05:18 AM UTC 24
Finished Sep 18 08:09:17 AM UTC 24
Peak memory 3087124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3354796009 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_stress_wr.3354796009
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/23.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/23.i2c_target_stretch.4185516356
Short name T850
Test name
Test status
Simulation time 354146396 ps
CPU time 8.17 seconds
Started Sep 18 08:05:19 AM UTC 24
Finished Sep 18 08:05:28 AM UTC 24
Peak memory 236316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4185516356 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_stretch.4185516356
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/23.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/23.i2c_target_timeout.1573263266
Short name T851
Test name
Test status
Simulation time 12368046472 ps
CPU time 7.32 seconds
Started Sep 18 08:05:20 AM UTC 24
Finished Sep 18 08:05:28 AM UTC 24
Peak memory 225560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1573263
266 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_timeout.1573263266
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/23.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/23.i2c_target_tx_stretch_ctrl.1259230273
Short name T863
Test name
Test status
Simulation time 130421170 ps
CPU time 4.09 seconds
Started Sep 18 08:05:32 AM UTC 24
Finished Sep 18 08:05:37 AM UTC 24
Peak memory 215320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1259230
273 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_tx_stretch_ctrl.1259230273
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/23.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/24.i2c_alert_test.604638390
Short name T892
Test name
Test status
Simulation time 19506976 ps
CPU time 1.02 seconds
Started Sep 18 08:06:07 AM UTC 24
Finished Sep 18 08:06:09 AM UTC 24
Peak memory 214260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=604638390 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_alert_test.604638390
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/24.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/24.i2c_host_error_intr.3105067042
Short name T875
Test name
Test status
Simulation time 303228858 ps
CPU time 2.96 seconds
Started Sep 18 08:05:41 AM UTC 24
Finished Sep 18 08:05:45 AM UTC 24
Peak memory 244660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3105067042 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 24.i2c_host_error_intr.3105067042
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/24.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/24.i2c_host_fifo_fmt_empty.3847615108
Short name T879
Test name
Test status
Simulation time 324863799 ps
CPU time 19.89 seconds
Started Sep 18 08:05:38 AM UTC 24
Finished Sep 18 08:05:59 AM UTC 24
Peak memory 279452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3847615108 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_fmt_empty.3847615108
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/24.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/24.i2c_host_fifo_full.1875865774
Short name T927
Test name
Test status
Simulation time 2059512847 ps
CPU time 58.5 seconds
Started Sep 18 08:05:40 AM UTC 24
Finished Sep 18 08:06:40 AM UTC 24
Peak memory 582368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1875865774 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_full.1875865774
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/24.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/24.i2c_host_fifo_overflow.2603943515
Short name T939
Test name
Test status
Simulation time 1812268597 ps
CPU time 75.66 seconds
Started Sep 18 08:05:37 AM UTC 24
Finished Sep 18 08:06:55 AM UTC 24
Peak memory 490280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2603943515 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_overflow.2603943515
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/24.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/24.i2c_host_fifo_reset_fmt.2970242734
Short name T871
Test name
Test status
Simulation time 228159614 ps
CPU time 1.49 seconds
Started Sep 18 08:05:37 AM UTC 24
Finished Sep 18 08:05:40 AM UTC 24
Peak memory 214900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2970242734 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_fmt.2970242734
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/24.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/24.i2c_host_fifo_reset_rx.1493861072
Short name T813
Test name
Test status
Simulation time 577516093 ps
CPU time 10.67 seconds
Started Sep 18 08:05:38 AM UTC 24
Finished Sep 18 08:05:50 AM UTC 24
Peak memory 254752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1493861072 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_rx.1493861072
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/24.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/24.i2c_host_fifo_watermark.3756439273
Short name T1045
Test name
Test status
Simulation time 21181903255 ps
CPU time 195.23 seconds
Started Sep 18 08:05:37 AM UTC 24
Finished Sep 18 08:08:55 AM UTC 24
Peak memory 1104608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3756439273 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_watermark.3756439273
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/24.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/24.i2c_host_may_nack.3370465013
Short name T890
Test name
Test status
Simulation time 427288455 ps
CPU time 4.2 seconds
Started Sep 18 08:06:02 AM UTC 24
Finished Sep 18 08:06:07 AM UTC 24
Peak memory 215200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3370465013 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.i2c_host_may_nack.3370465013
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/24.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/24.i2c_host_override.3998329836
Short name T869
Test name
Test status
Simulation time 79064156 ps
CPU time 1.1 seconds
Started Sep 18 08:05:37 AM UTC 24
Finished Sep 18 08:05:39 AM UTC 24
Peak memory 214916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3998329836 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.i2c_host_override.3998329836
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/24.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/24.i2c_host_perf.2936787374
Short name T1255
Test name
Test status
Simulation time 47483013704 ps
CPU time 432.4 seconds
Started Sep 18 08:05:40 AM UTC 24
Finished Sep 18 08:12:57 AM UTC 24
Peak memory 2931416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2936787374 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 24.i2c_host_perf.2936787374
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/24.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/24.i2c_host_perf_precise.1245637417
Short name T874
Test name
Test status
Simulation time 55156925 ps
CPU time 1.84 seconds
Started Sep 18 08:05:40 AM UTC 24
Finished Sep 18 08:05:42 AM UTC 24
Peak memory 214856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1245637417 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_perf_precise.1245637417
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/24.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/24.i2c_host_smoke.3451505252
Short name T903
Test name
Test status
Simulation time 3528635091 ps
CPU time 38.32 seconds
Started Sep 18 08:05:36 AM UTC 24
Finished Sep 18 08:06:16 AM UTC 24
Peak memory 394220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3451505252 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.i2c_host_smoke.3451505252
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/24.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/24.i2c_host_stretch_timeout.11408412
Short name T919
Test name
Test status
Simulation time 1030573841 ps
CPU time 53.61 seconds
Started Sep 18 08:05:40 AM UTC 24
Finished Sep 18 08:06:35 AM UTC 24
Peak memory 225432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=11408412 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ho
st_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_stretch_timeout.11408412
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/24.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/24.i2c_target_bad_addr.2287572480
Short name T894
Test name
Test status
Simulation time 3931455329 ps
CPU time 6.96 seconds
Started Sep 18 08:06:01 AM UTC 24
Finished Sep 18 08:06:09 AM UTC 24
Peak memory 227812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=2287572480 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_bad_ad
dr.2287572480
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/24.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/24.i2c_target_fifo_reset_acq.1201900297
Short name T877
Test name
Test status
Simulation time 141661643 ps
CPU time 1.7 seconds
Started Sep 18 08:05:56 AM UTC 24
Finished Sep 18 08:05:58 AM UTC 24
Peak memory 214784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1201900
297 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_fifo_reset_acq.1201900297
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/24.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/24.i2c_target_fifo_reset_tx.3498882823
Short name T882
Test name
Test status
Simulation time 252514854 ps
CPU time 2.54 seconds
Started Sep 18 08:05:58 AM UTC 24
Finished Sep 18 08:06:01 AM UTC 24
Peak memory 215324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3498882
823 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_fifo_reset_tx.3498882823
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/24.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/24.i2c_target_fifo_watermarks_acq.2475341879
Short name T886
Test name
Test status
Simulation time 274067980 ps
CPU time 2.15 seconds
Started Sep 18 08:06:02 AM UTC 24
Finished Sep 18 08:06:05 AM UTC 24
Peak memory 215176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2475341
879 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_fifo_watermar
ks_acq.2475341879
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/24.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/24.i2c_target_fifo_watermarks_tx.2508555528
Short name T888
Test name
Test status
Simulation time 95711913 ps
CPU time 1.58 seconds
Started Sep 18 08:06:03 AM UTC 24
Finished Sep 18 08:06:06 AM UTC 24
Peak memory 215032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2508555
528 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_fifo_watermark
s_tx.2508555528
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/24.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/24.i2c_target_hrst.2985661328
Short name T887
Test name
Test status
Simulation time 328630098 ps
CPU time 3.4 seconds
Started Sep 18 08:06:01 AM UTC 24
Finished Sep 18 08:06:05 AM UTC 24
Peak memory 232144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2985661
328 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_hrst.2985661328
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/24.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/24.i2c_target_intr_smoke.2930166299
Short name T881
Test name
Test status
Simulation time 4604246847 ps
CPU time 9.02 seconds
Started Sep 18 08:05:50 AM UTC 24
Finished Sep 18 08:06:01 AM UTC 24
Peak memory 232228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=293016
6299 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_intr_smoke.2930166299
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/24.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/24.i2c_target_intr_stress_wr.2141995567
Short name T993
Test name
Test status
Simulation time 15633079498 ps
CPU time 121.42 seconds
Started Sep 18 08:05:51 AM UTC 24
Finished Sep 18 08:07:55 AM UTC 24
Peak memory 2206756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2141995567 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_intr_stres
s_wr.2141995567
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/24.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/24.i2c_target_nack_acqfull.1645307970
Short name T895
Test name
Test status
Simulation time 562285925 ps
CPU time 3.54 seconds
Started Sep 18 08:06:04 AM UTC 24
Finished Sep 18 08:06:09 AM UTC 24
Peak memory 225484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1645307
970 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_nack_acqfull.1645307970
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/24.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/24.i2c_target_nack_acqfull_addr.287355668
Short name T899
Test name
Test status
Simulation time 1027443165 ps
CPU time 3.58 seconds
Started Sep 18 08:06:06 AM UTC 24
Finished Sep 18 08:06:10 AM UTC 24
Peak memory 215336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2873556
68 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_nack_acqfull_addr.287355668
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/24.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/24.i2c_target_nack_txstretch.3605317634
Short name T897
Test name
Test status
Simulation time 212574421 ps
CPU time 1.97 seconds
Started Sep 18 08:06:07 AM UTC 24
Finished Sep 18 08:06:10 AM UTC 24
Peak memory 231504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3605317
634 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_nack_txstretch.3605317634
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/24.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/24.i2c_target_perf.619340545
Short name T889
Test name
Test status
Simulation time 3073383802 ps
CPU time 6.68 seconds
Started Sep 18 08:05:59 AM UTC 24
Finished Sep 18 08:06:06 AM UTC 24
Peak memory 229732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6193405
45 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_perf.619340545
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/24.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/24.i2c_target_smbus_maxlen.4123939546
Short name T896
Test name
Test status
Simulation time 1972783157 ps
CPU time 3.76 seconds
Started Sep 18 08:06:04 AM UTC 24
Finished Sep 18 08:06:09 AM UTC 24
Peak memory 215072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4123939
546 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_smbus_maxlen.4123939546
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/24.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/24.i2c_target_smoke.2032676913
Short name T884
Test name
Test status
Simulation time 1944898597 ps
CPU time 19.98 seconds
Started Sep 18 08:05:41 AM UTC 24
Finished Sep 18 08:06:02 AM UTC 24
Peak memory 225624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2032676913 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_smoke.2032676913
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/24.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/24.i2c_target_stress_all.1578391494
Short name T963
Test name
Test status
Simulation time 16703059819 ps
CPU time 84.16 seconds
Started Sep 18 08:06:00 AM UTC 24
Finished Sep 18 08:07:26 AM UTC 24
Peak memory 580456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=157839
1494 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_stress_all.1578391494
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/24.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/24.i2c_target_stress_rd.3437800294
Short name T933
Test name
Test status
Simulation time 16525032215 ps
CPU time 58.03 seconds
Started Sep 18 08:05:43 AM UTC 24
Finished Sep 18 08:06:43 AM UTC 24
Peak memory 229792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3437800294 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_stress_rd.3437800294
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/24.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/24.i2c_target_stress_wr.1931099461
Short name T883
Test name
Test status
Simulation time 18246361771 ps
CPU time 17.46 seconds
Started Sep 18 08:05:43 AM UTC 24
Finished Sep 18 08:06:02 AM UTC 24
Peak memory 215580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1931099461 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_stress_wr.1931099461
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/24.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/24.i2c_target_stretch.1836328901
Short name T942
Test name
Test status
Simulation time 4634633749 ps
CPU time 76.15 seconds
Started Sep 18 08:05:45 AM UTC 24
Finished Sep 18 08:07:03 AM UTC 24
Peak memory 1065756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1836328901 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_stretch.1836328901
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/24.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/24.i2c_target_timeout.711512918
Short name T885
Test name
Test status
Simulation time 10231929968 ps
CPU time 12.28 seconds
Started Sep 18 08:05:51 AM UTC 24
Finished Sep 18 08:06:05 AM UTC 24
Peak memory 232280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7115129
18 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_timeout.711512918
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/24.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/24.i2c_target_tx_stretch_ctrl.2511539213
Short name T891
Test name
Test status
Simulation time 184201827 ps
CPU time 4.01 seconds
Started Sep 18 08:06:03 AM UTC 24
Finished Sep 18 08:06:08 AM UTC 24
Peak memory 215320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2511539
213 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_tx_stretch_ctrl.2511539213
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/24.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/25.i2c_alert_test.1327028979
Short name T924
Test name
Test status
Simulation time 28472708 ps
CPU time 0.94 seconds
Started Sep 18 08:06:36 AM UTC 24
Finished Sep 18 08:06:38 AM UTC 24
Peak memory 214840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1327028979 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_alert_test.1327028979
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/25.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/25.i2c_host_error_intr.380160963
Short name T902
Test name
Test status
Simulation time 274563057 ps
CPU time 2.4 seconds
Started Sep 18 08:06:11 AM UTC 24
Finished Sep 18 08:06:15 AM UTC 24
Peak memory 225520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=380160963 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 25.i2c_host_error_intr.380160963
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/25.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/25.i2c_host_fifo_fmt_empty.2002161832
Short name T911
Test name
Test status
Simulation time 298084823 ps
CPU time 17.79 seconds
Started Sep 18 08:06:10 AM UTC 24
Finished Sep 18 08:06:29 AM UTC 24
Peak memory 279460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2002161832 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_fmt_empty.2002161832
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/25.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/25.i2c_host_fifo_full.3041542484
Short name T1016
Test name
Test status
Simulation time 2342836384 ps
CPU time 129.66 seconds
Started Sep 18 08:06:10 AM UTC 24
Finished Sep 18 08:08:22 AM UTC 24
Peak memory 396020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3041542484 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_full.3041542484
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/25.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/25.i2c_host_fifo_overflow.3062831635
Short name T1002
Test name
Test status
Simulation time 1661869087 ps
CPU time 112.04 seconds
Started Sep 18 08:06:09 AM UTC 24
Finished Sep 18 08:08:03 AM UTC 24
Peak memory 615216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3062831635 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_overflow.3062831635
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/25.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/25.i2c_host_fifo_reset_fmt.1486243425
Short name T900
Test name
Test status
Simulation time 111867320 ps
CPU time 1.41 seconds
Started Sep 18 08:06:09 AM UTC 24
Finished Sep 18 08:06:11 AM UTC 24
Peak memory 214900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1486243425 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_fmt.1486243425
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/25.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/25.i2c_host_fifo_reset_rx.1274333323
Short name T908
Test name
Test status
Simulation time 365616402 ps
CPU time 13.05 seconds
Started Sep 18 08:06:10 AM UTC 24
Finished Sep 18 08:06:24 AM UTC 24
Peak memory 215248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1274333323 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_rx.1274333323
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/25.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/25.i2c_host_fifo_watermark.1181642883
Short name T1036
Test name
Test status
Simulation time 5201713255 ps
CPU time 154.27 seconds
Started Sep 18 08:06:08 AM UTC 24
Finished Sep 18 08:08:45 AM UTC 24
Peak memory 1503940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1181642883 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_watermark.1181642883
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/25.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/25.i2c_host_may_nack.1703930962
Short name T944
Test name
Test status
Simulation time 591652126 ps
CPU time 31.12 seconds
Started Sep 18 08:06:33 AM UTC 24
Finished Sep 18 08:07:05 AM UTC 24
Peak memory 215336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1703930962 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.i2c_host_may_nack.1703930962
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/25.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/25.i2c_host_override.1655553390
Short name T898
Test name
Test status
Simulation time 20229410 ps
CPU time 1.06 seconds
Started Sep 18 08:06:08 AM UTC 24
Finished Sep 18 08:06:10 AM UTC 24
Peak memory 214112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1655553390 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.i2c_host_override.1655553390
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/25.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/25.i2c_host_perf.1401121260
Short name T1289
Test name
Test status
Simulation time 24787617254 ps
CPU time 487.81 seconds
Started Sep 18 08:06:10 AM UTC 24
Finished Sep 18 08:14:24 AM UTC 24
Peak memory 250716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1401121260 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 25.i2c_host_perf.1401121260
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/25.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/25.i2c_host_perf_precise.442471340
Short name T904
Test name
Test status
Simulation time 80298608 ps
CPU time 4.65 seconds
Started Sep 18 08:06:10 AM UTC 24
Finished Sep 18 08:06:16 AM UTC 24
Peak memory 229724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=442471340 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_perf_precise.442471340
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/25.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/25.i2c_host_smoke.2916103817
Short name T973
Test name
Test status
Simulation time 9554253457 ps
CPU time 91.92 seconds
Started Sep 18 08:06:07 AM UTC 24
Finished Sep 18 08:07:41 AM UTC 24
Peak memory 340776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2916103817 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 25.i2c_host_smoke.2916103817
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/25.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/25.i2c_host_stretch_timeout.1093358243
Short name T937
Test name
Test status
Simulation time 669715750 ps
CPU time 35.94 seconds
Started Sep 18 08:06:10 AM UTC 24
Finished Sep 18 08:06:48 AM UTC 24
Peak memory 225488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1093358243 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_stretch_timeout.1093358243
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/25.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/25.i2c_target_bad_addr.3095479967
Short name T929
Test name
Test status
Simulation time 4676855397 ps
CPU time 8.36 seconds
Started Sep 18 08:06:30 AM UTC 24
Finished Sep 18 08:06:40 AM UTC 24
Peak memory 219484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=3095479967 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_bad_ad
dr.3095479967
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/25.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/25.i2c_target_fifo_reset_acq.503741119
Short name T910
Test name
Test status
Simulation time 315229992 ps
CPU time 1.54 seconds
Started Sep 18 08:06:25 AM UTC 24
Finished Sep 18 08:06:28 AM UTC 24
Peak memory 214740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5037411
19 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_fifo_reset_acq.503741119
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/25.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/25.i2c_target_fifo_reset_tx.3135650181
Short name T916
Test name
Test status
Simulation time 224350433 ps
CPU time 2.36 seconds
Started Sep 18 08:06:28 AM UTC 24
Finished Sep 18 08:06:32 AM UTC 24
Peak memory 225748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3135650
181 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_fifo_reset_tx.3135650181
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/25.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/25.i2c_target_fifo_watermarks_acq.4147581239
Short name T921
Test name
Test status
Simulation time 2680159368 ps
CPU time 3.62 seconds
Started Sep 18 08:06:33 AM UTC 24
Finished Sep 18 08:06:37 AM UTC 24
Peak memory 215528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4147581
239 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_fifo_watermar
ks_acq.4147581239
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/25.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/25.i2c_target_fifo_watermarks_tx.1547898587
Short name T920
Test name
Test status
Simulation time 779809048 ps
CPU time 1.58 seconds
Started Sep 18 08:06:33 AM UTC 24
Finished Sep 18 08:06:35 AM UTC 24
Peak memory 214852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1547898
587 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_fifo_watermark
s_tx.1547898587
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/25.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/25.i2c_target_intr_smoke.1571526676
Short name T912
Test name
Test status
Simulation time 4950879198 ps
CPU time 11.19 seconds
Started Sep 18 08:06:17 AM UTC 24
Finished Sep 18 08:06:29 AM UTC 24
Peak memory 231840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=157152
6676 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_intr_smoke.1571526676
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/25.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/25.i2c_target_intr_stress_wr.2953532352
Short name T981
Test name
Test status
Simulation time 7712554265 ps
CPU time 82.89 seconds
Started Sep 18 08:06:22 AM UTC 24
Finished Sep 18 08:07:46 AM UTC 24
Peak memory 1985308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2953532352 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_intr_stres
s_wr.2953532352
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/25.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/25.i2c_target_nack_acqfull.3587196963
Short name T931
Test name
Test status
Simulation time 6680854943 ps
CPU time 3.76 seconds
Started Sep 18 08:06:36 AM UTC 24
Finished Sep 18 08:06:41 AM UTC 24
Peak memory 225632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3587196
963 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_nack_acqfull.3587196963
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/25.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/25.i2c_target_nack_acqfull_addr.3122887856
Short name T932
Test name
Test status
Simulation time 10012888297 ps
CPU time 4.49 seconds
Started Sep 18 08:06:36 AM UTC 24
Finished Sep 18 08:06:41 AM UTC 24
Peak memory 215312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3122887
856 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_nack_acqfull_ad
dr.3122887856
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/25.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/25.i2c_target_nack_txstretch.1165994856
Short name T926
Test name
Test status
Simulation time 1368897908 ps
CPU time 2.6 seconds
Started Sep 18 08:06:36 AM UTC 24
Finished Sep 18 08:06:40 AM UTC 24
Peak memory 232140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1165994
856 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_nack_txstretch.1165994856
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/25.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/25.i2c_target_perf.3031810138
Short name T928
Test name
Test status
Simulation time 1686901668 ps
CPU time 10.56 seconds
Started Sep 18 08:06:28 AM UTC 24
Finished Sep 18 08:06:40 AM UTC 24
Peak memory 232340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3031810
138 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_perf.3031810138
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/25.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/25.i2c_target_smbus_maxlen.2222330961
Short name T925
Test name
Test status
Simulation time 470983874 ps
CPU time 2.79 seconds
Started Sep 18 08:06:35 AM UTC 24
Finished Sep 18 08:06:39 AM UTC 24
Peak memory 215204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2222330
961 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_smbus_maxlen.2222330961
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/25.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/25.i2c_target_smoke.1514005276
Short name T914
Test name
Test status
Simulation time 2014011391 ps
CPU time 17.57 seconds
Started Sep 18 08:06:12 AM UTC 24
Finished Sep 18 08:06:31 AM UTC 24
Peak memory 225760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1514005276 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_smoke.1514005276
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/25.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/25.i2c_target_stress_all.3213933575
Short name T1155
Test name
Test status
Simulation time 37502746586 ps
CPU time 257.05 seconds
Started Sep 18 08:06:28 AM UTC 24
Finished Sep 18 08:10:49 AM UTC 24
Peak memory 3062628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=321393
3575 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_stress_all.3213933575
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/25.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/25.i2c_target_stress_rd.1413163683
Short name T918
Test name
Test status
Simulation time 1211967058 ps
CPU time 18.14 seconds
Started Sep 18 08:06:16 AM UTC 24
Finished Sep 18 08:06:35 AM UTC 24
Peak memory 242448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1413163683 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_stress_rd.1413163683
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/25.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/25.i2c_target_stress_wr.345628977
Short name T997
Test name
Test status
Simulation time 41053787593 ps
CPU time 100.15 seconds
Started Sep 18 08:06:15 AM UTC 24
Finished Sep 18 08:07:57 AM UTC 24
Peak memory 1432336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=345628977 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_stress_wr.345628977
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/25.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/25.i2c_target_stretch.3321903564
Short name T975
Test name
Test status
Simulation time 5548517981 ps
CPU time 83.3 seconds
Started Sep 18 08:06:17 AM UTC 24
Finished Sep 18 08:07:42 AM UTC 24
Peak memory 691024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3321903564 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_stretch.3321903564
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/25.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/25.i2c_target_timeout.1119530615
Short name T913
Test name
Test status
Simulation time 6512637644 ps
CPU time 6.25 seconds
Started Sep 18 08:06:23 AM UTC 24
Finished Sep 18 08:06:30 AM UTC 24
Peak memory 232300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1119530
615 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_timeout.1119530615
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/25.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/25.i2c_target_tx_stretch_ctrl.607814610
Short name T923
Test name
Test status
Simulation time 88693213 ps
CPU time 3.82 seconds
Started Sep 18 08:06:33 AM UTC 24
Finished Sep 18 08:06:38 AM UTC 24
Peak memory 215320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6078146
10 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_tx_stretch_ctrl.607814610
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/25.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/26.i2c_alert_test.2313791742
Short name T957
Test name
Test status
Simulation time 16960390 ps
CPU time 1 seconds
Started Sep 18 08:07:20 AM UTC 24
Finished Sep 18 08:07:22 AM UTC 24
Peak memory 214840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2313791742 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_alert_test.2313791742
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/26.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/26.i2c_host_error_intr.3795463549
Short name T936
Test name
Test status
Simulation time 104326191 ps
CPU time 2.79 seconds
Started Sep 18 08:06:43 AM UTC 24
Finished Sep 18 08:06:47 AM UTC 24
Peak memory 225720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3795463549 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 26.i2c_host_error_intr.3795463549
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/26.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/26.i2c_host_fifo_fmt_empty.2423657156
Short name T935
Test name
Test status
Simulation time 198827984 ps
CPU time 3.69 seconds
Started Sep 18 08:06:40 AM UTC 24
Finished Sep 18 08:06:46 AM UTC 24
Peak memory 248464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2423657156 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_fmt_empty.2423657156
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/26.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/26.i2c_host_fifo_full.1817646827
Short name T1001
Test name
Test status
Simulation time 11134265805 ps
CPU time 77.11 seconds
Started Sep 18 08:06:42 AM UTC 24
Finished Sep 18 08:08:01 AM UTC 24
Peak memory 443252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1817646827 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_full.1817646827
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/26.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/26.i2c_host_fifo_overflow.4007259809
Short name T1083
Test name
Test status
Simulation time 2547068248 ps
CPU time 167.53 seconds
Started Sep 18 08:06:40 AM UTC 24
Finished Sep 18 08:09:31 AM UTC 24
Peak memory 830236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4007259809 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_overflow.4007259809
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/26.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/26.i2c_host_fifo_reset_fmt.530743313
Short name T934
Test name
Test status
Simulation time 138121836 ps
CPU time 1.55 seconds
Started Sep 18 08:06:40 AM UTC 24
Finished Sep 18 08:06:43 AM UTC 24
Peak memory 215044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=530743313 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_fmt.530743313
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/26.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/26.i2c_host_fifo_reset_rx.1878706217
Short name T938
Test name
Test status
Simulation time 866271641 ps
CPU time 11.07 seconds
Started Sep 18 08:06:40 AM UTC 24
Finished Sep 18 08:06:53 AM UTC 24
Peak memory 215168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1878706217 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_rx.1878706217
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/26.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/26.i2c_host_fifo_watermark.2428642150
Short name T1023
Test name
Test status
Simulation time 9754470178 ps
CPU time 105.63 seconds
Started Sep 18 08:06:39 AM UTC 24
Finished Sep 18 08:08:28 AM UTC 24
Peak memory 1436512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2428642150 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_watermark.2428642150
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/26.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/26.i2c_host_may_nack.1840554905
Short name T950
Test name
Test status
Simulation time 284235900 ps
CPU time 4.24 seconds
Started Sep 18 08:07:10 AM UTC 24
Finished Sep 18 08:07:15 AM UTC 24
Peak memory 215336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1840554905 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.i2c_host_may_nack.1840554905
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/26.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/26.i2c_host_override.2767240256
Short name T930
Test name
Test status
Simulation time 49139699 ps
CPU time 0.91 seconds
Started Sep 18 08:06:38 AM UTC 24
Finished Sep 18 08:06:40 AM UTC 24
Peak memory 214108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2767240256 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.i2c_host_override.2767240256
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/26.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/26.i2c_host_perf.450563567
Short name T966
Test name
Test status
Simulation time 7090442856 ps
CPU time 46.56 seconds
Started Sep 18 08:06:42 AM UTC 24
Finished Sep 18 08:07:30 AM UTC 24
Peak memory 314336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=450563567 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 26.i2c_host_perf.450563567
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/26.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/26.i2c_host_perf_precise.3850847854
Short name T961
Test name
Test status
Simulation time 2048230749 ps
CPU time 40.77 seconds
Started Sep 18 08:06:42 AM UTC 24
Finished Sep 18 08:07:24 AM UTC 24
Peak memory 215392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3850847854 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_perf_precise.3850847854
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/26.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/26.i2c_host_smoke.1256177835
Short name T953
Test name
Test status
Simulation time 9843702171 ps
CPU time 39.22 seconds
Started Sep 18 08:06:38 AM UTC 24
Finished Sep 18 08:07:19 AM UTC 24
Peak memory 426848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1256177835 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 26.i2c_host_smoke.1256177835
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/26.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/26.i2c_host_stretch_timeout.3137694137
Short name T952
Test name
Test status
Simulation time 1348982092 ps
CPU time 35.08 seconds
Started Sep 18 08:06:42 AM UTC 24
Finished Sep 18 08:07:19 AM UTC 24
Peak memory 225504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3137694137 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_stretch_timeout.3137694137
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/26.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/26.i2c_target_bad_addr.1252132661
Short name T949
Test name
Test status
Simulation time 8244750386 ps
CPU time 7.94 seconds
Started Sep 18 08:07:06 AM UTC 24
Finished Sep 18 08:07:15 AM UTC 24
Peak memory 232496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=1252132661 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_bad_ad
dr.1252132661
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/26.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/26.i2c_target_fifo_reset_acq.4003602405
Short name T945
Test name
Test status
Simulation time 327086791 ps
CPU time 1.7 seconds
Started Sep 18 08:07:03 AM UTC 24
Finished Sep 18 08:07:05 AM UTC 24
Peak memory 214780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4003602
405 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_fifo_reset_acq.4003602405
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/26.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/26.i2c_target_fifo_reset_tx.3060529113
Short name T946
Test name
Test status
Simulation time 957637611 ps
CPU time 1.29 seconds
Started Sep 18 08:07:04 AM UTC 24
Finished Sep 18 08:07:06 AM UTC 24
Peak memory 214904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3060529
113 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_fifo_reset_tx.3060529113
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/26.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/26.i2c_target_fifo_watermarks_acq.1346028334
Short name T951
Test name
Test status
Simulation time 12194044575 ps
CPU time 3.58 seconds
Started Sep 18 08:07:11 AM UTC 24
Finished Sep 18 08:07:16 AM UTC 24
Peak memory 215300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1346028
334 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_fifo_watermar
ks_acq.1346028334
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/26.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/26.i2c_target_fifo_watermarks_tx.3551970736
Short name T922
Test name
Test status
Simulation time 138429841 ps
CPU time 2.33 seconds
Started Sep 18 08:07:12 AM UTC 24
Finished Sep 18 08:07:15 AM UTC 24
Peak memory 215116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3551970
736 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_fifo_watermark
s_tx.3551970736
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/26.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/26.i2c_target_intr_smoke.1806078260
Short name T941
Test name
Test status
Simulation time 4077047549 ps
CPU time 6.64 seconds
Started Sep 18 08:06:54 AM UTC 24
Finished Sep 18 08:07:02 AM UTC 24
Peak memory 229728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=180607
8260 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_intr_smoke.1806078260
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/26.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/26.i2c_target_intr_stress_wr.2234273872
Short name T1201
Test name
Test status
Simulation time 25431949744 ps
CPU time 292.94 seconds
Started Sep 18 08:06:55 AM UTC 24
Finished Sep 18 08:11:52 AM UTC 24
Peak memory 3896164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2234273872 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_intr_stres
s_wr.2234273872
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/26.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/26.i2c_target_nack_acqfull.2898883830
Short name T958
Test name
Test status
Simulation time 552934351 ps
CPU time 4.35 seconds
Started Sep 18 08:07:16 AM UTC 24
Finished Sep 18 08:07:22 AM UTC 24
Peak memory 225568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2898883
830 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_nack_acqfull.2898883830
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/26.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/26.i2c_target_nack_acqfull_addr.3642617042
Short name T48
Test name
Test status
Simulation time 1052906190 ps
CPU time 3.17 seconds
Started Sep 18 08:07:16 AM UTC 24
Finished Sep 18 08:07:21 AM UTC 24
Peak memory 215404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3642617
042 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_nack_acqfull_ad
dr.3642617042
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/26.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/26.i2c_target_perf.1545381195
Short name T948
Test name
Test status
Simulation time 13073546853 ps
CPU time 6 seconds
Started Sep 18 08:07:04 AM UTC 24
Finished Sep 18 08:07:11 AM UTC 24
Peak memory 242468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1545381
195 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_perf.1545381195
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/26.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/26.i2c_target_smbus_maxlen.3898504262
Short name T956
Test name
Test status
Simulation time 483557679 ps
CPU time 3.86 seconds
Started Sep 18 08:07:16 AM UTC 24
Finished Sep 18 08:07:21 AM UTC 24
Peak memory 215072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3898504
262 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_smbus_maxlen.3898504262
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/26.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/26.i2c_target_smoke.4250657360
Short name T940
Test name
Test status
Simulation time 3077218322 ps
CPU time 10.36 seconds
Started Sep 18 08:06:44 AM UTC 24
Finished Sep 18 08:06:56 AM UTC 24
Peak memory 225696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4250657360 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_smoke.4250657360
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/26.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/26.i2c_target_stress_all.78048439
Short name T979
Test name
Test status
Simulation time 22223279317 ps
CPU time 37.16 seconds
Started Sep 18 08:07:06 AM UTC 24
Finished Sep 18 08:07:44 AM UTC 24
Peak memory 275308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=780484
39 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_stress_all.78048439
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/26.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/26.i2c_target_stress_rd.1698961348
Short name T954
Test name
Test status
Simulation time 1654616688 ps
CPU time 31.54 seconds
Started Sep 18 08:06:47 AM UTC 24
Finished Sep 18 08:07:20 AM UTC 24
Peak memory 248748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1698961348 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_stress_rd.1698961348
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/26.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/26.i2c_target_stress_wr.1743836193
Short name T969
Test name
Test status
Simulation time 15278186198 ps
CPU time 50.68 seconds
Started Sep 18 08:06:46 AM UTC 24
Finished Sep 18 08:07:38 AM UTC 24
Peak memory 215372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1743836193 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_stress_wr.1743836193
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/26.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/26.i2c_target_stretch.1859891782
Short name T943
Test name
Test status
Simulation time 2624646222 ps
CPU time 13.87 seconds
Started Sep 18 08:06:48 AM UTC 24
Finished Sep 18 08:07:03 AM UTC 24
Peak memory 289636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1859891782 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_stretch.1859891782
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/26.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/26.i2c_target_timeout.2236473176
Short name T947
Test name
Test status
Simulation time 1473153218 ps
CPU time 11.61 seconds
Started Sep 18 08:06:56 AM UTC 24
Finished Sep 18 08:07:09 AM UTC 24
Peak memory 232228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2236473
176 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_timeout.2236473176
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/26.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/26.i2c_target_tx_stretch_ctrl.1457796943
Short name T955
Test name
Test status
Simulation time 339980964 ps
CPU time 4.49 seconds
Started Sep 18 08:07:15 AM UTC 24
Finished Sep 18 08:07:21 AM UTC 24
Peak memory 215248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1457796
943 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_tx_stretch_ctrl.1457796943
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/26.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/27.i2c_alert_test.2214577669
Short name T988
Test name
Test status
Simulation time 16535816 ps
CPU time 0.94 seconds
Started Sep 18 08:07:50 AM UTC 24
Finished Sep 18 08:07:52 AM UTC 24
Peak memory 214840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2214577669 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_alert_test.2214577669
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/27.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/27.i2c_host_error_intr.3692223801
Short name T967
Test name
Test status
Simulation time 231241761 ps
CPU time 2.63 seconds
Started Sep 18 08:07:26 AM UTC 24
Finished Sep 18 08:07:30 AM UTC 24
Peak memory 225648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3692223801 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 27.i2c_host_error_intr.3692223801
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/27.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/27.i2c_host_fifo_fmt_empty.3644581476
Short name T968
Test name
Test status
Simulation time 1283041579 ps
CPU time 8.41 seconds
Started Sep 18 08:07:23 AM UTC 24
Finished Sep 18 08:07:33 AM UTC 24
Peak memory 285404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3644581476 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_fmt_empty.3644581476
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/27.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/27.i2c_host_fifo_full.3035322783
Short name T1048
Test name
Test status
Simulation time 1515627972 ps
CPU time 89.89 seconds
Started Sep 18 08:07:24 AM UTC 24
Finished Sep 18 08:08:56 AM UTC 24
Peak memory 420556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3035322783 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_full.3035322783
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/27.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/27.i2c_host_fifo_overflow.4136265899
Short name T1032
Test name
Test status
Simulation time 2256168303 ps
CPU time 74.45 seconds
Started Sep 18 08:07:22 AM UTC 24
Finished Sep 18 08:08:38 AM UTC 24
Peak memory 746268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4136265899 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_overflow.4136265899
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/27.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/27.i2c_host_fifo_reset_fmt.651085641
Short name T962
Test name
Test status
Simulation time 97424561 ps
CPU time 1.58 seconds
Started Sep 18 08:07:23 AM UTC 24
Finished Sep 18 08:07:26 AM UTC 24
Peak memory 214904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=651085641 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_fmt.651085641
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/27.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/27.i2c_host_fifo_reset_rx.1700984425
Short name T965
Test name
Test status
Simulation time 586907160 ps
CPU time 4.83 seconds
Started Sep 18 08:07:24 AM UTC 24
Finished Sep 18 08:07:30 AM UTC 24
Peak memory 242340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1700984425 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_rx.1700984425
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/27.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/27.i2c_host_fifo_watermark.3155755289
Short name T1053
Test name
Test status
Simulation time 20613155420 ps
CPU time 95.32 seconds
Started Sep 18 08:07:22 AM UTC 24
Finished Sep 18 08:08:59 AM UTC 24
Peak memory 1393436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3155755289 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_watermark.3155755289
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/27.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/27.i2c_host_may_nack.2496526364
Short name T1006
Test name
Test status
Simulation time 719756508 ps
CPU time 24.24 seconds
Started Sep 18 08:07:44 AM UTC 24
Finished Sep 18 08:08:09 AM UTC 24
Peak memory 215336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2496526364 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.i2c_host_may_nack.2496526364
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/27.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/27.i2c_host_override.1682860064
Short name T154
Test name
Test status
Simulation time 47379030 ps
CPU time 1.03 seconds
Started Sep 18 08:07:22 AM UTC 24
Finished Sep 18 08:07:24 AM UTC 24
Peak memory 214112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1682860064 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.i2c_host_override.1682860064
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/27.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/27.i2c_host_perf.1699464320
Short name T1140
Test name
Test status
Simulation time 50954322101 ps
CPU time 190.12 seconds
Started Sep 18 08:07:24 AM UTC 24
Finished Sep 18 08:10:37 AM UTC 24
Peak memory 787384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1699464320 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 27.i2c_host_perf.1699464320
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/27.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/27.i2c_host_perf_precise.3077611473
Short name T983
Test name
Test status
Simulation time 456281247 ps
CPU time 21.32 seconds
Started Sep 18 08:07:25 AM UTC 24
Finished Sep 18 08:07:48 AM UTC 24
Peak memory 215120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3077611473 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_perf_precise.3077611473
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/27.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/27.i2c_host_smoke.2812271260
Short name T1067
Test name
Test status
Simulation time 8209535365 ps
CPU time 108.52 seconds
Started Sep 18 08:07:21 AM UTC 24
Finished Sep 18 08:09:11 AM UTC 24
Peak memory 449512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2812271260 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 27.i2c_host_smoke.2812271260
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/27.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/27.i2c_host_stress_all.843574775
Short name T273
Test name
Test status
Simulation time 18736206808 ps
CPU time 514.72 seconds
Started Sep 18 08:07:27 AM UTC 24
Finished Sep 18 08:16:08 AM UTC 24
Peak memory 1092524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=843574775 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 27.i2c_host_stress_all.843574775
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/27.i2c_host_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/27.i2c_host_stretch_timeout.759379393
Short name T976
Test name
Test status
Simulation time 2908340385 ps
CPU time 15.19 seconds
Started Sep 18 08:07:25 AM UTC 24
Finished Sep 18 08:07:42 AM UTC 24
Peak memory 227692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=759379393 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_stretch_timeout.759379393
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/27.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/27.i2c_target_bad_addr.672165464
Short name T986
Test name
Test status
Simulation time 5414606844 ps
CPU time 7.96 seconds
Started Sep 18 08:07:42 AM UTC 24
Finished Sep 18 08:07:51 AM UTC 24
Peak memory 232344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=672165464 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_bad_addr.672165464
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/27.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/27.i2c_target_fifo_reset_acq.3008474687
Short name T977
Test name
Test status
Simulation time 251586720 ps
CPU time 2.15 seconds
Started Sep 18 08:07:39 AM UTC 24
Finished Sep 18 08:07:42 AM UTC 24
Peak memory 215256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3008474
687 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_fifo_reset_acq.3008474687
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/27.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/27.i2c_target_fifo_reset_tx.1058204173
Short name T978
Test name
Test status
Simulation time 369742779 ps
CPU time 1.43 seconds
Started Sep 18 08:07:40 AM UTC 24
Finished Sep 18 08:07:43 AM UTC 24
Peak memory 214904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1058204
173 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_fifo_reset_tx.1058204173
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/27.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/27.i2c_target_fifo_watermarks_acq.2208235400
Short name T985
Test name
Test status
Simulation time 1115424743 ps
CPU time 4.42 seconds
Started Sep 18 08:07:44 AM UTC 24
Finished Sep 18 08:07:49 AM UTC 24
Peak memory 215336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2208235
400 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_fifo_watermar
ks_acq.2208235400
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/27.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/27.i2c_target_fifo_watermarks_tx.2647605325
Short name T982
Test name
Test status
Simulation time 611886434 ps
CPU time 1.69 seconds
Started Sep 18 08:07:45 AM UTC 24
Finished Sep 18 08:07:47 AM UTC 24
Peak memory 214852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2647605
325 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_fifo_watermark
s_tx.2647605325
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/27.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/27.i2c_target_intr_smoke.3006676410
Short name T972
Test name
Test status
Simulation time 1274697817 ps
CPU time 7.31 seconds
Started Sep 18 08:07:31 AM UTC 24
Finished Sep 18 08:07:39 AM UTC 24
Peak memory 225816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=300667
6410 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_intr_smoke.3006676410
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/27.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/27.i2c_target_intr_stress_wr.489407314
Short name T1044
Test name
Test status
Simulation time 16056883760 ps
CPU time 80.3 seconds
Started Sep 18 08:07:33 AM UTC 24
Finished Sep 18 08:08:55 AM UTC 24
Peak memory 2018076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=489407314 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_intr_stress
_wr.489407314
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/27.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/27.i2c_target_nack_acqfull.1600427623
Short name T990
Test name
Test status
Simulation time 1166367478 ps
CPU time 3.83 seconds
Started Sep 18 08:07:48 AM UTC 24
Finished Sep 18 08:07:53 AM UTC 24
Peak memory 225636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1600427
623 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_nack_acqfull.1600427623
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/27.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/27.i2c_target_nack_acqfull_addr.2331237193
Short name T992
Test name
Test status
Simulation time 588365200 ps
CPU time 4.51 seconds
Started Sep 18 08:07:49 AM UTC 24
Finished Sep 18 08:07:55 AM UTC 24
Peak memory 215196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2331237
193 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_nack_acqfull_ad
dr.2331237193
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/27.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/27.i2c_target_nack_txstretch.4210450926
Short name T991
Test name
Test status
Simulation time 535643896 ps
CPU time 2.45 seconds
Started Sep 18 08:07:50 AM UTC 24
Finished Sep 18 08:07:54 AM UTC 24
Peak memory 232352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4210450
926 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_nack_txstretch.4210450926
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/27.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/27.i2c_target_perf.541691242
Short name T989
Test name
Test status
Simulation time 812819156 ps
CPU time 10.22 seconds
Started Sep 18 08:07:41 AM UTC 24
Finished Sep 18 08:07:53 AM UTC 24
Peak memory 234416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5416912
42 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_perf.541691242
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/27.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/27.i2c_target_smbus_maxlen.622425290
Short name T987
Test name
Test status
Simulation time 609575177 ps
CPU time 4.26 seconds
Started Sep 18 08:07:47 AM UTC 24
Finished Sep 18 08:07:52 AM UTC 24
Peak memory 215100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6224252
90 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_smbus_maxlen.622425290
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/27.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/27.i2c_target_smoke.3602841472
Short name T970
Test name
Test status
Simulation time 3157970839 ps
CPU time 9.48 seconds
Started Sep 18 08:07:28 AM UTC 24
Finished Sep 18 08:07:38 AM UTC 24
Peak memory 227872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3602841472 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_smoke.3602841472
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/27.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/27.i2c_target_stress_all.2686290580
Short name T1111
Test name
Test status
Simulation time 56388346184 ps
CPU time 140.94 seconds
Started Sep 18 08:07:42 AM UTC 24
Finished Sep 18 08:10:06 AM UTC 24
Peak memory 1602408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=268629
0580 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_stress_all.2686290580
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/27.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/27.i2c_target_stress_rd.3702276493
Short name T971
Test name
Test status
Simulation time 1754897002 ps
CPU time 6.52 seconds
Started Sep 18 08:07:31 AM UTC 24
Finished Sep 18 08:07:38 AM UTC 24
Peak memory 215384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3702276493 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_stress_rd.3702276493
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/27.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/27.i2c_target_stress_wr.1778031734
Short name T1532
Test name
Test status
Simulation time 47236543038 ps
CPU time 600.61 seconds
Started Sep 18 08:07:28 AM UTC 24
Finished Sep 18 08:17:34 AM UTC 24
Peak memory 7087072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1778031734 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_stress_wr.1778031734
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/27.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/27.i2c_target_stretch.1728234091
Short name T994
Test name
Test status
Simulation time 574037711 ps
CPU time 23.01 seconds
Started Sep 18 08:07:31 AM UTC 24
Finished Sep 18 08:07:55 AM UTC 24
Peak memory 299792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1728234091 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_stretch.1728234091
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/27.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/27.i2c_target_timeout.3676504477
Short name T984
Test name
Test status
Simulation time 5075760017 ps
CPU time 8.87 seconds
Started Sep 18 08:07:39 AM UTC 24
Finished Sep 18 08:07:49 AM UTC 24
Peak memory 225628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3676504
477 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_timeout.3676504477
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/27.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/27.i2c_target_tx_stretch_ctrl.3935486360
Short name T998
Test name
Test status
Simulation time 459955676 ps
CPU time 9.88 seconds
Started Sep 18 08:07:47 AM UTC 24
Finished Sep 18 08:07:58 AM UTC 24
Peak memory 215452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3935486
360 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_tx_stretch_ctrl.3935486360
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/27.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/28.i2c_alert_test.4176946823
Short name T1024
Test name
Test status
Simulation time 46527017 ps
CPU time 0.97 seconds
Started Sep 18 08:08:26 AM UTC 24
Finished Sep 18 08:08:28 AM UTC 24
Peak memory 214252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4176946823 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_alert_test.4176946823
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/28.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/28.i2c_host_error_intr.3568367436
Short name T1005
Test name
Test status
Simulation time 213757028 ps
CPU time 5.05 seconds
Started Sep 18 08:07:58 AM UTC 24
Finished Sep 18 08:08:04 AM UTC 24
Peak memory 225592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3568367436 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 28.i2c_host_error_intr.3568367436
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/28.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/28.i2c_host_fifo_fmt_empty.3936282824
Short name T1021
Test name
Test status
Simulation time 1054151222 ps
CPU time 29.79 seconds
Started Sep 18 08:07:55 AM UTC 24
Finished Sep 18 08:08:26 AM UTC 24
Peak memory 334612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3936282824 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_fmt_empty.3936282824
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/28.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/28.i2c_host_fifo_full.768658769
Short name T1078
Test name
Test status
Simulation time 12563510539 ps
CPU time 88.85 seconds
Started Sep 18 08:07:56 AM UTC 24
Finished Sep 18 08:09:26 AM UTC 24
Peak memory 551912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=768658769 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_full.768658769
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/28.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/28.i2c_host_fifo_overflow.1946009424
Short name T1137
Test name
Test status
Simulation time 8383367605 ps
CPU time 159.39 seconds
Started Sep 18 08:07:53 AM UTC 24
Finished Sep 18 08:10:36 AM UTC 24
Peak memory 770864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1946009424 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_overflow.1946009424
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/28.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/28.i2c_host_fifo_reset_fmt.3922902132
Short name T996
Test name
Test status
Simulation time 214971121 ps
CPU time 1.46 seconds
Started Sep 18 08:07:54 AM UTC 24
Finished Sep 18 08:07:56 AM UTC 24
Peak memory 214900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3922902132 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_fmt.3922902132
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/28.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/28.i2c_host_fifo_reset_rx.3845685050
Short name T1003
Test name
Test status
Simulation time 163164833 ps
CPU time 6.69 seconds
Started Sep 18 08:07:56 AM UTC 24
Finished Sep 18 08:08:03 AM UTC 24
Peak memory 240360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3845685050 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_rx.3845685050
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/28.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/28.i2c_host_fifo_watermark.2988452995
Short name T1063
Test name
Test status
Simulation time 2893586137 ps
CPU time 71.48 seconds
Started Sep 18 08:07:53 AM UTC 24
Finished Sep 18 08:09:07 AM UTC 24
Peak memory 820176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2988452995 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_watermark.2988452995
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/28.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/28.i2c_host_may_nack.3186170883
Short name T1015
Test name
Test status
Simulation time 982661619 ps
CPU time 8.27 seconds
Started Sep 18 08:08:19 AM UTC 24
Finished Sep 18 08:08:29 AM UTC 24
Peak memory 215324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3186170883 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.i2c_host_may_nack.3186170883
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/28.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/28.i2c_host_override.2556357871
Short name T995
Test name
Test status
Simulation time 44327976 ps
CPU time 0.91 seconds
Started Sep 18 08:07:53 AM UTC 24
Finished Sep 18 08:07:55 AM UTC 24
Peak memory 214112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2556357871 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.i2c_host_override.2556357871
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/28.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/28.i2c_host_perf.591288866
Short name T1185
Test name
Test status
Simulation time 48439760296 ps
CPU time 210.9 seconds
Started Sep 18 08:07:56 AM UTC 24
Finished Sep 18 08:11:30 AM UTC 24
Peak memory 1330012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=591288866 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 28.i2c_host_perf.591288866
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/28.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/28.i2c_host_perf_precise.2596973183
Short name T999
Test name
Test status
Simulation time 270044915 ps
CPU time 2.27 seconds
Started Sep 18 08:07:56 AM UTC 24
Finished Sep 18 08:07:59 AM UTC 24
Peak memory 215124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2596973183 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_perf_precise.2596973183
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/28.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/28.i2c_host_smoke.3080491097
Short name T1030
Test name
Test status
Simulation time 1927870165 ps
CPU time 43.55 seconds
Started Sep 18 08:07:52 AM UTC 24
Finished Sep 18 08:08:37 AM UTC 24
Peak memory 434916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3080491097 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 28.i2c_host_smoke.3080491097
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/28.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/28.i2c_host_stress_all.681200065
Short name T21
Test name
Test status
Simulation time 22493597110 ps
CPU time 798.91 seconds
Started Sep 18 08:07:59 AM UTC 24
Finished Sep 18 08:21:27 AM UTC 24
Peak memory 2175796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=681200065 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 28.i2c_host_stress_all.681200065
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/28.i2c_host_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/28.i2c_host_stretch_timeout.684242337
Short name T1014
Test name
Test status
Simulation time 1938445051 ps
CPU time 21.44 seconds
Started Sep 18 08:07:57 AM UTC 24
Finished Sep 18 08:08:20 AM UTC 24
Peak memory 225488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=684242337 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_stretch_timeout.684242337
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/28.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/28.i2c_target_bad_addr.1843847165
Short name T974
Test name
Test status
Simulation time 10285760694 ps
CPU time 9.1 seconds
Started Sep 18 08:08:18 AM UTC 24
Finished Sep 18 08:08:28 AM UTC 24
Peak memory 225704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=1843847165 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_bad_ad
dr.1843847165
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/28.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/28.i2c_target_fifo_reset_acq.4010387657
Short name T1008
Test name
Test status
Simulation time 141253869 ps
CPU time 1.59 seconds
Started Sep 18 08:08:12 AM UTC 24
Finished Sep 18 08:08:14 AM UTC 24
Peak memory 214780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4010387
657 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_fifo_reset_acq.4010387657
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/28.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/28.i2c_target_fifo_reset_tx.2270963437
Short name T1011
Test name
Test status
Simulation time 222306722 ps
CPU time 2.54 seconds
Started Sep 18 08:08:14 AM UTC 24
Finished Sep 18 08:08:17 AM UTC 24
Peak memory 215324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2270963
437 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_fifo_reset_tx.2270963437
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/28.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/28.i2c_target_fifo_watermarks_acq.1683193246
Short name T1020
Test name
Test status
Simulation time 1069646670 ps
CPU time 4.06 seconds
Started Sep 18 08:08:20 AM UTC 24
Finished Sep 18 08:08:25 AM UTC 24
Peak memory 215316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1683193
246 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_fifo_watermar
ks_acq.1683193246
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/28.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/28.i2c_target_fifo_watermarks_tx.3659518186
Short name T1019
Test name
Test status
Simulation time 443003337 ps
CPU time 1.74 seconds
Started Sep 18 08:08:21 AM UTC 24
Finished Sep 18 08:08:24 AM UTC 24
Peak memory 214852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3659518
186 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_fifo_watermark
s_tx.3659518186
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/28.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/28.i2c_target_hrst.695388146
Short name T1018
Test name
Test status
Simulation time 293905099 ps
CPU time 4.06 seconds
Started Sep 18 08:08:18 AM UTC 24
Finished Sep 18 08:08:23 AM UTC 24
Peak memory 225572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6953881
46 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_hrst.695388146
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/28.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/28.i2c_target_intr_smoke.1348678190
Short name T1013
Test name
Test status
Simulation time 1455810484 ps
CPU time 12.41 seconds
Started Sep 18 08:08:04 AM UTC 24
Finished Sep 18 08:08:18 AM UTC 24
Peak memory 232432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=134867
8190 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_intr_smoke.1348678190
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/28.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/28.i2c_target_intr_stress_wr.223003980
Short name T1101
Test name
Test status
Simulation time 14596094486 ps
CPU time 108.85 seconds
Started Sep 18 08:08:05 AM UTC 24
Finished Sep 18 08:09:55 AM UTC 24
Peak memory 1917788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=223003980 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_intr_stress
_wr.223003980
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/28.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/28.i2c_target_nack_acqfull.2378192493
Short name T959
Test name
Test status
Simulation time 6141303765 ps
CPU time 3.61 seconds
Started Sep 18 08:08:24 AM UTC 24
Finished Sep 18 08:08:28 AM UTC 24
Peak memory 225688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2378192
493 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_nack_acqfull.2378192493
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/28.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/28.i2c_target_nack_acqfull_addr.1816932397
Short name T1025
Test name
Test status
Simulation time 1740330825 ps
CPU time 3.24 seconds
Started Sep 18 08:08:25 AM UTC 24
Finished Sep 18 08:08:29 AM UTC 24
Peak memory 215336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1816932
397 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_nack_acqfull_ad
dr.1816932397
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/28.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/28.i2c_target_perf.1053779506
Short name T1017
Test name
Test status
Simulation time 2189857882 ps
CPU time 6.42 seconds
Started Sep 18 08:08:15 AM UTC 24
Finished Sep 18 08:08:23 AM UTC 24
Peak memory 225564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1053779
506 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_perf.1053779506
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/28.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/28.i2c_target_smbus_maxlen.118283749
Short name T1022
Test name
Test status
Simulation time 450697554 ps
CPU time 3.09 seconds
Started Sep 18 08:08:23 AM UTC 24
Finished Sep 18 08:08:28 AM UTC 24
Peak memory 215116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1182837
49 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_smbus_maxlen.118283749
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/28.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/28.i2c_target_smoke.3072301323
Short name T1010
Test name
Test status
Simulation time 3401169843 ps
CPU time 16.06 seconds
Started Sep 18 08:08:00 AM UTC 24
Finished Sep 18 08:08:17 AM UTC 24
Peak memory 225624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3072301323 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_smoke.3072301323
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/28.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/28.i2c_target_stress_all.1620915591
Short name T1047
Test name
Test status
Simulation time 84993281624 ps
CPU time 37.9 seconds
Started Sep 18 08:08:16 AM UTC 24
Finished Sep 18 08:08:56 AM UTC 24
Peak memory 279404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=162091
5591 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_stress_all.1620915591
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/28.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/28.i2c_target_stress_rd.2055796406
Short name T1009
Test name
Test status
Simulation time 785190400 ps
CPU time 12.62 seconds
Started Sep 18 08:08:01 AM UTC 24
Finished Sep 18 08:08:15 AM UTC 24
Peak memory 229844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2055796406 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_stress_rd.2055796406
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/28.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/28.i2c_target_stress_wr.3843712798
Short name T1718
Test name
Test status
Simulation time 51256771284 ps
CPU time 762.56 seconds
Started Sep 18 08:08:01 AM UTC 24
Finished Sep 18 08:20:51 AM UTC 24
Peak memory 8307544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3843712798 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_stress_wr.3843712798
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/28.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/28.i2c_target_stretch.1928598147
Short name T1007
Test name
Test status
Simulation time 1175803513 ps
CPU time 7.03 seconds
Started Sep 18 08:08:03 AM UTC 24
Finished Sep 18 08:08:11 AM UTC 24
Peak memory 225580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1928598147 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_stretch.1928598147
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/28.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/28.i2c_target_timeout.3591632192
Short name T1012
Test name
Test status
Simulation time 2849190702 ps
CPU time 11.86 seconds
Started Sep 18 08:08:05 AM UTC 24
Finished Sep 18 08:08:17 AM UTC 24
Peak memory 225616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3591632
192 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_timeout.3591632192
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/28.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/28.i2c_target_tx_stretch_ctrl.1030659651
Short name T1026
Test name
Test status
Simulation time 140744154 ps
CPU time 4.42 seconds
Started Sep 18 08:08:22 AM UTC 24
Finished Sep 18 08:08:28 AM UTC 24
Peak memory 215456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1030659
651 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_tx_stretch_ctrl.1030659651
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/28.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/29.i2c_alert_test.3802553574
Short name T1059
Test name
Test status
Simulation time 18677173 ps
CPU time 0.96 seconds
Started Sep 18 08:09:00 AM UTC 24
Finished Sep 18 08:09:02 AM UTC 24
Peak memory 214840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3802553574 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_alert_test.3802553574
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/29.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/29.i2c_host_error_intr.965298080
Short name T1029
Test name
Test status
Simulation time 68016104 ps
CPU time 1.87 seconds
Started Sep 18 08:08:33 AM UTC 24
Finished Sep 18 08:08:36 AM UTC 24
Peak memory 224736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=965298080 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 29.i2c_host_error_intr.965298080
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/29.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/29.i2c_host_fifo_fmt_empty.3308523262
Short name T1033
Test name
Test status
Simulation time 1348214955 ps
CPU time 9.19 seconds
Started Sep 18 08:08:29 AM UTC 24
Finished Sep 18 08:08:40 AM UTC 24
Peak memory 281308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3308523262 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_fmt_empty.3308523262
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/29.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/29.i2c_host_fifo_full.455411635
Short name T1118
Test name
Test status
Simulation time 4132693959 ps
CPU time 98.01 seconds
Started Sep 18 08:08:29 AM UTC 24
Finished Sep 18 08:10:10 AM UTC 24
Peak memory 225576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=455411635 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_full.455411635
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/29.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/29.i2c_host_fifo_overflow.3062017916
Short name T1091
Test name
Test status
Simulation time 1611262370 ps
CPU time 62.33 seconds
Started Sep 18 08:08:29 AM UTC 24
Finished Sep 18 08:09:33 AM UTC 24
Peak memory 625384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3062017916 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_overflow.3062017916
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/29.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/29.i2c_host_fifo_reset_fmt.2768419895
Short name T1027
Test name
Test status
Simulation time 437936917 ps
CPU time 1.64 seconds
Started Sep 18 08:08:29 AM UTC 24
Finished Sep 18 08:08:32 AM UTC 24
Peak memory 214900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2768419895 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_fmt.2768419895
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/29.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/29.i2c_host_fifo_reset_rx.3000853161
Short name T1028
Test name
Test status
Simulation time 1103795428 ps
CPU time 3.9 seconds
Started Sep 18 08:08:29 AM UTC 24
Finished Sep 18 08:08:35 AM UTC 24
Peak memory 240416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3000853161 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_rx.3000853161
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/29.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/29.i2c_host_fifo_watermark.746712389
Short name T1170
Test name
Test status
Simulation time 12351556655 ps
CPU time 154.19 seconds
Started Sep 18 08:08:28 AM UTC 24
Finished Sep 18 08:11:05 AM UTC 24
Peak memory 871136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=746712389 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_watermark.746712389
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/29.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/29.i2c_host_may_nack.2493411492
Short name T1051
Test name
Test status
Simulation time 332524173 ps
CPU time 3.94 seconds
Started Sep 18 08:08:54 AM UTC 24
Finished Sep 18 08:08:59 AM UTC 24
Peak memory 215336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2493411492 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.i2c_host_may_nack.2493411492
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/29.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/29.i2c_host_mode_toggle.1326432981
Short name T1049
Test name
Test status
Simulation time 490130338 ps
CPU time 3.77 seconds
Started Sep 18 08:08:53 AM UTC 24
Finished Sep 18 08:08:58 AM UTC 24
Peak memory 225492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1326432981 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_mode_toggle.1326432981
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/29.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/29.i2c_host_override.4204410670
Short name T980
Test name
Test status
Simulation time 32206298 ps
CPU time 1.07 seconds
Started Sep 18 08:08:28 AM UTC 24
Finished Sep 18 08:08:30 AM UTC 24
Peak memory 214112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4204410670 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.i2c_host_override.4204410670
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/29.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/29.i2c_host_perf.2703825379
Short name T38
Test name
Test status
Simulation time 310321244 ps
CPU time 16.31 seconds
Started Sep 18 08:08:29 AM UTC 24
Finished Sep 18 08:08:48 AM UTC 24
Peak memory 229588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2703825379 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 29.i2c_host_perf.2703825379
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/29.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/29.i2c_host_perf_precise.601089591
Short name T1031
Test name
Test status
Simulation time 213490702 ps
CPU time 6.01 seconds
Started Sep 18 08:08:30 AM UTC 24
Finished Sep 18 08:08:38 AM UTC 24
Peak memory 252712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=601089591 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_perf_precise.601089591
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/29.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/29.i2c_host_smoke.4229819147
Short name T1115
Test name
Test status
Simulation time 7920542495 ps
CPU time 99.44 seconds
Started Sep 18 08:08:27 AM UTC 24
Finished Sep 18 08:10:09 AM UTC 24
Peak memory 324516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4229819147 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.i2c_host_smoke.4229819147
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/29.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/29.i2c_host_stretch_timeout.443861287
Short name T1038
Test name
Test status
Simulation time 3454313126 ps
CPU time 16.12 seconds
Started Sep 18 08:08:31 AM UTC 24
Finished Sep 18 08:08:48 AM UTC 24
Peak memory 242484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=443861287 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_stretch_timeout.443861287
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/29.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/29.i2c_target_bad_addr.3619441214
Short name T1052
Test name
Test status
Simulation time 2868015428 ps
CPU time 6.44 seconds
Started Sep 18 08:08:52 AM UTC 24
Finished Sep 18 08:08:59 AM UTC 24
Peak memory 225828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=3619441214 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_bad_ad
dr.3619441214
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/29.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/29.i2c_target_fifo_reset_acq.1658047900
Short name T1040
Test name
Test status
Simulation time 484033502 ps
CPU time 1.59 seconds
Started Sep 18 08:08:48 AM UTC 24
Finished Sep 18 08:08:51 AM UTC 24
Peak memory 214784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1658047
900 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_fifo_reset_acq.1658047900
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/29.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/29.i2c_target_fifo_reset_tx.1504906223
Short name T1041
Test name
Test status
Simulation time 520482675 ps
CPU time 1.79 seconds
Started Sep 18 08:08:48 AM UTC 24
Finished Sep 18 08:08:51 AM UTC 24
Peak memory 224904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1504906
223 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_fifo_reset_tx.1504906223
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/29.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/29.i2c_target_fifo_watermarks_acq.13088320
Short name T1055
Test name
Test status
Simulation time 403200965 ps
CPU time 3.75 seconds
Started Sep 18 08:08:56 AM UTC 24
Finished Sep 18 08:09:01 AM UTC 24
Peak memory 215108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1308832
0 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_fifo_watermarks
_acq.13088320
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/29.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/29.i2c_target_fifo_watermarks_tx.986563582
Short name T1050
Test name
Test status
Simulation time 111718248 ps
CPU time 1.68 seconds
Started Sep 18 08:08:56 AM UTC 24
Finished Sep 18 08:08:59 AM UTC 24
Peak memory 214788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9865635
82 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_fifo_watermarks
_tx.986563582
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/29.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/29.i2c_target_intr_smoke.4125849939
Short name T1042
Test name
Test status
Simulation time 9561651033 ps
CPU time 9.7 seconds
Started Sep 18 08:08:41 AM UTC 24
Finished Sep 18 08:08:52 AM UTC 24
Peak memory 231768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=412584
9939 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_intr_smoke.4125849939
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/29.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/29.i2c_target_intr_stress_wr.582627590
Short name T1079
Test name
Test status
Simulation time 21194927311 ps
CPU time 41.92 seconds
Started Sep 18 08:08:44 AM UTC 24
Finished Sep 18 08:09:27 AM UTC 24
Peak memory 1080080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=582627590 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_intr_stress
_wr.582627590
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/29.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/29.i2c_target_nack_acqfull.3203350900
Short name T1060
Test name
Test status
Simulation time 2359139893 ps
CPU time 4.56 seconds
Started Sep 18 08:08:57 AM UTC 24
Finished Sep 18 08:09:03 AM UTC 24
Peak memory 225760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3203350
900 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_nack_acqfull.3203350900
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/29.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/29.i2c_target_nack_acqfull_addr.2091541018
Short name T1061
Test name
Test status
Simulation time 451406612 ps
CPU time 3.82 seconds
Started Sep 18 08:08:58 AM UTC 24
Finished Sep 18 08:09:03 AM UTC 24
Peak memory 215204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2091541
018 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_nack_acqfull_ad
dr.2091541018
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/29.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/29.i2c_target_perf.3051947517
Short name T1046
Test name
Test status
Simulation time 475621060 ps
CPU time 4.94 seconds
Started Sep 18 08:08:50 AM UTC 24
Finished Sep 18 08:08:55 AM UTC 24
Peak memory 225568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3051947
517 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_perf.3051947517
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/29.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/29.i2c_target_smbus_maxlen.3334403258
Short name T1054
Test name
Test status
Simulation time 617143835 ps
CPU time 3.21 seconds
Started Sep 18 08:08:56 AM UTC 24
Finished Sep 18 08:09:00 AM UTC 24
Peak memory 215144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3334403
258 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_smbus_maxlen.3334403258
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/29.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/29.i2c_target_smoke.518535113
Short name T1058
Test name
Test status
Simulation time 2337674563 ps
CPU time 23.54 seconds
Started Sep 18 08:08:37 AM UTC 24
Finished Sep 18 08:09:02 AM UTC 24
Peak memory 225736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=518535113 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_smoke.518535113
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/29.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/29.i2c_target_stress_all.2926856532
Short name T1089
Test name
Test status
Simulation time 27626032317 ps
CPU time 42.21 seconds
Started Sep 18 08:08:50 AM UTC 24
Finished Sep 18 08:09:33 AM UTC 24
Peak memory 281448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=292685
6532 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_stress_all.2926856532
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/29.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/29.i2c_target_stress_rd.2015608140
Short name T1039
Test name
Test status
Simulation time 545714083 ps
CPU time 8.76 seconds
Started Sep 18 08:08:39 AM UTC 24
Finished Sep 18 08:08:49 AM UTC 24
Peak memory 227612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2015608140 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_stress_rd.2015608140
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/29.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/29.i2c_target_stress_wr.682658054
Short name T1035
Test name
Test status
Simulation time 12160324787 ps
CPU time 5.14 seconds
Started Sep 18 08:08:38 AM UTC 24
Finished Sep 18 08:08:44 AM UTC 24
Peak memory 215388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=682658054 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_stress_wr.682658054
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/29.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/29.i2c_target_stretch.2343899762
Short name T1034
Test name
Test status
Simulation time 1324458585 ps
CPU time 2.89 seconds
Started Sep 18 08:08:39 AM UTC 24
Finished Sep 18 08:08:43 AM UTC 24
Peak memory 246492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2343899762 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_stretch.2343899762
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/29.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/29.i2c_target_timeout.4216547519
Short name T1043
Test name
Test status
Simulation time 1118921564 ps
CPU time 7.07 seconds
Started Sep 18 08:08:45 AM UTC 24
Finished Sep 18 08:08:53 AM UTC 24
Peak memory 225496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4216547
519 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_timeout.4216547519
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/29.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/29.i2c_target_tx_stretch_ctrl.3966358767
Short name T1064
Test name
Test status
Simulation time 350696227 ps
CPU time 9.76 seconds
Started Sep 18 08:08:56 AM UTC 24
Finished Sep 18 08:09:07 AM UTC 24
Peak memory 215328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3966358
767 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_tx_stretch_ctrl.3966358767
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/29.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/3.i2c_alert_test.1089852284
Short name T325
Test name
Test status
Simulation time 27852069 ps
CPU time 0.95 seconds
Started Sep 18 07:55:34 AM UTC 24
Finished Sep 18 07:55:36 AM UTC 24
Peak memory 214840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1089852284 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_alert_test.1089852284
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/3.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/3.i2c_host_error_intr.1117477278
Short name T26
Test name
Test status
Simulation time 1149411728 ps
CPU time 3.66 seconds
Started Sep 18 07:55:14 AM UTC 24
Finished Sep 18 07:55:19 AM UTC 24
Peak memory 225592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1117477278 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 3.i2c_host_error_intr.1117477278
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/3.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/3.i2c_host_fifo_fmt_empty.1806714255
Short name T246
Test name
Test status
Simulation time 946758050 ps
CPU time 7.33 seconds
Started Sep 18 07:55:13 AM UTC 24
Finished Sep 18 07:55:21 AM UTC 24
Peak memory 265060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1806714255 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_fmt_empty.1806714255
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/3.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/3.i2c_host_fifo_full.1966209325
Short name T434
Test name
Test status
Simulation time 12187493430 ps
CPU time 156.41 seconds
Started Sep 18 07:55:13 AM UTC 24
Finished Sep 18 07:57:52 AM UTC 24
Peak memory 656072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1966209325 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_full.1966209325
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/3.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/3.i2c_host_fifo_overflow.1139329433
Short name T107
Test name
Test status
Simulation time 11015049295 ps
CPU time 83.78 seconds
Started Sep 18 07:55:12 AM UTC 24
Finished Sep 18 07:56:37 AM UTC 24
Peak memory 854880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1139329433 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_overflow.1139329433
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/3.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/3.i2c_host_fifo_reset_rx.2999098805
Short name T191
Test name
Test status
Simulation time 487736194 ps
CPU time 5.07 seconds
Started Sep 18 07:55:13 AM UTC 24
Finished Sep 18 07:55:19 AM UTC 24
Peak memory 236256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2999098805 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_rx.2999098805
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/3.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/3.i2c_host_fifo_watermark.3610259836
Short name T84
Test name
Test status
Simulation time 15046823408 ps
CPU time 63.64 seconds
Started Sep 18 07:55:12 AM UTC 24
Finished Sep 18 07:56:17 AM UTC 24
Peak memory 1112984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3610259836 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_watermark.3610259836
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/3.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/3.i2c_host_may_nack.1376000620
Short name T31
Test name
Test status
Simulation time 1544058749 ps
CPU time 6.48 seconds
Started Sep 18 07:55:27 AM UTC 24
Finished Sep 18 07:55:35 AM UTC 24
Peak memory 215256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1376000620 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.i2c_host_may_nack.1376000620
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/3.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/3.i2c_host_mode_toggle.2958188398
Short name T23
Test name
Test status
Simulation time 197409581 ps
CPU time 2.47 seconds
Started Sep 18 07:55:25 AM UTC 24
Finished Sep 18 07:55:29 AM UTC 24
Peak memory 215308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2958188398 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_mode_toggle.2958188398
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/3.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/3.i2c_host_override.1158795191
Short name T310
Test name
Test status
Simulation time 80681199 ps
CPU time 0.9 seconds
Started Sep 18 07:55:11 AM UTC 24
Finished Sep 18 07:55:13 AM UTC 24
Peak memory 214108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1158795191 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.i2c_host_override.1158795191
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/3.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/3.i2c_host_perf_precise.229185209
Short name T44
Test name
Test status
Simulation time 107084769 ps
CPU time 1.46 seconds
Started Sep 18 07:55:14 AM UTC 24
Finished Sep 18 07:55:16 AM UTC 24
Peak memory 214908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=229185209 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_perf_precise.229185209
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/3.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/3.i2c_host_smoke.2303165611
Short name T287
Test name
Test status
Simulation time 3803321833 ps
CPU time 78.71 seconds
Started Sep 18 07:55:10 AM UTC 24
Finished Sep 18 07:56:31 AM UTC 24
Peak memory 367592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2303165611 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.i2c_host_smoke.2303165611
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/3.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/3.i2c_host_stretch_timeout.3699709187
Short name T195
Test name
Test status
Simulation time 831161638 ps
CPU time 13.4 seconds
Started Sep 18 07:55:14 AM UTC 24
Finished Sep 18 07:55:28 AM UTC 24
Peak memory 229668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3699709187 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_stretch_timeout.3699709187
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/3.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/3.i2c_sec_cm.4127723781
Short name T202
Test name
Test status
Simulation time 147907442 ps
CPU time 1.33 seconds
Started Sep 18 07:55:33 AM UTC 24
Finished Sep 18 07:55:35 AM UTC 24
Peak memory 244508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4127723781 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_sec_cm.4127723781
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/3.i2c_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/3.i2c_target_bad_addr.1763808194
Short name T317
Test name
Test status
Simulation time 6172507322 ps
CPU time 6.02 seconds
Started Sep 18 07:55:23 AM UTC 24
Finished Sep 18 07:55:30 AM UTC 24
Peak memory 225636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=1763808194 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_bad_addr.1763808194
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/3.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/3.i2c_target_fifo_reset_acq.3998184449
Short name T313
Test name
Test status
Simulation time 110976705 ps
CPU time 1.46 seconds
Started Sep 18 07:55:20 AM UTC 24
Finished Sep 18 07:55:22 AM UTC 24
Peak memory 214784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3998184
449 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_fifo_reset_acq.3998184449
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/3.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/3.i2c_target_fifo_reset_tx.50788394
Short name T314
Test name
Test status
Simulation time 763342167 ps
CPU time 1.87 seconds
Started Sep 18 07:55:20 AM UTC 24
Finished Sep 18 07:55:23 AM UTC 24
Peak memory 214788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5078839
4 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_fifo_reset_tx.50788394
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/3.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/3.i2c_target_fifo_watermarks_acq.2238886422
Short name T319
Test name
Test status
Simulation time 84747788 ps
CPU time 1.41 seconds
Started Sep 18 07:55:29 AM UTC 24
Finished Sep 18 07:55:32 AM UTC 24
Peak memory 215028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2238886
422 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_fifo_watermark
s_acq.2238886422
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/3.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/3.i2c_target_fifo_watermarks_tx.2760134817
Short name T320
Test name
Test status
Simulation time 161488860 ps
CPU time 2.36 seconds
Started Sep 18 07:55:29 AM UTC 24
Finished Sep 18 07:55:32 AM UTC 24
Peak memory 215120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2760134
817 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_fifo_watermarks
_tx.2760134817
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/3.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/3.i2c_target_hrst.1840810455
Short name T198
Test name
Test status
Simulation time 482405161 ps
CPU time 3.57 seconds
Started Sep 18 07:55:24 AM UTC 24
Finished Sep 18 07:55:29 AM UTC 24
Peak memory 217556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1840810
455 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_hrst.1840810455
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/3.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/3.i2c_target_intr_smoke.591652913
Short name T270
Test name
Test status
Simulation time 795577426 ps
CPU time 8.19 seconds
Started Sep 18 07:55:17 AM UTC 24
Finished Sep 18 07:55:27 AM UTC 24
Peak memory 225624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=591652
913 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_intr_smoke.591652913
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/3.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/3.i2c_target_intr_stress_wr.4007471522
Short name T162
Test name
Test status
Simulation time 7350878638 ps
CPU time 69.62 seconds
Started Sep 18 07:55:17 AM UTC 24
Finished Sep 18 07:56:29 AM UTC 24
Peak memory 1893412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=4007471522 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_intr_stress
_wr.4007471522
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/3.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/3.i2c_target_nack_acqfull.52927654
Short name T166
Test name
Test status
Simulation time 4356028315 ps
CPU time 4.85 seconds
Started Sep 18 07:55:30 AM UTC 24
Finished Sep 18 07:55:36 AM UTC 24
Peak memory 225688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5292765
4 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_nack_acqfull.52927654
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/3.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/3.i2c_target_nack_acqfull_addr.803994675
Short name T167
Test name
Test status
Simulation time 2212766928 ps
CPU time 4.43 seconds
Started Sep 18 07:55:31 AM UTC 24
Finished Sep 18 07:55:37 AM UTC 24
Peak memory 215256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8039946
75 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_nack_acqfull_addr.803994675
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/3.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/3.i2c_target_nack_txstretch.918311812
Short name T60
Test name
Test status
Simulation time 365927796 ps
CPU time 2.68 seconds
Started Sep 18 07:55:32 AM UTC 24
Finished Sep 18 07:55:36 AM UTC 24
Peak memory 232224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9183118
12 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_nack_txstretch.918311812
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/3.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/3.i2c_target_perf.3247093464
Short name T316
Test name
Test status
Simulation time 813849078 ps
CPU time 5.79 seconds
Started Sep 18 07:55:22 AM UTC 24
Finished Sep 18 07:55:29 AM UTC 24
Peak memory 225756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3247093
464 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_perf.3247093464
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/3.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/3.i2c_target_smbus_maxlen.2378753613
Short name T323
Test name
Test status
Simulation time 411666611 ps
CPU time 4.13 seconds
Started Sep 18 07:55:29 AM UTC 24
Finished Sep 18 07:55:34 AM UTC 24
Peak memory 215076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2378753
613 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_smbus_maxlen.2378753613
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/3.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/3.i2c_target_smoke.437917415
Short name T327
Test name
Test status
Simulation time 1345582631 ps
CPU time 20.41 seconds
Started Sep 18 07:55:15 AM UTC 24
Finished Sep 18 07:55:37 AM UTC 24
Peak memory 225752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=437917415 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_smoke.437917415
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/3.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/3.i2c_target_stress_all.687830707
Short name T242
Test name
Test status
Simulation time 68016582459 ps
CPU time 148.1 seconds
Started Sep 18 07:55:22 AM UTC 24
Finished Sep 18 07:57:52 AM UTC 24
Peak memory 1586024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=687830
707 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_stress_all.687830707
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/3.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/3.i2c_target_stress_rd.3493450146
Short name T176
Test name
Test status
Simulation time 4686215297 ps
CPU time 52 seconds
Started Sep 18 07:55:16 AM UTC 24
Finished Sep 18 07:56:10 AM UTC 24
Peak memory 227860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3493450146 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_stress_rd.3493450146
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/3.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/3.i2c_target_stress_wr.1095836773
Short name T328
Test name
Test status
Simulation time 22131320166 ps
CPU time 20.62 seconds
Started Sep 18 07:55:16 AM UTC 24
Finished Sep 18 07:55:38 AM UTC 24
Peak memory 215528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1095836773 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_stress_wr.1095836773
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/3.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/3.i2c_target_stretch.3912149968
Short name T318
Test name
Test status
Simulation time 3120037801 ps
CPU time 14.15 seconds
Started Sep 18 07:55:16 AM UTC 24
Finished Sep 18 07:55:32 AM UTC 24
Peak memory 275284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3912149968 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_stretch.3912149968
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/3.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/3.i2c_target_timeout.927826744
Short name T321
Test name
Test status
Simulation time 4673757597 ps
CPU time 12.11 seconds
Started Sep 18 07:55:19 AM UTC 24
Finished Sep 18 07:55:33 AM UTC 24
Peak memory 242508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9278267
44 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_timeout.927826744
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/3.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/3.i2c_target_tx_stretch_ctrl.738366821
Short name T324
Test name
Test status
Simulation time 107619706 ps
CPU time 4.36 seconds
Started Sep 18 07:55:29 AM UTC 24
Finished Sep 18 07:55:35 AM UTC 24
Peak memory 215508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7383668
21 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_tx_stretch_ctrl.738366821
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/3.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/30.i2c_alert_test.4108349093
Short name T1092
Test name
Test status
Simulation time 43144298 ps
CPU time 0.97 seconds
Started Sep 18 08:09:32 AM UTC 24
Finished Sep 18 08:09:34 AM UTC 24
Peak memory 214840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4108349093 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_alert_test.4108349093
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/30.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/30.i2c_host_error_intr.2383188342
Short name T1065
Test name
Test status
Simulation time 83921576 ps
CPU time 1.92 seconds
Started Sep 18 08:09:05 AM UTC 24
Finished Sep 18 08:09:08 AM UTC 24
Peak memory 231576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2383188342 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 30.i2c_host_error_intr.2383188342
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/30.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/30.i2c_host_fifo_fmt_empty.2783950495
Short name T1075
Test name
Test status
Simulation time 347289523 ps
CPU time 19.14 seconds
Started Sep 18 08:09:03 AM UTC 24
Finished Sep 18 08:09:23 AM UTC 24
Peak memory 293528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2783950495 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_fmt_empty.2783950495
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/30.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/30.i2c_host_fifo_full.1699869283
Short name T1135
Test name
Test status
Simulation time 11279964131 ps
CPU time 87.46 seconds
Started Sep 18 08:09:03 AM UTC 24
Finished Sep 18 08:10:33 AM UTC 24
Peak memory 627568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1699869283 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_full.1699869283
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/30.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/30.i2c_host_fifo_overflow.990840380
Short name T1146
Test name
Test status
Simulation time 3072027673 ps
CPU time 98.56 seconds
Started Sep 18 08:09:01 AM UTC 24
Finished Sep 18 08:10:41 AM UTC 24
Peak memory 588504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=990840380 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_overflow.990840380
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/30.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/30.i2c_host_fifo_reset_fmt.819325773
Short name T1062
Test name
Test status
Simulation time 632110108 ps
CPU time 1.62 seconds
Started Sep 18 08:09:02 AM UTC 24
Finished Sep 18 08:09:04 AM UTC 24
Peak memory 214904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=819325773 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_fmt.819325773
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/30.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/30.i2c_host_fifo_reset_rx.1811800741
Short name T1066
Test name
Test status
Simulation time 798489805 ps
CPU time 6.46 seconds
Started Sep 18 08:09:03 AM UTC 24
Finished Sep 18 08:09:10 AM UTC 24
Peak memory 215268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1811800741 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_rx.1811800741
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/30.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/30.i2c_host_fifo_watermark.1828340578
Short name T1302
Test name
Test status
Simulation time 4744983556 ps
CPU time 289.05 seconds
Started Sep 18 08:09:01 AM UTC 24
Finished Sep 18 08:13:54 AM UTC 24
Peak memory 1401704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1828340578 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_watermark.1828340578
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/30.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/30.i2c_host_may_nack.162039029
Short name T1097
Test name
Test status
Simulation time 291663790 ps
CPU time 11.04 seconds
Started Sep 18 08:09:27 AM UTC 24
Finished Sep 18 08:09:39 AM UTC 24
Peak memory 215316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=162039029 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 30.i2c_host_may_nack.162039029
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/30.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/30.i2c_host_mode_toggle.2463988892
Short name T1082
Test name
Test status
Simulation time 162435148 ps
CPU time 3.21 seconds
Started Sep 18 08:09:24 AM UTC 24
Finished Sep 18 08:09:29 AM UTC 24
Peak memory 215328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2463988892 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_mode_toggle.2463988892
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/30.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/30.i2c_host_override.1717124447
Short name T1056
Test name
Test status
Simulation time 51255322 ps
CPU time 1.02 seconds
Started Sep 18 08:09:00 AM UTC 24
Finished Sep 18 08:09:02 AM UTC 24
Peak memory 214112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1717124447 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.i2c_host_override.1717124447
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/30.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/30.i2c_host_perf.727830195
Short name T1264
Test name
Test status
Simulation time 6470122123 ps
CPU time 242.62 seconds
Started Sep 18 08:09:03 AM UTC 24
Finished Sep 18 08:13:09 AM UTC 24
Peak memory 225628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=727830195 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 30.i2c_host_perf.727830195
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/30.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/30.i2c_host_perf_precise.402103411
Short name T1069
Test name
Test status
Simulation time 225481233 ps
CPU time 11.48 seconds
Started Sep 18 08:09:04 AM UTC 24
Finished Sep 18 08:09:17 AM UTC 24
Peak memory 215180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=402103411 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_perf_precise.402103411
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/30.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/30.i2c_host_smoke.3074096893
Short name T1086
Test name
Test status
Simulation time 1739535449 ps
CPU time 31.09 seconds
Started Sep 18 08:09:00 AM UTC 24
Finished Sep 18 08:09:32 AM UTC 24
Peak memory 354808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3074096893 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 30.i2c_host_smoke.3074096893
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/30.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/30.i2c_host_stretch_timeout.1118813216
Short name T1072
Test name
Test status
Simulation time 3469863985 ps
CPU time 14.46 seconds
Started Sep 18 08:09:04 AM UTC 24
Finished Sep 18 08:09:20 AM UTC 24
Peak memory 231640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1118813216 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_stretch_timeout.1118813216
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/30.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/30.i2c_target_bad_addr.2912081777
Short name T1087
Test name
Test status
Simulation time 1164774256 ps
CPU time 7.66 seconds
Started Sep 18 08:09:23 AM UTC 24
Finished Sep 18 08:09:32 AM UTC 24
Peak memory 225572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=2912081777 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_bad_ad
dr.2912081777
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/30.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/30.i2c_target_fifo_reset_acq.3377374148
Short name T1074
Test name
Test status
Simulation time 745296312 ps
CPU time 1.55 seconds
Started Sep 18 08:09:20 AM UTC 24
Finished Sep 18 08:09:23 AM UTC 24
Peak memory 214784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3377374
148 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_fifo_reset_acq.3377374148
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/30.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/30.i2c_target_fifo_reset_tx.3090913617
Short name T1076
Test name
Test status
Simulation time 425371349 ps
CPU time 1.24 seconds
Started Sep 18 08:09:21 AM UTC 24
Finished Sep 18 08:09:23 AM UTC 24
Peak memory 215020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3090913
617 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_fifo_reset_tx.3090913617
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/30.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/30.i2c_target_fifo_watermarks_acq.2569372707
Short name T1085
Test name
Test status
Simulation time 1111411020 ps
CPU time 2.53 seconds
Started Sep 18 08:09:28 AM UTC 24
Finished Sep 18 08:09:31 AM UTC 24
Peak memory 215112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2569372
707 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_fifo_watermar
ks_acq.2569372707
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/30.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/30.i2c_target_fifo_watermarks_tx.408560815
Short name T1084
Test name
Test status
Simulation time 77464526 ps
CPU time 1.38 seconds
Started Sep 18 08:09:29 AM UTC 24
Finished Sep 18 08:09:31 AM UTC 24
Peak memory 214788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4085608
15 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_fifo_watermarks
_tx.408560815
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/30.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/30.i2c_target_intr_smoke.1189601905
Short name T1088
Test name
Test status
Simulation time 1617472995 ps
CPU time 17.54 seconds
Started Sep 18 08:09:14 AM UTC 24
Finished Sep 18 08:09:32 AM UTC 24
Peak memory 232220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=118960
1905 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_intr_smoke.1189601905
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/30.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/30.i2c_target_intr_stress_wr.361075385
Short name T1133
Test name
Test status
Simulation time 11937020848 ps
CPU time 68.94 seconds
Started Sep 18 08:09:15 AM UTC 24
Finished Sep 18 08:10:25 AM UTC 24
Peak memory 1379104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=361075385 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_intr_stress
_wr.361075385
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/30.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/30.i2c_target_nack_acqfull.1584989268
Short name T1093
Test name
Test status
Simulation time 976746015 ps
CPU time 3.31 seconds
Started Sep 18 08:09:30 AM UTC 24
Finished Sep 18 08:09:34 AM UTC 24
Peak memory 225636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1584989
268 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_nack_acqfull.1584989268
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/30.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/30.i2c_target_nack_acqfull_addr.3822245070
Short name T49
Test name
Test status
Simulation time 925393038 ps
CPU time 3.34 seconds
Started Sep 18 08:09:30 AM UTC 24
Finished Sep 18 08:09:34 AM UTC 24
Peak memory 215264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3822245
070 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_nack_acqfull_ad
dr.3822245070
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/30.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/30.i2c_target_nack_txstretch.897701945
Short name T1096
Test name
Test status
Simulation time 227245181 ps
CPU time 2.28 seconds
Started Sep 18 08:09:32 AM UTC 24
Finished Sep 18 08:09:35 AM UTC 24
Peak memory 232288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8977019
45 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_nack_txstretch.897701945
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/30.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/30.i2c_target_perf.4119546960
Short name T1081
Test name
Test status
Simulation time 14911010316 ps
CPU time 5.67 seconds
Started Sep 18 08:09:21 AM UTC 24
Finished Sep 18 08:09:28 AM UTC 24
Peak memory 225816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4119546
960 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_perf.4119546960
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/30.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/30.i2c_target_smbus_maxlen.4039097534
Short name T1090
Test name
Test status
Simulation time 507156178 ps
CPU time 3.26 seconds
Started Sep 18 08:09:29 AM UTC 24
Finished Sep 18 08:09:33 AM UTC 24
Peak memory 215076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4039097
534 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_smbus_maxlen.4039097534
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/30.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/30.i2c_target_smoke.2144384045
Short name T1077
Test name
Test status
Simulation time 5734264857 ps
CPU time 17.24 seconds
Started Sep 18 08:09:07 AM UTC 24
Finished Sep 18 08:09:26 AM UTC 24
Peak memory 225880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2144384045 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_smoke.2144384045
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/30.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/30.i2c_target_stress_all.977719453
Short name T1382
Test name
Test status
Simulation time 46564423877 ps
CPU time 361.3 seconds
Started Sep 18 08:09:21 AM UTC 24
Finished Sep 18 08:15:28 AM UTC 24
Peak memory 2949988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=977719
453 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_stress_all.977719453
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/30.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/30.i2c_target_stress_rd.3324034554
Short name T1094
Test name
Test status
Simulation time 1144520467 ps
CPU time 21.42 seconds
Started Sep 18 08:09:12 AM UTC 24
Finished Sep 18 08:09:34 AM UTC 24
Peak memory 232276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3324034554 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_stress_rd.3324034554
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/30.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/30.i2c_target_stress_wr.1738823604
Short name T1156
Test name
Test status
Simulation time 25742840363 ps
CPU time 98.64 seconds
Started Sep 18 08:09:09 AM UTC 24
Finished Sep 18 08:10:49 AM UTC 24
Peak memory 1585940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1738823604 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_stress_wr.1738823604
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/30.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/30.i2c_target_stretch.679136794
Short name T1071
Test name
Test status
Simulation time 511485882 ps
CPU time 5.48 seconds
Started Sep 18 08:09:13 AM UTC 24
Finished Sep 18 08:09:19 AM UTC 24
Peak memory 291556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=679136794 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_stretch.679136794
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/30.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/30.i2c_target_timeout.273378908
Short name T1080
Test name
Test status
Simulation time 2512722591 ps
CPU time 8.67 seconds
Started Sep 18 08:09:18 AM UTC 24
Finished Sep 18 08:09:28 AM UTC 24
Peak memory 232352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2733789
08 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_timeout.273378908
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/30.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/30.i2c_target_tx_stretch_ctrl.2669112496
Short name T1057
Test name
Test status
Simulation time 555651110 ps
CPU time 12.79 seconds
Started Sep 18 08:09:29 AM UTC 24
Finished Sep 18 08:09:43 AM UTC 24
Peak memory 215324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2669112
496 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_tx_stretch_ctrl.2669112496
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/30.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/31.i2c_alert_test.3019504692
Short name T1120
Test name
Test status
Simulation time 50283341 ps
CPU time 1.03 seconds
Started Sep 18 08:10:10 AM UTC 24
Finished Sep 18 08:10:12 AM UTC 24
Peak memory 214840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3019504692 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_alert_test.3019504692
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/31.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/31.i2c_host_error_intr.4150482638
Short name T1098
Test name
Test status
Simulation time 161422651 ps
CPU time 4 seconds
Started Sep 18 08:09:36 AM UTC 24
Finished Sep 18 08:09:41 AM UTC 24
Peak memory 246516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4150482638 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 31.i2c_host_error_intr.4150482638
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/31.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/31.i2c_host_fifo_fmt_empty.3300328969
Short name T1099
Test name
Test status
Simulation time 240058576 ps
CPU time 5.48 seconds
Started Sep 18 08:09:34 AM UTC 24
Finished Sep 18 08:09:41 AM UTC 24
Peak memory 248512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3300328969 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_fmt_empty.3300328969
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/31.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/31.i2c_host_fifo_full.1559744376
Short name T1167
Test name
Test status
Simulation time 39565058014 ps
CPU time 81.88 seconds
Started Sep 18 08:09:36 AM UTC 24
Finished Sep 18 08:10:59 AM UTC 24
Peak memory 527132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1559744376 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_full.1559744376
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/31.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/31.i2c_host_fifo_overflow.4160873697
Short name T1215
Test name
Test status
Simulation time 14877337484 ps
CPU time 150.42 seconds
Started Sep 18 08:09:33 AM UTC 24
Finished Sep 18 08:12:06 AM UTC 24
Peak memory 822136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4160873697 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_overflow.4160873697
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/31.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/31.i2c_host_fifo_reset_rx.3539571365
Short name T1037
Test name
Test status
Simulation time 954057473 ps
CPU time 15.74 seconds
Started Sep 18 08:09:34 AM UTC 24
Finished Sep 18 08:09:51 AM UTC 24
Peak memory 215252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3539571365 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_rx.3539571365
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/31.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/31.i2c_host_fifo_watermark.1901548318
Short name T1262
Test name
Test status
Simulation time 3581428405 ps
CPU time 210.3 seconds
Started Sep 18 08:09:33 AM UTC 24
Finished Sep 18 08:13:07 AM UTC 24
Peak memory 1129308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1901548318 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_watermark.1901548318
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/31.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/31.i2c_host_may_nack.2681446398
Short name T1129
Test name
Test status
Simulation time 1049401397 ps
CPU time 14.39 seconds
Started Sep 18 08:10:02 AM UTC 24
Finished Sep 18 08:10:18 AM UTC 24
Peak memory 215244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2681446398 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.i2c_host_may_nack.2681446398
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/31.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/31.i2c_host_override.3850331822
Short name T1095
Test name
Test status
Simulation time 188243160 ps
CPU time 0.91 seconds
Started Sep 18 08:09:33 AM UTC 24
Finished Sep 18 08:09:35 AM UTC 24
Peak memory 214112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3850331822 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.i2c_host_override.3850331822
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/31.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/31.i2c_host_perf.2466032248
Short name T1109
Test name
Test status
Simulation time 22471788670 ps
CPU time 24.02 seconds
Started Sep 18 08:09:36 AM UTC 24
Finished Sep 18 08:10:01 AM UTC 24
Peak memory 215300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2466032248 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 31.i2c_host_perf.2466032248
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/31.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/31.i2c_host_perf_precise.3875512161
Short name T1100
Test name
Test status
Simulation time 3037456644 ps
CPU time 12.59 seconds
Started Sep 18 08:09:36 AM UTC 24
Finished Sep 18 08:09:49 AM UTC 24
Peak memory 271124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3875512161 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_perf_precise.3875512161
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/31.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/31.i2c_host_smoke.2597761165
Short name T1164
Test name
Test status
Simulation time 2709373776 ps
CPU time 81.83 seconds
Started Sep 18 08:09:32 AM UTC 24
Finished Sep 18 08:10:56 AM UTC 24
Peak memory 396068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2597761165 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 31.i2c_host_smoke.2597761165
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/31.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/31.i2c_host_stretch_timeout.1178032952
Short name T1116
Test name
Test status
Simulation time 1974067509 ps
CPU time 31.52 seconds
Started Sep 18 08:09:36 AM UTC 24
Finished Sep 18 08:10:09 AM UTC 24
Peak memory 225560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1178032952 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_stretch_timeout.1178032952
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/31.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/31.i2c_target_bad_addr.672266151
Short name T1114
Test name
Test status
Simulation time 2923436368 ps
CPU time 5.35 seconds
Started Sep 18 08:10:01 AM UTC 24
Finished Sep 18 08:10:08 AM UTC 24
Peak memory 227696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=672266151 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_bad_addr.672266151
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/31.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/31.i2c_target_fifo_reset_acq.1008918039
Short name T1105
Test name
Test status
Simulation time 207144593 ps
CPU time 0.91 seconds
Started Sep 18 08:09:58 AM UTC 24
Finished Sep 18 08:10:00 AM UTC 24
Peak memory 214216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1008918
039 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_fifo_reset_acq.1008918039
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/31.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/31.i2c_target_fifo_reset_tx.330506601
Short name T1106
Test name
Test status
Simulation time 156936108 ps
CPU time 1.58 seconds
Started Sep 18 08:09:58 AM UTC 24
Finished Sep 18 08:10:00 AM UTC 24
Peak memory 214844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3305066
01 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_fifo_reset_tx.330506601
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/31.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/31.i2c_target_fifo_watermarks_acq.1357186732
Short name T1123
Test name
Test status
Simulation time 7088936081 ps
CPU time 4.63 seconds
Started Sep 18 08:10:07 AM UTC 24
Finished Sep 18 08:10:13 AM UTC 24
Peak memory 215320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1357186
732 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_fifo_watermar
ks_acq.1357186732
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/31.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/31.i2c_target_fifo_watermarks_tx.1616745654
Short name T1117
Test name
Test status
Simulation time 186520326 ps
CPU time 1.61 seconds
Started Sep 18 08:10:07 AM UTC 24
Finished Sep 18 08:10:10 AM UTC 24
Peak memory 214852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1616745
654 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_fifo_watermark
s_tx.1616745654
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/31.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/31.i2c_target_hrst.1434488670
Short name T1113
Test name
Test status
Simulation time 1066294361 ps
CPU time 3.96 seconds
Started Sep 18 08:10:01 AM UTC 24
Finished Sep 18 08:10:06 AM UTC 24
Peak memory 225692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1434488
670 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_hrst.1434488670
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/31.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/31.i2c_target_intr_smoke.6751466
Short name T1103
Test name
Test status
Simulation time 2594634870 ps
CPU time 12.85 seconds
Started Sep 18 08:09:43 AM UTC 24
Finished Sep 18 08:09:57 AM UTC 24
Peak memory 232436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=675146
6 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_intr_smoke.6751466
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/31.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/31.i2c_target_intr_stress_wr.1187785698
Short name T1192
Test name
Test status
Simulation time 9682096501 ps
CPU time 103.22 seconds
Started Sep 18 08:09:50 AM UTC 24
Finished Sep 18 08:11:36 AM UTC 24
Peak memory 2442012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1187785698 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_intr_stres
s_wr.1187785698
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/31.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/31.i2c_target_nack_acqfull.3882694941
Short name T1125
Test name
Test status
Simulation time 2094655732 ps
CPU time 5.07 seconds
Started Sep 18 08:10:07 AM UTC 24
Finished Sep 18 08:10:14 AM UTC 24
Peak memory 225636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3882694
941 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_nack_acqfull.3882694941
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/31.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/31.i2c_target_nack_acqfull_addr.419695745
Short name T1126
Test name
Test status
Simulation time 486964118 ps
CPU time 4.75 seconds
Started Sep 18 08:10:09 AM UTC 24
Finished Sep 18 08:10:14 AM UTC 24
Peak memory 215196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4196957
45 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_nack_acqfull_addr.419695745
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/31.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/31.i2c_target_nack_txstretch.3795749637
Short name T1124
Test name
Test status
Simulation time 256861208 ps
CPU time 2.36 seconds
Started Sep 18 08:10:10 AM UTC 24
Finished Sep 18 08:10:13 AM UTC 24
Peak memory 232148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3795749
637 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_nack_txstretch.3795749637
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/31.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/31.i2c_target_perf.2714867357
Short name T1112
Test name
Test status
Simulation time 4698319421 ps
CPU time 5.13 seconds
Started Sep 18 08:10:00 AM UTC 24
Finished Sep 18 08:10:06 AM UTC 24
Peak memory 219616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2714867
357 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_perf.2714867357
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/31.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/31.i2c_target_smbus_maxlen.742979015
Short name T1121
Test name
Test status
Simulation time 1070504446 ps
CPU time 4.1 seconds
Started Sep 18 08:10:07 AM UTC 24
Finished Sep 18 08:10:13 AM UTC 24
Peak memory 215224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7429790
15 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_smbus_maxlen.742979015
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/31.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/31.i2c_target_smoke.1628808570
Short name T90
Test name
Test status
Simulation time 749994296 ps
CPU time 27.48 seconds
Started Sep 18 08:09:38 AM UTC 24
Finished Sep 18 08:10:07 AM UTC 24
Peak memory 225772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1628808570 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_smoke.1628808570
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/31.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/31.i2c_target_stress_all.3461868276
Short name T1735
Test name
Test status
Simulation time 39440607787 ps
CPU time 752.41 seconds
Started Sep 18 08:10:01 AM UTC 24
Finished Sep 18 08:22:42 AM UTC 24
Peak memory 6929384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=346186
8276 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_stress_all.3461868276
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/31.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/31.i2c_target_stress_rd.4160182018
Short name T1107
Test name
Test status
Simulation time 3154430053 ps
CPU time 17.03 seconds
Started Sep 18 08:09:42 AM UTC 24
Finished Sep 18 08:10:00 AM UTC 24
Peak memory 232228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4160182018 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_stress_rd.4160182018
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/31.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/31.i2c_target_stress_wr.961018796
Short name T1739
Test name
Test status
Simulation time 51609812809 ps
CPU time 806.1 seconds
Started Sep 18 08:09:39 AM UTC 24
Finished Sep 18 08:23:13 AM UTC 24
Peak memory 8053728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=961018796 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_stress_wr.961018796
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/31.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/31.i2c_target_stretch.4061631036
Short name T1102
Test name
Test status
Simulation time 2350427801 ps
CPU time 13.85 seconds
Started Sep 18 08:09:42 AM UTC 24
Finished Sep 18 08:09:57 AM UTC 24
Peak memory 347108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4061631036 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_stretch.4061631036
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/31.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/31.i2c_target_timeout.84587745
Short name T1108
Test name
Test status
Simulation time 1294270106 ps
CPU time 7.29 seconds
Started Sep 18 08:09:52 AM UTC 24
Finished Sep 18 08:10:01 AM UTC 24
Peak memory 229592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8458774
5 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_timeout.84587745
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/31.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/31.i2c_target_tx_stretch_ctrl.484254635
Short name T1119
Test name
Test status
Simulation time 56405822 ps
CPU time 2.17 seconds
Started Sep 18 08:10:07 AM UTC 24
Finished Sep 18 08:10:11 AM UTC 24
Peak memory 215324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4842546
35 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_tx_stretch_ctrl.484254635
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/31.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/32.i2c_alert_test.2714121144
Short name T1157
Test name
Test status
Simulation time 27854946 ps
CPU time 0.99 seconds
Started Sep 18 08:10:47 AM UTC 24
Finished Sep 18 08:10:49 AM UTC 24
Peak memory 214840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2714121144 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_alert_test.2714121144
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/32.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/32.i2c_host_error_intr.3433739810
Short name T1131
Test name
Test status
Simulation time 191531897 ps
CPU time 3.15 seconds
Started Sep 18 08:10:15 AM UTC 24
Finished Sep 18 08:10:21 AM UTC 24
Peak memory 225592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3433739810 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 32.i2c_host_error_intr.3433739810
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/32.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/32.i2c_host_fifo_fmt_empty.1953070076
Short name T1132
Test name
Test status
Simulation time 490852295 ps
CPU time 6.72 seconds
Started Sep 18 08:10:14 AM UTC 24
Finished Sep 18 08:10:22 AM UTC 24
Peak memory 265120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1953070076 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_fmt_empty.1953070076
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/32.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/32.i2c_host_fifo_full.1547098139
Short name T1195
Test name
Test status
Simulation time 11742625720 ps
CPU time 82.6 seconds
Started Sep 18 08:10:14 AM UTC 24
Finished Sep 18 08:11:39 AM UTC 24
Peak memory 349160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1547098139 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_full.1547098139
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/32.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/32.i2c_host_fifo_overflow.1793916393
Short name T1168
Test name
Test status
Simulation time 1519727839 ps
CPU time 46.86 seconds
Started Sep 18 08:10:13 AM UTC 24
Finished Sep 18 08:11:02 AM UTC 24
Peak memory 561840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1793916393 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_overflow.1793916393
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/32.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/32.i2c_host_fifo_reset_fmt.3018566426
Short name T1128
Test name
Test status
Simulation time 131283570 ps
CPU time 1.78 seconds
Started Sep 18 08:10:13 AM UTC 24
Finished Sep 18 08:10:16 AM UTC 24
Peak memory 215080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3018566426 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_fmt.3018566426
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/32.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/32.i2c_host_fifo_reset_rx.3972354808
Short name T1134
Test name
Test status
Simulation time 156312385 ps
CPU time 10.67 seconds
Started Sep 18 08:10:14 AM UTC 24
Finished Sep 18 08:10:26 AM UTC 24
Peak memory 242408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3972354808 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_rx.3972354808
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/32.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/32.i2c_host_fifo_watermark.2069725471
Short name T1238
Test name
Test status
Simulation time 39085084195 ps
CPU time 143.13 seconds
Started Sep 18 08:10:12 AM UTC 24
Finished Sep 18 08:12:38 AM UTC 24
Peak memory 1547160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2069725471 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_watermark.2069725471
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/32.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/32.i2c_host_override.3375245901
Short name T1122
Test name
Test status
Simulation time 19057005 ps
CPU time 1.08 seconds
Started Sep 18 08:10:11 AM UTC 24
Finished Sep 18 08:10:13 AM UTC 24
Peak memory 214112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3375245901 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.i2c_host_override.3375245901
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/32.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/32.i2c_host_perf.1418774480
Short name T1323
Test name
Test status
Simulation time 20060810411 ps
CPU time 232.02 seconds
Started Sep 18 08:10:14 AM UTC 24
Finished Sep 18 08:14:10 AM UTC 24
Peak memory 215380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1418774480 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 32.i2c_host_perf.1418774480
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/32.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/32.i2c_host_perf_precise.1152507962
Short name T1130
Test name
Test status
Simulation time 94235573 ps
CPU time 1.96 seconds
Started Sep 18 08:10:15 AM UTC 24
Finished Sep 18 08:10:19 AM UTC 24
Peak memory 214924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1152507962 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_perf_precise.1152507962
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/32.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/32.i2c_host_smoke.2311477167
Short name T1138
Test name
Test status
Simulation time 1190304503 ps
CPU time 24.05 seconds
Started Sep 18 08:10:11 AM UTC 24
Finished Sep 18 08:10:36 AM UTC 24
Peak memory 373408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2311477167 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.i2c_host_smoke.2311477167
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/32.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/32.i2c_host_stretch_timeout.2355866721
Short name T1143
Test name
Test status
Simulation time 849560194 ps
CPU time 21.05 seconds
Started Sep 18 08:10:15 AM UTC 24
Finished Sep 18 08:10:39 AM UTC 24
Peak memory 231632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2355866721 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_stretch_timeout.2355866721
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/32.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/32.i2c_target_bad_addr.3151807893
Short name T1148
Test name
Test status
Simulation time 1603175691 ps
CPU time 4.94 seconds
Started Sep 18 08:10:38 AM UTC 24
Finished Sep 18 08:10:44 AM UTC 24
Peak memory 219428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=3151807893 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_bad_ad
dr.3151807893
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/32.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/32.i2c_target_fifo_reset_acq.1401166303
Short name T1144
Test name
Test status
Simulation time 445850585 ps
CPU time 1.86 seconds
Started Sep 18 08:10:36 AM UTC 24
Finished Sep 18 08:10:39 AM UTC 24
Peak memory 214784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1401166
303 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_fifo_reset_acq.1401166303
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/32.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/32.i2c_target_fifo_reset_tx.4211532685
Short name T1145
Test name
Test status
Simulation time 196718637 ps
CPU time 1.25 seconds
Started Sep 18 08:10:37 AM UTC 24
Finished Sep 18 08:10:39 AM UTC 24
Peak memory 214904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4211532
685 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_fifo_reset_tx.4211532685
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/32.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/32.i2c_target_fifo_watermarks_acq.3694716359
Short name T1152
Test name
Test status
Simulation time 1852643931 ps
CPU time 4.39 seconds
Started Sep 18 08:10:41 AM UTC 24
Finished Sep 18 08:10:46 AM UTC 24
Peak memory 215320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3694716
359 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_fifo_watermar
ks_acq.3694716359
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/32.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/32.i2c_target_fifo_watermarks_tx.2213109565
Short name T1150
Test name
Test status
Simulation time 156688052 ps
CPU time 2.53 seconds
Started Sep 18 08:10:42 AM UTC 24
Finished Sep 18 08:10:45 AM UTC 24
Peak memory 215116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2213109
565 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_fifo_watermark
s_tx.2213109565
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/32.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/32.i2c_target_hrst.1140387196
Short name T1147
Test name
Test status
Simulation time 630804248 ps
CPU time 2.89 seconds
Started Sep 18 08:10:39 AM UTC 24
Finished Sep 18 08:10:42 AM UTC 24
Peak memory 225632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1140387
196 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_hrst.1140387196
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/32.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/32.i2c_target_intr_smoke.2044934949
Short name T1142
Test name
Test status
Simulation time 1160176320 ps
CPU time 10.99 seconds
Started Sep 18 08:10:26 AM UTC 24
Finished Sep 18 08:10:38 AM UTC 24
Peak memory 224040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=204493
4949 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_intr_smoke.2044934949
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/32.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/32.i2c_target_intr_stress_wr.2861290328
Short name T1200
Test name
Test status
Simulation time 18418925034 ps
CPU time 79.57 seconds
Started Sep 18 08:10:27 AM UTC 24
Finished Sep 18 08:11:48 AM UTC 24
Peak memory 1510168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2861290328 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_intr_stres
s_wr.2861290328
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/32.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/32.i2c_target_nack_acqfull.823445235
Short name T1161
Test name
Test status
Simulation time 927434292 ps
CPU time 3.97 seconds
Started Sep 18 08:10:46 AM UTC 24
Finished Sep 18 08:10:51 AM UTC 24
Peak memory 225572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8234452
35 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_nack_acqfull.823445235
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/32.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/32.i2c_target_nack_acqfull_addr.96155664
Short name T1159
Test name
Test status
Simulation time 1516963804 ps
CPU time 3.05 seconds
Started Sep 18 08:10:46 AM UTC 24
Finished Sep 18 08:10:50 AM UTC 24
Peak memory 215196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9615566
4 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_nack_acqfull_addr.96155664
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/32.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/32.i2c_target_nack_txstretch.2485884326
Short name T1158
Test name
Test status
Simulation time 279219526 ps
CPU time 2.4 seconds
Started Sep 18 08:10:46 AM UTC 24
Finished Sep 18 08:10:49 AM UTC 24
Peak memory 232080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2485884
326 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_nack_txstretch.2485884326
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/32.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/32.i2c_target_perf.3791553666
Short name T1154
Test name
Test status
Simulation time 1043792270 ps
CPU time 9.78 seconds
Started Sep 18 08:10:37 AM UTC 24
Finished Sep 18 08:10:48 AM UTC 24
Peak memory 225624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3791553
666 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_perf.3791553666
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/32.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/32.i2c_target_smbus_maxlen.4264938366
Short name T1160
Test name
Test status
Simulation time 2191576468 ps
CPU time 4.36 seconds
Started Sep 18 08:10:45 AM UTC 24
Finished Sep 18 08:10:50 AM UTC 24
Peak memory 215060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4264938
366 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_smbus_maxlen.4264938366
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/32.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/32.i2c_target_smoke.4263962293
Short name T1139
Test name
Test status
Simulation time 1969141518 ps
CPU time 16.12 seconds
Started Sep 18 08:10:19 AM UTC 24
Finished Sep 18 08:10:36 AM UTC 24
Peak memory 225696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4263962293 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_smoke.4263962293
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/32.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/32.i2c_target_stress_all.2581887898
Short name T1104
Test name
Test status
Simulation time 46360044594 ps
CPU time 43.53 seconds
Started Sep 18 08:10:38 AM UTC 24
Finished Sep 18 08:11:23 AM UTC 24
Peak memory 242540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=258188
7898 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_stress_all.2581887898
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/32.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/32.i2c_target_stress_rd.157851948
Short name T1197
Test name
Test status
Simulation time 5170175566 ps
CPU time 78.5 seconds
Started Sep 18 08:10:22 AM UTC 24
Finished Sep 18 08:11:42 AM UTC 24
Peak memory 231700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=157851948 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_stress_rd.157851948
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/32.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/32.i2c_target_stress_wr.1071323131
Short name T1624
Test name
Test status
Simulation time 48264360095 ps
CPU time 523.29 seconds
Started Sep 18 08:10:21 AM UTC 24
Finished Sep 18 08:19:10 AM UTC 24
Peak memory 6231000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1071323131 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_stress_wr.1071323131
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/32.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/32.i2c_target_stretch.1655521645
Short name T1136
Test name
Test status
Simulation time 2317174730 ps
CPU time 8.54 seconds
Started Sep 18 08:10:23 AM UTC 24
Finished Sep 18 08:10:33 AM UTC 24
Peak memory 279324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1655521645 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_stretch.1655521645
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/32.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/32.i2c_target_timeout.489416426
Short name T1151
Test name
Test status
Simulation time 1420201964 ps
CPU time 11.66 seconds
Started Sep 18 08:10:33 AM UTC 24
Finished Sep 18 08:10:46 AM UTC 24
Peak memory 232236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4894164
26 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_timeout.489416426
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/32.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/32.i2c_target_tx_stretch_ctrl.3062034948
Short name T1153
Test name
Test status
Simulation time 162069795 ps
CPU time 4.19 seconds
Started Sep 18 08:10:43 AM UTC 24
Finished Sep 18 08:10:48 AM UTC 24
Peak memory 215320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3062034
948 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_tx_stretch_ctrl.3062034948
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/32.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/33.i2c_alert_test.958392738
Short name T1183
Test name
Test status
Simulation time 57413023 ps
CPU time 0.96 seconds
Started Sep 18 08:11:28 AM UTC 24
Finished Sep 18 08:11:30 AM UTC 24
Peak memory 214608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=958392738 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_alert_test.958392738
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/33.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/33.i2c_host_error_intr.160592595
Short name T1165
Test name
Test status
Simulation time 157677599 ps
CPU time 2.04 seconds
Started Sep 18 08:10:54 AM UTC 24
Finished Sep 18 08:10:57 AM UTC 24
Peak memory 227780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=160592595 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 33.i2c_host_error_intr.160592595
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/33.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/33.i2c_host_fifo_fmt_empty.1666351232
Short name T1172
Test name
Test status
Simulation time 288918289 ps
CPU time 15.69 seconds
Started Sep 18 08:10:51 AM UTC 24
Finished Sep 18 08:11:08 AM UTC 24
Peak memory 275148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1666351232 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_fmt_empty.1666351232
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/33.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/33.i2c_host_fifo_full.2954540278
Short name T1248
Test name
Test status
Simulation time 7592139804 ps
CPU time 114.39 seconds
Started Sep 18 08:10:51 AM UTC 24
Finished Sep 18 08:12:48 AM UTC 24
Peak memory 678632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2954540278 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_full.2954540278
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/33.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/33.i2c_host_fifo_overflow.3987773194
Short name T1199
Test name
Test status
Simulation time 7361824928 ps
CPU time 52.59 seconds
Started Sep 18 08:10:51 AM UTC 24
Finished Sep 18 08:11:45 AM UTC 24
Peak memory 623460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3987773194 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_overflow.3987773194
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/33.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/33.i2c_host_fifo_reset_fmt.773245059
Short name T1163
Test name
Test status
Simulation time 166226529 ps
CPU time 1.63 seconds
Started Sep 18 08:10:51 AM UTC 24
Finished Sep 18 08:10:54 AM UTC 24
Peak memory 214900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=773245059 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_fmt.773245059
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/33.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/33.i2c_host_fifo_reset_rx.894516386
Short name T1166
Test name
Test status
Simulation time 191651910 ps
CPU time 5.81 seconds
Started Sep 18 08:10:51 AM UTC 24
Finished Sep 18 08:10:58 AM UTC 24
Peak memory 215248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=894516386 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_rx.894516386
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/33.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/33.i2c_host_fifo_watermark.1826224985
Short name T1232
Test name
Test status
Simulation time 15848137562 ps
CPU time 93.17 seconds
Started Sep 18 08:10:49 AM UTC 24
Finished Sep 18 08:12:24 AM UTC 24
Peak memory 1188680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1826224985 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_watermark.1826224985
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/33.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/33.i2c_host_may_nack.2005102250
Short name T1188
Test name
Test status
Simulation time 1419687375 ps
CPU time 11.43 seconds
Started Sep 18 08:11:20 AM UTC 24
Finished Sep 18 08:11:33 AM UTC 24
Peak memory 215252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2005102250 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.i2c_host_may_nack.2005102250
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/33.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/33.i2c_host_override.1597435384
Short name T1162
Test name
Test status
Simulation time 46833449 ps
CPU time 1.14 seconds
Started Sep 18 08:10:49 AM UTC 24
Finished Sep 18 08:10:51 AM UTC 24
Peak memory 214112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1597435384 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.i2c_host_override.1597435384
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/33.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/33.i2c_host_perf.2903995306
Short name T1214
Test name
Test status
Simulation time 28482279803 ps
CPU time 71.91 seconds
Started Sep 18 08:10:52 AM UTC 24
Finished Sep 18 08:12:06 AM UTC 24
Peak memory 901988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2903995306 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 33.i2c_host_perf.2903995306
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/33.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/33.i2c_host_perf_precise.3320573808
Short name T1169
Test name
Test status
Simulation time 469387066 ps
CPU time 8.31 seconds
Started Sep 18 08:10:52 AM UTC 24
Finished Sep 18 08:11:02 AM UTC 24
Peak memory 215352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3320573808 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_perf_precise.3320573808
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/33.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/33.i2c_host_smoke.2818390653
Short name T1209
Test name
Test status
Simulation time 4797976496 ps
CPU time 72.26 seconds
Started Sep 18 08:10:47 AM UTC 24
Finished Sep 18 08:12:01 AM UTC 24
Peak memory 359144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2818390653 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.i2c_host_smoke.2818390653
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/33.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/33.i2c_host_stretch_timeout.1130972876
Short name T1171
Test name
Test status
Simulation time 2104722834 ps
CPU time 11.89 seconds
Started Sep 18 08:10:52 AM UTC 24
Finished Sep 18 08:11:05 AM UTC 24
Peak memory 225504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1130972876 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_stretch_timeout.1130972876
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/33.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/33.i2c_target_bad_addr.1019522428
Short name T1149
Test name
Test status
Simulation time 509741953 ps
CPU time 4.89 seconds
Started Sep 18 08:11:16 AM UTC 24
Finished Sep 18 08:11:22 AM UTC 24
Peak memory 227620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=1019522428 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_bad_ad
dr.1019522428
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/33.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/33.i2c_target_fifo_reset_acq.970208061
Short name T1174
Test name
Test status
Simulation time 551229925 ps
CPU time 1.9 seconds
Started Sep 18 08:11:11 AM UTC 24
Finished Sep 18 08:11:14 AM UTC 24
Peak memory 214844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9702080
61 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_fifo_reset_acq.970208061
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/33.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/33.i2c_target_fifo_reset_tx.4194568176
Short name T1176
Test name
Test status
Simulation time 456530662 ps
CPU time 1.76 seconds
Started Sep 18 08:11:13 AM UTC 24
Finished Sep 18 08:11:16 AM UTC 24
Peak memory 214904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4194568
176 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_fifo_reset_tx.4194568176
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/33.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/33.i2c_target_fifo_watermarks_acq.499785772
Short name T1180
Test name
Test status
Simulation time 605117491 ps
CPU time 2.78 seconds
Started Sep 18 08:11:21 AM UTC 24
Finished Sep 18 08:11:25 AM UTC 24
Peak memory 215300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4997857
72 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_fifo_watermark
s_acq.499785772
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/33.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/33.i2c_target_fifo_watermarks_tx.3463195599
Short name T1178
Test name
Test status
Simulation time 255359011 ps
CPU time 1.43 seconds
Started Sep 18 08:11:21 AM UTC 24
Finished Sep 18 08:11:24 AM UTC 24
Peak memory 214848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3463195
599 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_fifo_watermark
s_tx.3463195599
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/33.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/33.i2c_target_hrst.2847700041
Short name T1141
Test name
Test status
Simulation time 250805410 ps
CPU time 3.44 seconds
Started Sep 18 08:11:16 AM UTC 24
Finished Sep 18 08:11:21 AM UTC 24
Peak memory 225632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2847700
041 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_hrst.2847700041
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/33.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/33.i2c_target_intr_smoke.2927031188
Short name T1173
Test name
Test status
Simulation time 2945704394 ps
CPU time 6.97 seconds
Started Sep 18 08:11:02 AM UTC 24
Finished Sep 18 08:11:10 AM UTC 24
Peak memory 229656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=292703
1188 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_intr_smoke.2927031188
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/33.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/33.i2c_target_intr_stress_wr.470579189
Short name T1191
Test name
Test status
Simulation time 14662238470 ps
CPU time 26.92 seconds
Started Sep 18 08:11:06 AM UTC 24
Finished Sep 18 08:11:34 AM UTC 24
Peak memory 523268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=470579189 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_intr_stress
_wr.470579189
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/33.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/33.i2c_target_nack_acqfull.4115830265
Short name T1186
Test name
Test status
Simulation time 1158127946 ps
CPU time 4.74 seconds
Started Sep 18 08:11:25 AM UTC 24
Finished Sep 18 08:11:30 AM UTC 24
Peak memory 225564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4115830
265 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_nack_acqfull.4115830265
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/33.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/33.i2c_target_nack_acqfull_addr.4152467954
Short name T1187
Test name
Test status
Simulation time 2053207693 ps
CPU time 5.02 seconds
Started Sep 18 08:11:26 AM UTC 24
Finished Sep 18 08:11:32 AM UTC 24
Peak memory 215260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4152467
954 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_nack_acqfull_ad
dr.4152467954
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/33.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/33.i2c_target_perf.726256236
Short name T1179
Test name
Test status
Simulation time 2780602908 ps
CPU time 8.3 seconds
Started Sep 18 08:11:15 AM UTC 24
Finished Sep 18 08:11:24 AM UTC 24
Peak memory 231780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7262562
36 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_perf.726256236
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/33.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/33.i2c_target_smbus_maxlen.3747393564
Short name T1184
Test name
Test status
Simulation time 1734343496 ps
CPU time 4.37 seconds
Started Sep 18 08:11:25 AM UTC 24
Finished Sep 18 08:11:30 AM UTC 24
Peak memory 215224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3747393
564 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_smbus_maxlen.3747393564
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/33.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/33.i2c_target_smoke.3081798545
Short name T1177
Test name
Test status
Simulation time 3281581711 ps
CPU time 16.46 seconds
Started Sep 18 08:10:58 AM UTC 24
Finished Sep 18 08:11:16 AM UTC 24
Peak memory 225620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3081798545 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_smoke.3081798545
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/33.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/33.i2c_target_stress_all.2523097509
Short name T1331
Test name
Test status
Simulation time 82203592125 ps
CPU time 192.97 seconds
Started Sep 18 08:11:16 AM UTC 24
Finished Sep 18 08:14:32 AM UTC 24
Peak memory 2138976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=252309
7509 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_stress_all.2523097509
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/33.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/33.i2c_target_stress_rd.2019371814
Short name T1208
Test name
Test status
Simulation time 1230660051 ps
CPU time 57.62 seconds
Started Sep 18 08:11:00 AM UTC 24
Finished Sep 18 08:12:00 AM UTC 24
Peak memory 227796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2019371814 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_stress_rd.2019371814
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/33.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/33.i2c_target_stress_wr.2063113086
Short name T1402
Test name
Test status
Simulation time 48823990900 ps
CPU time 282.04 seconds
Started Sep 18 08:10:59 AM UTC 24
Finished Sep 18 08:15:45 AM UTC 24
Peak memory 3652576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2063113086 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_stress_wr.2063113086
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/33.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/33.i2c_target_stretch.2118315678
Short name T1175
Test name
Test status
Simulation time 514059652 ps
CPU time 11.96 seconds
Started Sep 18 08:11:02 AM UTC 24
Finished Sep 18 08:11:15 AM UTC 24
Peak memory 254948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2118315678 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_stretch.2118315678
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/33.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/33.i2c_target_timeout.2599292317
Short name T1110
Test name
Test status
Simulation time 6426599131 ps
CPU time 11.75 seconds
Started Sep 18 08:11:07 AM UTC 24
Finished Sep 18 08:11:19 AM UTC 24
Peak memory 242464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2599292
317 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_timeout.2599292317
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/33.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/33.i2c_target_tx_stretch_ctrl.110203154
Short name T1181
Test name
Test status
Simulation time 92258683 ps
CPU time 3.21 seconds
Started Sep 18 08:11:23 AM UTC 24
Finished Sep 18 08:11:27 AM UTC 24
Peak memory 215320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1102031
54 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_tx_stretch_ctrl.110203154
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/33.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/34.i2c_alert_test.3589749088
Short name T1223
Test name
Test status
Simulation time 49411055 ps
CPU time 1.06 seconds
Started Sep 18 08:12:07 AM UTC 24
Finished Sep 18 08:12:10 AM UTC 24
Peak memory 214840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3589749088 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_alert_test.3589749088
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/34.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/34.i2c_host_error_intr.2113189923
Short name T1198
Test name
Test status
Simulation time 532409031 ps
CPU time 4.34 seconds
Started Sep 18 08:11:39 AM UTC 24
Finished Sep 18 08:11:44 AM UTC 24
Peak memory 232216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2113189923 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 34.i2c_host_error_intr.2113189923
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/34.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/34.i2c_host_fifo_fmt_empty.125744492
Short name T1194
Test name
Test status
Simulation time 272988909 ps
CPU time 5.71 seconds
Started Sep 18 08:11:32 AM UTC 24
Finished Sep 18 08:11:39 AM UTC 24
Peak memory 263124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=125744492 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_fmt_empty.125744492
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/34.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/34.i2c_host_fifo_full.2660052122
Short name T1306
Test name
Test status
Simulation time 10384922382 ps
CPU time 140.32 seconds
Started Sep 18 08:11:33 AM UTC 24
Finished Sep 18 08:13:56 AM UTC 24
Peak memory 326468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2660052122 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_full.2660052122
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/34.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/34.i2c_host_fifo_overflow.1417817548
Short name T1244
Test name
Test status
Simulation time 2068070063 ps
CPU time 70.74 seconds
Started Sep 18 08:11:31 AM UTC 24
Finished Sep 18 08:12:44 AM UTC 24
Peak memory 717528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1417817548 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_overflow.1417817548
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/34.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/34.i2c_host_fifo_reset_fmt.2762841750
Short name T1190
Test name
Test status
Simulation time 348110457 ps
CPU time 1.04 seconds
Started Sep 18 08:11:31 AM UTC 24
Finished Sep 18 08:11:33 AM UTC 24
Peak memory 214900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2762841750 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_fmt.2762841750
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/34.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/34.i2c_host_fifo_reset_rx.242438671
Short name T1196
Test name
Test status
Simulation time 688147776 ps
CPU time 4.86 seconds
Started Sep 18 08:11:33 AM UTC 24
Finished Sep 18 08:11:39 AM UTC 24
Peak memory 215320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=242438671 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_rx.242438671
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/34.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/34.i2c_host_fifo_watermark.964645483
Short name T1412
Test name
Test status
Simulation time 17993208820 ps
CPU time 259.34 seconds
Started Sep 18 08:11:31 AM UTC 24
Finished Sep 18 08:15:54 AM UTC 24
Peak memory 1317672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=964645483 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_watermark.964645483
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/34.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/34.i2c_host_may_nack.1275554313
Short name T1221
Test name
Test status
Simulation time 334050037 ps
CPU time 6.7 seconds
Started Sep 18 08:12:01 AM UTC 24
Finished Sep 18 08:12:09 AM UTC 24
Peak memory 215268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1275554313 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.i2c_host_may_nack.1275554313
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/34.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/34.i2c_host_override.121276600
Short name T1189
Test name
Test status
Simulation time 21751503 ps
CPU time 0.99 seconds
Started Sep 18 08:11:31 AM UTC 24
Finished Sep 18 08:11:33 AM UTC 24
Peak memory 214108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=121276600 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 34.i2c_host_override.121276600
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/34.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/34.i2c_host_perf.2348791740
Short name T1219
Test name
Test status
Simulation time 26278393665 ps
CPU time 32.36 seconds
Started Sep 18 08:11:35 AM UTC 24
Finished Sep 18 08:12:08 AM UTC 24
Peak memory 215372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2348791740 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 34.i2c_host_perf.2348791740
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/34.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/34.i2c_host_perf_precise.561519721
Short name T1193
Test name
Test status
Simulation time 209628549 ps
CPU time 2.05 seconds
Started Sep 18 08:11:35 AM UTC 24
Finished Sep 18 08:11:38 AM UTC 24
Peak memory 225444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=561519721 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_perf_precise.561519721
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/34.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/34.i2c_host_smoke.2008276905
Short name T1249
Test name
Test status
Simulation time 3259883849 ps
CPU time 75.17 seconds
Started Sep 18 08:11:31 AM UTC 24
Finished Sep 18 08:12:48 AM UTC 24
Peak memory 439204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2008276905 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.i2c_host_smoke.2008276905
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/34.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/34.i2c_host_stress_all.1908074799
Short name T135
Test name
Test status
Simulation time 12986320771 ps
CPU time 320.36 seconds
Started Sep 18 08:11:40 AM UTC 24
Finished Sep 18 08:17:04 AM UTC 24
Peak memory 3099484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1908074799 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 34.i2c_host_stress_all.1908074799
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/34.i2c_host_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/34.i2c_host_stretch_timeout.1586007720
Short name T1202
Test name
Test status
Simulation time 1219980829 ps
CPU time 14.7 seconds
Started Sep 18 08:11:37 AM UTC 24
Finished Sep 18 08:11:52 AM UTC 24
Peak memory 225432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1586007720 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_stretch_timeout.1586007720
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/34.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/34.i2c_target_bad_addr.2354677142
Short name T1217
Test name
Test status
Simulation time 1187784257 ps
CPU time 8.66 seconds
Started Sep 18 08:11:58 AM UTC 24
Finished Sep 18 08:12:07 AM UTC 24
Peak memory 219428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=2354677142 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_bad_ad
dr.2354677142
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/34.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/34.i2c_target_fifo_reset_acq.2920417048
Short name T1205
Test name
Test status
Simulation time 777762297 ps
CPU time 2.63 seconds
Started Sep 18 08:11:53 AM UTC 24
Finished Sep 18 08:11:57 AM UTC 24
Peak memory 215328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2920417
048 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_fifo_reset_acq.2920417048
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/34.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/34.i2c_target_fifo_reset_tx.4132493031
Short name T1206
Test name
Test status
Simulation time 202858144 ps
CPU time 2.54 seconds
Started Sep 18 08:11:55 AM UTC 24
Finished Sep 18 08:11:58 AM UTC 24
Peak memory 225684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4132493
031 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_fifo_reset_tx.4132493031
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/34.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/34.i2c_target_fifo_watermarks_acq.420669535
Short name T1216
Test name
Test status
Simulation time 10722728544 ps
CPU time 4.2 seconds
Started Sep 18 08:12:02 AM UTC 24
Finished Sep 18 08:12:07 AM UTC 24
Peak memory 215536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4206695
35 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_fifo_watermark
s_acq.420669535
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/34.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/34.i2c_target_fifo_watermarks_tx.1783409391
Short name T1218
Test name
Test status
Simulation time 138278074 ps
CPU time 2.06 seconds
Started Sep 18 08:12:04 AM UTC 24
Finished Sep 18 08:12:08 AM UTC 24
Peak memory 215116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1783409
391 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_fifo_watermark
s_tx.1783409391
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/34.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/34.i2c_target_hrst.265648668
Short name T1213
Test name
Test status
Simulation time 349388957 ps
CPU time 5.03 seconds
Started Sep 18 08:11:59 AM UTC 24
Finished Sep 18 08:12:05 AM UTC 24
Peak memory 225568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2656486
68 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_hrst.265648668
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/34.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/34.i2c_target_intr_smoke.998181132
Short name T1204
Test name
Test status
Simulation time 3848410542 ps
CPU time 9.15 seconds
Started Sep 18 08:11:46 AM UTC 24
Finished Sep 18 08:11:56 AM UTC 24
Peak memory 232232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=998181
132 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_intr_smoke.998181132
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/34.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/34.i2c_target_intr_stress_wr.1708421235
Short name T1210
Test name
Test status
Simulation time 5254686699 ps
CPU time 12.93 seconds
Started Sep 18 08:11:49 AM UTC 24
Finished Sep 18 08:12:03 AM UTC 24
Peak memory 467736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1708421235 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_intr_stres
s_wr.1708421235
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/34.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/34.i2c_target_nack_acqfull.3387989017
Short name T1227
Test name
Test status
Simulation time 2460289514 ps
CPU time 4.08 seconds
Started Sep 18 08:12:06 AM UTC 24
Finished Sep 18 08:12:11 AM UTC 24
Peak memory 225764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3387989
017 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_nack_acqfull.3387989017
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/34.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/34.i2c_target_nack_acqfull_addr.1836591503
Short name T1226
Test name
Test status
Simulation time 530023685 ps
CPU time 3.72 seconds
Started Sep 18 08:12:06 AM UTC 24
Finished Sep 18 08:12:11 AM UTC 24
Peak memory 215336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1836591
503 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_nack_acqfull_ad
dr.1836591503
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/34.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/34.i2c_target_nack_txstretch.3632785104
Short name T1222
Test name
Test status
Simulation time 128562239 ps
CPU time 2.07 seconds
Started Sep 18 08:12:06 AM UTC 24
Finished Sep 18 08:12:09 AM UTC 24
Peak memory 232356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3632785
104 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_nack_txstretch.3632785104
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/34.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/34.i2c_target_perf.1151875730
Short name T1212
Test name
Test status
Simulation time 2310780368 ps
CPU time 6.6 seconds
Started Sep 18 08:11:57 AM UTC 24
Finished Sep 18 08:12:04 AM UTC 24
Peak memory 225632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1151875
730 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_perf.1151875730
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/34.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/34.i2c_target_smbus_maxlen.1515858145
Short name T1224
Test name
Test status
Simulation time 2887824606 ps
CPU time 3.5 seconds
Started Sep 18 08:12:05 AM UTC 24
Finished Sep 18 08:12:10 AM UTC 24
Peak memory 215084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1515858
145 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_smbus_maxlen.1515858145
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/34.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/34.i2c_target_smoke.600899440
Short name T1230
Test name
Test status
Simulation time 18437816419 ps
CPU time 38.51 seconds
Started Sep 18 08:11:40 AM UTC 24
Finished Sep 18 08:12:20 AM UTC 24
Peak memory 225816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=600899440 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_smoke.600899440
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/34.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/34.i2c_target_stress_all.2086637852
Short name T1356
Test name
Test status
Simulation time 17901717472 ps
CPU time 176.81 seconds
Started Sep 18 08:11:58 AM UTC 24
Finished Sep 18 08:14:57 AM UTC 24
Peak memory 2329492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=208663
7852 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_stress_all.2086637852
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/34.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/34.i2c_target_stress_rd.2388537716
Short name T1207
Test name
Test status
Simulation time 1495486814 ps
CPU time 14.76 seconds
Started Sep 18 08:11:43 AM UTC 24
Finished Sep 18 08:11:59 AM UTC 24
Peak memory 224004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2388537716 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_stress_rd.2388537716
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/34.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/34.i2c_target_stress_wr.1759334289
Short name T1263
Test name
Test status
Simulation time 31889557883 ps
CPU time 86.93 seconds
Started Sep 18 08:11:40 AM UTC 24
Finished Sep 18 08:13:09 AM UTC 24
Peak memory 1450776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1759334289 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_stress_wr.1759334289
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/34.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/34.i2c_target_stretch.3399434553
Short name T1203
Test name
Test status
Simulation time 308425131 ps
CPU time 7.08 seconds
Started Sep 18 08:11:45 AM UTC 24
Finished Sep 18 08:11:53 AM UTC 24
Peak memory 228188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3399434553 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_stretch.3399434553
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/34.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/34.i2c_target_timeout.1424394173
Short name T1211
Test name
Test status
Simulation time 2365905589 ps
CPU time 9.52 seconds
Started Sep 18 08:11:53 AM UTC 24
Finished Sep 18 08:12:04 AM UTC 24
Peak memory 232420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1424394
173 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_timeout.1424394173
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/34.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/34.i2c_target_tx_stretch_ctrl.2245573268
Short name T1220
Test name
Test status
Simulation time 97173690 ps
CPU time 2.44 seconds
Started Sep 18 08:12:05 AM UTC 24
Finished Sep 18 08:12:09 AM UTC 24
Peak memory 215320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2245573
268 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_tx_stretch_ctrl.2245573268
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/34.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/35.i2c_alert_test.2151704008
Short name T1182
Test name
Test status
Simulation time 51035208 ps
CPU time 1 seconds
Started Sep 18 08:12:51 AM UTC 24
Finished Sep 18 08:12:53 AM UTC 24
Peak memory 214840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2151704008 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_alert_test.2151704008
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/35.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/35.i2c_host_error_intr.2467546333
Short name T1229
Test name
Test status
Simulation time 357611354 ps
CPU time 3.97 seconds
Started Sep 18 08:12:12 AM UTC 24
Finished Sep 18 08:12:17 AM UTC 24
Peak memory 225656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2467546333 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 35.i2c_host_error_intr.2467546333
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/35.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/35.i2c_host_fifo_fmt_empty.1150549185
Short name T1235
Test name
Test status
Simulation time 1194905708 ps
CPU time 17.93 seconds
Started Sep 18 08:12:10 AM UTC 24
Finished Sep 18 08:12:29 AM UTC 24
Peak memory 279188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1150549185 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_fmt_empty.1150549185
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/35.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/35.i2c_host_fifo_full.2958789142
Short name T1358
Test name
Test status
Simulation time 5153085994 ps
CPU time 165.81 seconds
Started Sep 18 08:12:11 AM UTC 24
Finished Sep 18 08:14:59 AM UTC 24
Peak memory 756648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2958789142 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_full.2958789142
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/35.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/35.i2c_host_fifo_overflow.841520730
Short name T1279
Test name
Test status
Simulation time 1299416800 ps
CPU time 74.4 seconds
Started Sep 18 08:12:10 AM UTC 24
Finished Sep 18 08:13:26 AM UTC 24
Peak memory 539360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=841520730 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_overflow.841520730
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/35.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/35.i2c_host_fifo_reset_fmt.3334641712
Short name T1228
Test name
Test status
Simulation time 98394762 ps
CPU time 1.51 seconds
Started Sep 18 08:12:10 AM UTC 24
Finished Sep 18 08:12:13 AM UTC 24
Peak memory 215020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3334641712 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_fmt.3334641712
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/35.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/35.i2c_host_fifo_reset_rx.3987170621
Short name T1231
Test name
Test status
Simulation time 594877195 ps
CPU time 10.31 seconds
Started Sep 18 08:12:10 AM UTC 24
Finished Sep 18 08:12:22 AM UTC 24
Peak memory 240284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3987170621 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_rx.3987170621
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/35.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/35.i2c_host_fifo_watermark.449540233
Short name T1303
Test name
Test status
Simulation time 12613275109 ps
CPU time 104.13 seconds
Started Sep 18 08:12:09 AM UTC 24
Finished Sep 18 08:13:55 AM UTC 24
Peak memory 1536804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=449540233 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_watermark.449540233
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/35.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/35.i2c_host_may_nack.1614025660
Short name T1257
Test name
Test status
Simulation time 340441900 ps
CPU time 12.83 seconds
Started Sep 18 08:12:45 AM UTC 24
Finished Sep 18 08:12:58 AM UTC 24
Peak memory 215464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1614025660 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.i2c_host_may_nack.1614025660
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/35.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/35.i2c_host_override.3542329877
Short name T1225
Test name
Test status
Simulation time 46079244 ps
CPU time 0.86 seconds
Started Sep 18 08:12:09 AM UTC 24
Finished Sep 18 08:12:11 AM UTC 24
Peak memory 214112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3542329877 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.i2c_host_override.3542329877
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/35.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/35.i2c_host_perf.783098328
Short name T1252
Test name
Test status
Simulation time 6554829915 ps
CPU time 41.12 seconds
Started Sep 18 08:12:11 AM UTC 24
Finished Sep 18 08:12:54 AM UTC 24
Peak memory 543440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=783098328 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 35.i2c_host_perf.783098328
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/35.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/35.i2c_host_perf_precise.502585128
Short name T1272
Test name
Test status
Simulation time 2795487796 ps
CPU time 65.18 seconds
Started Sep 18 08:12:11 AM UTC 24
Finished Sep 18 08:13:18 AM UTC 24
Peak memory 215316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=502585128 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_perf_precise.502585128
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/35.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/35.i2c_host_smoke.2137730537
Short name T1243
Test name
Test status
Simulation time 1441615246 ps
CPU time 33.34 seconds
Started Sep 18 08:12:09 AM UTC 24
Finished Sep 18 08:12:43 AM UTC 24
Peak memory 422808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2137730537 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.i2c_host_smoke.2137730537
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/35.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/35.i2c_host_stretch_timeout.2943533977
Short name T1233
Test name
Test status
Simulation time 6074245916 ps
CPU time 14.57 seconds
Started Sep 18 08:12:12 AM UTC 24
Finished Sep 18 08:12:28 AM UTC 24
Peak memory 231792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2943533977 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_stretch_timeout.2943533977
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/35.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/35.i2c_target_bad_addr.818176449
Short name T1246
Test name
Test status
Simulation time 2244224170 ps
CPU time 4.8 seconds
Started Sep 18 08:12:39 AM UTC 24
Finished Sep 18 08:12:45 AM UTC 24
Peak memory 225612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=818176449 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_bad_addr.818176449
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/35.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/35.i2c_target_fifo_reset_acq.2776692108
Short name T1240
Test name
Test status
Simulation time 135878670 ps
CPU time 1.51 seconds
Started Sep 18 08:12:36 AM UTC 24
Finished Sep 18 08:12:39 AM UTC 24
Peak memory 214220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2776692
108 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_fifo_reset_acq.2776692108
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/35.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/35.i2c_target_fifo_reset_tx.2007640272
Short name T1242
Test name
Test status
Simulation time 472941944 ps
CPU time 2.51 seconds
Started Sep 18 08:12:37 AM UTC 24
Finished Sep 18 08:12:41 AM UTC 24
Peak memory 215324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2007640
272 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_fifo_reset_tx.2007640272
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/35.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/35.i2c_target_fifo_watermarks_acq.757563803
Short name T1251
Test name
Test status
Simulation time 2339035367 ps
CPU time 5.24 seconds
Started Sep 18 08:12:45 AM UTC 24
Finished Sep 18 08:12:51 AM UTC 24
Peak memory 215580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7575638
03 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_fifo_watermark
s_acq.757563803
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/35.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/35.i2c_target_fifo_watermarks_tx.2864516197
Short name T1247
Test name
Test status
Simulation time 111703488 ps
CPU time 1.85 seconds
Started Sep 18 08:12:45 AM UTC 24
Finished Sep 18 08:12:47 AM UTC 24
Peak memory 215032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2864516
197 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_fifo_watermark
s_tx.2864516197
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/35.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/35.i2c_target_intr_smoke.3596867284
Short name T1241
Test name
Test status
Simulation time 1588217013 ps
CPU time 9.57 seconds
Started Sep 18 08:12:29 AM UTC 24
Finished Sep 18 08:12:40 AM UTC 24
Peak memory 225508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=359686
7284 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_intr_smoke.3596867284
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/35.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/35.i2c_target_intr_stress_wr.3879263004
Short name T1372
Test name
Test status
Simulation time 11064433906 ps
CPU time 167.71 seconds
Started Sep 18 08:12:30 AM UTC 24
Finished Sep 18 08:15:20 AM UTC 24
Peak memory 2872156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3879263004 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_intr_stres
s_wr.3879263004
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/35.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/35.i2c_target_nack_acqfull.1114740810
Short name T1253
Test name
Test status
Simulation time 848527267 ps
CPU time 3.85 seconds
Started Sep 18 08:12:48 AM UTC 24
Finished Sep 18 08:12:53 AM UTC 24
Peak memory 225636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1114740
810 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_nack_acqfull.1114740810
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/35.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/35.i2c_target_nack_acqfull_addr.876086963
Short name T1254
Test name
Test status
Simulation time 1053548962 ps
CPU time 4.54 seconds
Started Sep 18 08:12:49 AM UTC 24
Finished Sep 18 08:12:54 AM UTC 24
Peak memory 215336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8760869
63 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_nack_acqfull_addr.876086963
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/35.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/35.i2c_target_perf.3599700770
Short name T1245
Test name
Test status
Simulation time 894757353 ps
CPU time 3.9 seconds
Started Sep 18 08:12:39 AM UTC 24
Finished Sep 18 08:12:44 AM UTC 24
Peak memory 231888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3599700
770 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_perf.3599700770
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/35.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/35.i2c_target_smbus_maxlen.1012414824
Short name T1250
Test name
Test status
Simulation time 1606651319 ps
CPU time 3.73 seconds
Started Sep 18 08:12:46 AM UTC 24
Finished Sep 18 08:12:50 AM UTC 24
Peak memory 215096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1012414
824 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_smbus_maxlen.1012414824
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/35.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/35.i2c_target_smoke.3931278214
Short name T1261
Test name
Test status
Simulation time 1156415781 ps
CPU time 42.97 seconds
Started Sep 18 08:12:18 AM UTC 24
Finished Sep 18 08:13:03 AM UTC 24
Peak memory 225548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3931278214 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_smoke.3931278214
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/35.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/35.i2c_target_stress_all.601366207
Short name T1369
Test name
Test status
Simulation time 105152496870 ps
CPU time 155.64 seconds
Started Sep 18 08:12:39 AM UTC 24
Finished Sep 18 08:15:17 AM UTC 24
Peak memory 1436512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=601366
207 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_stress_all.601366207
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/35.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/35.i2c_target_stress_rd.2969996166
Short name T1258
Test name
Test status
Simulation time 699462695 ps
CPU time 34.91 seconds
Started Sep 18 08:12:23 AM UTC 24
Finished Sep 18 08:12:59 AM UTC 24
Peak memory 225560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2969996166 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_stress_rd.2969996166
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/35.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/35.i2c_target_stress_wr.931017119
Short name T1234
Test name
Test status
Simulation time 17660792868 ps
CPU time 6.95 seconds
Started Sep 18 08:12:21 AM UTC 24
Finished Sep 18 08:12:29 AM UTC 24
Peak memory 215384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=931017119 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_stress_wr.931017119
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/35.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/35.i2c_target_stretch.4277645562
Short name T1236
Test name
Test status
Simulation time 1122347404 ps
CPU time 4.31 seconds
Started Sep 18 08:12:26 AM UTC 24
Finished Sep 18 08:12:31 AM UTC 24
Peak memory 234252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4277645562 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_stretch.4277645562
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/35.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/35.i2c_target_timeout.1374557734
Short name T1239
Test name
Test status
Simulation time 4698985276 ps
CPU time 7.44 seconds
Started Sep 18 08:12:30 AM UTC 24
Finished Sep 18 08:12:39 AM UTC 24
Peak memory 242524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1374557
734 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_timeout.1374557734
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/35.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/35.i2c_target_tx_stretch_ctrl.469709883
Short name T1269
Test name
Test status
Simulation time 1465757252 ps
CPU time 27.93 seconds
Started Sep 18 08:12:46 AM UTC 24
Finished Sep 18 08:13:15 AM UTC 24
Peak memory 215320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4697098
83 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_tx_stretch_ctrl.469709883
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/35.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/36.i2c_alert_test.2406879377
Short name T1284
Test name
Test status
Simulation time 100359830 ps
CPU time 0.91 seconds
Started Sep 18 08:13:28 AM UTC 24
Finished Sep 18 08:13:30 AM UTC 24
Peak memory 214900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2406879377 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_alert_test.2406879377
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/36.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/36.i2c_host_error_intr.854180217
Short name T1266
Test name
Test status
Simulation time 207425757 ps
CPU time 9.91 seconds
Started Sep 18 08:13:02 AM UTC 24
Finished Sep 18 08:13:13 AM UTC 24
Peak memory 248804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=854180217 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 36.i2c_host_error_intr.854180217
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/36.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/36.i2c_host_fifo_fmt_empty.166032628
Short name T1260
Test name
Test status
Simulation time 429443962 ps
CPU time 5.2 seconds
Started Sep 18 08:12:56 AM UTC 24
Finished Sep 18 08:13:02 AM UTC 24
Peak memory 250528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=166032628 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_fmt_empty.166032628
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/36.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/36.i2c_host_fifo_full.383676041
Short name T1410
Test name
Test status
Simulation time 2795523976 ps
CPU time 173.35 seconds
Started Sep 18 08:12:58 AM UTC 24
Finished Sep 18 08:15:54 AM UTC 24
Peak memory 422772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=383676041 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_full.383676041
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/36.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/36.i2c_host_fifo_overflow.192014929
Short name T1385
Test name
Test status
Simulation time 2340555392 ps
CPU time 151.91 seconds
Started Sep 18 08:12:54 AM UTC 24
Finished Sep 18 08:15:29 AM UTC 24
Peak memory 774952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=192014929 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_overflow.192014929
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/36.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/36.i2c_host_fifo_reset_fmt.3773147115
Short name T1256
Test name
Test status
Simulation time 118343983 ps
CPU time 1.85 seconds
Started Sep 18 08:12:54 AM UTC 24
Finished Sep 18 08:12:57 AM UTC 24
Peak memory 214900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3773147115 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_fmt.3773147115
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/36.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/36.i2c_host_fifo_reset_rx.1105450750
Short name T1265
Test name
Test status
Simulation time 807912824 ps
CPU time 12.68 seconds
Started Sep 18 08:12:56 AM UTC 24
Finished Sep 18 08:13:09 AM UTC 24
Peak memory 215268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1105450750 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_rx.1105450750
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/36.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/36.i2c_host_fifo_watermark.1820511789
Short name T1346
Test name
Test status
Simulation time 4761171674 ps
CPU time 116.36 seconds
Started Sep 18 08:12:53 AM UTC 24
Finished Sep 18 08:14:52 AM UTC 24
Peak memory 1381052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1820511789 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_watermark.1820511789
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/36.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/36.i2c_host_may_nack.4147903959
Short name T1292
Test name
Test status
Simulation time 6342937682 ps
CPU time 11.03 seconds
Started Sep 18 08:13:21 AM UTC 24
Finished Sep 18 08:13:34 AM UTC 24
Peak memory 215448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4147903959 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.i2c_host_may_nack.4147903959
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/36.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/36.i2c_host_override.3429481810
Short name T155
Test name
Test status
Simulation time 29044638 ps
CPU time 0.97 seconds
Started Sep 18 08:12:53 AM UTC 24
Finished Sep 18 08:12:55 AM UTC 24
Peak memory 214112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3429481810 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.i2c_host_override.3429481810
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/36.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/36.i2c_host_perf.4137313424
Short name T1276
Test name
Test status
Simulation time 2742717139 ps
CPU time 26.37 seconds
Started Sep 18 08:12:58 AM UTC 24
Finished Sep 18 08:13:25 AM UTC 24
Peak memory 239836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4137313424 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 36.i2c_host_perf.4137313424
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/36.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/36.i2c_host_perf_precise.1561267189
Short name T1267
Test name
Test status
Simulation time 2681997780 ps
CPU time 13.38 seconds
Started Sep 18 08:12:59 AM UTC 24
Finished Sep 18 08:13:13 AM UTC 24
Peak memory 233704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1561267189 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_perf_precise.1561267189
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/36.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/36.i2c_host_smoke.162674820
Short name T1334
Test name
Test status
Simulation time 2767774953 ps
CPU time 102.38 seconds
Started Sep 18 08:12:52 AM UTC 24
Finished Sep 18 08:14:37 AM UTC 24
Peak memory 445156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=162674820 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 36.i2c_host_smoke.162674820
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/36.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/36.i2c_host_stretch_timeout.2314015730
Short name T1271
Test name
Test status
Simulation time 3015386073 ps
CPU time 16.27 seconds
Started Sep 18 08:13:00 AM UTC 24
Finished Sep 18 08:13:17 AM UTC 24
Peak memory 232344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2314015730 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_stretch_timeout.2314015730
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/36.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/36.i2c_target_bad_addr.1176534034
Short name T1282
Test name
Test status
Simulation time 965570395 ps
CPU time 7.82 seconds
Started Sep 18 08:13:19 AM UTC 24
Finished Sep 18 08:13:28 AM UTC 24
Peak memory 225572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=1176534034 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_bad_ad
dr.1176534034
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/36.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/36.i2c_target_fifo_reset_acq.1862872377
Short name T1270
Test name
Test status
Simulation time 265007485 ps
CPU time 1.38 seconds
Started Sep 18 08:13:15 AM UTC 24
Finished Sep 18 08:13:17 AM UTC 24
Peak memory 214784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1862872
377 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_fifo_reset_acq.1862872377
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/36.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/36.i2c_target_fifo_reset_tx.313300229
Short name T1273
Test name
Test status
Simulation time 992326668 ps
CPU time 1.86 seconds
Started Sep 18 08:13:16 AM UTC 24
Finished Sep 18 08:13:19 AM UTC 24
Peak memory 214804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3133002
29 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_fifo_reset_tx.313300229
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/36.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/36.i2c_target_fifo_watermarks_acq.3485076775
Short name T1283
Test name
Test status
Simulation time 496991999 ps
CPU time 3.88 seconds
Started Sep 18 08:13:24 AM UTC 24
Finished Sep 18 08:13:29 AM UTC 24
Peak memory 215340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3485076
775 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_fifo_watermar
ks_acq.3485076775
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/36.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/36.i2c_target_intr_smoke.3511655200
Short name T1275
Test name
Test status
Simulation time 1291685480 ps
CPU time 12.79 seconds
Started Sep 18 08:13:10 AM UTC 24
Finished Sep 18 08:13:24 AM UTC 24
Peak memory 229792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=351165
5200 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_intr_smoke.3511655200
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/36.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/36.i2c_target_intr_stress_wr.2185543367
Short name T1341
Test name
Test status
Simulation time 24714393351 ps
CPU time 90.75 seconds
Started Sep 18 08:13:10 AM UTC 24
Finished Sep 18 08:14:43 AM UTC 24
Peak memory 1123108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2185543367 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_intr_stres
s_wr.2185543367
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/36.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/36.i2c_target_nack_acqfull.1739559062
Short name T1291
Test name
Test status
Simulation time 474063465 ps
CPU time 4.3 seconds
Started Sep 18 08:13:27 AM UTC 24
Finished Sep 18 08:13:32 AM UTC 24
Peak memory 225580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1739559
062 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_nack_acqfull.1739559062
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/36.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/36.i2c_target_nack_acqfull_addr.2390974183
Short name T1288
Test name
Test status
Simulation time 1003829722 ps
CPU time 3.38 seconds
Started Sep 18 08:13:27 AM UTC 24
Finished Sep 18 08:13:31 AM UTC 24
Peak memory 215340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2390974
183 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_nack_acqfull_ad
dr.2390974183
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/36.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/36.i2c_target_perf.1036003529
Short name T1278
Test name
Test status
Simulation time 2932175737 ps
CPU time 6.9 seconds
Started Sep 18 08:13:18 AM UTC 24
Finished Sep 18 08:13:26 AM UTC 24
Peak memory 225688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1036003
529 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_perf.1036003529
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/36.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/36.i2c_target_smbus_maxlen.639265053
Short name T1290
Test name
Test status
Simulation time 5504175302 ps
CPU time 4.39 seconds
Started Sep 18 08:13:27 AM UTC 24
Finished Sep 18 08:13:32 AM UTC 24
Peak memory 215092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6392650
53 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_smbus_maxlen.639265053
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/36.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/36.i2c_target_smoke.197879616
Short name T1287
Test name
Test status
Simulation time 3049175104 ps
CPU time 25.61 seconds
Started Sep 18 08:13:04 AM UTC 24
Finished Sep 18 08:13:31 AM UTC 24
Peak memory 217544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=197879616 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_smoke.197879616
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/36.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/36.i2c_target_stress_all.2529773943
Short name T1461
Test name
Test status
Simulation time 38599259309 ps
CPU time 185.49 seconds
Started Sep 18 08:13:18 AM UTC 24
Finished Sep 18 08:16:26 AM UTC 24
Peak memory 2599720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=252977
3943 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_stress_all.2529773943
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/36.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/36.i2c_target_stress_rd.1759628722
Short name T1274
Test name
Test status
Simulation time 6540610628 ps
CPU time 11.06 seconds
Started Sep 18 08:13:08 AM UTC 24
Finished Sep 18 08:13:20 AM UTC 24
Peak memory 219472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1759628722 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_stress_rd.1759628722
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/36.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/36.i2c_target_stress_wr.3078258243
Short name T1297
Test name
Test status
Simulation time 10035650885 ps
CPU time 36.96 seconds
Started Sep 18 08:13:07 AM UTC 24
Finished Sep 18 08:13:46 AM UTC 24
Peak memory 215516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3078258243 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_stress_wr.3078258243
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/36.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/36.i2c_target_stretch.1989240032
Short name T1268
Test name
Test status
Simulation time 223235339 ps
CPU time 3.07 seconds
Started Sep 18 08:13:09 AM UTC 24
Finished Sep 18 08:13:13 AM UTC 24
Peak memory 215392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1989240032 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_stretch.1989240032
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/36.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/36.i2c_target_timeout.4242067238
Short name T1277
Test name
Test status
Simulation time 4338419101 ps
CPU time 10.74 seconds
Started Sep 18 08:13:14 AM UTC 24
Finished Sep 18 08:13:25 AM UTC 24
Peak memory 232228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4242067
238 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_timeout.4242067238
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/36.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/36.i2c_target_tx_stretch_ctrl.2625797483
Short name T1285
Test name
Test status
Simulation time 153881717 ps
CPU time 3.97 seconds
Started Sep 18 08:13:26 AM UTC 24
Finished Sep 18 08:13:31 AM UTC 24
Peak memory 215324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2625797
483 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_tx_stretch_ctrl.2625797483
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/36.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/37.i2c_alert_test.1666884221
Short name T1319
Test name
Test status
Simulation time 17116256 ps
CPU time 1.01 seconds
Started Sep 18 08:14:06 AM UTC 24
Finished Sep 18 08:14:09 AM UTC 24
Peak memory 214840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1666884221 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_alert_test.1666884221
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/37.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/37.i2c_host_error_intr.2571118743
Short name T1295
Test name
Test status
Simulation time 448351523 ps
CPU time 2.51 seconds
Started Sep 18 08:13:35 AM UTC 24
Finished Sep 18 08:13:38 AM UTC 24
Peak memory 225572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2571118743 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 37.i2c_host_error_intr.2571118743
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/37.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/37.i2c_host_fifo_fmt_empty.2772621874
Short name T1300
Test name
Test status
Simulation time 1266144897 ps
CPU time 17.76 seconds
Started Sep 18 08:13:31 AM UTC 24
Finished Sep 18 08:13:50 AM UTC 24
Peak memory 283284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2772621874 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_fmt_empty.2772621874
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/37.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/37.i2c_host_fifo_full.370658678
Short name T1445
Test name
Test status
Simulation time 4845670887 ps
CPU time 161.86 seconds
Started Sep 18 08:13:32 AM UTC 24
Finished Sep 18 08:16:17 AM UTC 24
Peak memory 779044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=370658678 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_full.370658678
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/37.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/37.i2c_host_fifo_overflow.1241149866
Short name T1327
Test name
Test status
Simulation time 8329201444 ps
CPU time 44.28 seconds
Started Sep 18 08:13:30 AM UTC 24
Finished Sep 18 08:14:16 AM UTC 24
Peak memory 521184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1241149866 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_overflow.1241149866
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/37.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/37.i2c_host_fifo_reset_fmt.117149215
Short name T1293
Test name
Test status
Simulation time 329252774 ps
CPU time 1.76 seconds
Started Sep 18 08:13:31 AM UTC 24
Finished Sep 18 08:13:34 AM UTC 24
Peak memory 214904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=117149215 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_fmt.117149215
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/37.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/37.i2c_host_fifo_reset_rx.3714650695
Short name T1296
Test name
Test status
Simulation time 119522102 ps
CPU time 4.85 seconds
Started Sep 18 08:13:32 AM UTC 24
Finished Sep 18 08:13:38 AM UTC 24
Peak memory 230120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3714650695 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_rx.3714650695
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/37.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/37.i2c_host_fifo_watermark.1714950590
Short name T1348
Test name
Test status
Simulation time 13471354617 ps
CPU time 81.82 seconds
Started Sep 18 08:13:30 AM UTC 24
Finished Sep 18 08:14:54 AM UTC 24
Peak memory 1043236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1714950590 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_watermark.1714950590
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/37.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/37.i2c_host_may_nack.2238188090
Short name T1317
Test name
Test status
Simulation time 1446878249 ps
CPU time 8.24 seconds
Started Sep 18 08:13:58 AM UTC 24
Finished Sep 18 08:14:07 AM UTC 24
Peak memory 215452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2238188090 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.i2c_host_may_nack.2238188090
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/37.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/37.i2c_host_override.145436474
Short name T1286
Test name
Test status
Simulation time 129744344 ps
CPU time 0.94 seconds
Started Sep 18 08:13:29 AM UTC 24
Finished Sep 18 08:13:31 AM UTC 24
Peak memory 214108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=145436474 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 37.i2c_host_override.145436474
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/37.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/37.i2c_host_perf.3733184155
Short name T1749
Test name
Test status
Simulation time 28002875277 ps
CPU time 1177.35 seconds
Started Sep 18 08:13:32 AM UTC 24
Finished Sep 18 08:33:23 AM UTC 24
Peak memory 570132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3733184155 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 37.i2c_host_perf.3733184155
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/37.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/37.i2c_host_perf_precise.2579713883
Short name T1352
Test name
Test status
Simulation time 6081072164 ps
CPU time 80.54 seconds
Started Sep 18 08:13:34 AM UTC 24
Finished Sep 18 08:14:56 AM UTC 24
Peak memory 590696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2579713883 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_perf_precise.2579713883
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/37.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/37.i2c_host_smoke.2159244609
Short name T1324
Test name
Test status
Simulation time 12931308628 ps
CPU time 41.91 seconds
Started Sep 18 08:13:29 AM UTC 24
Finished Sep 18 08:14:12 AM UTC 24
Peak memory 447248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2159244609 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 37.i2c_host_smoke.2159244609
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/37.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/37.i2c_host_stretch_timeout.4124386927
Short name T1298
Test name
Test status
Simulation time 720069361 ps
CPU time 12.66 seconds
Started Sep 18 08:13:34 AM UTC 24
Finished Sep 18 08:13:47 AM UTC 24
Peak memory 231844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4124386927 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_stretch_timeout.4124386927
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/37.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/37.i2c_target_bad_addr.888201998
Short name T1314
Test name
Test status
Simulation time 862402336 ps
CPU time 7.6 seconds
Started Sep 18 08:13:57 AM UTC 24
Finished Sep 18 08:14:05 AM UTC 24
Peak memory 229796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=888201998 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_bad_addr.888201998
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/37.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/37.i2c_target_fifo_reset_acq.1691647389
Short name T1304
Test name
Test status
Simulation time 155325627 ps
CPU time 1.19 seconds
Started Sep 18 08:13:53 AM UTC 24
Finished Sep 18 08:13:55 AM UTC 24
Peak memory 214784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1691647
389 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_fifo_reset_acq.1691647389
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/37.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/37.i2c_target_fifo_reset_tx.2869347325
Short name T1307
Test name
Test status
Simulation time 304467021 ps
CPU time 1.43 seconds
Started Sep 18 08:13:54 AM UTC 24
Finished Sep 18 08:13:57 AM UTC 24
Peak memory 214904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2869347
325 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_fifo_reset_tx.2869347325
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/37.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/37.i2c_target_fifo_watermarks_acq.1465806529
Short name T1312
Test name
Test status
Simulation time 433615002 ps
CPU time 3.97 seconds
Started Sep 18 08:13:58 AM UTC 24
Finished Sep 18 08:14:03 AM UTC 24
Peak memory 215324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1465806
529 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_fifo_watermar
ks_acq.1465806529
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/37.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/37.i2c_target_fifo_watermarks_tx.2813057014
Short name T1313
Test name
Test status
Simulation time 942917664 ps
CPU time 2.35 seconds
Started Sep 18 08:14:00 AM UTC 24
Finished Sep 18 08:14:03 AM UTC 24
Peak memory 215244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2813057
014 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_fifo_watermark
s_tx.2813057014
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/37.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/37.i2c_target_hrst.1013515103
Short name T1310
Test name
Test status
Simulation time 728510714 ps
CPU time 3.94 seconds
Started Sep 18 08:13:57 AM UTC 24
Finished Sep 18 08:14:02 AM UTC 24
Peak memory 232236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1013515
103 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_hrst.1013515103
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/37.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/37.i2c_target_intr_smoke.2845138890
Short name T1305
Test name
Test status
Simulation time 4704100946 ps
CPU time 8.45 seconds
Started Sep 18 08:13:46 AM UTC 24
Finished Sep 18 08:13:56 AM UTC 24
Peak memory 219428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=284513
8890 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_intr_smoke.2845138890
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/37.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/37.i2c_target_intr_stress_wr.2720984687
Short name T1399
Test name
Test status
Simulation time 20719395738 ps
CPU time 110.33 seconds
Started Sep 18 08:13:48 AM UTC 24
Finished Sep 18 08:15:41 AM UTC 24
Peak memory 2612072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2720984687 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_intr_stres
s_wr.2720984687
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/37.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/37.i2c_target_nack_acqfull.595689110
Short name T1320
Test name
Test status
Simulation time 2318341234 ps
CPU time 5.06 seconds
Started Sep 18 08:14:03 AM UTC 24
Finished Sep 18 08:14:09 AM UTC 24
Peak memory 225692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5956891
10 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_nack_acqfull.595689110
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/37.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/37.i2c_target_nack_acqfull_addr.2744958248
Short name T1322
Test name
Test status
Simulation time 10785812008 ps
CPU time 4.44 seconds
Started Sep 18 08:14:04 AM UTC 24
Finished Sep 18 08:14:10 AM UTC 24
Peak memory 215324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2744958
248 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_nack_acqfull_ad
dr.2744958248
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/37.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/37.i2c_target_nack_txstretch.396081982
Short name T1318
Test name
Test status
Simulation time 765402288 ps
CPU time 2.66 seconds
Started Sep 18 08:14:04 AM UTC 24
Finished Sep 18 08:14:08 AM UTC 24
Peak memory 232216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3960819
82 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_nack_txstretch.396081982
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/37.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/37.i2c_target_perf.2681660440
Short name T1311
Test name
Test status
Simulation time 613215021 ps
CPU time 7.14 seconds
Started Sep 18 08:13:54 AM UTC 24
Finished Sep 18 08:14:03 AM UTC 24
Peak memory 229592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2681660
440 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_perf.2681660440
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/37.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/37.i2c_target_smbus_maxlen.2546132860
Short name T1316
Test name
Test status
Simulation time 1827474068 ps
CPU time 3.16 seconds
Started Sep 18 08:14:02 AM UTC 24
Finished Sep 18 08:14:06 AM UTC 24
Peak memory 215220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2546132
860 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_smbus_maxlen.2546132860
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/37.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/37.i2c_target_smoke.797932842
Short name T1299
Test name
Test status
Simulation time 641430469 ps
CPU time 11.99 seconds
Started Sep 18 08:13:36 AM UTC 24
Finished Sep 18 08:13:49 AM UTC 24
Peak memory 225184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=797932842 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_smoke.797932842
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/37.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/37.i2c_target_stress_all.2227316926
Short name T1364
Test name
Test status
Simulation time 41364188932 ps
CPU time 74.29 seconds
Started Sep 18 08:13:56 AM UTC 24
Finished Sep 18 08:15:12 AM UTC 24
Peak memory 988012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=222731
6926 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_stress_all.2227316926
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/37.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/37.i2c_target_stress_rd.286821076
Short name T1301
Test name
Test status
Simulation time 722182372 ps
CPU time 11.56 seconds
Started Sep 18 08:13:39 AM UTC 24
Finished Sep 18 08:13:52 AM UTC 24
Peak memory 221536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=286821076 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_stress_rd.286821076
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/37.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/37.i2c_target_stress_wr.1965278054
Short name T1529
Test name
Test status
Simulation time 63728229249 ps
CPU time 226.7 seconds
Started Sep 18 08:13:36 AM UTC 24
Finished Sep 18 08:17:25 AM UTC 24
Peak memory 2925216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1965278054 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_stress_wr.1965278054
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/37.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/37.i2c_target_stretch.2618913527
Short name T1309
Test name
Test status
Simulation time 4994899371 ps
CPU time 18.31 seconds
Started Sep 18 08:13:39 AM UTC 24
Finished Sep 18 08:13:59 AM UTC 24
Peak memory 488272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2618913527 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_stretch.2618913527
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/37.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/37.i2c_target_timeout.3647737185
Short name T1308
Test name
Test status
Simulation time 2246135196 ps
CPU time 7.03 seconds
Started Sep 18 08:13:49 AM UTC 24
Finished Sep 18 08:13:57 AM UTC 24
Peak memory 229728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3647737
185 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_timeout.3647737185
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/37.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/37.i2c_target_tx_stretch_ctrl.758643336
Short name T1315
Test name
Test status
Simulation time 167802517 ps
CPU time 2.48 seconds
Started Sep 18 08:14:02 AM UTC 24
Finished Sep 18 08:14:06 AM UTC 24
Peak memory 215320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7586433
36 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_tx_stretch_ctrl.758643336
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/37.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/38.i2c_alert_test.582033489
Short name T1353
Test name
Test status
Simulation time 22212194 ps
CPU time 1.01 seconds
Started Sep 18 08:14:54 AM UTC 24
Finished Sep 18 08:14:56 AM UTC 24
Peak memory 214608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=582033489 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_alert_test.582033489
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/38.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/38.i2c_host_error_intr.822118060
Short name T1329
Test name
Test status
Simulation time 613706312 ps
CPU time 8.5 seconds
Started Sep 18 08:14:16 AM UTC 24
Finished Sep 18 08:14:26 AM UTC 24
Peak memory 248756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=822118060 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 38.i2c_host_error_intr.822118060
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/38.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/38.i2c_host_fifo_fmt_empty.182552151
Short name T1281
Test name
Test status
Simulation time 767694399 ps
CPU time 10.01 seconds
Started Sep 18 08:14:10 AM UTC 24
Finished Sep 18 08:14:21 AM UTC 24
Peak memory 291616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=182552151 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_fmt_empty.182552151
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/38.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/38.i2c_host_fifo_full.1322172025
Short name T1368
Test name
Test status
Simulation time 10279601970 ps
CPU time 64.7 seconds
Started Sep 18 08:14:11 AM UTC 24
Finished Sep 18 08:15:17 AM UTC 24
Peak memory 433064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1322172025 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_full.1322172025
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/38.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/38.i2c_host_fifo_overflow.2133771292
Short name T1414
Test name
Test status
Simulation time 1598298833 ps
CPU time 104.22 seconds
Started Sep 18 08:14:09 AM UTC 24
Finished Sep 18 08:15:55 AM UTC 24
Peak memory 582368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2133771292 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_overflow.2133771292
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/38.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/38.i2c_host_fifo_reset_fmt.2733478803
Short name T1325
Test name
Test status
Simulation time 101099897 ps
CPU time 1.61 seconds
Started Sep 18 08:14:10 AM UTC 24
Finished Sep 18 08:14:12 AM UTC 24
Peak memory 214900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2733478803 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_fmt.2733478803
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/38.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/38.i2c_host_fifo_reset_rx.2851244764
Short name T1328
Test name
Test status
Simulation time 331004873 ps
CPU time 7.18 seconds
Started Sep 18 08:14:11 AM UTC 24
Finished Sep 18 08:14:19 AM UTC 24
Peak memory 246496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2851244764 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_rx.2851244764
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/38.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/38.i2c_host_fifo_watermark.3194529339
Short name T1407
Test name
Test status
Simulation time 3966513953 ps
CPU time 99.35 seconds
Started Sep 18 08:14:09 AM UTC 24
Finished Sep 18 08:15:50 AM UTC 24
Peak memory 1198944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3194529339 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_watermark.3194529339
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/38.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/38.i2c_host_may_nack.2570972955
Short name T1354
Test name
Test status
Simulation time 1672735178 ps
CPU time 11.64 seconds
Started Sep 18 08:14:44 AM UTC 24
Finished Sep 18 08:14:56 AM UTC 24
Peak memory 215248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2570972955 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.i2c_host_may_nack.2570972955
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/38.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/38.i2c_host_override.1930306280
Short name T1321
Test name
Test status
Simulation time 132000576 ps
CPU time 1.04 seconds
Started Sep 18 08:14:08 AM UTC 24
Finished Sep 18 08:14:10 AM UTC 24
Peak memory 214112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1930306280 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.i2c_host_override.1930306280
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/38.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/38.i2c_host_perf.4123222643
Short name T1333
Test name
Test status
Simulation time 3685205178 ps
CPU time 20.7 seconds
Started Sep 18 08:14:11 AM UTC 24
Finished Sep 18 08:14:33 AM UTC 24
Peak memory 225768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4123222643 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 38.i2c_host_perf.4123222643
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/38.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/38.i2c_host_perf_precise.1477402679
Short name T1326
Test name
Test status
Simulation time 361434211 ps
CPU time 1.64 seconds
Started Sep 18 08:14:13 AM UTC 24
Finished Sep 18 08:14:16 AM UTC 24
Peak memory 214744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1477402679 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_perf_precise.1477402679
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/38.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/38.i2c_host_smoke.1260919910
Short name T1374
Test name
Test status
Simulation time 1495032603 ps
CPU time 73.37 seconds
Started Sep 18 08:14:06 AM UTC 24
Finished Sep 18 08:15:22 AM UTC 24
Peak memory 369452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1260919910 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 38.i2c_host_smoke.1260919910
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/38.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/38.i2c_host_stretch_timeout.1924892147
Short name T1330
Test name
Test status
Simulation time 759212636 ps
CPU time 14.71 seconds
Started Sep 18 08:14:13 AM UTC 24
Finished Sep 18 08:14:29 AM UTC 24
Peak memory 227488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1924892147 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_stretch_timeout.1924892147
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/38.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/38.i2c_target_bad_addr.2400537116
Short name T1342
Test name
Test status
Simulation time 789253461 ps
CPU time 5.22 seconds
Started Sep 18 08:14:40 AM UTC 24
Finished Sep 18 08:14:46 AM UTC 24
Peak memory 229668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=2400537116 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_bad_ad
dr.2400537116
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/38.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/38.i2c_target_fifo_reset_acq.2821125433
Short name T1337
Test name
Test status
Simulation time 169484628 ps
CPU time 1.6 seconds
Started Sep 18 08:14:37 AM UTC 24
Finished Sep 18 08:14:40 AM UTC 24
Peak memory 214784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2821125
433 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_fifo_reset_acq.2821125433
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/38.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/38.i2c_target_fifo_reset_tx.1437969122
Short name T1335
Test name
Test status
Simulation time 166448174 ps
CPU time 1.14 seconds
Started Sep 18 08:14:37 AM UTC 24
Finished Sep 18 08:14:39 AM UTC 24
Peak memory 214904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1437969
122 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_fifo_reset_tx.1437969122
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/38.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/38.i2c_target_fifo_watermarks_acq.935401239
Short name T1344
Test name
Test status
Simulation time 896634076 ps
CPU time 4.72 seconds
Started Sep 18 08:14:44 AM UTC 24
Finished Sep 18 08:14:49 AM UTC 24
Peak memory 215252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9354012
39 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_fifo_watermark
s_acq.935401239
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/38.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/38.i2c_target_fifo_watermarks_tx.1579843710
Short name T1343
Test name
Test status
Simulation time 156975676 ps
CPU time 1.57 seconds
Started Sep 18 08:14:47 AM UTC 24
Finished Sep 18 08:14:49 AM UTC 24
Peak memory 215032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1579843
710 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_fifo_watermark
s_tx.1579843710
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/38.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/38.i2c_target_intr_smoke.2029132790
Short name T1336
Test name
Test status
Simulation time 20332326447 ps
CPU time 8.44 seconds
Started Sep 18 08:14:30 AM UTC 24
Finished Sep 18 08:14:39 AM UTC 24
Peak memory 232360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=202913
2790 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_intr_smoke.2029132790
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/38.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/38.i2c_target_intr_stress_wr.1058738892
Short name T1338
Test name
Test status
Simulation time 10580190775 ps
CPU time 7.06 seconds
Started Sep 18 08:14:33 AM UTC 24
Finished Sep 18 08:14:41 AM UTC 24
Peak memory 285664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1058738892 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_intr_stres
s_wr.1058738892
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/38.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/38.i2c_target_nack_acqfull.2706013880
Short name T1349
Test name
Test status
Simulation time 2057474781 ps
CPU time 3.82 seconds
Started Sep 18 08:14:50 AM UTC 24
Finished Sep 18 08:14:55 AM UTC 24
Peak memory 225292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2706013
880 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_nack_acqfull.2706013880
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/38.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/38.i2c_target_nack_acqfull_addr.436438277
Short name T1355
Test name
Test status
Simulation time 1901315835 ps
CPU time 4.7 seconds
Started Sep 18 08:14:51 AM UTC 24
Finished Sep 18 08:14:57 AM UTC 24
Peak memory 215260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4364382
77 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_nack_acqfull_addr.436438277
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/38.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/38.i2c_target_perf.1893339395
Short name T1345
Test name
Test status
Simulation time 3574824635 ps
CPU time 8.8 seconds
Started Sep 18 08:14:40 AM UTC 24
Finished Sep 18 08:14:50 AM UTC 24
Peak memory 229796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1893339
395 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_perf.1893339395
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/38.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/38.i2c_target_smbus_maxlen.2506070972
Short name T1350
Test name
Test status
Simulation time 587952440 ps
CPU time 4.46 seconds
Started Sep 18 08:14:50 AM UTC 24
Finished Sep 18 08:14:55 AM UTC 24
Peak memory 215068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2506070
972 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_smbus_maxlen.2506070972
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/38.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/38.i2c_target_smoke.1995195863
Short name T1339
Test name
Test status
Simulation time 2383750365 ps
CPU time 20.47 seconds
Started Sep 18 08:14:20 AM UTC 24
Finished Sep 18 08:14:42 AM UTC 24
Peak memory 225828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1995195863 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_smoke.1995195863
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/38.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/38.i2c_target_stress_all.1271179639
Short name T1537
Test name
Test status
Simulation time 31756502022 ps
CPU time 173.24 seconds
Started Sep 18 08:14:40 AM UTC 24
Finished Sep 18 08:17:36 AM UTC 24
Peak memory 1831904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=127117
9639 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_stress_all.1271179639
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/38.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/38.i2c_target_stress_rd.1654016621
Short name T1363
Test name
Test status
Simulation time 3367455755 ps
CPU time 43.51 seconds
Started Sep 18 08:14:25 AM UTC 24
Finished Sep 18 08:15:10 AM UTC 24
Peak memory 225812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1654016621 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_stress_rd.1654016621
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/38.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/38.i2c_target_stress_wr.2168739630
Short name T1742
Test name
Test status
Simulation time 50516197416 ps
CPU time 666.78 seconds
Started Sep 18 08:14:22 AM UTC 24
Finished Sep 18 08:25:36 AM UTC 24
Peak memory 7187488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2168739630 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_stress_wr.2168739630
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/38.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/38.i2c_target_stretch.2050156137
Short name T1332
Test name
Test status
Simulation time 2663115118 ps
CPU time 4.28 seconds
Started Sep 18 08:14:27 AM UTC 24
Finished Sep 18 08:14:32 AM UTC 24
Peak memory 232140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2050156137 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_stretch.2050156137
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/38.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/38.i2c_target_timeout.2744968336
Short name T1340
Test name
Test status
Simulation time 1430478790 ps
CPU time 8.5 seconds
Started Sep 18 08:14:33 AM UTC 24
Finished Sep 18 08:14:42 AM UTC 24
Peak memory 242460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2744968
336 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_timeout.2744968336
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/38.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/38.i2c_target_tx_stretch_ctrl.3927394313
Short name T1347
Test name
Test status
Simulation time 256884753 ps
CPU time 4.22 seconds
Started Sep 18 08:14:48 AM UTC 24
Finished Sep 18 08:14:53 AM UTC 24
Peak memory 215248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3927394
313 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_tx_stretch_ctrl.3927394313
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/38.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/39.i2c_alert_test.1659111437
Short name T1384
Test name
Test status
Simulation time 99669548 ps
CPU time 1.05 seconds
Started Sep 18 08:15:27 AM UTC 24
Finished Sep 18 08:15:29 AM UTC 24
Peak memory 214840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1659111437 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_alert_test.1659111437
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/39.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/39.i2c_host_error_intr.1801075617
Short name T1359
Test name
Test status
Simulation time 341221321 ps
CPU time 2.4 seconds
Started Sep 18 08:15:00 AM UTC 24
Finished Sep 18 08:15:03 AM UTC 24
Peak memory 225656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1801075617 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 39.i2c_host_error_intr.1801075617
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/39.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/39.i2c_host_fifo_fmt_empty.3804685996
Short name T1361
Test name
Test status
Simulation time 306169533 ps
CPU time 7.78 seconds
Started Sep 18 08:14:58 AM UTC 24
Finished Sep 18 08:15:06 AM UTC 24
Peak memory 277268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3804685996 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_fmt_empty.3804685996
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/39.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/39.i2c_host_fifo_full.3636390755
Short name T1424
Test name
Test status
Simulation time 2184444490 ps
CPU time 59.21 seconds
Started Sep 18 08:14:58 AM UTC 24
Finished Sep 18 08:15:58 AM UTC 24
Peak memory 488228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3636390755 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_full.3636390755
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/39.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/39.i2c_host_fifo_overflow.528733996
Short name T1466
Test name
Test status
Simulation time 10131688218 ps
CPU time 92.89 seconds
Started Sep 18 08:14:56 AM UTC 24
Finished Sep 18 08:16:31 AM UTC 24
Peak memory 834268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=528733996 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_overflow.528733996
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/39.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/39.i2c_host_fifo_reset_fmt.4155645240
Short name T1357
Test name
Test status
Simulation time 245753990 ps
CPU time 1.7 seconds
Started Sep 18 08:14:56 AM UTC 24
Finished Sep 18 08:14:59 AM UTC 24
Peak memory 214900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4155645240 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_fmt.4155645240
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/39.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/39.i2c_host_fifo_reset_rx.1866772055
Short name T1360
Test name
Test status
Simulation time 156862755 ps
CPU time 5.88 seconds
Started Sep 18 08:14:58 AM UTC 24
Finished Sep 18 08:15:04 AM UTC 24
Peak memory 242472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1866772055 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_rx.1866772055
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/39.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/39.i2c_host_fifo_watermark.2639582877
Short name T1462
Test name
Test status
Simulation time 13611404202 ps
CPU time 88.84 seconds
Started Sep 18 08:14:56 AM UTC 24
Finished Sep 18 08:16:27 AM UTC 24
Peak memory 981984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2639582877 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_watermark.2639582877
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/39.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/39.i2c_host_may_nack.2388974471
Short name T1387
Test name
Test status
Simulation time 421448663 ps
CPU time 7.02 seconds
Started Sep 18 08:15:21 AM UTC 24
Finished Sep 18 08:15:29 AM UTC 24
Peak memory 215304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2388974471 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.i2c_host_may_nack.2388974471
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/39.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/39.i2c_host_mode_toggle.2089327205
Short name T1378
Test name
Test status
Simulation time 901551274 ps
CPU time 3.3 seconds
Started Sep 18 08:15:21 AM UTC 24
Finished Sep 18 08:15:25 AM UTC 24
Peak memory 227492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2089327205 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_mode_toggle.2089327205
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/39.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/39.i2c_host_perf.915767871
Short name T1388
Test name
Test status
Simulation time 3008173375 ps
CPU time 30.48 seconds
Started Sep 18 08:14:58 AM UTC 24
Finished Sep 18 08:15:29 AM UTC 24
Peak memory 240492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=915767871 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 39.i2c_host_perf.915767871
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/39.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/39.i2c_host_perf_precise.837017807
Short name T1365
Test name
Test status
Simulation time 798157083 ps
CPU time 12.04 seconds
Started Sep 18 08:14:59 AM UTC 24
Finished Sep 18 08:15:12 AM UTC 24
Peak memory 232156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=837017807 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_perf_precise.837017807
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/39.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/39.i2c_host_smoke.3819535103
Short name T1379
Test name
Test status
Simulation time 1400576017 ps
CPU time 30.38 seconds
Started Sep 18 08:14:54 AM UTC 24
Finished Sep 18 08:15:26 AM UTC 24
Peak memory 379728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3819535103 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 39.i2c_host_smoke.3819535103
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/39.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/39.i2c_host_stretch_timeout.1730097154
Short name T1362
Test name
Test status
Simulation time 916376729 ps
CPU time 8.54 seconds
Started Sep 18 08:15:00 AM UTC 24
Finished Sep 18 08:15:09 AM UTC 24
Peak memory 225632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1730097154 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_stretch_timeout.1730097154
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/39.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/39.i2c_target_bad_addr.838643892
Short name T1381
Test name
Test status
Simulation time 790610225 ps
CPU time 8.13 seconds
Started Sep 18 08:15:18 AM UTC 24
Finished Sep 18 08:15:27 AM UTC 24
Peak memory 225628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=838643892 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_bad_addr.838643892
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/39.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/39.i2c_target_fifo_reset_acq.1012906637
Short name T1367
Test name
Test status
Simulation time 535060261 ps
CPU time 1.82 seconds
Started Sep 18 08:15:14 AM UTC 24
Finished Sep 18 08:15:16 AM UTC 24
Peak memory 214784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1012906
637 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_fifo_reset_acq.1012906637
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/39.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/39.i2c_target_fifo_reset_tx.891108504
Short name T1370
Test name
Test status
Simulation time 1376773431 ps
CPU time 1.68 seconds
Started Sep 18 08:15:16 AM UTC 24
Finished Sep 18 08:15:18 AM UTC 24
Peak memory 214844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8911085
04 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_fifo_reset_tx.891108504
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/39.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/39.i2c_target_fifo_watermarks_acq.2456604548
Short name T1380
Test name
Test status
Simulation time 6732728113 ps
CPU time 4.86 seconds
Started Sep 18 08:15:21 AM UTC 24
Finished Sep 18 08:15:27 AM UTC 24
Peak memory 215448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2456604
548 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_fifo_watermar
ks_acq.2456604548
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/39.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/39.i2c_target_fifo_watermarks_tx.1181723521
Short name T1377
Test name
Test status
Simulation time 149385887 ps
CPU time 2.13 seconds
Started Sep 18 08:15:22 AM UTC 24
Finished Sep 18 08:15:25 AM UTC 24
Peak memory 215044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1181723
521 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_fifo_watermark
s_tx.1181723521
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/39.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/39.i2c_target_intr_smoke.2834131110
Short name T1373
Test name
Test status
Simulation time 2438088658 ps
CPU time 10.43 seconds
Started Sep 18 08:15:10 AM UTC 24
Finished Sep 18 08:15:22 AM UTC 24
Peak memory 229712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=283413
1110 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_intr_smoke.2834131110
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/39.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/39.i2c_target_intr_stress_wr.4046176560
Short name T1395
Test name
Test status
Simulation time 14210466324 ps
CPU time 22.63 seconds
Started Sep 18 08:15:10 AM UTC 24
Finished Sep 18 08:15:34 AM UTC 24
Peak memory 516968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=4046176560 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_intr_stres
s_wr.4046176560
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/39.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/39.i2c_target_nack_acqfull.1196129595
Short name T1389
Test name
Test status
Simulation time 563163619 ps
CPU time 4.22 seconds
Started Sep 18 08:15:25 AM UTC 24
Finished Sep 18 08:15:30 AM UTC 24
Peak memory 225540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1196129
595 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_nack_acqfull.1196129595
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/39.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/39.i2c_target_nack_acqfull_addr.512841856
Short name T1393
Test name
Test status
Simulation time 571230832 ps
CPU time 4.68 seconds
Started Sep 18 08:15:27 AM UTC 24
Finished Sep 18 08:15:32 AM UTC 24
Peak memory 215260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5128418
56 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_nack_acqfull_addr.512841856
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/39.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/39.i2c_target_nack_txstretch.3662025396
Short name T1391
Test name
Test status
Simulation time 393601682 ps
CPU time 2.7 seconds
Started Sep 18 08:15:27 AM UTC 24
Finished Sep 18 08:15:30 AM UTC 24
Peak memory 232148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3662025
396 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_nack_txstretch.3662025396
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/39.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/39.i2c_target_perf.248500995
Short name T1376
Test name
Test status
Simulation time 505684858 ps
CPU time 5.74 seconds
Started Sep 18 08:15:17 AM UTC 24
Finished Sep 18 08:15:24 AM UTC 24
Peak memory 225564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2485009
95 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_perf.248500995
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/39.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/39.i2c_target_smbus_maxlen.1193552883
Short name T1386
Test name
Test status
Simulation time 427398718 ps
CPU time 3.43 seconds
Started Sep 18 08:15:24 AM UTC 24
Finished Sep 18 08:15:29 AM UTC 24
Peak memory 214940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1193552
883 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_smbus_maxlen.1193552883
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/39.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/39.i2c_target_smoke.820902556
Short name T1425
Test name
Test status
Simulation time 2350771933 ps
CPU time 53.45 seconds
Started Sep 18 08:15:04 AM UTC 24
Finished Sep 18 08:15:59 AM UTC 24
Peak memory 225632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=820902556 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_smoke.820902556
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/39.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/39.i2c_target_stress_all.4132240683
Short name T1446
Test name
Test status
Simulation time 38142688982 ps
CPU time 57.79 seconds
Started Sep 18 08:15:18 AM UTC 24
Finished Sep 18 08:16:17 AM UTC 24
Peak memory 564056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=413224
0683 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_stress_all.4132240683
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/39.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/39.i2c_target_stress_rd.782689149
Short name T1375
Test name
Test status
Simulation time 598216715 ps
CPU time 15.05 seconds
Started Sep 18 08:15:07 AM UTC 24
Finished Sep 18 08:15:23 AM UTC 24
Peak memory 217372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=782689149 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_stress_rd.782689149
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/39.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/39.i2c_target_stress_wr.1739565816
Short name T1366
Test name
Test status
Simulation time 21182571713 ps
CPU time 7.05 seconds
Started Sep 18 08:15:05 AM UTC 24
Finished Sep 18 08:15:13 AM UTC 24
Peak memory 215444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1739565816 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_stress_wr.1739565816
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/39.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/39.i2c_target_stretch.455085722
Short name T1397
Test name
Test status
Simulation time 3652880570 ps
CPU time 25.75 seconds
Started Sep 18 08:15:09 AM UTC 24
Finished Sep 18 08:15:36 AM UTC 24
Peak memory 328732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=455085722 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_stretch.455085722
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/39.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/39.i2c_target_timeout.3054103736
Short name T1371
Test name
Test status
Simulation time 4249884110 ps
CPU time 6.47 seconds
Started Sep 18 08:15:13 AM UTC 24
Finished Sep 18 08:15:20 AM UTC 24
Peak memory 225760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3054103
736 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_timeout.3054103736
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/39.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/39.i2c_target_tx_stretch_ctrl.3291436237
Short name T1383
Test name
Test status
Simulation time 110094267 ps
CPU time 4.29 seconds
Started Sep 18 08:15:22 AM UTC 24
Finished Sep 18 08:15:28 AM UTC 24
Peak memory 215328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3291436
237 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_tx_stretch_ctrl.3291436237
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/39.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/4.i2c_alert_test.2206530827
Short name T132
Test name
Test status
Simulation time 26502632 ps
CPU time 0.94 seconds
Started Sep 18 07:55:55 AM UTC 24
Finished Sep 18 07:55:57 AM UTC 24
Peak memory 214840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2206530827 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_alert_test.2206530827
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/4.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/4.i2c_host_error_intr.1701614401
Short name T19
Test name
Test status
Simulation time 161283600 ps
CPU time 1.81 seconds
Started Sep 18 07:55:37 AM UTC 24
Finished Sep 18 07:55:40 AM UTC 24
Peak memory 214704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1701614401 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 4.i2c_host_error_intr.1701614401
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/4.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/4.i2c_host_fifo_fmt_empty.3522040531
Short name T334
Test name
Test status
Simulation time 801531533 ps
CPU time 9.91 seconds
Started Sep 18 07:55:36 AM UTC 24
Finished Sep 18 07:55:47 AM UTC 24
Peak memory 268944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3522040531 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_fmt_empty.3522040531
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/4.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/4.i2c_host_fifo_full.2627133646
Short name T39
Test name
Test status
Simulation time 9292057814 ps
CPU time 78.98 seconds
Started Sep 18 07:55:36 AM UTC 24
Finished Sep 18 07:56:57 AM UTC 24
Peak memory 713568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2627133646 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_full.2627133646
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/4.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/4.i2c_host_fifo_overflow.612819210
Short name T106
Test name
Test status
Simulation time 8647737493 ps
CPU time 53.7 seconds
Started Sep 18 07:55:36 AM UTC 24
Finished Sep 18 07:56:31 AM UTC 24
Peak memory 539552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=612819210 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_overflow.612819210
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/4.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/4.i2c_host_fifo_reset_fmt.2346327159
Short name T329
Test name
Test status
Simulation time 181201642 ps
CPU time 1.33 seconds
Started Sep 18 07:55:36 AM UTC 24
Finished Sep 18 07:55:38 AM UTC 24
Peak memory 214820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2346327159 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_fmt.2346327159
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/4.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/4.i2c_host_fifo_reset_rx.1273742346
Short name T192
Test name
Test status
Simulation time 175409847 ps
CPU time 8.2 seconds
Started Sep 18 07:55:36 AM UTC 24
Finished Sep 18 07:55:45 AM UTC 24
Peak memory 244384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1273742346 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_rx.1273742346
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/4.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/4.i2c_host_fifo_watermark.4281811457
Short name T465
Test name
Test status
Simulation time 4069516738 ps
CPU time 165.25 seconds
Started Sep 18 07:55:35 AM UTC 24
Finished Sep 18 07:58:23 AM UTC 24
Peak memory 971532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4281811457 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_watermark.4281811457
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/4.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/4.i2c_host_override.2576737256
Short name T326
Test name
Test status
Simulation time 29553235 ps
CPU time 1.08 seconds
Started Sep 18 07:55:34 AM UTC 24
Finished Sep 18 07:55:36 AM UTC 24
Peak memory 214108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2576737256 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.i2c_host_override.2576737256
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/4.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/4.i2c_host_perf.3065002620
Short name T572
Test name
Test status
Simulation time 27559236360 ps
CPU time 264.5 seconds
Started Sep 18 07:55:37 AM UTC 24
Finished Sep 18 08:00:06 AM UTC 24
Peak memory 316180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3065002620 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 4.i2c_host_perf.3065002620
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/4.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/4.i2c_host_perf_precise.110793251
Short name T332
Test name
Test status
Simulation time 63233375 ps
CPU time 3.7 seconds
Started Sep 18 07:55:37 AM UTC 24
Finished Sep 18 07:55:42 AM UTC 24
Peak memory 215188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=110793251 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_perf_precise.110793251
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/4.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/4.i2c_host_smoke.208516441
Short name T345
Test name
Test status
Simulation time 1778945393 ps
CPU time 35.58 seconds
Started Sep 18 07:55:34 AM UTC 24
Finished Sep 18 07:56:11 AM UTC 24
Peak memory 396144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=208516441 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 4.i2c_host_smoke.208516441
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/4.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/4.i2c_host_stress_all.4111698323
Short name T274
Test name
Test status
Simulation time 13687146868 ps
CPU time 1037.96 seconds
Started Sep 18 07:55:38 AM UTC 24
Finished Sep 18 08:13:07 AM UTC 24
Peak memory 2063148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4111698323 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 4.i2c_host_stress_all.4111698323
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/4.i2c_host_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/4.i2c_host_stretch_timeout.2908712506
Short name T180
Test name
Test status
Simulation time 685699549 ps
CPU time 12.83 seconds
Started Sep 18 07:55:37 AM UTC 24
Finished Sep 18 07:55:51 AM UTC 24
Peak memory 227492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2908712506 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_stretch_timeout.2908712506
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/4.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/4.i2c_sec_cm.2418722888
Short name T133
Test name
Test status
Simulation time 78196556 ps
CPU time 1.28 seconds
Started Sep 18 07:55:55 AM UTC 24
Finished Sep 18 07:55:57 AM UTC 24
Peak memory 244508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2418722888 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_sec_cm.2418722888
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/4.i2c_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/4.i2c_target_bad_addr.3561162315
Short name T128
Test name
Test status
Simulation time 3445401542 ps
CPU time 5.32 seconds
Started Sep 18 07:55:48 AM UTC 24
Finished Sep 18 07:55:54 AM UTC 24
Peak memory 225820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=3561162315 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_bad_addr.3561162315
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/4.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/4.i2c_target_fifo_reset_acq.2239852762
Short name T337
Test name
Test status
Simulation time 162444713 ps
CPU time 1.9 seconds
Started Sep 18 07:55:46 AM UTC 24
Finished Sep 18 07:55:49 AM UTC 24
Peak memory 214784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2239852
762 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_fifo_reset_acq.2239852762
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/4.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/4.i2c_target_fifo_reset_tx.1841662660
Short name T335
Test name
Test status
Simulation time 238272571 ps
CPU time 1.33 seconds
Started Sep 18 07:55:46 AM UTC 24
Finished Sep 18 07:55:48 AM UTC 24
Peak memory 214096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1841662
660 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_fifo_reset_tx.1841662660
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/4.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/4.i2c_target_fifo_watermarks_acq.3589008828
Short name T131
Test name
Test status
Simulation time 517607434 ps
CPU time 3.75 seconds
Started Sep 18 07:55:52 AM UTC 24
Finished Sep 18 07:55:56 AM UTC 24
Peak memory 215396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3589008
828 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_fifo_watermark
s_acq.3589008828
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/4.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/4.i2c_target_fifo_watermarks_tx.3206074032
Short name T127
Test name
Test status
Simulation time 484330757 ps
CPU time 1.86 seconds
Started Sep 18 07:55:52 AM UTC 24
Finished Sep 18 07:55:54 AM UTC 24
Peak memory 214856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3206074
032 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_fifo_watermarks
_tx.3206074032
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/4.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/4.i2c_target_hrst.126352966
Short name T125
Test name
Test status
Simulation time 883406857 ps
CPU time 2.71 seconds
Started Sep 18 07:55:49 AM UTC 24
Finished Sep 18 07:55:53 AM UTC 24
Peak memory 227808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1263529
66 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_hrst.126352966
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/4.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/4.i2c_target_intr_smoke.3174364220
Short name T129
Test name
Test status
Simulation time 1194341294 ps
CPU time 11.01 seconds
Started Sep 18 07:55:43 AM UTC 24
Finished Sep 18 07:55:55 AM UTC 24
Peak memory 229644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=317436
4220 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_intr_smoke.3174364220
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/4.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/4.i2c_target_intr_stress_wr.4081793903
Short name T54
Test name
Test status
Simulation time 17161648014 ps
CPU time 28.45 seconds
Started Sep 18 07:55:43 AM UTC 24
Finished Sep 18 07:56:12 AM UTC 24
Peak memory 709312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=4081793903 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_intr_stress
_wr.4081793903
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/4.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/4.i2c_target_nack_acqfull.2406335781
Short name T344
Test name
Test status
Simulation time 515118283 ps
CPU time 4.39 seconds
Started Sep 18 07:55:53 AM UTC 24
Finished Sep 18 07:55:58 AM UTC 24
Peak memory 225764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2406335
781 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_nack_acqfull.2406335781
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/4.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/4.i2c_target_nack_acqfull_addr.727851446
Short name T342
Test name
Test status
Simulation time 503994265 ps
CPU time 2.98 seconds
Started Sep 18 07:55:54 AM UTC 24
Finished Sep 18 07:55:58 AM UTC 24
Peak memory 215256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7278514
46 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_nack_acqfull_addr.727851446
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/4.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/4.i2c_target_perf.1499869983
Short name T130
Test name
Test status
Simulation time 6321763555 ps
CPU time 7.77 seconds
Started Sep 18 07:55:47 AM UTC 24
Finished Sep 18 07:55:56 AM UTC 24
Peak memory 232400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1499869
983 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_perf.1499869983
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/4.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/4.i2c_target_smbus_maxlen.1336359180
Short name T340
Test name
Test status
Simulation time 949701881 ps
CPU time 3.77 seconds
Started Sep 18 07:55:53 AM UTC 24
Finished Sep 18 07:55:57 AM UTC 24
Peak memory 215004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1336359
180 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_smbus_maxlen.1336359180
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/4.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/4.i2c_target_smoke.2767496275
Short name T339
Test name
Test status
Simulation time 6057369099 ps
CPU time 17.92 seconds
Started Sep 18 07:55:38 AM UTC 24
Finished Sep 18 07:55:57 AM UTC 24
Peak memory 229716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2767496275 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_smoke.2767496275
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/4.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/4.i2c_target_stress_all.2168255328
Short name T662
Test name
Test status
Simulation time 69257861693 ps
CPU time 353.81 seconds
Started Sep 18 07:55:47 AM UTC 24
Finished Sep 18 08:01:45 AM UTC 24
Peak memory 4004640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=216825
5328 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_stress_all.2168255328
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/4.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/4.i2c_target_stress_rd.2320381864
Short name T173
Test name
Test status
Simulation time 3195865913 ps
CPU time 25.88 seconds
Started Sep 18 07:55:40 AM UTC 24
Finished Sep 18 07:56:07 AM UTC 24
Peak memory 234316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2320381864 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_stress_rd.2320381864
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/4.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/4.i2c_target_stress_wr.1114592085
Short name T55
Test name
Test status
Simulation time 33503417117 ps
CPU time 87.85 seconds
Started Sep 18 07:55:39 AM UTC 24
Finished Sep 18 07:57:09 AM UTC 24
Peak memory 1823708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1114592085 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_stress_wr.1114592085
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/4.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/4.i2c_target_stretch.3909063005
Short name T96
Test name
Test status
Simulation time 3464293997 ps
CPU time 70.38 seconds
Started Sep 18 07:55:40 AM UTC 24
Finished Sep 18 07:56:53 AM UTC 24
Peak memory 943056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3909063005 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_stretch.3909063005
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/4.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/4.i2c_target_timeout.4014241695
Short name T126
Test name
Test status
Simulation time 1804501513 ps
CPU time 9.19 seconds
Started Sep 18 07:55:44 AM UTC 24
Finished Sep 18 07:55:54 AM UTC 24
Peak memory 225760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4014241
695 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_timeout.4014241695
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/4.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/4.i2c_target_tx_stretch_ctrl.3985279591
Short name T349
Test name
Test status
Simulation time 366555203 ps
CPU time 9.89 seconds
Started Sep 18 07:55:53 AM UTC 24
Finished Sep 18 07:56:04 AM UTC 24
Peak memory 215244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3985279
591 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_tx_stretch_ctrl.3985279591
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/4.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/40.i2c_alert_test.446490947
Short name T1420
Test name
Test status
Simulation time 37838700 ps
CPU time 0.96 seconds
Started Sep 18 08:15:55 AM UTC 24
Finished Sep 18 08:15:57 AM UTC 24
Peak memory 214260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=446490947 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_alert_test.446490947
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/40.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/40.i2c_host_error_intr.3656969206
Short name T1398
Test name
Test status
Simulation time 401809932 ps
CPU time 3.08 seconds
Started Sep 18 08:15:31 AM UTC 24
Finished Sep 18 08:15:37 AM UTC 24
Peak memory 225776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3656969206 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 40.i2c_host_error_intr.3656969206
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/40.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/40.i2c_host_fifo_fmt_empty.824493112
Short name T1417
Test name
Test status
Simulation time 462757338 ps
CPU time 24.44 seconds
Started Sep 18 08:15:30 AM UTC 24
Finished Sep 18 08:15:57 AM UTC 24
Peak memory 316048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=824493112 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_fmt_empty.824493112
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/40.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/40.i2c_host_fifo_full.4189081287
Short name T1533
Test name
Test status
Simulation time 4875381886 ps
CPU time 121.31 seconds
Started Sep 18 08:15:30 AM UTC 24
Finished Sep 18 08:17:35 AM UTC 24
Peak memory 367340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4189081287 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_full.4189081287
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/40.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/40.i2c_host_fifo_overflow.1190797226
Short name T1567
Test name
Test status
Simulation time 2680992706 ps
CPU time 151.51 seconds
Started Sep 18 08:15:29 AM UTC 24
Finished Sep 18 08:18:04 AM UTC 24
Peak memory 789540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1190797226 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_overflow.1190797226
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/40.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/40.i2c_host_fifo_reset_fmt.877871372
Short name T1394
Test name
Test status
Simulation time 152996292 ps
CPU time 1.32 seconds
Started Sep 18 08:15:30 AM UTC 24
Finished Sep 18 08:15:33 AM UTC 24
Peak memory 214904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=877871372 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_fmt.877871372
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/40.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/40.i2c_host_fifo_reset_rx.2439246960
Short name T1396
Test name
Test status
Simulation time 261747092 ps
CPU time 4.01 seconds
Started Sep 18 08:15:30 AM UTC 24
Finished Sep 18 08:15:36 AM UTC 24
Peak memory 236324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2439246960 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_rx.2439246960
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/40.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/40.i2c_host_fifo_watermark.722035997
Short name T1489
Test name
Test status
Simulation time 20824636038 ps
CPU time 76.29 seconds
Started Sep 18 08:15:29 AM UTC 24
Finished Sep 18 08:16:48 AM UTC 24
Peak memory 907976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=722035997 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_watermark.722035997
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/40.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/40.i2c_host_may_nack.1048350174
Short name T1418
Test name
Test status
Simulation time 1188185708 ps
CPU time 5.92 seconds
Started Sep 18 08:15:50 AM UTC 24
Finished Sep 18 08:15:57 AM UTC 24
Peak memory 215248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1048350174 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.i2c_host_may_nack.1048350174
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/40.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/40.i2c_host_override.1163000872
Short name T1390
Test name
Test status
Simulation time 50154510 ps
CPU time 1.03 seconds
Started Sep 18 08:15:28 AM UTC 24
Finished Sep 18 08:15:30 AM UTC 24
Peak memory 214108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1163000872 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.i2c_host_override.1163000872
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/40.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/40.i2c_host_perf.1971857887
Short name T1408
Test name
Test status
Simulation time 1198614723 ps
CPU time 18.08 seconds
Started Sep 18 08:15:30 AM UTC 24
Finished Sep 18 08:15:51 AM UTC 24
Peak memory 349096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1971857887 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 40.i2c_host_perf.1971857887
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/40.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/40.i2c_host_perf_precise.1497042148
Short name T1400
Test name
Test status
Simulation time 3039213256 ps
CPU time 12.02 seconds
Started Sep 18 08:15:30 AM UTC 24
Finished Sep 18 08:15:44 AM UTC 24
Peak memory 299556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1497042148 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_perf_precise.1497042148
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/40.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/40.i2c_host_smoke.3012739873
Short name T1436
Test name
Test status
Simulation time 18128201839 ps
CPU time 39.63 seconds
Started Sep 18 08:15:28 AM UTC 24
Finished Sep 18 08:16:09 AM UTC 24
Peak memory 344808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3012739873 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 40.i2c_host_smoke.3012739873
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/40.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/40.i2c_host_stretch_timeout.278306566
Short name T1444
Test name
Test status
Simulation time 4024883585 ps
CPU time 43.84 seconds
Started Sep 18 08:15:30 AM UTC 24
Finished Sep 18 08:16:16 AM UTC 24
Peak memory 225640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=278306566 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_stretch_timeout.278306566
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/40.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/40.i2c_target_bad_addr.3996493566
Short name T1413
Test name
Test status
Simulation time 3748053650 ps
CPU time 5.97 seconds
Started Sep 18 08:15:48 AM UTC 24
Finished Sep 18 08:15:55 AM UTC 24
Peak memory 217444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=3996493566 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_bad_ad
dr.3996493566
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/40.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/40.i2c_target_fifo_reset_acq.3929388962
Short name T1404
Test name
Test status
Simulation time 835229296 ps
CPU time 2.49 seconds
Started Sep 18 08:15:44 AM UTC 24
Finished Sep 18 08:15:48 AM UTC 24
Peak memory 215328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3929388
962 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_fifo_reset_acq.3929388962
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/40.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/40.i2c_target_fifo_reset_tx.959925640
Short name T296
Test name
Test status
Simulation time 387937900 ps
CPU time 2.49 seconds
Started Sep 18 08:15:45 AM UTC 24
Finished Sep 18 08:15:49 AM UTC 24
Peak memory 225764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9599256
40 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_fifo_reset_tx.959925640
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/40.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/40.i2c_target_fifo_watermarks_acq.3839544491
Short name T1415
Test name
Test status
Simulation time 483392615 ps
CPU time 3.17 seconds
Started Sep 18 08:15:51 AM UTC 24
Finished Sep 18 08:15:55 AM UTC 24
Peak memory 215044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3839544
491 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_fifo_watermar
ks_acq.3839544491
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/40.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/40.i2c_target_fifo_watermarks_tx.59500173
Short name T1411
Test name
Test status
Simulation time 2083077729 ps
CPU time 1.76 seconds
Started Sep 18 08:15:51 AM UTC 24
Finished Sep 18 08:15:54 AM UTC 24
Peak memory 214720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5950017
3 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_fifo_watermarks_tx.59500173
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/40.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/40.i2c_target_intr_smoke.90455393
Short name T1403
Test name
Test status
Simulation time 3018470428 ps
CPU time 8.01 seconds
Started Sep 18 08:15:37 AM UTC 24
Finished Sep 18 08:15:46 AM UTC 24
Peak memory 246660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=904553
93 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_intr_smoke.90455393
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/40.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/40.i2c_target_intr_stress_wr.3789110804
Short name T1430
Test name
Test status
Simulation time 7277176770 ps
CPU time 23.84 seconds
Started Sep 18 08:15:37 AM UTC 24
Finished Sep 18 08:16:02 AM UTC 24
Peak memory 215440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3789110804 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_intr_stres
s_wr.3789110804
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/40.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/40.i2c_target_nack_acqfull.2190461552
Short name T1427
Test name
Test status
Simulation time 2559836255 ps
CPU time 4.27 seconds
Started Sep 18 08:15:54 AM UTC 24
Finished Sep 18 08:15:59 AM UTC 24
Peak memory 225632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2190461
552 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_nack_acqfull.2190461552
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/40.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/40.i2c_target_nack_acqfull_addr.2532463172
Short name T1428
Test name
Test status
Simulation time 1935161169 ps
CPU time 3.87 seconds
Started Sep 18 08:15:55 AM UTC 24
Finished Sep 18 08:16:00 AM UTC 24
Peak memory 215336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2532463
172 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_nack_acqfull_ad
dr.2532463172
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/40.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/40.i2c_target_nack_txstretch.599228033
Short name T1422
Test name
Test status
Simulation time 299884194 ps
CPU time 1.88 seconds
Started Sep 18 08:15:55 AM UTC 24
Finished Sep 18 08:15:58 AM UTC 24
Peak memory 231684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5992280
33 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_nack_txstretch.599228033
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/40.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/40.i2c_target_perf.3741539722
Short name T1409
Test name
Test status
Simulation time 3050366435 ps
CPU time 7.13 seconds
Started Sep 18 08:15:45 AM UTC 24
Finished Sep 18 08:15:53 AM UTC 24
Peak memory 231832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3741539
722 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_perf.3741539722
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/40.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/40.i2c_target_smbus_maxlen.1122617617
Short name T1419
Test name
Test status
Simulation time 564418324 ps
CPU time 4.03 seconds
Started Sep 18 08:15:52 AM UTC 24
Finished Sep 18 08:15:57 AM UTC 24
Peak memory 215068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1122617
617 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_smbus_maxlen.1122617617
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/40.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/40.i2c_target_smoke.1930986100
Short name T1351
Test name
Test status
Simulation time 2677541875 ps
CPU time 12.41 seconds
Started Sep 18 08:15:34 AM UTC 24
Finished Sep 18 08:15:48 AM UTC 24
Peak memory 225676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1930986100 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_smoke.1930986100
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/40.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/40.i2c_target_stress_all.1709250262
Short name T1680
Test name
Test status
Simulation time 46277188393 ps
CPU time 262.65 seconds
Started Sep 18 08:15:46 AM UTC 24
Finished Sep 18 08:20:13 AM UTC 24
Peak memory 2368324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=170925
0262 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_stress_all.1709250262
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/40.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/40.i2c_target_stress_rd.2590976736
Short name T1401
Test name
Test status
Simulation time 1470892387 ps
CPU time 8.82 seconds
Started Sep 18 08:15:35 AM UTC 24
Finished Sep 18 08:15:45 AM UTC 24
Peak memory 229644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2590976736 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_stress_rd.2590976736
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/40.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/40.i2c_target_stress_wr.3649110565
Short name T1405
Test name
Test status
Simulation time 23008422131 ps
CPU time 14.42 seconds
Started Sep 18 08:15:34 AM UTC 24
Finished Sep 18 08:15:50 AM UTC 24
Peak memory 287680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3649110565 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_stress_wr.3649110565
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/40.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/40.i2c_target_stretch.650152391
Short name T1416
Test name
Test status
Simulation time 4146340937 ps
CPU time 18.78 seconds
Started Sep 18 08:15:36 AM UTC 24
Finished Sep 18 08:15:56 AM UTC 24
Peak memory 275296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=650152391 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_stretch.650152391
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/40.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/40.i2c_target_timeout.39391579
Short name T1406
Test name
Test status
Simulation time 7158529802 ps
CPU time 11.68 seconds
Started Sep 18 08:15:37 AM UTC 24
Finished Sep 18 08:15:50 AM UTC 24
Peak memory 225764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3939157
9 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_timeout.39391579
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/40.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/40.i2c_target_tx_stretch_ctrl.4195175726
Short name T1426
Test name
Test status
Simulation time 391530437 ps
CPU time 6.84 seconds
Started Sep 18 08:15:51 AM UTC 24
Finished Sep 18 08:15:59 AM UTC 24
Peak memory 215312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4195175
726 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_tx_stretch_ctrl.4195175726
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/40.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/41.i2c_alert_test.2387595826
Short name T1450
Test name
Test status
Simulation time 28935678 ps
CPU time 0.93 seconds
Started Sep 18 08:16:19 AM UTC 24
Finished Sep 18 08:16:21 AM UTC 24
Peak memory 214840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2387595826 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_alert_test.2387595826
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/41.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/41.i2c_host_error_intr.2753219291
Short name T1433
Test name
Test status
Simulation time 361901022 ps
CPU time 4.98 seconds
Started Sep 18 08:15:59 AM UTC 24
Finished Sep 18 08:16:05 AM UTC 24
Peak memory 225644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2753219291 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 41.i2c_host_error_intr.2753219291
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/41.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/41.i2c_host_fifo_fmt_empty.3879442397
Short name T1431
Test name
Test status
Simulation time 254625992 ps
CPU time 5.49 seconds
Started Sep 18 08:15:58 AM UTC 24
Finished Sep 18 08:16:04 AM UTC 24
Peak memory 264544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3879442397 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_fmt_empty.3879442397
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/41.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/41.i2c_host_fifo_full.2560199612
Short name T1499
Test name
Test status
Simulation time 2541249171 ps
CPU time 58.42 seconds
Started Sep 18 08:15:58 AM UTC 24
Finished Sep 18 08:16:58 AM UTC 24
Peak memory 347056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2560199612 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_full.2560199612
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/41.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/41.i2c_host_fifo_overflow.1847572578
Short name T1485
Test name
Test status
Simulation time 37736739007 ps
CPU time 111.54 seconds
Started Sep 18 08:15:57 AM UTC 24
Finished Sep 18 08:17:50 AM UTC 24
Peak memory 660264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1847572578 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_overflow.1847572578
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/41.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/41.i2c_host_fifo_reset_fmt.859435112
Short name T1429
Test name
Test status
Simulation time 567408127 ps
CPU time 1.64 seconds
Started Sep 18 08:15:58 AM UTC 24
Finished Sep 18 08:16:00 AM UTC 24
Peak memory 214904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=859435112 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_fmt.859435112
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/41.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/41.i2c_host_fifo_reset_rx.2325402569
Short name T1432
Test name
Test status
Simulation time 200125643 ps
CPU time 5.6 seconds
Started Sep 18 08:15:58 AM UTC 24
Finished Sep 18 08:16:04 AM UTC 24
Peak memory 238312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2325402569 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_rx.2325402569
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/41.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/41.i2c_host_fifo_watermark.1601118696
Short name T1526
Test name
Test status
Simulation time 32276324770 ps
CPU time 84.12 seconds
Started Sep 18 08:15:56 AM UTC 24
Finished Sep 18 08:17:23 AM UTC 24
Peak memory 1039132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1601118696 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_watermark.1601118696
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/41.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/41.i2c_host_may_nack.3038943072
Short name T1453
Test name
Test status
Simulation time 5373086642 ps
CPU time 7.58 seconds
Started Sep 18 08:16:13 AM UTC 24
Finished Sep 18 08:16:22 AM UTC 24
Peak memory 215332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3038943072 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.i2c_host_may_nack.3038943072
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/41.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/41.i2c_host_mode_toggle.2841833460
Short name T1442
Test name
Test status
Simulation time 119237210 ps
CPU time 2.09 seconds
Started Sep 18 08:16:13 AM UTC 24
Finished Sep 18 08:16:16 AM UTC 24
Peak memory 215248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2841833460 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_mode_toggle.2841833460
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/41.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/41.i2c_host_override.3809188112
Short name T1423
Test name
Test status
Simulation time 102721853 ps
CPU time 0.99 seconds
Started Sep 18 08:15:56 AM UTC 24
Finished Sep 18 08:15:58 AM UTC 24
Peak memory 214112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3809188112 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.i2c_host_override.3809188112
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/41.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/41.i2c_host_perf.40710898
Short name T1471
Test name
Test status
Simulation time 7906048157 ps
CPU time 34.86 seconds
Started Sep 18 08:15:59 AM UTC 24
Finished Sep 18 08:16:35 AM UTC 24
Peak memory 543528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=40710898 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ho
st_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 41.i2c_host_perf.40710898
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/41.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/41.i2c_host_perf_precise.427226615
Short name T1456
Test name
Test status
Simulation time 6043633629 ps
CPU time 21.9 seconds
Started Sep 18 08:15:59 AM UTC 24
Finished Sep 18 08:16:22 AM UTC 24
Peak memory 215260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=427226615 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_perf_precise.427226615
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/41.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/41.i2c_host_smoke.2123020525
Short name T1534
Test name
Test status
Simulation time 2044745942 ps
CPU time 97.32 seconds
Started Sep 18 08:15:55 AM UTC 24
Finished Sep 18 08:17:35 AM UTC 24
Peak memory 467876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2123020525 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.i2c_host_smoke.2123020525
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/41.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/41.i2c_host_stretch_timeout.4045305864
Short name T1438
Test name
Test status
Simulation time 568140243 ps
CPU time 12.32 seconds
Started Sep 18 08:15:59 AM UTC 24
Finished Sep 18 08:16:12 AM UTC 24
Peak memory 232192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4045305864 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_stretch_timeout.4045305864
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/41.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/41.i2c_target_bad_addr.442303071
Short name T1447
Test name
Test status
Simulation time 2270586859 ps
CPU time 7.34 seconds
Started Sep 18 08:16:10 AM UTC 24
Finished Sep 18 08:16:18 AM UTC 24
Peak memory 217368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=442303071 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_bad_addr.442303071
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/41.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/41.i2c_target_fifo_reset_acq.1914369800
Short name T1435
Test name
Test status
Simulation time 285139674 ps
CPU time 1.88 seconds
Started Sep 18 08:16:06 AM UTC 24
Finished Sep 18 08:16:09 AM UTC 24
Peak memory 214532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1914369
800 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_fifo_reset_acq.1914369800
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/41.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/41.i2c_target_fifo_reset_tx.2261546927
Short name T1437
Test name
Test status
Simulation time 162407872 ps
CPU time 1.67 seconds
Started Sep 18 08:16:09 AM UTC 24
Finished Sep 18 08:16:11 AM UTC 24
Peak memory 214864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2261546
927 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_fifo_reset_tx.2261546927
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/41.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/41.i2c_target_fifo_watermarks_acq.4068382989
Short name T1454
Test name
Test status
Simulation time 888188147 ps
CPU time 4.49 seconds
Started Sep 18 08:16:16 AM UTC 24
Finished Sep 18 08:16:22 AM UTC 24
Peak memory 215392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4068382
989 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_fifo_watermar
ks_acq.4068382989
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/41.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/41.i2c_target_fifo_watermarks_tx.4249169741
Short name T1449
Test name
Test status
Simulation time 449479202 ps
CPU time 1.95 seconds
Started Sep 18 08:16:16 AM UTC 24
Finished Sep 18 08:16:19 AM UTC 24
Peak memory 214852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4249169
741 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_fifo_watermark
s_tx.4249169741
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/41.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/41.i2c_target_hrst.4060996050
Short name T1439
Test name
Test status
Simulation time 257747695 ps
CPU time 2.06 seconds
Started Sep 18 08:16:12 AM UTC 24
Finished Sep 18 08:16:15 AM UTC 24
Peak memory 215328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4060996
050 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_hrst.4060996050
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/41.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/41.i2c_target_intr_smoke.2361788134
Short name T1440
Test name
Test status
Simulation time 1336196132 ps
CPU time 12.16 seconds
Started Sep 18 08:16:02 AM UTC 24
Finished Sep 18 08:16:16 AM UTC 24
Peak memory 232348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=236178
8134 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_intr_smoke.2361788134
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/41.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/41.i2c_target_intr_stress_wr.1924569179
Short name T1443
Test name
Test status
Simulation time 7533338598 ps
CPU time 11.64 seconds
Started Sep 18 08:16:04 AM UTC 24
Finished Sep 18 08:16:16 AM UTC 24
Peak memory 215568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1924569179 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_intr_stres
s_wr.1924569179
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/41.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/41.i2c_target_nack_acqfull.1244079196
Short name T1452
Test name
Test status
Simulation time 2069551833 ps
CPU time 3.16 seconds
Started Sep 18 08:16:18 AM UTC 24
Finished Sep 18 08:16:22 AM UTC 24
Peak memory 225492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1244079
196 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_nack_acqfull.1244079196
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/41.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/41.i2c_target_nack_acqfull_addr.3323175975
Short name T1458
Test name
Test status
Simulation time 1990714131 ps
CPU time 4.6 seconds
Started Sep 18 08:16:18 AM UTC 24
Finished Sep 18 08:16:23 AM UTC 24
Peak memory 215152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3323175
975 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_nack_acqfull_ad
dr.3323175975
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/41.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/41.i2c_target_nack_txstretch.1002175003
Short name T1451
Test name
Test status
Simulation time 549720134 ps
CPU time 2.33 seconds
Started Sep 18 08:16:18 AM UTC 24
Finished Sep 18 08:16:21 AM UTC 24
Peak memory 232228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1002175
003 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_nack_txstretch.1002175003
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/41.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/41.i2c_target_perf.719331745
Short name T1448
Test name
Test status
Simulation time 1440529461 ps
CPU time 8.79 seconds
Started Sep 18 08:16:09 AM UTC 24
Finished Sep 18 08:16:19 AM UTC 24
Peak memory 231716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7193317
45 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_perf.719331745
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/41.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/41.i2c_target_smbus_maxlen.2418863789
Short name T1457
Test name
Test status
Simulation time 506636920 ps
CPU time 4.32 seconds
Started Sep 18 08:16:17 AM UTC 24
Finished Sep 18 08:16:23 AM UTC 24
Peak memory 214988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2418863
789 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_smbus_maxlen.2418863789
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/41.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/41.i2c_target_smoke.568679876
Short name T91
Test name
Test status
Simulation time 3863925980 ps
CPU time 10.67 seconds
Started Sep 18 08:16:00 AM UTC 24
Finished Sep 18 08:16:12 AM UTC 24
Peak memory 225612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=568679876 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_smoke.568679876
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/41.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/41.i2c_target_stress_all.2343984100
Short name T1740
Test name
Test status
Simulation time 35085812246 ps
CPU time 419.18 seconds
Started Sep 18 08:16:10 AM UTC 24
Finished Sep 18 08:23:14 AM UTC 24
Peak memory 5170216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=234398
4100 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_stress_all.2343984100
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/41.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/41.i2c_target_stress_rd.2859334453
Short name T1469
Test name
Test status
Simulation time 2726760426 ps
CPU time 31.31 seconds
Started Sep 18 08:16:01 AM UTC 24
Finished Sep 18 08:16:34 AM UTC 24
Peak memory 225484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2859334453 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_stress_rd.2859334453
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/41.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/41.i2c_target_stress_wr.3699020648
Short name T1748
Test name
Test status
Simulation time 54570495367 ps
CPU time 959.9 seconds
Started Sep 18 08:16:00 AM UTC 24
Finished Sep 18 08:32:10 AM UTC 24
Peak memory 8764248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3699020648 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_stress_wr.3699020648
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/41.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/41.i2c_target_stretch.894074862
Short name T1460
Test name
Test status
Simulation time 2658819673 ps
CPU time 22.45 seconds
Started Sep 18 08:16:01 AM UTC 24
Finished Sep 18 08:16:26 AM UTC 24
Peak memory 342860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=894074862 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_stretch.894074862
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/41.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/41.i2c_target_timeout.863522240
Short name T1441
Test name
Test status
Simulation time 2484842132 ps
CPU time 10.33 seconds
Started Sep 18 08:16:05 AM UTC 24
Finished Sep 18 08:16:16 AM UTC 24
Peak memory 232424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8635222
40 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_timeout.863522240
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/41.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/41.i2c_target_tx_stretch_ctrl.1353812084
Short name T1464
Test name
Test status
Simulation time 456884787 ps
CPU time 10.07 seconds
Started Sep 18 08:16:16 AM UTC 24
Finished Sep 18 08:16:28 AM UTC 24
Peak memory 215248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1353812
084 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_tx_stretch_ctrl.1353812084
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/41.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/42.i2c_alert_test.2308287213
Short name T1483
Test name
Test status
Simulation time 20229279 ps
CPU time 1.04 seconds
Started Sep 18 08:16:43 AM UTC 24
Finished Sep 18 08:16:45 AM UTC 24
Peak memory 214840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2308287213 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_alert_test.2308287213
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/42.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/42.i2c_host_error_intr.1039904181
Short name T1467
Test name
Test status
Simulation time 2516474767 ps
CPU time 7.28 seconds
Started Sep 18 08:16:25 AM UTC 24
Finished Sep 18 08:16:33 AM UTC 24
Peak memory 246652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1039904181 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 42.i2c_host_error_intr.1039904181
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/42.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/42.i2c_host_fifo_fmt_empty.544241010
Short name T1463
Test name
Test status
Simulation time 1257574180 ps
CPU time 4.08 seconds
Started Sep 18 08:16:22 AM UTC 24
Finished Sep 18 08:16:27 AM UTC 24
Peak memory 248540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=544241010 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_fmt_empty.544241010
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/42.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/42.i2c_host_fifo_full.3852695332
Short name T1536
Test name
Test status
Simulation time 2553352294 ps
CPU time 70.83 seconds
Started Sep 18 08:16:23 AM UTC 24
Finished Sep 18 08:17:36 AM UTC 24
Peak memory 615276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3852695332 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_full.3852695332
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/42.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/42.i2c_host_fifo_overflow.1224883823
Short name T1518
Test name
Test status
Simulation time 22377747544 ps
CPU time 56.55 seconds
Started Sep 18 08:16:21 AM UTC 24
Finished Sep 18 08:17:19 AM UTC 24
Peak memory 670684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1224883823 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_overflow.1224883823
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/42.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/42.i2c_host_fifo_reset_fmt.2165087224
Short name T1459
Test name
Test status
Simulation time 149211465 ps
CPU time 1.9 seconds
Started Sep 18 08:16:22 AM UTC 24
Finished Sep 18 08:16:25 AM UTC 24
Peak memory 214900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2165087224 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_fmt.2165087224
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/42.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/42.i2c_host_fifo_reset_rx.3364989016
Short name T1465
Test name
Test status
Simulation time 164553754 ps
CPU time 5.13 seconds
Started Sep 18 08:16:23 AM UTC 24
Finished Sep 18 08:16:30 AM UTC 24
Peak memory 215324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3364989016 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_rx.3364989016
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/42.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/42.i2c_host_fifo_watermark.167759525
Short name T1565
Test name
Test status
Simulation time 57462582033 ps
CPU time 99.18 seconds
Started Sep 18 08:16:20 AM UTC 24
Finished Sep 18 08:18:01 AM UTC 24
Peak memory 1245972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=167759525 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_watermark.167759525
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/42.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/42.i2c_host_may_nack.291379411
Short name T1492
Test name
Test status
Simulation time 1132858734 ps
CPU time 10.96 seconds
Started Sep 18 08:16:38 AM UTC 24
Finished Sep 18 08:16:50 AM UTC 24
Peak memory 215256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=291379411 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 42.i2c_host_may_nack.291379411
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/42.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/42.i2c_host_mode_toggle.2126925024
Short name T1421
Test name
Test status
Simulation time 302294914 ps
CPU time 3.03 seconds
Started Sep 18 08:16:38 AM UTC 24
Finished Sep 18 08:16:42 AM UTC 24
Peak memory 225644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2126925024 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_mode_toggle.2126925024
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/42.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/42.i2c_host_override.2677699696
Short name T1455
Test name
Test status
Simulation time 38223547 ps
CPU time 1.05 seconds
Started Sep 18 08:16:20 AM UTC 24
Finished Sep 18 08:16:22 AM UTC 24
Peak memory 214112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2677699696 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.i2c_host_override.2677699696
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/42.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/42.i2c_host_perf.1033399504
Short name T1513
Test name
Test status
Simulation time 5257613448 ps
CPU time 50.74 seconds
Started Sep 18 08:16:23 AM UTC 24
Finished Sep 18 08:17:16 AM UTC 24
Peak memory 424868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1033399504 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 42.i2c_host_perf.1033399504
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/42.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/42.i2c_host_perf_precise.1633760705
Short name T1627
Test name
Test status
Simulation time 5788966956 ps
CPU time 166.24 seconds
Started Sep 18 08:16:23 AM UTC 24
Finished Sep 18 08:19:13 AM UTC 24
Peak memory 901844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1633760705 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_perf_precise.1633760705
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/42.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/42.i2c_host_smoke.311022921
Short name T1547
Test name
Test status
Simulation time 3899447658 ps
CPU time 85.8 seconds
Started Sep 18 08:16:19 AM UTC 24
Finished Sep 18 08:17:46 AM UTC 24
Peak memory 369432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=311022921 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 42.i2c_host_smoke.311022921
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/42.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/42.i2c_host_stretch_timeout.3081952188
Short name T1474
Test name
Test status
Simulation time 732699790 ps
CPU time 13.58 seconds
Started Sep 18 08:16:23 AM UTC 24
Finished Sep 18 08:16:38 AM UTC 24
Peak memory 225632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3081952188 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_stretch_timeout.3081952188
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/42.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/42.i2c_target_bad_addr.2473094980
Short name T1491
Test name
Test status
Simulation time 2677516420 ps
CPU time 10.32 seconds
Started Sep 18 08:16:37 AM UTC 24
Finished Sep 18 08:16:48 AM UTC 24
Peak memory 219420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=2473094980 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_bad_ad
dr.2473094980
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/42.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/42.i2c_target_fifo_reset_acq.2813482361
Short name T1472
Test name
Test status
Simulation time 226465446 ps
CPU time 1.54 seconds
Started Sep 18 08:16:34 AM UTC 24
Finished Sep 18 08:16:37 AM UTC 24
Peak memory 215020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2813482
361 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_fifo_reset_acq.2813482361
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/42.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/42.i2c_target_fifo_reset_tx.3695431176
Short name T1475
Test name
Test status
Simulation time 256025304 ps
CPU time 2.45 seconds
Started Sep 18 08:16:35 AM UTC 24
Finished Sep 18 08:16:39 AM UTC 24
Peak memory 225668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3695431
176 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_fifo_reset_tx.3695431176
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/42.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/42.i2c_target_fifo_watermarks_acq.623273282
Short name T1481
Test name
Test status
Simulation time 764484857 ps
CPU time 4.75 seconds
Started Sep 18 08:16:39 AM UTC 24
Finished Sep 18 08:16:45 AM UTC 24
Peak memory 215320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6232732
82 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_fifo_watermark
s_acq.623273282
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/42.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/42.i2c_target_fifo_watermarks_tx.3531660329
Short name T1479
Test name
Test status
Simulation time 69132431 ps
CPU time 1.31 seconds
Started Sep 18 08:16:40 AM UTC 24
Finished Sep 18 08:16:42 AM UTC 24
Peak memory 215032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3531660
329 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_fifo_watermark
s_tx.3531660329
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/42.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/42.i2c_target_hrst.3770601306
Short name T1434
Test name
Test status
Simulation time 520527097 ps
CPU time 3.32 seconds
Started Sep 18 08:16:38 AM UTC 24
Finished Sep 18 08:16:42 AM UTC 24
Peak memory 225544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3770601
306 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_hrst.3770601306
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/42.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/42.i2c_target_intr_smoke.2118409876
Short name T1470
Test name
Test status
Simulation time 1083121123 ps
CPU time 5.1 seconds
Started Sep 18 08:16:28 AM UTC 24
Finished Sep 18 08:16:34 AM UTC 24
Peak memory 225564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=211840
9876 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_intr_smoke.2118409876
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/42.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/42.i2c_target_intr_stress_wr.3760973338
Short name T1484
Test name
Test status
Simulation time 3408045215 ps
CPU time 15.34 seconds
Started Sep 18 08:16:30 AM UTC 24
Finished Sep 18 08:16:46 AM UTC 24
Peak memory 574296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3760973338 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_intr_stres
s_wr.3760973338
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/42.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/42.i2c_target_nack_acqfull.1379423305
Short name T1487
Test name
Test status
Simulation time 423895397 ps
CPU time 4.17 seconds
Started Sep 18 08:16:42 AM UTC 24
Finished Sep 18 08:16:47 AM UTC 24
Peak memory 225708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1379423
305 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_nack_acqfull.1379423305
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/42.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/42.i2c_target_nack_acqfull_addr.1832762768
Short name T1490
Test name
Test status
Simulation time 3747120417 ps
CPU time 4.65 seconds
Started Sep 18 08:16:42 AM UTC 24
Finished Sep 18 08:16:48 AM UTC 24
Peak memory 215184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1832762
768 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_nack_acqfull_ad
dr.1832762768
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/42.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/42.i2c_target_perf.1917188133
Short name T1478
Test name
Test status
Simulation time 4478700971 ps
CPU time 4.93 seconds
Started Sep 18 08:16:35 AM UTC 24
Finished Sep 18 08:16:41 AM UTC 24
Peak memory 225760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1917188
133 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_perf.1917188133
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/42.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/42.i2c_target_smbus_maxlen.3284145346
Short name T1486
Test name
Test status
Simulation time 4317200053 ps
CPU time 3.87 seconds
Started Sep 18 08:16:42 AM UTC 24
Finished Sep 18 08:16:47 AM UTC 24
Peak memory 215160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3284145
346 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_smbus_maxlen.3284145346
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/42.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/42.i2c_target_smoke.1332939767
Short name T1476
Test name
Test status
Simulation time 3857688092 ps
CPU time 11.55 seconds
Started Sep 18 08:16:27 AM UTC 24
Finished Sep 18 08:16:39 AM UTC 24
Peak memory 225688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1332939767 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_smoke.1332939767
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/42.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/42.i2c_target_stress_all.154592257
Short name T1504
Test name
Test status
Simulation time 25158362651 ps
CPU time 30.86 seconds
Started Sep 18 08:16:35 AM UTC 24
Finished Sep 18 08:17:07 AM UTC 24
Peak memory 265048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=154592
257 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_stress_all.154592257
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/42.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/42.i2c_target_stress_rd.2059992032
Short name T1494
Test name
Test status
Simulation time 1946111662 ps
CPU time 22.59 seconds
Started Sep 18 08:16:28 AM UTC 24
Finished Sep 18 08:16:52 AM UTC 24
Peak memory 242648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2059992032 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_stress_rd.2059992032
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/42.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/42.i2c_target_stress_wr.1189382898
Short name T1473
Test name
Test status
Simulation time 14073012987 ps
CPU time 8.92 seconds
Started Sep 18 08:16:27 AM UTC 24
Finished Sep 18 08:16:37 AM UTC 24
Peak memory 215524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1189382898 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_stress_wr.1189382898
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/42.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/42.i2c_target_stretch.4038848027
Short name T1482
Test name
Test status
Simulation time 1627323311 ps
CPU time 15.77 seconds
Started Sep 18 08:16:28 AM UTC 24
Finished Sep 18 08:16:45 AM UTC 24
Peak memory 373548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4038848027 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_stretch.4038848027
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/42.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/42.i2c_target_timeout.2046692506
Short name T1477
Test name
Test status
Simulation time 9098212042 ps
CPU time 7.94 seconds
Started Sep 18 08:16:32 AM UTC 24
Finished Sep 18 08:16:41 AM UTC 24
Peak memory 242460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2046692
506 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_timeout.2046692506
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/42.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/42.i2c_target_tx_stretch_ctrl.3743556303
Short name T1480
Test name
Test status
Simulation time 77698480 ps
CPU time 2.63 seconds
Started Sep 18 08:16:40 AM UTC 24
Finished Sep 18 08:16:43 AM UTC 24
Peak memory 215320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3743556
303 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_tx_stretch_ctrl.3743556303
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/42.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/43.i2c_alert_test.2495900380
Short name T1516
Test name
Test status
Simulation time 42209406 ps
CPU time 0.98 seconds
Started Sep 18 08:17:17 AM UTC 24
Finished Sep 18 08:17:19 AM UTC 24
Peak memory 214840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2495900380 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_alert_test.2495900380
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/43.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/43.i2c_host_error_intr.2025048216
Short name T1497
Test name
Test status
Simulation time 573545957 ps
CPU time 7.12 seconds
Started Sep 18 08:16:49 AM UTC 24
Finished Sep 18 08:16:57 AM UTC 24
Peak memory 238520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2025048216 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 43.i2c_host_error_intr.2025048216
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/43.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/43.i2c_host_fifo_fmt_empty.1673896817
Short name T1498
Test name
Test status
Simulation time 1105639275 ps
CPU time 8.46 seconds
Started Sep 18 08:16:48 AM UTC 24
Finished Sep 18 08:16:57 AM UTC 24
Peak memory 271076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1673896817 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_fmt_empty.1673896817
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/43.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/43.i2c_host_fifo_full.210103188
Short name T1559
Test name
Test status
Simulation time 9092775520 ps
CPU time 63.22 seconds
Started Sep 18 08:16:48 AM UTC 24
Finished Sep 18 08:17:53 AM UTC 24
Peak memory 394084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=210103188 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_full.210103188
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/43.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/43.i2c_host_fifo_overflow.3803651360
Short name T1550
Test name
Test status
Simulation time 7450350836 ps
CPU time 60.13 seconds
Started Sep 18 08:16:47 AM UTC 24
Finished Sep 18 08:17:48 AM UTC 24
Peak memory 691044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3803651360 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_overflow.3803651360
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/43.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/43.i2c_host_fifo_reset_fmt.185676716
Short name T1493
Test name
Test status
Simulation time 134877331 ps
CPU time 1.74 seconds
Started Sep 18 08:16:48 AM UTC 24
Finished Sep 18 08:16:50 AM UTC 24
Peak memory 214900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=185676716 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_fmt.185676716
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/43.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/43.i2c_host_fifo_reset_rx.1397800876
Short name T1495
Test name
Test status
Simulation time 447714700 ps
CPU time 3.99 seconds
Started Sep 18 08:16:48 AM UTC 24
Finished Sep 18 08:16:53 AM UTC 24
Peak memory 215324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1397800876 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_rx.1397800876
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/43.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/43.i2c_host_fifo_watermark.1455152357
Short name T1676
Test name
Test status
Simulation time 14471077477 ps
CPU time 203.02 seconds
Started Sep 18 08:16:46 AM UTC 24
Finished Sep 18 08:20:12 AM UTC 24
Peak memory 1106720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1455152357 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_watermark.1455152357
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/43.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/43.i2c_host_may_nack.840489130
Short name T1519
Test name
Test status
Simulation time 494173043 ps
CPU time 8.97 seconds
Started Sep 18 08:17:09 AM UTC 24
Finished Sep 18 08:17:19 AM UTC 24
Peak memory 215316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=840489130 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 43.i2c_host_may_nack.840489130
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/43.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/43.i2c_host_mode_toggle.4244758152
Short name T1509
Test name
Test status
Simulation time 148203729 ps
CPU time 3.25 seconds
Started Sep 18 08:17:08 AM UTC 24
Finished Sep 18 08:17:13 AM UTC 24
Peak memory 225640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4244758152 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_mode_toggle.4244758152
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/43.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/43.i2c_host_override.3540228540
Short name T1488
Test name
Test status
Simulation time 85816832 ps
CPU time 1.07 seconds
Started Sep 18 08:16:45 AM UTC 24
Finished Sep 18 08:16:47 AM UTC 24
Peak memory 214112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3540228540 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.i2c_host_override.3540228540
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/43.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/43.i2c_host_perf.191454671
Short name T1738
Test name
Test status
Simulation time 26707453494 ps
CPU time 370.47 seconds
Started Sep 18 08:16:49 AM UTC 24
Finished Sep 18 08:23:04 AM UTC 24
Peak memory 225640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=191454671 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 43.i2c_host_perf.191454671
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/43.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/43.i2c_host_perf_precise.4022301416
Short name T1496
Test name
Test status
Simulation time 298712011 ps
CPU time 4.1 seconds
Started Sep 18 08:16:49 AM UTC 24
Finished Sep 18 08:16:54 AM UTC 24
Peak memory 215200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4022301416 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_perf_precise.4022301416
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/43.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/43.i2c_host_smoke.302916829
Short name T1581
Test name
Test status
Simulation time 6994381425 ps
CPU time 87.41 seconds
Started Sep 18 08:16:44 AM UTC 24
Finished Sep 18 08:18:14 AM UTC 24
Peak memory 363488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=302916829 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 43.i2c_host_smoke.302916829
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/43.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/43.i2c_host_stretch_timeout.1760251326
Short name T1500
Test name
Test status
Simulation time 626047644 ps
CPU time 9.83 seconds
Started Sep 18 08:16:49 AM UTC 24
Finished Sep 18 08:17:00 AM UTC 24
Peak memory 227548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1760251326 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_stretch_timeout.1760251326
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/43.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/43.i2c_target_bad_addr.3004482994
Short name T1512
Test name
Test status
Simulation time 4086657489 ps
CPU time 7.8 seconds
Started Sep 18 08:17:06 AM UTC 24
Finished Sep 18 08:17:15 AM UTC 24
Peak memory 225636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=3004482994 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_bad_ad
dr.3004482994
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/43.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/43.i2c_target_fifo_reset_acq.2786542258
Short name T1501
Test name
Test status
Simulation time 158849678 ps
CPU time 1.88 seconds
Started Sep 18 08:17:01 AM UTC 24
Finished Sep 18 08:17:04 AM UTC 24
Peak memory 214784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2786542
258 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_fifo_reset_acq.2786542258
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/43.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/43.i2c_target_fifo_reset_tx.3421600398
Short name T1502
Test name
Test status
Simulation time 619658238 ps
CPU time 2.06 seconds
Started Sep 18 08:17:02 AM UTC 24
Finished Sep 18 08:17:05 AM UTC 24
Peak memory 215452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3421600
398 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_fifo_reset_tx.3421600398
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/43.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/43.i2c_target_fifo_watermarks_acq.1188893738
Short name T1515
Test name
Test status
Simulation time 1410333253 ps
CPU time 5.11 seconds
Started Sep 18 08:17:11 AM UTC 24
Finished Sep 18 08:17:18 AM UTC 24
Peak memory 215384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1188893
738 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_fifo_watermar
ks_acq.1188893738
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/43.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/43.i2c_target_fifo_watermarks_tx.1256315589
Short name T1514
Test name
Test status
Simulation time 689888963 ps
CPU time 2.52 seconds
Started Sep 18 08:17:12 AM UTC 24
Finished Sep 18 08:17:16 AM UTC 24
Peak memory 215044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1256315
589 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_fifo_watermark
s_tx.1256315589
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/43.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/43.i2c_target_hrst.2319170036
Short name T1507
Test name
Test status
Simulation time 229623627 ps
CPU time 2.08 seconds
Started Sep 18 08:17:08 AM UTC 24
Finished Sep 18 08:17:11 AM UTC 24
Peak memory 225752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2319170
036 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_hrst.2319170036
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/43.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/43.i2c_target_intr_smoke.1150989458
Short name T1503
Test name
Test status
Simulation time 9904668649 ps
CPU time 8.27 seconds
Started Sep 18 08:16:57 AM UTC 24
Finished Sep 18 08:17:07 AM UTC 24
Peak memory 232024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=115098
9458 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_intr_smoke.1150989458
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/43.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/43.i2c_target_intr_stress_wr.273287835
Short name T1505
Test name
Test status
Simulation time 9053555296 ps
CPU time 8.62 seconds
Started Sep 18 08:16:59 AM UTC 24
Finished Sep 18 08:17:08 AM UTC 24
Peak memory 215360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=273287835 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_intr_stress
_wr.273287835
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/43.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/43.i2c_target_nack_acqfull.572487684
Short name T1522
Test name
Test status
Simulation time 528878645 ps
CPU time 4.92 seconds
Started Sep 18 08:17:15 AM UTC 24
Finished Sep 18 08:17:20 AM UTC 24
Peak memory 225700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5724876
84 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_nack_acqfull.572487684
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/43.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/43.i2c_target_nack_acqfull_addr.2406149710
Short name T1523
Test name
Test status
Simulation time 703935692 ps
CPU time 4.99 seconds
Started Sep 18 08:17:15 AM UTC 24
Finished Sep 18 08:17:21 AM UTC 24
Peak memory 215260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2406149
710 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_nack_acqfull_ad
dr.2406149710
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/43.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/43.i2c_target_perf.2780221062
Short name T1511
Test name
Test status
Simulation time 2268977442 ps
CPU time 7.8 seconds
Started Sep 18 08:17:05 AM UTC 24
Finished Sep 18 08:17:14 AM UTC 24
Peak memory 227736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2780221
062 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_perf.2780221062
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/43.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/43.i2c_target_smbus_maxlen.2626802757
Short name T1517
Test name
Test status
Simulation time 1076788346 ps
CPU time 4.36 seconds
Started Sep 18 08:17:13 AM UTC 24
Finished Sep 18 08:17:19 AM UTC 24
Peak memory 215000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2626802
757 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_smbus_maxlen.2626802757
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/43.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/43.i2c_target_smoke.1859092037
Short name T1510
Test name
Test status
Simulation time 1204806141 ps
CPU time 20.83 seconds
Started Sep 18 08:16:51 AM UTC 24
Finished Sep 18 08:17:13 AM UTC 24
Peak memory 225552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1859092037 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_smoke.1859092037
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/43.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/43.i2c_target_stress_all.3175944724
Short name T1631
Test name
Test status
Simulation time 50759983902 ps
CPU time 130.04 seconds
Started Sep 18 08:17:05 AM UTC 24
Finished Sep 18 08:19:17 AM UTC 24
Peak memory 1801060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=317594
4724 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_stress_all.3175944724
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/43.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/43.i2c_target_stress_rd.3968675153
Short name T1525
Test name
Test status
Simulation time 473085179 ps
CPU time 26.58 seconds
Started Sep 18 08:16:53 AM UTC 24
Finished Sep 18 08:17:21 AM UTC 24
Peak memory 225696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3968675153 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_stress_rd.3968675153
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/43.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/43.i2c_target_stress_wr.2079315946
Short name T1602
Test name
Test status
Simulation time 47517531788 ps
CPU time 106.23 seconds
Started Sep 18 08:16:52 AM UTC 24
Finished Sep 18 08:18:40 AM UTC 24
Peak memory 1776476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2079315946 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_stress_wr.2079315946
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/43.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/43.i2c_target_stretch.3647360239
Short name T1508
Test name
Test status
Simulation time 6698265707 ps
CPU time 16.25 seconds
Started Sep 18 08:16:54 AM UTC 24
Finished Sep 18 08:17:12 AM UTC 24
Peak memory 400148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3647360239 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_stretch.3647360239
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/43.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/43.i2c_target_timeout.1124028084
Short name T1506
Test name
Test status
Simulation time 1138190293 ps
CPU time 10.43 seconds
Started Sep 18 08:16:59 AM UTC 24
Finished Sep 18 08:17:10 AM UTC 24
Peak memory 242408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1124028
084 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_timeout.1124028084
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/43.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/43.i2c_target_tx_stretch_ctrl.2647093117
Short name T1521
Test name
Test status
Simulation time 199536361 ps
CPU time 6.24 seconds
Started Sep 18 08:17:12 AM UTC 24
Finished Sep 18 08:17:20 AM UTC 24
Peak memory 215304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2647093
117 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_tx_stretch_ctrl.2647093117
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/43.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/44.i2c_alert_test.1773416837
Short name T1520
Test name
Test status
Simulation time 15348923 ps
CPU time 1.03 seconds
Started Sep 18 08:17:48 AM UTC 24
Finished Sep 18 08:17:50 AM UTC 24
Peak memory 214840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1773416837 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_alert_test.1773416837
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/44.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/44.i2c_host_error_intr.3652551933
Short name T1531
Test name
Test status
Simulation time 2269547181 ps
CPU time 4.85 seconds
Started Sep 18 08:17:23 AM UTC 24
Finished Sep 18 08:17:29 AM UTC 24
Peak memory 225636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3652551933 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 44.i2c_host_error_intr.3652551933
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/44.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/44.i2c_host_fifo_fmt_empty.3604816796
Short name T1542
Test name
Test status
Simulation time 413068553 ps
CPU time 18.17 seconds
Started Sep 18 08:17:20 AM UTC 24
Finished Sep 18 08:17:40 AM UTC 24
Peak memory 293596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3604816796 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_fmt_empty.3604816796
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/44.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/44.i2c_host_fifo_full.446283550
Short name T1578
Test name
Test status
Simulation time 1920527423 ps
CPU time 50.52 seconds
Started Sep 18 08:17:20 AM UTC 24
Finished Sep 18 08:18:13 AM UTC 24
Peak memory 344836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=446283550 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_full.446283550
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/44.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/44.i2c_host_fifo_overflow.2957244405
Short name T1603
Test name
Test status
Simulation time 14238707497 ps
CPU time 78.7 seconds
Started Sep 18 08:17:20 AM UTC 24
Finished Sep 18 08:18:41 AM UTC 24
Peak memory 834408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2957244405 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_overflow.2957244405
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/44.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/44.i2c_host_fifo_reset_fmt.3870974909
Short name T1527
Test name
Test status
Simulation time 572332706 ps
CPU time 2.14 seconds
Started Sep 18 08:17:20 AM UTC 24
Finished Sep 18 08:17:23 AM UTC 24
Peak memory 215380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3870974909 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_fmt.3870974909
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/44.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/44.i2c_host_fifo_reset_rx.233554400
Short name T1530
Test name
Test status
Simulation time 1818127790 ps
CPU time 3.99 seconds
Started Sep 18 08:17:20 AM UTC 24
Finished Sep 18 08:17:26 AM UTC 24
Peak memory 215320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=233554400 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_rx.233554400
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/44.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/44.i2c_host_fifo_watermark.879685603
Short name T1687
Test name
Test status
Simulation time 7872313388 ps
CPU time 175.57 seconds
Started Sep 18 08:17:20 AM UTC 24
Finished Sep 18 08:20:19 AM UTC 24
Peak memory 986020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=879685603 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_watermark.879685603
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/44.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/44.i2c_host_may_nack.307832831
Short name T1549
Test name
Test status
Simulation time 420962949 ps
CPU time 7.05 seconds
Started Sep 18 08:17:40 AM UTC 24
Finished Sep 18 08:17:48 AM UTC 24
Peak memory 215328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=307832831 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 44.i2c_host_may_nack.307832831
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/44.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/44.i2c_host_override.4072990254
Short name T1524
Test name
Test status
Simulation time 90991022 ps
CPU time 1.04 seconds
Started Sep 18 08:17:19 AM UTC 24
Finished Sep 18 08:17:21 AM UTC 24
Peak memory 214112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4072990254 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.i2c_host_override.4072990254
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/44.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/44.i2c_host_perf.173334136
Short name T1705
Test name
Test status
Simulation time 6155744561 ps
CPU time 197.81 seconds
Started Sep 18 08:17:21 AM UTC 24
Finished Sep 18 08:20:42 AM UTC 24
Peak memory 1653544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=173334136 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 44.i2c_host_perf.173334136
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/44.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/44.i2c_host_perf_precise.2191358051
Short name T1528
Test name
Test status
Simulation time 41931731 ps
CPU time 2.07 seconds
Started Sep 18 08:17:22 AM UTC 24
Finished Sep 18 08:17:25 AM UTC 24
Peak memory 233680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2191358051 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_perf_precise.2191358051
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/44.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/44.i2c_host_smoke.409788236
Short name T1539
Test name
Test status
Simulation time 5765304206 ps
CPU time 20.44 seconds
Started Sep 18 08:17:17 AM UTC 24
Finished Sep 18 08:17:38 AM UTC 24
Peak memory 295772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=409788236 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 44.i2c_host_smoke.409788236
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/44.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/44.i2c_host_stretch_timeout.4242033527
Short name T1548
Test name
Test status
Simulation time 2252134489 ps
CPU time 24.64 seconds
Started Sep 18 08:17:22 AM UTC 24
Finished Sep 18 08:17:48 AM UTC 24
Peak memory 241880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4242033527 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_stretch_timeout.4242033527
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/44.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/44.i2c_target_bad_addr.796698468
Short name T1553
Test name
Test status
Simulation time 932339122 ps
CPU time 8.46 seconds
Started Sep 18 08:17:40 AM UTC 24
Finished Sep 18 08:17:49 AM UTC 24
Peak memory 232140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=796698468 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_bad_addr.796698468
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/44.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/44.i2c_target_fifo_reset_acq.1984404669
Short name T1540
Test name
Test status
Simulation time 346871679 ps
CPU time 1.46 seconds
Started Sep 18 08:17:36 AM UTC 24
Finished Sep 18 08:17:39 AM UTC 24
Peak memory 214784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1984404
669 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_fifo_reset_acq.1984404669
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/44.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/44.i2c_target_fifo_reset_tx.1816458021
Short name T1541
Test name
Test status
Simulation time 184616371 ps
CPU time 1.94 seconds
Started Sep 18 08:17:36 AM UTC 24
Finished Sep 18 08:17:39 AM UTC 24
Peak memory 214904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1816458
021 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_fifo_reset_tx.1816458021
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/44.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/44.i2c_target_fifo_watermarks_acq.4194793795
Short name T1545
Test name
Test status
Simulation time 1682528387 ps
CPU time 4.51 seconds
Started Sep 18 08:17:41 AM UTC 24
Finished Sep 18 08:17:46 AM UTC 24
Peak memory 215328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4194793
795 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_fifo_watermar
ks_acq.4194793795
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/44.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/44.i2c_target_fifo_watermarks_tx.759582967
Short name T1546
Test name
Test status
Simulation time 144837076 ps
CPU time 2.5 seconds
Started Sep 18 08:17:43 AM UTC 24
Finished Sep 18 08:17:46 AM UTC 24
Peak memory 215048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7595829
67 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_fifo_watermarks
_tx.759582967
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/44.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/44.i2c_target_intr_smoke.2259067885
Short name T1538
Test name
Test status
Simulation time 628546917 ps
CPU time 5.81 seconds
Started Sep 18 08:17:30 AM UTC 24
Finished Sep 18 08:17:37 AM UTC 24
Peak memory 225492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=225906
7885 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_intr_smoke.2259067885
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/44.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/44.i2c_target_intr_stress_wr.3254194403
Short name T1544
Test name
Test status
Simulation time 8695870837 ps
CPU time 7.54 seconds
Started Sep 18 08:17:35 AM UTC 24
Finished Sep 18 08:17:44 AM UTC 24
Peak memory 215384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3254194403 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_intr_stres
s_wr.3254194403
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/44.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/44.i2c_target_nack_acqfull.4106529219
Short name T1556
Test name
Test status
Simulation time 2409325204 ps
CPU time 3.21 seconds
Started Sep 18 08:17:47 AM UTC 24
Finished Sep 18 08:17:51 AM UTC 24
Peak memory 225560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4106529
219 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_nack_acqfull.4106529219
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/44.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/44.i2c_target_nack_acqfull_addr.246068544
Short name T1560
Test name
Test status
Simulation time 739264481 ps
CPU time 4.88 seconds
Started Sep 18 08:17:47 AM UTC 24
Finished Sep 18 08:17:53 AM UTC 24
Peak memory 215268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2460685
44 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_nack_acqfull_addr.246068544
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/44.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/44.i2c_target_nack_txstretch.274361018
Short name T1555
Test name
Test status
Simulation time 260056129 ps
CPU time 1.89 seconds
Started Sep 18 08:17:47 AM UTC 24
Finished Sep 18 08:17:50 AM UTC 24
Peak memory 232104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2743610
18 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_nack_txstretch.274361018
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/44.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/44.i2c_target_perf.660655675
Short name T1551
Test name
Test status
Simulation time 1822730158 ps
CPU time 10.81 seconds
Started Sep 18 08:17:36 AM UTC 24
Finished Sep 18 08:17:48 AM UTC 24
Peak memory 232156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6606556
75 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_perf.660655675
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/44.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/44.i2c_target_smbus_maxlen.1292026193
Short name T1554
Test name
Test status
Simulation time 1576884304 ps
CPU time 3.5 seconds
Started Sep 18 08:17:45 AM UTC 24
Finished Sep 18 08:17:50 AM UTC 24
Peak memory 215092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1292026
193 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_smbus_maxlen.1292026193
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/44.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/44.i2c_target_smoke.2830159903
Short name T1543
Test name
Test status
Simulation time 1958738762 ps
CPU time 16.84 seconds
Started Sep 18 08:17:25 AM UTC 24
Finished Sep 18 08:17:43 AM UTC 24
Peak memory 225752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2830159903 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_smoke.2830159903
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/44.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/44.i2c_target_stress_all.2371839913
Short name T1741
Test name
Test status
Simulation time 66322905557 ps
CPU time 337.49 seconds
Started Sep 18 08:17:38 AM UTC 24
Finished Sep 18 08:23:19 AM UTC 24
Peak memory 2870244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=237183
9913 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_stress_all.2371839913
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/44.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/44.i2c_target_stress_rd.1987126577
Short name T1564
Test name
Test status
Simulation time 562125307 ps
CPU time 30.13 seconds
Started Sep 18 08:17:26 AM UTC 24
Finished Sep 18 08:17:58 AM UTC 24
Peak memory 215392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1987126577 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_stress_rd.1987126577
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/44.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/44.i2c_target_stress_wr.3309264111
Short name T1743
Test name
Test status
Simulation time 43948929555 ps
CPU time 514.86 seconds
Started Sep 18 08:17:26 AM UTC 24
Finished Sep 18 08:26:06 AM UTC 24
Peak memory 6063072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3309264111 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_stress_wr.3309264111
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/44.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/44.i2c_target_stretch.3583439035
Short name T1535
Test name
Test status
Simulation time 5857428401 ps
CPU time 8.37 seconds
Started Sep 18 08:17:26 AM UTC 24
Finished Sep 18 08:17:36 AM UTC 24
Peak memory 303956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3583439035 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_stretch.3583439035
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/44.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/44.i2c_target_timeout.2297225766
Short name T1552
Test name
Test status
Simulation time 2474582961 ps
CPU time 12.31 seconds
Started Sep 18 08:17:35 AM UTC 24
Finished Sep 18 08:17:49 AM UTC 24
Peak memory 232296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2297225
766 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_timeout.2297225766
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/44.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/44.i2c_target_tx_stretch_ctrl.871566061
Short name T1561
Test name
Test status
Simulation time 432322145 ps
CPU time 9.24 seconds
Started Sep 18 08:17:44 AM UTC 24
Finished Sep 18 08:17:54 AM UTC 24
Peak memory 215252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8715660
61 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_tx_stretch_ctrl.871566061
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/44.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/45.i2c_alert_test.1152956148
Short name T1588
Test name
Test status
Simulation time 44045593 ps
CPU time 0.98 seconds
Started Sep 18 08:18:15 AM UTC 24
Finished Sep 18 08:18:17 AM UTC 24
Peak memory 214840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1152956148 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_alert_test.1152956148
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/45.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/45.i2c_host_error_intr.2993573640
Short name T1563
Test name
Test status
Simulation time 260445916 ps
CPU time 3.19 seconds
Started Sep 18 08:17:52 AM UTC 24
Finished Sep 18 08:17:56 AM UTC 24
Peak memory 242612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2993573640 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 45.i2c_host_error_intr.2993573640
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/45.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/45.i2c_host_fifo_fmt_empty.3808872232
Short name T1568
Test name
Test status
Simulation time 503670140 ps
CPU time 13.88 seconds
Started Sep 18 08:17:51 AM UTC 24
Finished Sep 18 08:18:06 AM UTC 24
Peak memory 318172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3808872232 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_fmt_empty.3808872232
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/45.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/45.i2c_host_fifo_full.370865594
Short name T1637
Test name
Test status
Simulation time 3783609099 ps
CPU time 98.28 seconds
Started Sep 18 08:17:51 AM UTC 24
Finished Sep 18 08:19:31 AM UTC 24
Peak memory 496360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=370865594 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_full.370865594
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/45.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/45.i2c_host_fifo_overflow.24697520
Short name T1598
Test name
Test status
Simulation time 2826142000 ps
CPU time 38.85 seconds
Started Sep 18 08:17:50 AM UTC 24
Finished Sep 18 08:18:30 AM UTC 24
Peak memory 465692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=24697520 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ho
st_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_overflow.24697520
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/45.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/45.i2c_host_fifo_reset_fmt.2225293935
Short name T1558
Test name
Test status
Simulation time 358009703 ps
CPU time 1.69 seconds
Started Sep 18 08:17:50 AM UTC 24
Finished Sep 18 08:17:52 AM UTC 24
Peak memory 214900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2225293935 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_fmt.2225293935
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/45.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/45.i2c_host_fifo_reset_rx.3118323244
Short name T1562
Test name
Test status
Simulation time 285252314 ps
CPU time 3.41 seconds
Started Sep 18 08:17:51 AM UTC 24
Finished Sep 18 08:17:55 AM UTC 24
Peak memory 215324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3118323244 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_rx.3118323244
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/45.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/45.i2c_host_fifo_watermark.1631855415
Short name T1731
Test name
Test status
Simulation time 17432997095 ps
CPU time 237.34 seconds
Started Sep 18 08:17:50 AM UTC 24
Finished Sep 18 08:21:50 AM UTC 24
Peak memory 1293156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1631855415 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_watermark.1631855415
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/45.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/45.i2c_host_may_nack.842447753
Short name T1587
Test name
Test status
Simulation time 463512600 ps
CPU time 7.46 seconds
Started Sep 18 08:18:08 AM UTC 24
Finished Sep 18 08:18:17 AM UTC 24
Peak memory 215328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=842447753 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 45.i2c_host_may_nack.842447753
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/45.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/45.i2c_host_mode_toggle.2169010757
Short name T1577
Test name
Test status
Simulation time 1039605121 ps
CPU time 2.35 seconds
Started Sep 18 08:18:08 AM UTC 24
Finished Sep 18 08:18:11 AM UTC 24
Peak memory 225644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2169010757 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_mode_toggle.2169010757
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/45.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/45.i2c_host_override.3697008431
Short name T1557
Test name
Test status
Simulation time 17229784 ps
CPU time 1 seconds
Started Sep 18 08:17:50 AM UTC 24
Finished Sep 18 08:17:51 AM UTC 24
Peak memory 214088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3697008431 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.i2c_host_override.3697008431
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/45.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/45.i2c_host_perf.2090612490
Short name T1611
Test name
Test status
Simulation time 12332971634 ps
CPU time 60.69 seconds
Started Sep 18 08:17:51 AM UTC 24
Finished Sep 18 08:18:53 AM UTC 24
Peak memory 246568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2090612490 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 45.i2c_host_perf.2090612490
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/45.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/45.i2c_host_perf_precise.1028316981
Short name T1572
Test name
Test status
Simulation time 600972589 ps
CPU time 14.34 seconds
Started Sep 18 08:17:52 AM UTC 24
Finished Sep 18 08:18:07 AM UTC 24
Peak memory 303912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1028316981 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_perf_precise.1028316981
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/45.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/45.i2c_host_smoke.1118717688
Short name T1571
Test name
Test status
Simulation time 2440101861 ps
CPU time 17.37 seconds
Started Sep 18 08:17:48 AM UTC 24
Finished Sep 18 08:18:07 AM UTC 24
Peak memory 297820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1118717688 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 45.i2c_host_smoke.1118717688
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/45.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/45.i2c_host_stretch_timeout.2199193199
Short name T1566
Test name
Test status
Simulation time 2623129913 ps
CPU time 10.28 seconds
Started Sep 18 08:17:52 AM UTC 24
Finished Sep 18 08:18:03 AM UTC 24
Peak memory 232316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2199193199 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_stretch_timeout.2199193199
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/45.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/45.i2c_target_bad_addr.3514884466
Short name T1583
Test name
Test status
Simulation time 3609000368 ps
CPU time 5.77 seconds
Started Sep 18 08:18:08 AM UTC 24
Finished Sep 18 08:18:15 AM UTC 24
Peak memory 225692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=3514884466 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_bad_ad
dr.3514884466
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/45.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/45.i2c_target_fifo_reset_acq.2363714420
Short name T1574
Test name
Test status
Simulation time 894703896 ps
CPU time 1.94 seconds
Started Sep 18 08:18:05 AM UTC 24
Finished Sep 18 08:18:08 AM UTC 24
Peak memory 214744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2363714
420 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_fifo_reset_acq.2363714420
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/45.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/45.i2c_target_fifo_watermarks_acq.2521746481
Short name T1580
Test name
Test status
Simulation time 251411964 ps
CPU time 2.97 seconds
Started Sep 18 08:18:09 AM UTC 24
Finished Sep 18 08:18:13 AM UTC 24
Peak memory 215240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2521746
481 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_fifo_watermar
ks_acq.2521746481
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/45.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/45.i2c_target_fifo_watermarks_tx.3038453890
Short name T1582
Test name
Test status
Simulation time 273028050 ps
CPU time 1.24 seconds
Started Sep 18 08:18:11 AM UTC 24
Finished Sep 18 08:18:14 AM UTC 24
Peak memory 215032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3038453
890 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_fifo_watermark
s_tx.3038453890
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/45.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/45.i2c_target_intr_smoke.3521990007
Short name T1570
Test name
Test status
Simulation time 4650544374 ps
CPU time 7.86 seconds
Started Sep 18 08:17:58 AM UTC 24
Finished Sep 18 08:18:06 AM UTC 24
Peak memory 232272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=352199
0007 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_intr_smoke.3521990007
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/45.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/45.i2c_target_intr_stress_wr.184190623
Short name T1585
Test name
Test status
Simulation time 3407414462 ps
CPU time 17 seconds
Started Sep 18 08:17:59 AM UTC 24
Finished Sep 18 08:18:17 AM UTC 24
Peak memory 586592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=184190623 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_intr_stress
_wr.184190623
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/45.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/45.i2c_target_nack_acqfull.1861409497
Short name T1592
Test name
Test status
Simulation time 3626580002 ps
CPU time 3.54 seconds
Started Sep 18 08:18:14 AM UTC 24
Finished Sep 18 08:18:18 AM UTC 24
Peak memory 225816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1861409
497 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_nack_acqfull.1861409497
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/45.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/45.i2c_target_nack_acqfull_addr.3033850131
Short name T1593
Test name
Test status
Simulation time 1767669953 ps
CPU time 3.69 seconds
Started Sep 18 08:18:14 AM UTC 24
Finished Sep 18 08:18:18 AM UTC 24
Peak memory 215264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3033850
131 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_nack_acqfull_ad
dr.3033850131
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/45.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/45.i2c_target_nack_txstretch.3880484183
Short name T1589
Test name
Test status
Simulation time 1094580775 ps
CPU time 2.31 seconds
Started Sep 18 08:18:14 AM UTC 24
Finished Sep 18 08:18:17 AM UTC 24
Peak memory 232356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3880484
183 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_nack_txstretch.3880484183
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/45.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/45.i2c_target_perf.2195587531
Short name T1579
Test name
Test status
Simulation time 4981418606 ps
CPU time 5.16 seconds
Started Sep 18 08:18:07 AM UTC 24
Finished Sep 18 08:18:13 AM UTC 24
Peak memory 231832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2195587
531 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_perf.2195587531
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/45.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/45.i2c_target_smbus_maxlen.2182402361
Short name T1590
Test name
Test status
Simulation time 1681306004 ps
CPU time 4.01 seconds
Started Sep 18 08:18:13 AM UTC 24
Finished Sep 18 08:18:18 AM UTC 24
Peak memory 215220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2182402
361 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_smbus_maxlen.2182402361
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/45.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/45.i2c_target_smoke.3210022452
Short name T1600
Test name
Test status
Simulation time 4797370285 ps
CPU time 36.6 seconds
Started Sep 18 08:17:53 AM UTC 24
Finished Sep 18 08:18:31 AM UTC 24
Peak memory 225816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3210022452 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_smoke.3210022452
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/45.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/45.i2c_target_stress_all.3316202628
Short name T1690
Test name
Test status
Simulation time 17641618352 ps
CPU time 131.54 seconds
Started Sep 18 08:18:07 AM UTC 24
Finished Sep 18 08:20:21 AM UTC 24
Peak memory 1334164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=331620
2628 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_stress_all.3316202628
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/45.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/45.i2c_target_stress_rd.131697275
Short name T1575
Test name
Test status
Simulation time 9686513576 ps
CPU time 11.57 seconds
Started Sep 18 08:17:55 AM UTC 24
Finished Sep 18 08:18:08 AM UTC 24
Peak memory 231720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=131697275 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_stress_rd.131697275
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/45.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/45.i2c_target_stress_wr.3432389568
Short name T1733
Test name
Test status
Simulation time 33317332906 ps
CPU time 253.64 seconds
Started Sep 18 08:17:54 AM UTC 24
Finished Sep 18 08:22:11 AM UTC 24
Peak memory 3541776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3432389568 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_stress_wr.3432389568
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/45.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/45.i2c_target_stretch.1498494228
Short name T1586
Test name
Test status
Simulation time 1845737755 ps
CPU time 19.11 seconds
Started Sep 18 08:17:56 AM UTC 24
Finished Sep 18 08:18:17 AM UTC 24
Peak memory 416792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1498494228 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_stretch.1498494228
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/45.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/45.i2c_target_timeout.37965878
Short name T1576
Test name
Test status
Simulation time 10991308149 ps
CPU time 8.15 seconds
Started Sep 18 08:18:02 AM UTC 24
Finished Sep 18 08:18:11 AM UTC 24
Peak memory 231908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3796587
8 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_timeout.37965878
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/45.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/45.i2c_target_tx_stretch_ctrl.3674497666
Short name T1584
Test name
Test status
Simulation time 114384652 ps
CPU time 2.89 seconds
Started Sep 18 08:18:12 AM UTC 24
Finished Sep 18 08:18:15 AM UTC 24
Peak memory 215260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3674497
666 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_tx_stretch_ctrl.3674497666
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/45.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/46.i2c_alert_test.2464472347
Short name T1618
Test name
Test status
Simulation time 17160542 ps
CPU time 1 seconds
Started Sep 18 08:19:03 AM UTC 24
Finished Sep 18 08:19:05 AM UTC 24
Peak memory 214840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2464472347 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_alert_test.2464472347
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/46.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/46.i2c_host_error_intr.3757917388
Short name T1596
Test name
Test status
Simulation time 372909627 ps
CPU time 2.63 seconds
Started Sep 18 08:18:20 AM UTC 24
Finished Sep 18 08:18:23 AM UTC 24
Peak memory 225720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3757917388 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 46.i2c_host_error_intr.3757917388
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/46.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_fmt_empty.2209803340
Short name T1601
Test name
Test status
Simulation time 278153802 ps
CPU time 17.24 seconds
Started Sep 18 08:18:17 AM UTC 24
Finished Sep 18 08:18:36 AM UTC 24
Peak memory 270992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2209803340 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_fmt_empty.2209803340
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/46.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_full.4225294326
Short name T1696
Test name
Test status
Simulation time 9224343971 ps
CPU time 129.75 seconds
Started Sep 18 08:18:18 AM UTC 24
Finished Sep 18 08:20:30 AM UTC 24
Peak memory 504616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4225294326 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_full.4225294326
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/46.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_overflow.2605885335
Short name T1662
Test name
Test status
Simulation time 10779353476 ps
CPU time 90.49 seconds
Started Sep 18 08:18:17 AM UTC 24
Finished Sep 18 08:19:50 AM UTC 24
Peak memory 791404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2605885335 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_overflow.2605885335
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/46.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_reset_fmt.2271144721
Short name T1594
Test name
Test status
Simulation time 485474676 ps
CPU time 1.3 seconds
Started Sep 18 08:18:17 AM UTC 24
Finished Sep 18 08:18:19 AM UTC 24
Peak memory 214900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2271144721 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_fmt.2271144721
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/46.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_reset_rx.430476427
Short name T1597
Test name
Test status
Simulation time 365321789 ps
CPU time 6.73 seconds
Started Sep 18 08:18:17 AM UTC 24
Finished Sep 18 08:18:25 AM UTC 24
Peak memory 215320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=430476427 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_rx.430476427
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/46.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_watermark.2958809695
Short name T1675
Test name
Test status
Simulation time 5117497786 ps
CPU time 111.35 seconds
Started Sep 18 08:18:16 AM UTC 24
Finished Sep 18 08:20:10 AM UTC 24
Peak memory 1397520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2958809695 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_watermark.2958809695
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/46.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/46.i2c_host_may_nack.867112045
Short name T258
Test name
Test status
Simulation time 1518031063 ps
CPU time 15.84 seconds
Started Sep 18 08:18:50 AM UTC 24
Finished Sep 18 08:19:07 AM UTC 24
Peak memory 215192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=867112045 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 46.i2c_host_may_nack.867112045
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/46.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/46.i2c_host_mode_toggle.1989800769
Short name T1608
Test name
Test status
Simulation time 834881583 ps
CPU time 2.03 seconds
Started Sep 18 08:18:46 AM UTC 24
Finished Sep 18 08:18:49 AM UTC 24
Peak memory 227692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1989800769 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_mode_toggle.1989800769
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/46.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/46.i2c_host_override.1914205176
Short name T1591
Test name
Test status
Simulation time 27547433 ps
CPU time 0.91 seconds
Started Sep 18 08:18:16 AM UTC 24
Finished Sep 18 08:18:18 AM UTC 24
Peak memory 214112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1914205176 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.i2c_host_override.1914205176
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/46.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/46.i2c_host_perf.2918536041
Short name T1616
Test name
Test status
Simulation time 27223562554 ps
CPU time 63.43 seconds
Started Sep 18 08:18:18 AM UTC 24
Finished Sep 18 08:19:24 AM UTC 24
Peak memory 236248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2918536041 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 46.i2c_host_perf.2918536041
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/46.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/46.i2c_host_perf_precise.617797137
Short name T1595
Test name
Test status
Simulation time 44101437 ps
CPU time 1.59 seconds
Started Sep 18 08:18:18 AM UTC 24
Finished Sep 18 08:18:21 AM UTC 24
Peak memory 234868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=617797137 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_perf_precise.617797137
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/46.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/46.i2c_host_smoke.914712499
Short name T1632
Test name
Test status
Simulation time 11388911605 ps
CPU time 62.82 seconds
Started Sep 18 08:18:15 AM UTC 24
Finished Sep 18 08:19:19 AM UTC 24
Peak memory 308004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=914712499 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 46.i2c_host_smoke.914712499
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/46.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/46.i2c_host_stretch_timeout.1885319257
Short name T1617
Test name
Test status
Simulation time 5814070155 ps
CPU time 41.96 seconds
Started Sep 18 08:18:20 AM UTC 24
Finished Sep 18 08:19:03 AM UTC 24
Peak memory 225552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1885319257 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_stretch_timeout.1885319257
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/46.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/46.i2c_target_bad_addr.1030417099
Short name T1610
Test name
Test status
Simulation time 878154735 ps
CPU time 8.64 seconds
Started Sep 18 08:18:44 AM UTC 24
Finished Sep 18 08:18:53 AM UTC 24
Peak memory 225764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=1030417099 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_bad_ad
dr.1030417099
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/46.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/46.i2c_target_fifo_reset_acq.1339604410
Short name T1605
Test name
Test status
Simulation time 283309574 ps
CPU time 1.55 seconds
Started Sep 18 08:18:40 AM UTC 24
Finished Sep 18 08:18:43 AM UTC 24
Peak memory 214740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1339604
410 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_fifo_reset_acq.1339604410
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/46.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/46.i2c_target_fifo_reset_tx.4083139091
Short name T1606
Test name
Test status
Simulation time 367419630 ps
CPU time 1.58 seconds
Started Sep 18 08:18:41 AM UTC 24
Finished Sep 18 08:18:44 AM UTC 24
Peak memory 214904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4083139
091 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_fifo_reset_tx.4083139091
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/46.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/46.i2c_target_fifo_watermarks_acq.1527165650
Short name T1614
Test name
Test status
Simulation time 1009484779 ps
CPU time 5.7 seconds
Started Sep 18 08:18:53 AM UTC 24
Finished Sep 18 08:19:00 AM UTC 24
Peak memory 215464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1527165
650 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_fifo_watermar
ks_acq.1527165650
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/46.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/46.i2c_target_fifo_watermarks_tx.3186677917
Short name T1612
Test name
Test status
Simulation time 208583180 ps
CPU time 1.48 seconds
Started Sep 18 08:18:54 AM UTC 24
Finished Sep 18 08:18:57 AM UTC 24
Peak memory 214852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3186677
917 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_fifo_watermark
s_tx.3186677917
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/46.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/46.i2c_target_intr_smoke.868968797
Short name T1607
Test name
Test status
Simulation time 1108390872 ps
CPU time 11.81 seconds
Started Sep 18 08:18:31 AM UTC 24
Finished Sep 18 08:18:45 AM UTC 24
Peak memory 232296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=868968
797 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_intr_smoke.868968797
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/46.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/46.i2c_target_intr_stress_wr.2421983031
Short name T1706
Test name
Test status
Simulation time 20816004023 ps
CPU time 127.71 seconds
Started Sep 18 08:18:32 AM UTC 24
Finished Sep 18 08:20:43 AM UTC 24
Peak memory 2509592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2421983031 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_intr_stres
s_wr.2421983031
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/46.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/46.i2c_target_nack_acqfull.432570046
Short name T1620
Test name
Test status
Simulation time 612608464 ps
CPU time 4.69 seconds
Started Sep 18 08:19:00 AM UTC 24
Finished Sep 18 08:19:06 AM UTC 24
Peak memory 225664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4325700
46 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_nack_acqfull.432570046
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/46.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/46.i2c_target_nack_acqfull_addr.1615869732
Short name T1621
Test name
Test status
Simulation time 519369859 ps
CPU time 5.26 seconds
Started Sep 18 08:19:00 AM UTC 24
Finished Sep 18 08:19:07 AM UTC 24
Peak memory 215144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1615869
732 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_nack_acqfull_ad
dr.1615869732
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/46.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/46.i2c_target_nack_txstretch.1833811280
Short name T1619
Test name
Test status
Simulation time 516181375 ps
CPU time 2.39 seconds
Started Sep 18 08:19:02 AM UTC 24
Finished Sep 18 08:19:06 AM UTC 24
Peak memory 232348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1833811
280 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_nack_txstretch.1833811280
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/46.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/46.i2c_target_perf.3072803186
Short name T1609
Test name
Test status
Simulation time 2085200392 ps
CPU time 8.48 seconds
Started Sep 18 08:18:41 AM UTC 24
Finished Sep 18 08:18:52 AM UTC 24
Peak memory 242604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3072803
186 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_perf.3072803186
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/46.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/46.i2c_target_smbus_maxlen.2872776953
Short name T1615
Test name
Test status
Simulation time 1499870910 ps
CPU time 3.63 seconds
Started Sep 18 08:18:57 AM UTC 24
Finished Sep 18 08:19:02 AM UTC 24
Peak memory 215096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2872776
953 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_smbus_maxlen.2872776953
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/46.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/46.i2c_target_smoke.1929093613
Short name T1613
Test name
Test status
Simulation time 1126618534 ps
CPU time 37.38 seconds
Started Sep 18 08:18:21 AM UTC 24
Finished Sep 18 08:18:59 AM UTC 24
Peak memory 225624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1929093613 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_smoke.1929093613
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/46.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/46.i2c_target_stress_all.3643739455
Short name T1734
Test name
Test status
Simulation time 48545634934 ps
CPU time 233.54 seconds
Started Sep 18 08:18:44 AM UTC 24
Finished Sep 18 08:22:40 AM UTC 24
Peak memory 2218848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=364373
9455 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_stress_all.3643739455
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/46.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/46.i2c_target_stress_rd.900355198
Short name T1599
Test name
Test status
Simulation time 1356451928 ps
CPU time 6.31 seconds
Started Sep 18 08:18:24 AM UTC 24
Finished Sep 18 08:18:31 AM UTC 24
Peak memory 215308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=900355198 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_stress_rd.900355198
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/46.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/46.i2c_target_stress_wr.2150715882
Short name T1633
Test name
Test status
Simulation time 38421260873 ps
CPU time 56.34 seconds
Started Sep 18 08:18:22 AM UTC 24
Finished Sep 18 08:19:20 AM UTC 24
Peak memory 1231640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2150715882 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_stress_wr.2150715882
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/46.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/46.i2c_target_stretch.3837053808
Short name T1626
Test name
Test status
Simulation time 2660185665 ps
CPU time 44.58 seconds
Started Sep 18 08:18:26 AM UTC 24
Finished Sep 18 08:19:12 AM UTC 24
Peak memory 811868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3837053808 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_stretch.3837053808
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/46.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/46.i2c_target_timeout.4201079020
Short name T1604
Test name
Test status
Simulation time 1457761718 ps
CPU time 9.38 seconds
Started Sep 18 08:18:32 AM UTC 24
Finished Sep 18 08:18:43 AM UTC 24
Peak memory 225568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4201079
020 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_timeout.4201079020
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/46.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/46.i2c_target_tx_stretch_ctrl.2063003251
Short name T1622
Test name
Test status
Simulation time 604477443 ps
CPU time 12.29 seconds
Started Sep 18 08:18:54 AM UTC 24
Finished Sep 18 08:19:08 AM UTC 24
Peak memory 215320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2063003
251 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_tx_stretch_ctrl.2063003251
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/46.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/47.i2c_alert_test.1394096906
Short name T1652
Test name
Test status
Simulation time 54605696 ps
CPU time 0.97 seconds
Started Sep 18 08:19:39 AM UTC 24
Finished Sep 18 08:19:41 AM UTC 24
Peak memory 214900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1394096906 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_alert_test.1394096906
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/47.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/47.i2c_host_error_intr.2304236990
Short name T1569
Test name
Test status
Simulation time 122597603 ps
CPU time 6.28 seconds
Started Sep 18 08:19:14 AM UTC 24
Finished Sep 18 08:19:22 AM UTC 24
Peak memory 242752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2304236990 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 47.i2c_host_error_intr.2304236990
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/47.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_fmt_empty.2366356533
Short name T1628
Test name
Test status
Simulation time 281579516 ps
CPU time 6.48 seconds
Started Sep 18 08:19:08 AM UTC 24
Finished Sep 18 08:19:15 AM UTC 24
Peak memory 271004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2366356533 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_fmt_empty.2366356533
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/47.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_full.2548904966
Short name T1732
Test name
Test status
Simulation time 3091459481 ps
CPU time 165.69 seconds
Started Sep 18 08:19:10 AM UTC 24
Finished Sep 18 08:21:58 AM UTC 24
Peak memory 494508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2548904966 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_full.2548904966
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/47.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_overflow.773260878
Short name T1698
Test name
Test status
Simulation time 10523382259 ps
CPU time 84.39 seconds
Started Sep 18 08:19:07 AM UTC 24
Finished Sep 18 08:20:33 AM UTC 24
Peak memory 887588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=773260878 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_overflow.773260878
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/47.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_reset_fmt.3683581726
Short name T1625
Test name
Test status
Simulation time 178971153 ps
CPU time 1.92 seconds
Started Sep 18 08:19:08 AM UTC 24
Finished Sep 18 08:19:11 AM UTC 24
Peak memory 214920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3683581726 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_fmt.3683581726
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/47.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_reset_rx.848457746
Short name T1629
Test name
Test status
Simulation time 164827778 ps
CPU time 5.79 seconds
Started Sep 18 08:19:09 AM UTC 24
Finished Sep 18 08:19:16 AM UTC 24
Peak memory 215264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=848457746 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_rx.848457746
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/47.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_watermark.1926846812
Short name T1722
Test name
Test status
Simulation time 7403996784 ps
CPU time 106.96 seconds
Started Sep 18 08:19:07 AM UTC 24
Finished Sep 18 08:20:56 AM UTC 24
Peak memory 1178468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1926846812 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_watermark.1926846812
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/47.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/47.i2c_host_may_nack.3671578565
Short name T1649
Test name
Test status
Simulation time 489592432 ps
CPU time 6.35 seconds
Started Sep 18 08:19:32 AM UTC 24
Finished Sep 18 08:19:40 AM UTC 24
Peak memory 215208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3671578565 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.i2c_host_may_nack.3671578565
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/47.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/47.i2c_host_mode_toggle.85492052
Short name T1639
Test name
Test status
Simulation time 236802879 ps
CPU time 2.19 seconds
Started Sep 18 08:19:31 AM UTC 24
Finished Sep 18 08:19:34 AM UTC 24
Peak memory 232100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=85492052 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ho
st_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 47.i2c_host_mode_toggle.85492052
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/47.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/47.i2c_host_override.2762597599
Short name T1623
Test name
Test status
Simulation time 83435939 ps
CPU time 1.07 seconds
Started Sep 18 08:19:07 AM UTC 24
Finished Sep 18 08:19:09 AM UTC 24
Peak memory 214112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2762597599 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.i2c_host_override.2762597599
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/47.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/47.i2c_host_perf.2711420973
Short name T1573
Test name
Test status
Simulation time 2304999746 ps
CPU time 12.02 seconds
Started Sep 18 08:19:11 AM UTC 24
Finished Sep 18 08:19:25 AM UTC 24
Peak memory 269288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2711420973 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 47.i2c_host_perf.2711420973
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/47.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/47.i2c_host_perf_precise.1294752913
Short name T1630
Test name
Test status
Simulation time 115997720 ps
CPU time 3.25 seconds
Started Sep 18 08:19:11 AM UTC 24
Finished Sep 18 08:19:16 AM UTC 24
Peak memory 215248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1294752913 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_perf_precise.1294752913
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/47.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/47.i2c_host_smoke.3560201153
Short name T1660
Test name
Test status
Simulation time 2021593549 ps
CPU time 43.44 seconds
Started Sep 18 08:19:03 AM UTC 24
Finished Sep 18 08:19:48 AM UTC 24
Peak memory 361320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3560201153 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.i2c_host_smoke.3560201153
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/47.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/47.i2c_host_stretch_timeout.3037731503
Short name T1663
Test name
Test status
Simulation time 641609552 ps
CPU time 35.26 seconds
Started Sep 18 08:19:13 AM UTC 24
Finished Sep 18 08:19:50 AM UTC 24
Peak memory 225572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3037731503 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_stretch_timeout.3037731503
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/47.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/47.i2c_target_bad_addr.2434451162
Short name T1638
Test name
Test status
Simulation time 2559760374 ps
CPU time 2.91 seconds
Started Sep 18 08:19:28 AM UTC 24
Finished Sep 18 08:19:32 AM UTC 24
Peak memory 225764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=2434451162 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_bad_ad
dr.2434451162
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/47.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/47.i2c_target_fifo_reset_acq.2411612687
Short name T1634
Test name
Test status
Simulation time 355080970 ps
CPU time 2.46 seconds
Started Sep 18 08:19:24 AM UTC 24
Finished Sep 18 08:19:27 AM UTC 24
Peak memory 215112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2411612
687 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_fifo_reset_acq.2411612687
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/47.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/47.i2c_target_fifo_reset_tx.2376271578
Short name T1635
Test name
Test status
Simulation time 351858805 ps
CPU time 2.1 seconds
Started Sep 18 08:19:26 AM UTC 24
Finished Sep 18 08:19:29 AM UTC 24
Peak memory 215252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2376271
578 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_fifo_reset_tx.2376271578
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/47.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/47.i2c_target_fifo_watermarks_acq.710429833
Short name T1645
Test name
Test status
Simulation time 486754073 ps
CPU time 3.57 seconds
Started Sep 18 08:19:34 AM UTC 24
Finished Sep 18 08:19:38 AM UTC 24
Peak memory 215252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7104298
33 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_fifo_watermark
s_acq.710429833
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/47.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/47.i2c_target_fifo_watermarks_tx.3721662417
Short name T1646
Test name
Test status
Simulation time 244910329 ps
CPU time 1.82 seconds
Started Sep 18 08:19:36 AM UTC 24
Finished Sep 18 08:19:38 AM UTC 24
Peak memory 214848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3721662
417 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_fifo_watermark
s_tx.3721662417
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/47.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/47.i2c_target_intr_smoke.1217035078
Short name T1636
Test name
Test status
Simulation time 1311368459 ps
CPU time 10.08 seconds
Started Sep 18 08:19:20 AM UTC 24
Finished Sep 18 08:19:31 AM UTC 24
Peak memory 232308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=121703
5078 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_intr_smoke.1217035078
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/47.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/47.i2c_target_intr_stress_wr.2685260429
Short name T1657
Test name
Test status
Simulation time 14483308058 ps
CPU time 22.37 seconds
Started Sep 18 08:19:21 AM UTC 24
Finished Sep 18 08:19:44 AM UTC 24
Peak memory 510792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2685260429 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_intr_stres
s_wr.2685260429
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/47.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/47.i2c_target_nack_acqfull.485990444
Short name T1653
Test name
Test status
Simulation time 955389250 ps
CPU time 4.97 seconds
Started Sep 18 08:19:36 AM UTC 24
Finished Sep 18 08:19:42 AM UTC 24
Peak memory 225500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4859904
44 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_nack_acqfull.485990444
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/47.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/47.i2c_target_nack_acqfull_addr.2022300224
Short name T1655
Test name
Test status
Simulation time 1872333971 ps
CPU time 4.6 seconds
Started Sep 18 08:19:37 AM UTC 24
Finished Sep 18 08:19:42 AM UTC 24
Peak memory 215092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2022300
224 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_nack_acqfull_ad
dr.2022300224
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/47.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/47.i2c_target_nack_txstretch.341438714
Short name T1648
Test name
Test status
Simulation time 486424319 ps
CPU time 1.99 seconds
Started Sep 18 08:19:37 AM UTC 24
Finished Sep 18 08:19:40 AM UTC 24
Peak memory 231344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3414387
14 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_nack_txstretch.341438714
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/47.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/47.i2c_target_perf.1049814964
Short name T1643
Test name
Test status
Simulation time 1654968817 ps
CPU time 6.26 seconds
Started Sep 18 08:19:28 AM UTC 24
Finished Sep 18 08:19:35 AM UTC 24
Peak memory 225696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1049814
964 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_perf.1049814964
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/47.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/47.i2c_target_smbus_maxlen.3366468731
Short name T1647
Test name
Test status
Simulation time 1414336412 ps
CPU time 3.04 seconds
Started Sep 18 08:19:36 AM UTC 24
Finished Sep 18 08:19:40 AM UTC 24
Peak memory 215000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3366468
731 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_smbus_maxlen.3366468731
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/47.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/47.i2c_target_smoke.4009292703
Short name T1644
Test name
Test status
Simulation time 1281975506 ps
CPU time 19 seconds
Started Sep 18 08:19:16 AM UTC 24
Finished Sep 18 08:19:36 AM UTC 24
Peak memory 225752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4009292703 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_smoke.4009292703
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/47.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/47.i2c_target_stress_all.3419612986
Short name T1728
Test name
Test status
Simulation time 52903309311 ps
CPU time 126.28 seconds
Started Sep 18 08:19:28 AM UTC 24
Finished Sep 18 08:21:37 AM UTC 24
Peak memory 1192752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=341961
2986 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_stress_all.3419612986
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/47.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/47.i2c_target_stress_rd.763274395
Short name T1641
Test name
Test status
Simulation time 836831937 ps
CPU time 16.16 seconds
Started Sep 18 08:19:18 AM UTC 24
Finished Sep 18 08:19:35 AM UTC 24
Peak memory 231708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=763274395 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_stress_rd.763274395
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/47.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/47.i2c_target_stress_wr.621995680
Short name T1640
Test name
Test status
Simulation time 15495436461 ps
CPU time 16.09 seconds
Started Sep 18 08:19:18 AM UTC 24
Finished Sep 18 08:19:35 AM UTC 24
Peak memory 215568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=621995680 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_stress_wr.621995680
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/47.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/47.i2c_target_timeout.1410816278
Short name T1642
Test name
Test status
Simulation time 1333612781 ps
CPU time 11 seconds
Started Sep 18 08:19:23 AM UTC 24
Finished Sep 18 08:19:35 AM UTC 24
Peak memory 225552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1410816
278 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_timeout.1410816278
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/47.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/47.i2c_target_tx_stretch_ctrl.3107696181
Short name T1651
Test name
Test status
Simulation time 111165141 ps
CPU time 3.93 seconds
Started Sep 18 08:19:36 AM UTC 24
Finished Sep 18 08:19:41 AM UTC 24
Peak memory 215084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3107696
181 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_tx_stretch_ctrl.3107696181
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/47.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/48.i2c_alert_test.3243693400
Short name T1683
Test name
Test status
Simulation time 18435205 ps
CPU time 1.04 seconds
Started Sep 18 08:20:14 AM UTC 24
Finished Sep 18 08:20:16 AM UTC 24
Peak memory 214840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3243693400 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_alert_test.3243693400
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/48.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/48.i2c_host_error_intr.3355314275
Short name T1661
Test name
Test status
Simulation time 431782341 ps
CPU time 3.5 seconds
Started Sep 18 08:19:45 AM UTC 24
Finished Sep 18 08:19:49 AM UTC 24
Peak memory 225648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3355314275 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 48.i2c_host_error_intr.3355314275
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/48.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_fmt_empty.2818793285
Short name T1664
Test name
Test status
Simulation time 2040452373 ps
CPU time 12.17 seconds
Started Sep 18 08:19:41 AM UTC 24
Finished Sep 18 08:19:55 AM UTC 24
Peak memory 295644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2818793285 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_fmt_empty.2818793285
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/48.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_full.1158493179
Short name T1725
Test name
Test status
Simulation time 3215679239 ps
CPU time 100.21 seconds
Started Sep 18 08:19:43 AM UTC 24
Finished Sep 18 08:21:25 AM UTC 24
Peak memory 637924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1158493179 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_full.1158493179
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/48.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_overflow.3170945909
Short name T1707
Test name
Test status
Simulation time 1940453760 ps
CPU time 60.85 seconds
Started Sep 18 08:19:41 AM UTC 24
Finished Sep 18 08:20:44 AM UTC 24
Peak memory 703100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3170945909 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_overflow.3170945909
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/48.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_reset_fmt.2257024883
Short name T1656
Test name
Test status
Simulation time 272249831 ps
CPU time 1.45 seconds
Started Sep 18 08:19:41 AM UTC 24
Finished Sep 18 08:19:44 AM UTC 24
Peak memory 214816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2257024883 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_fmt.2257024883
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/48.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_reset_rx.2293379080
Short name T1658
Test name
Test status
Simulation time 136037222 ps
CPU time 3.56 seconds
Started Sep 18 08:19:41 AM UTC 24
Finished Sep 18 08:19:46 AM UTC 24
Peak memory 234272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2293379080 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_rx.2293379080
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/48.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_watermark.2936971573
Short name T1736
Test name
Test status
Simulation time 3640145481 ps
CPU time 195.21 seconds
Started Sep 18 08:19:40 AM UTC 24
Finished Sep 18 08:22:58 AM UTC 24
Peak memory 1127204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2936971573 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_watermark.2936971573
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/48.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/48.i2c_host_may_nack.1092551017
Short name T1681
Test name
Test status
Simulation time 215261697 ps
CPU time 4.56 seconds
Started Sep 18 08:20:08 AM UTC 24
Finished Sep 18 08:20:14 AM UTC 24
Peak memory 215332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1092551017 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.i2c_host_may_nack.1092551017
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/48.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/48.i2c_host_mode_toggle.2790404141
Short name T263
Test name
Test status
Simulation time 174731808 ps
CPU time 3.6 seconds
Started Sep 18 08:20:05 AM UTC 24
Finished Sep 18 08:20:09 AM UTC 24
Peak memory 215404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2790404141 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_mode_toggle.2790404141
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/48.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/48.i2c_host_override.21743610
Short name T1654
Test name
Test status
Simulation time 51722116 ps
CPU time 1.05 seconds
Started Sep 18 08:19:40 AM UTC 24
Finished Sep 18 08:19:42 AM UTC 24
Peak memory 214104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21743610 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ho
st_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 48.i2c_host_override.21743610
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/48.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/48.i2c_host_perf.1290652133
Short name T1744
Test name
Test status
Simulation time 74009986666 ps
CPU time 380.59 seconds
Started Sep 18 08:19:43 AM UTC 24
Finished Sep 18 08:26:08 AM UTC 24
Peak memory 215528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1290652133 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 48.i2c_host_perf.1290652133
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/48.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/48.i2c_host_perf_precise.1746440733
Short name T1659
Test name
Test status
Simulation time 160044612 ps
CPU time 2.5 seconds
Started Sep 18 08:19:44 AM UTC 24
Finished Sep 18 08:19:47 AM UTC 24
Peak memory 233628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1746440733 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_perf_precise.1746440733
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/48.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/48.i2c_host_smoke.2497509820
Short name T1677
Test name
Test status
Simulation time 1663572086 ps
CPU time 31.74 seconds
Started Sep 18 08:19:39 AM UTC 24
Finished Sep 18 08:20:12 AM UTC 24
Peak memory 369384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2497509820 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.i2c_host_smoke.2497509820
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/48.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/48.i2c_host_stretch_timeout.1139411330
Short name T1668
Test name
Test status
Simulation time 762706415 ps
CPU time 16.69 seconds
Started Sep 18 08:19:44 AM UTC 24
Finished Sep 18 08:20:01 AM UTC 24
Peak memory 232172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1139411330 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_stretch_timeout.1139411330
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/48.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/48.i2c_target_bad_addr.3695585925
Short name T1672
Test name
Test status
Simulation time 1245472893 ps
CPU time 4.31 seconds
Started Sep 18 08:20:03 AM UTC 24
Finished Sep 18 08:20:08 AM UTC 24
Peak memory 217384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=3695585925 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_bad_ad
dr.3695585925
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/48.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/48.i2c_target_fifo_reset_acq.1787343698
Short name T1669
Test name
Test status
Simulation time 238450030 ps
CPU time 2.21 seconds
Started Sep 18 08:19:58 AM UTC 24
Finished Sep 18 08:20:02 AM UTC 24
Peak memory 215112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1787343
698 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_fifo_reset_acq.1787343698
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/48.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/48.i2c_target_fifo_reset_tx.3762644420
Short name T1667
Test name
Test status
Simulation time 232776349 ps
CPU time 1.58 seconds
Started Sep 18 08:19:59 AM UTC 24
Finished Sep 18 08:20:01 AM UTC 24
Peak memory 214904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3762644
420 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_fifo_reset_tx.3762644420
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/48.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/48.i2c_target_fifo_watermarks_acq.2689891561
Short name T1679
Test name
Test status
Simulation time 556802870 ps
CPU time 2.46 seconds
Started Sep 18 08:20:09 AM UTC 24
Finished Sep 18 08:20:13 AM UTC 24
Peak memory 215112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2689891
561 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_fifo_watermar
ks_acq.2689891561
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/48.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/48.i2c_target_fifo_watermarks_tx.1459667659
Short name T1678
Test name
Test status
Simulation time 136482256 ps
CPU time 2.35 seconds
Started Sep 18 08:20:09 AM UTC 24
Finished Sep 18 08:20:12 AM UTC 24
Peak memory 215308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1459667
659 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_fifo_watermark
s_tx.1459667659
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/48.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/48.i2c_target_intr_smoke.837759739
Short name T1666
Test name
Test status
Simulation time 658585906 ps
CPU time 8.23 seconds
Started Sep 18 08:19:50 AM UTC 24
Finished Sep 18 08:19:59 AM UTC 24
Peak memory 231960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=837759
739 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_intr_smoke.837759739
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/48.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/48.i2c_target_intr_stress_wr.2700552199
Short name T1665
Test name
Test status
Simulation time 5582363321 ps
CPU time 6.63 seconds
Started Sep 18 08:19:50 AM UTC 24
Finished Sep 18 08:19:58 AM UTC 24
Peak memory 215512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2700552199 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_intr_stres
s_wr.2700552199
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/48.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/48.i2c_target_nack_acqfull.833364833
Short name T1686
Test name
Test status
Simulation time 2552908484 ps
CPU time 5.69 seconds
Started Sep 18 08:20:10 AM UTC 24
Finished Sep 18 08:20:17 AM UTC 24
Peak memory 225620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8333648
33 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_nack_acqfull.833364833
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/48.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/48.i2c_target_nack_acqfull_addr.1986155763
Short name T1685
Test name
Test status
Simulation time 1947062815 ps
CPU time 4.08 seconds
Started Sep 18 08:20:12 AM UTC 24
Finished Sep 18 08:20:17 AM UTC 24
Peak memory 215260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1986155
763 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_nack_acqfull_ad
dr.1986155763
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/48.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/48.i2c_target_perf.2928099908
Short name T1673
Test name
Test status
Simulation time 699502224 ps
CPU time 7.13 seconds
Started Sep 18 08:20:01 AM UTC 24
Finished Sep 18 08:20:09 AM UTC 24
Peak memory 229592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2928099
908 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_perf.2928099908
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/48.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/48.i2c_target_smbus_maxlen.1401100702
Short name T1682
Test name
Test status
Simulation time 1640741451 ps
CPU time 2.7 seconds
Started Sep 18 08:20:10 AM UTC 24
Finished Sep 18 08:20:14 AM UTC 24
Peak memory 215096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1401100
702 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_smbus_maxlen.1401100702
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/48.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/48.i2c_target_smoke.822739442
Short name T1670
Test name
Test status
Simulation time 7085640140 ps
CPU time 15.93 seconds
Started Sep 18 08:19:47 AM UTC 24
Finished Sep 18 08:20:04 AM UTC 24
Peak memory 229912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=822739442 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_smoke.822739442
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/48.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/48.i2c_target_stress_all.3752618790
Short name T1746
Test name
Test status
Simulation time 53118493518 ps
CPU time 396.86 seconds
Started Sep 18 08:20:02 AM UTC 24
Finished Sep 18 08:26:43 AM UTC 24
Peak memory 4099100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=375261
8790 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_stress_all.3752618790
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/48.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/48.i2c_target_stress_rd.1355529494
Short name T1697
Test name
Test status
Simulation time 1981545094 ps
CPU time 40.3 seconds
Started Sep 18 08:19:49 AM UTC 24
Finished Sep 18 08:20:31 AM UTC 24
Peak memory 225560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1355529494 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_stress_rd.1355529494
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/48.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/48.i2c_target_stress_wr.1108755646
Short name T1700
Test name
Test status
Simulation time 15834850627 ps
CPU time 45.68 seconds
Started Sep 18 08:19:48 AM UTC 24
Finished Sep 18 08:20:35 AM UTC 24
Peak memory 215444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1108755646 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_stress_wr.1108755646
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/48.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/48.i2c_target_stretch.4096187011
Short name T1671
Test name
Test status
Simulation time 3149601562 ps
CPU time 15.61 seconds
Started Sep 18 08:19:50 AM UTC 24
Finished Sep 18 08:20:07 AM UTC 24
Peak memory 396260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4096187011 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_stretch.4096187011
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/48.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/48.i2c_target_timeout.3189149752
Short name T1674
Test name
Test status
Simulation time 5561868663 ps
CPU time 12.77 seconds
Started Sep 18 08:19:55 AM UTC 24
Finished Sep 18 08:20:09 AM UTC 24
Peak memory 225688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3189149
752 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_timeout.3189149752
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/48.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/48.i2c_target_tx_stretch_ctrl.3554581187
Short name T1688
Test name
Test status
Simulation time 312947842 ps
CPU time 7.41 seconds
Started Sep 18 08:20:10 AM UTC 24
Finished Sep 18 08:20:19 AM UTC 24
Peak memory 215244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3554581
187 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_tx_stretch_ctrl.3554581187
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/48.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/49.i2c_alert_test.3021758723
Short name T1717
Test name
Test status
Simulation time 32969536 ps
CPU time 0.85 seconds
Started Sep 18 08:20:48 AM UTC 24
Finished Sep 18 08:20:50 AM UTC 24
Peak memory 214840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3021758723 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_alert_test.3021758723
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/49.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/49.i2c_host_error_intr.57367475
Short name T1694
Test name
Test status
Simulation time 458828140 ps
CPU time 2.63 seconds
Started Sep 18 08:20:20 AM UTC 24
Finished Sep 18 08:20:24 AM UTC 24
Peak memory 225572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=57367475 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ho
st_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.i2c_host_error_intr.57367475
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/49.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_fmt_empty.30439204
Short name T1650
Test name
Test status
Simulation time 1890839983 ps
CPU time 28.27 seconds
Started Sep 18 08:20:17 AM UTC 24
Finished Sep 18 08:20:47 AM UTC 24
Peak memory 342928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=30439204 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_fmt_empty.30439204
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/49.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_full.2956806246
Short name T1737
Test name
Test status
Simulation time 2992021195 ps
CPU time 161.81 seconds
Started Sep 18 08:20:18 AM UTC 24
Finished Sep 18 08:23:03 AM UTC 24
Peak memory 473848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2956806246 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_full.2956806246
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/49.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_overflow.3075600065
Short name T1723
Test name
Test status
Simulation time 9430856118 ps
CPU time 53.38 seconds
Started Sep 18 08:20:15 AM UTC 24
Finished Sep 18 08:21:10 AM UTC 24
Peak memory 650012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3075600065 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_overflow.3075600065
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/49.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_reset_fmt.2418570022
Short name T1689
Test name
Test status
Simulation time 548758839 ps
CPU time 2.11 seconds
Started Sep 18 08:20:16 AM UTC 24
Finished Sep 18 08:20:19 AM UTC 24
Peak memory 215180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2418570022 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_fmt.2418570022
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/49.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_reset_rx.30598343
Short name T1691
Test name
Test status
Simulation time 158280561 ps
CPU time 3.69 seconds
Started Sep 18 08:20:17 AM UTC 24
Finished Sep 18 08:20:22 AM UTC 24
Peak memory 215320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=30598343 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_rx.30598343
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/49.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_watermark.3553745853
Short name T1730
Test name
Test status
Simulation time 44760693887 ps
CPU time 87.22 seconds
Started Sep 18 08:20:15 AM UTC 24
Finished Sep 18 08:21:44 AM UTC 24
Peak memory 1247964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3553745853 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_watermark.3553745853
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/49.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/49.i2c_host_may_nack.3529926816
Short name T1721
Test name
Test status
Simulation time 282221530 ps
CPU time 10.64 seconds
Started Sep 18 08:20:43 AM UTC 24
Finished Sep 18 08:20:54 AM UTC 24
Peak memory 215332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3529926816 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.i2c_host_may_nack.3529926816
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/49.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/49.i2c_host_mode_toggle.2041296793
Short name T1709
Test name
Test status
Simulation time 261726866 ps
CPU time 1.71 seconds
Started Sep 18 08:20:43 AM UTC 24
Finished Sep 18 08:20:45 AM UTC 24
Peak memory 214864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2041296793 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_mode_toggle.2041296793
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/49.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/49.i2c_host_override.3504054556
Short name T1684
Test name
Test status
Simulation time 101780728 ps
CPU time 0.97 seconds
Started Sep 18 08:20:14 AM UTC 24
Finished Sep 18 08:20:16 AM UTC 24
Peak memory 214112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3504054556 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.i2c_host_override.3504054556
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/49.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/49.i2c_host_perf.2867893641
Short name T1693
Test name
Test status
Simulation time 280949714 ps
CPU time 3.64 seconds
Started Sep 18 08:20:18 AM UTC 24
Finished Sep 18 08:20:23 AM UTC 24
Peak memory 240296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2867893641 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 49.i2c_host_perf.2867893641
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/49.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/49.i2c_host_perf_precise.115920117
Short name T1692
Test name
Test status
Simulation time 97060394 ps
CPU time 2.36 seconds
Started Sep 18 08:20:19 AM UTC 24
Finished Sep 18 08:20:23 AM UTC 24
Peak memory 215136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=115920117 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_perf_precise.115920117
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/49.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/49.i2c_host_smoke.630617414
Short name T1729
Test name
Test status
Simulation time 33287083435 ps
CPU time 84.04 seconds
Started Sep 18 08:20:14 AM UTC 24
Finished Sep 18 08:21:39 AM UTC 24
Peak memory 379668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=630617414 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 49.i2c_host_smoke.630617414
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/49.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/49.i2c_host_stretch_timeout.1250720707
Short name T1724
Test name
Test status
Simulation time 2024711236 ps
CPU time 50.19 seconds
Started Sep 18 08:20:20 AM UTC 24
Finished Sep 18 08:21:12 AM UTC 24
Peak memory 225696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1250720707 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_stretch_timeout.1250720707
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/49.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/49.i2c_target_bad_addr.2505146434
Short name T1714
Test name
Test status
Simulation time 4204194271 ps
CPU time 8.73 seconds
Started Sep 18 08:20:37 AM UTC 24
Finished Sep 18 08:20:47 AM UTC 24
Peak memory 231704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=2505146434 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_bad_ad
dr.2505146434
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/49.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/49.i2c_target_fifo_reset_acq.637702669
Short name T1701
Test name
Test status
Simulation time 154648509 ps
CPU time 1.08 seconds
Started Sep 18 08:20:34 AM UTC 24
Finished Sep 18 08:20:36 AM UTC 24
Peak memory 214848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6377026
69 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_fifo_reset_acq.637702669
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/49.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/49.i2c_target_fifo_reset_tx.1511693860
Short name T1702
Test name
Test status
Simulation time 320444395 ps
CPU time 2.08 seconds
Started Sep 18 08:20:34 AM UTC 24
Finished Sep 18 08:20:37 AM UTC 24
Peak memory 225492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1511693
860 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_fifo_reset_tx.1511693860
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/49.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/49.i2c_target_fifo_watermarks_acq.809411385
Short name T1711
Test name
Test status
Simulation time 833883035 ps
CPU time 2.32 seconds
Started Sep 18 08:20:44 AM UTC 24
Finished Sep 18 08:20:47 AM UTC 24
Peak memory 215032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8094113
85 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_fifo_watermark
s_acq.809411385
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/49.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/49.i2c_target_fifo_watermarks_tx.171853926
Short name T1712
Test name
Test status
Simulation time 154558091 ps
CPU time 2.44 seconds
Started Sep 18 08:20:44 AM UTC 24
Finished Sep 18 08:20:47 AM UTC 24
Peak memory 215120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1718539
26 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_fifo_watermarks
_tx.171853926
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/49.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/49.i2c_target_intr_smoke.2830151976
Short name T1699
Test name
Test status
Simulation time 2101567531 ps
CPU time 8.67 seconds
Started Sep 18 08:20:25 AM UTC 24
Finished Sep 18 08:20:35 AM UTC 24
Peak memory 232244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=283015
1976 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_intr_smoke.2830151976
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/49.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/49.i2c_target_intr_stress_wr.669975460
Short name T1708
Test name
Test status
Simulation time 4071498777 ps
CPU time 14.71 seconds
Started Sep 18 08:20:28 AM UTC 24
Finished Sep 18 08:20:44 AM UTC 24
Peak memory 215308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=669975460 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_intr_stress
_wr.669975460
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/49.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/49.i2c_target_nack_acqfull.3732767364
Short name T1720
Test name
Test status
Simulation time 1860651206 ps
CPU time 4.15 seconds
Started Sep 18 08:20:46 AM UTC 24
Finished Sep 18 08:20:51 AM UTC 24
Peak memory 225536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3732767
364 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_nack_acqfull.3732767364
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/49.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/49.i2c_target_nack_acqfull_addr.1678430564
Short name T1716
Test name
Test status
Simulation time 2188745506 ps
CPU time 2.63 seconds
Started Sep 18 08:20:46 AM UTC 24
Finished Sep 18 08:20:50 AM UTC 24
Peak memory 215380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1678430
564 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_nack_acqfull_ad
dr.1678430564
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/49.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/49.i2c_target_nack_txstretch.4195320409
Short name T1719
Test name
Test status
Simulation time 571267323 ps
CPU time 2.49 seconds
Started Sep 18 08:20:47 AM UTC 24
Finished Sep 18 08:20:51 AM UTC 24
Peak memory 232148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4195320
409 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_nack_txstretch.4195320409
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/49.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/49.i2c_target_perf.2110505491
Short name T1710
Test name
Test status
Simulation time 3114942774 ps
CPU time 8.98 seconds
Started Sep 18 08:20:35 AM UTC 24
Finished Sep 18 08:20:46 AM UTC 24
Peak memory 232292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2110505
491 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_perf.2110505491
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/49.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/49.i2c_target_smbus_maxlen.1271273931
Short name T1715
Test name
Test status
Simulation time 851250612 ps
CPU time 3.41 seconds
Started Sep 18 08:20:45 AM UTC 24
Finished Sep 18 08:20:49 AM UTC 24
Peak memory 215204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1271273
931 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_smbus_maxlen.1271273931
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/49.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/49.i2c_target_smoke.2996480002
Short name T1704
Test name
Test status
Simulation time 1274795421 ps
CPU time 19.54 seconds
Started Sep 18 08:20:22 AM UTC 24
Finished Sep 18 08:20:42 AM UTC 24
Peak memory 225632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2996480002 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_smoke.2996480002
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/49.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/49.i2c_target_stress_all.515628950
Short name T1726
Test name
Test status
Simulation time 5945594586 ps
CPU time 46.94 seconds
Started Sep 18 08:20:36 AM UTC 24
Finished Sep 18 08:21:25 AM UTC 24
Peak memory 279372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=515628
950 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_stress_all.515628950
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/49.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/49.i2c_target_stress_rd.796272165
Short name T1727
Test name
Test status
Simulation time 7898697024 ps
CPU time 70.62 seconds
Started Sep 18 08:20:24 AM UTC 24
Finished Sep 18 08:21:36 AM UTC 24
Peak memory 229776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=796272165 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_stress_rd.796272165
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/49.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/49.i2c_target_stress_wr.4130205241
Short name T1751
Test name
Test status
Simulation time 59396498893 ps
CPU time 1146.32 seconds
Started Sep 18 08:20:23 AM UTC 24
Finished Sep 18 08:39:40 AM UTC 24
Peak memory 10070880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4130205241 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_stress_wr.4130205241
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/49.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/49.i2c_target_stretch.3600109826
Short name T1695
Test name
Test status
Simulation time 683480807 ps
CPU time 2.88 seconds
Started Sep 18 08:20:24 AM UTC 24
Finished Sep 18 08:20:28 AM UTC 24
Peak memory 225580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3600109826 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_stretch.3600109826
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/49.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/49.i2c_target_timeout.4050783989
Short name T1703
Test name
Test status
Simulation time 1932092120 ps
CPU time 9.77 seconds
Started Sep 18 08:20:31 AM UTC 24
Finished Sep 18 08:20:42 AM UTC 24
Peak memory 225580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4050783
989 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_timeout.4050783989
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/49.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/49.i2c_target_tx_stretch_ctrl.1188011848
Short name T1713
Test name
Test status
Simulation time 53530793 ps
CPU time 1.37 seconds
Started Sep 18 08:20:45 AM UTC 24
Finished Sep 18 08:20:47 AM UTC 24
Peak memory 214864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1188011
848 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_tx_stretch_ctrl.1188011848
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/49.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/5.i2c_alert_test.3283472945
Short name T311
Test name
Test status
Simulation time 74622598 ps
CPU time 0.92 seconds
Started Sep 18 07:56:17 AM UTC 24
Finished Sep 18 07:56:19 AM UTC 24
Peak memory 214840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3283472945 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_alert_test.3283472945
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/5.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/5.i2c_host_error_intr.1376349124
Short name T30
Test name
Test status
Simulation time 251687579 ps
CPU time 2.34 seconds
Started Sep 18 07:55:59 AM UTC 24
Finished Sep 18 07:56:02 AM UTC 24
Peak memory 225776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1376349124 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 5.i2c_host_error_intr.1376349124
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/5.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/5.i2c_host_fifo_fmt_empty.2546483647
Short name T219
Test name
Test status
Simulation time 267353262 ps
CPU time 7.25 seconds
Started Sep 18 07:55:57 AM UTC 24
Finished Sep 18 07:56:06 AM UTC 24
Peak memory 267048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2546483647 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_fmt_empty.2546483647
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/5.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/5.i2c_host_fifo_full.1410532548
Short name T169
Test name
Test status
Simulation time 2081003720 ps
CPU time 59.7 seconds
Started Sep 18 07:55:58 AM UTC 24
Finished Sep 18 07:57:00 AM UTC 24
Peak memory 545484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1410532548 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_full.1410532548
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/5.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/5.i2c_host_fifo_overflow.961258356
Short name T193
Test name
Test status
Simulation time 1983759046 ps
CPU time 57.97 seconds
Started Sep 18 07:55:56 AM UTC 24
Finished Sep 18 07:56:56 AM UTC 24
Peak memory 688796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=961258356 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_overflow.961258356
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/5.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/5.i2c_host_fifo_reset_fmt.2917807835
Short name T244
Test name
Test status
Simulation time 145827624 ps
CPU time 1.89 seconds
Started Sep 18 07:55:57 AM UTC 24
Finished Sep 18 07:56:00 AM UTC 24
Peak memory 214924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2917807835 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_fmt.2917807835
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/5.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/5.i2c_host_fifo_reset_rx.103339531
Short name T168
Test name
Test status
Simulation time 1850754444 ps
CPU time 7.16 seconds
Started Sep 18 07:55:58 AM UTC 24
Finished Sep 18 07:56:07 AM UTC 24
Peak memory 254624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=103339531 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_rx.103339531
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/5.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/5.i2c_host_fifo_watermark.1177206583
Short name T118
Test name
Test status
Simulation time 7662621798 ps
CPU time 68.15 seconds
Started Sep 18 07:55:56 AM UTC 24
Finished Sep 18 07:57:06 AM UTC 24
Peak memory 992164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1177206583 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_watermark.1177206583
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/5.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/5.i2c_host_may_nack.4177676031
Short name T252
Test name
Test status
Simulation time 1341848145 ps
CPU time 16.28 seconds
Started Sep 18 07:56:13 AM UTC 24
Finished Sep 18 07:56:30 AM UTC 24
Peak memory 215184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4177676031 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.i2c_host_may_nack.4177676031
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/5.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/5.i2c_host_override.1255181044
Short name T343
Test name
Test status
Simulation time 19544581 ps
CPU time 1.01 seconds
Started Sep 18 07:55:56 AM UTC 24
Finished Sep 18 07:55:58 AM UTC 24
Peak memory 214108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1255181044 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.i2c_host_override.1255181044
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/5.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/5.i2c_host_perf.3862876878
Short name T330
Test name
Test status
Simulation time 1269964095 ps
CPU time 20.36 seconds
Started Sep 18 07:55:59 AM UTC 24
Finished Sep 18 07:56:20 AM UTC 24
Peak memory 225508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3862876878 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 5.i2c_host_perf.3862876878
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/5.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/5.i2c_host_perf_precise.1958417347
Short name T346
Test name
Test status
Simulation time 55593495 ps
CPU time 1.45 seconds
Started Sep 18 07:55:59 AM UTC 24
Finished Sep 18 07:56:01 AM UTC 24
Peak memory 214848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1958417347 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_perf_precise.1958417347
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/5.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/5.i2c_host_smoke.3660916616
Short name T33
Test name
Test status
Simulation time 6943961169 ps
CPU time 25.05 seconds
Started Sep 18 07:55:55 AM UTC 24
Finished Sep 18 07:56:21 AM UTC 24
Peak memory 314148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3660916616 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.i2c_host_smoke.3660916616
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/5.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/5.i2c_host_stretch_timeout.232929075
Short name T341
Test name
Test status
Simulation time 1356809830 ps
CPU time 13.88 seconds
Started Sep 18 07:55:59 AM UTC 24
Finished Sep 18 07:56:14 AM UTC 24
Peak memory 227548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=232929075 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_stretch_timeout.232929075
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/5.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/5.i2c_target_bad_addr.3761168397
Short name T157
Test name
Test status
Simulation time 3295983880 ps
CPU time 8.2 seconds
Started Sep 18 07:56:10 AM UTC 24
Finished Sep 18 07:56:20 AM UTC 24
Peak memory 225560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=3761168397 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_bad_addr.3761168397
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/5.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/5.i2c_target_fifo_reset_acq.3091668500
Short name T333
Test name
Test status
Simulation time 222673272 ps
CPU time 1.61 seconds
Started Sep 18 07:56:07 AM UTC 24
Finished Sep 18 07:56:10 AM UTC 24
Peak memory 214784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3091668
500 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_fifo_reset_acq.3091668500
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/5.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/5.i2c_target_fifo_reset_tx.1930519837
Short name T175
Test name
Test status
Simulation time 340401536 ps
CPU time 1.33 seconds
Started Sep 18 07:56:07 AM UTC 24
Finished Sep 18 07:56:10 AM UTC 24
Peak memory 214780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1930519
837 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_fifo_reset_tx.1930519837
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/5.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/5.i2c_target_fifo_watermarks_acq.194841728
Short name T354
Test name
Test status
Simulation time 590738447 ps
CPU time 5.13 seconds
Started Sep 18 07:56:13 AM UTC 24
Finished Sep 18 07:56:19 AM UTC 24
Peak memory 215252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1948417
28 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_fifo_watermarks
_acq.194841728
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/5.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/5.i2c_target_fifo_watermarks_tx.1738259396
Short name T351
Test name
Test status
Simulation time 152069609 ps
CPU time 2.19 seconds
Started Sep 18 07:56:14 AM UTC 24
Finished Sep 18 07:56:17 AM UTC 24
Peak memory 215048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1738259
396 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_fifo_watermarks
_tx.1738259396
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/5.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/5.i2c_target_hrst.2954446727
Short name T348
Test name
Test status
Simulation time 846380903 ps
CPU time 2.88 seconds
Started Sep 18 07:56:11 AM UTC 24
Finished Sep 18 07:56:14 AM UTC 24
Peak memory 225500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2954446
727 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_hrst.2954446727
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/5.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/5.i2c_target_intr_smoke.2804642560
Short name T347
Test name
Test status
Simulation time 2100358191 ps
CPU time 7.76 seconds
Started Sep 18 07:56:02 AM UTC 24
Finished Sep 18 07:56:11 AM UTC 24
Peak memory 232236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=280464
2560 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_intr_smoke.2804642560
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/5.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/5.i2c_target_intr_stress_wr.1857015566
Short name T178
Test name
Test status
Simulation time 8434600131 ps
CPU time 9.61 seconds
Started Sep 18 07:56:03 AM UTC 24
Finished Sep 18 07:56:14 AM UTC 24
Peak memory 215364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1857015566 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_intr_stress
_wr.1857015566
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/5.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/5.i2c_target_nack_acqfull.252259177
Short name T156
Test name
Test status
Simulation time 900646740 ps
CPU time 3.6 seconds
Started Sep 18 07:56:15 AM UTC 24
Finished Sep 18 07:56:20 AM UTC 24
Peak memory 225576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2522591
77 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_nack_acqfull.252259177
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/5.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/5.i2c_target_nack_acqfull_addr.881320361
Short name T159
Test name
Test status
Simulation time 998920490 ps
CPU time 3.4 seconds
Started Sep 18 07:56:16 AM UTC 24
Finished Sep 18 07:56:20 AM UTC 24
Peak memory 215328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8813203
61 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_nack_acqfull_addr.881320361
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/5.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/5.i2c_target_nack_txstretch.831490813
Short name T181
Test name
Test status
Simulation time 469630365 ps
CPU time 1.84 seconds
Started Sep 18 07:56:16 AM UTC 24
Finished Sep 18 07:56:19 AM UTC 24
Peak memory 231628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8314908
13 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_nack_txstretch.831490813
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/5.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/5.i2c_target_perf.816894153
Short name T174
Test name
Test status
Simulation time 2815738290 ps
CPU time 5.71 seconds
Started Sep 18 07:56:08 AM UTC 24
Finished Sep 18 07:56:15 AM UTC 24
Peak memory 232348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8168941
53 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_perf.816894153
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/5.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/5.i2c_target_smbus_maxlen.3943441709
Short name T158
Test name
Test status
Simulation time 1342286923 ps
CPU time 4.32 seconds
Started Sep 18 07:56:15 AM UTC 24
Finished Sep 18 07:56:20 AM UTC 24
Peak memory 215068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3943441
709 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_smbus_maxlen.3943441709
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/5.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/5.i2c_target_smoke.2821475251
Short name T352
Test name
Test status
Simulation time 2349876459 ps
CPU time 15.53 seconds
Started Sep 18 07:56:01 AM UTC 24
Finished Sep 18 07:56:17 AM UTC 24
Peak memory 217632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2821475251 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_smoke.2821475251
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/5.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/5.i2c_target_stress_all.3902351443
Short name T98
Test name
Test status
Simulation time 27095684963 ps
CPU time 42.76 seconds
Started Sep 18 07:56:10 AM UTC 24
Finished Sep 18 07:56:55 AM UTC 24
Peak memory 248652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=390235
1443 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_stress_all.3902351443
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/5.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/5.i2c_target_stress_rd.3362071084
Short name T262
Test name
Test status
Simulation time 641048172 ps
CPU time 15.54 seconds
Started Sep 18 07:56:02 AM UTC 24
Finished Sep 18 07:56:19 AM UTC 24
Peak memory 229660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3362071084 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_stress_rd.3362071084
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/5.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/5.i2c_target_stress_wr.3125283179
Short name T177
Test name
Test status
Simulation time 14146893279 ps
CPU time 13.59 seconds
Started Sep 18 07:56:01 AM UTC 24
Finished Sep 18 07:56:15 AM UTC 24
Peak memory 215372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3125283179 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_stress_wr.3125283179
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/5.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/5.i2c_target_stretch.1629173049
Short name T353
Test name
Test status
Simulation time 1162884114 ps
CPU time 15.08 seconds
Started Sep 18 07:56:02 AM UTC 24
Finished Sep 18 07:56:18 AM UTC 24
Peak memory 265128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1629173049 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_stretch.1629173049
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/5.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/5.i2c_target_timeout.3257178685
Short name T338
Test name
Test status
Simulation time 4502314274 ps
CPU time 6.75 seconds
Started Sep 18 07:56:04 AM UTC 24
Finished Sep 18 07:56:12 AM UTC 24
Peak memory 225624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3257178
685 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_timeout.3257178685
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/5.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/5.i2c_target_tx_stretch_ctrl.2815426946
Short name T360
Test name
Test status
Simulation time 1429299778 ps
CPU time 19.59 seconds
Started Sep 18 07:56:15 AM UTC 24
Finished Sep 18 07:56:36 AM UTC 24
Peak memory 215316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2815426
946 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_tx_stretch_ctrl.2815426946
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/5.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/6.i2c_alert_test.1253043689
Short name T369
Test name
Test status
Simulation time 17042250 ps
CPU time 1 seconds
Started Sep 18 07:56:43 AM UTC 24
Finished Sep 18 07:56:45 AM UTC 24
Peak memory 214492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1253043689 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_alert_test.1253043689
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/6.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/6.i2c_host_error_intr.2762535626
Short name T161
Test name
Test status
Simulation time 976967415 ps
CPU time 5.31 seconds
Started Sep 18 07:56:21 AM UTC 24
Finished Sep 18 07:56:27 AM UTC 24
Peak memory 225576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2762535626 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 6.i2c_host_error_intr.2762535626
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/6.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/6.i2c_host_fifo_fmt_empty.135007450
Short name T358
Test name
Test status
Simulation time 397808101 ps
CPU time 11 seconds
Started Sep 18 07:56:21 AM UTC 24
Finished Sep 18 07:56:33 AM UTC 24
Peak memory 301852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=135007450 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_fmt_empty.135007450
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/6.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/6.i2c_host_fifo_full.2346602247
Short name T171
Test name
Test status
Simulation time 12457994234 ps
CPU time 57.71 seconds
Started Sep 18 07:56:21 AM UTC 24
Finished Sep 18 07:57:20 AM UTC 24
Peak memory 439280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2346602247 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_full.2346602247
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/6.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/6.i2c_host_fifo_overflow.1250728782
Short name T194
Test name
Test status
Simulation time 1337746082 ps
CPU time 35.82 seconds
Started Sep 18 07:56:20 AM UTC 24
Finished Sep 18 07:56:57 AM UTC 24
Peak memory 496412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1250728782 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_overflow.1250728782
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/6.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/6.i2c_host_fifo_reset_fmt.2448988971
Short name T160
Test name
Test status
Simulation time 255753641 ps
CPU time 1.39 seconds
Started Sep 18 07:56:20 AM UTC 24
Finished Sep 18 07:56:22 AM UTC 24
Peak memory 214904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2448988971 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_fmt.2448988971
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/6.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/6.i2c_host_fifo_reset_rx.3924198406
Short name T356
Test name
Test status
Simulation time 163177335 ps
CPU time 10.33 seconds
Started Sep 18 07:56:21 AM UTC 24
Finished Sep 18 07:56:32 AM UTC 24
Peak memory 215196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3924198406 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_rx.3924198406
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/6.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/6.i2c_host_fifo_watermark.4002711075
Short name T119
Test name
Test status
Simulation time 40592846276 ps
CPU time 74.55 seconds
Started Sep 18 07:56:20 AM UTC 24
Finished Sep 18 07:57:36 AM UTC 24
Peak memory 1045280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4002711075 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_watermark.4002711075
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/6.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/6.i2c_host_may_nack.3574347739
Short name T367
Test name
Test status
Simulation time 1062728256 ps
CPU time 4.4 seconds
Started Sep 18 07:56:36 AM UTC 24
Finished Sep 18 07:56:42 AM UTC 24
Peak memory 215252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3574347739 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.i2c_host_may_nack.3574347739
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/6.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/6.i2c_host_override.3071085328
Short name T146
Test name
Test status
Simulation time 193656329 ps
CPU time 0.8 seconds
Started Sep 18 07:56:17 AM UTC 24
Finished Sep 18 07:56:19 AM UTC 24
Peak memory 214108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3071085328 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.i2c_host_override.3071085328
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/6.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/6.i2c_host_perf.3380494936
Short name T16
Test name
Test status
Simulation time 31096880021 ps
CPU time 67.61 seconds
Started Sep 18 07:56:21 AM UTC 24
Finished Sep 18 07:57:30 AM UTC 24
Peak memory 429028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3380494936 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 6.i2c_host_perf.3380494936
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/6.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/6.i2c_host_perf_precise.3059781386
Short name T1294
Test name
Test status
Simulation time 24309749685 ps
CPU time 1023.17 seconds
Started Sep 18 07:56:21 AM UTC 24
Finished Sep 18 08:13:34 AM UTC 24
Peak memory 3986072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3059781386 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_perf_precise.3059781386
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/6.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/6.i2c_host_smoke.412257345
Short name T376
Test name
Test status
Simulation time 2786175781 ps
CPU time 30.16 seconds
Started Sep 18 07:56:17 AM UTC 24
Finished Sep 18 07:56:49 AM UTC 24
Peak memory 283432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=412257345 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 6.i2c_host_smoke.412257345
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/6.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/6.i2c_host_stress_all.2302394373
Short name T1745
Test name
Test status
Simulation time 71712380868 ps
CPU time 1793.78 seconds
Started Sep 18 07:56:21 AM UTC 24
Finished Sep 18 08:26:33 AM UTC 24
Peak memory 3810012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2302394373 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 6.i2c_host_stress_all.2302394373
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/6.i2c_host_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/6.i2c_host_stretch_timeout.3994367459
Short name T99
Test name
Test status
Simulation time 4352145203 ps
CPU time 32.31 seconds
Started Sep 18 07:56:21 AM UTC 24
Finished Sep 18 07:56:55 AM UTC 24
Peak memory 225764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3994367459 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_stretch_timeout.3994367459
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/6.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/6.i2c_target_bad_addr.2555922919
Short name T364
Test name
Test status
Simulation time 2047605363 ps
CPU time 5.87 seconds
Started Sep 18 07:56:33 AM UTC 24
Finished Sep 18 07:56:40 AM UTC 24
Peak memory 219352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=2555922919 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_bad_addr.2555922919
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/6.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/6.i2c_target_fifo_reset_acq.3924930409
Short name T359
Test name
Test status
Simulation time 274461288 ps
CPU time 2.83 seconds
Started Sep 18 07:56:32 AM UTC 24
Finished Sep 18 07:56:35 AM UTC 24
Peak memory 215328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3924930
409 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_fifo_reset_acq.3924930409
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/6.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/6.i2c_target_fifo_reset_tx.2143906564
Short name T197
Test name
Test status
Simulation time 240061860 ps
CPU time 1.78 seconds
Started Sep 18 07:56:32 AM UTC 24
Finished Sep 18 07:56:34 AM UTC 24
Peak memory 214780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2143906
564 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_fifo_reset_tx.2143906564
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/6.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/6.i2c_target_fifo_watermarks_acq.141089133
Short name T365
Test name
Test status
Simulation time 2117486154 ps
CPU time 4.18 seconds
Started Sep 18 07:56:36 AM UTC 24
Finished Sep 18 07:56:41 AM UTC 24
Peak memory 215340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1410891
33 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_fifo_watermarks
_acq.141089133
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/6.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/6.i2c_target_fifo_watermarks_tx.237146389
Short name T363
Test name
Test status
Simulation time 623553131 ps
CPU time 1.28 seconds
Started Sep 18 07:56:37 AM UTC 24
Finished Sep 18 07:56:39 AM UTC 24
Peak memory 214788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2371463
89 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_fifo_watermarks_tx.237146389
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/6.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/6.i2c_target_intr_smoke.1867713608
Short name T361
Test name
Test status
Simulation time 2357479560 ps
CPU time 11.92 seconds
Started Sep 18 07:56:23 AM UTC 24
Finished Sep 18 07:56:36 AM UTC 24
Peak memory 242612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=186771
3608 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_intr_smoke.1867713608
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/6.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/6.i2c_target_intr_stress_wr.1943415791
Short name T370
Test name
Test status
Simulation time 6311920738 ps
CPU time 15.27 seconds
Started Sep 18 07:56:29 AM UTC 24
Finished Sep 18 07:56:45 AM UTC 24
Peak memory 531212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1943415791 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_intr_stress
_wr.1943415791
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/6.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/6.i2c_target_nack_acqfull.4058066704
Short name T368
Test name
Test status
Simulation time 3653609058 ps
CPU time 3.77 seconds
Started Sep 18 07:56:39 AM UTC 24
Finished Sep 18 07:56:45 AM UTC 24
Peak memory 225700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4058066
704 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_nack_acqfull.4058066704
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/6.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/6.i2c_target_nack_acqfull_addr.1122395966
Short name T374
Test name
Test status
Simulation time 445322622 ps
CPU time 4.31 seconds
Started Sep 18 07:56:41 AM UTC 24
Finished Sep 18 07:56:46 AM UTC 24
Peak memory 215268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1122395
966 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_nack_acqfull_addr.1122395966
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/6.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/6.i2c_target_nack_txstretch.802447435
Short name T182
Test name
Test status
Simulation time 369201361 ps
CPU time 2.63 seconds
Started Sep 18 07:56:41 AM UTC 24
Finished Sep 18 07:56:44 AM UTC 24
Peak memory 232228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8024474
35 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_nack_txstretch.802447435
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/6.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/6.i2c_target_perf.2146978176
Short name T366
Test name
Test status
Simulation time 2675934682 ps
CPU time 8.67 seconds
Started Sep 18 07:56:32 AM UTC 24
Finished Sep 18 07:56:41 AM UTC 24
Peak memory 225568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2146978
176 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_perf.2146978176
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/6.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/6.i2c_target_smbus_maxlen.2079759992
Short name T372
Test name
Test status
Simulation time 2127436187 ps
CPU time 4.35 seconds
Started Sep 18 07:56:39 AM UTC 24
Finished Sep 18 07:56:45 AM UTC 24
Peak memory 215096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2079759
992 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_smbus_maxlen.2079759992
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/6.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/6.i2c_target_smoke.1192244650
Short name T85
Test name
Test status
Simulation time 1706466907 ps
CPU time 27 seconds
Started Sep 18 07:56:21 AM UTC 24
Finished Sep 18 07:56:49 AM UTC 24
Peak memory 225756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1192244650 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_smoke.1192244650
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/6.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/6.i2c_target_stress_rd.1465583935
Short name T95
Test name
Test status
Simulation time 6268027709 ps
CPU time 26.89 seconds
Started Sep 18 07:56:23 AM UTC 24
Finished Sep 18 07:56:51 AM UTC 24
Peak memory 242740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1465583935 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_stress_rd.1465583935
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/6.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/6.i2c_target_stress_wr.2611104948
Short name T373
Test name
Test status
Simulation time 16617654769 ps
CPU time 22.99 seconds
Started Sep 18 07:56:21 AM UTC 24
Finished Sep 18 07:56:45 AM UTC 24
Peak memory 215440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2611104948 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_stress_wr.2611104948
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/6.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/6.i2c_target_stretch.474530648
Short name T97
Test name
Test status
Simulation time 4194972903 ps
CPU time 29.87 seconds
Started Sep 18 07:56:23 AM UTC 24
Finished Sep 18 07:56:54 AM UTC 24
Peak memory 633880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=474530648 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_stretch.474530648
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/6.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/6.i2c_target_timeout.1862828701
Short name T362
Test name
Test status
Simulation time 2369353532 ps
CPU time 7.31 seconds
Started Sep 18 07:56:31 AM UTC 24
Finished Sep 18 07:56:39 AM UTC 24
Peak memory 231704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1862828
701 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_timeout.1862828701
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/6.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/6.i2c_target_tx_stretch_ctrl.4042005052
Short name T371
Test name
Test status
Simulation time 289683454 ps
CPU time 5.39 seconds
Started Sep 18 07:56:38 AM UTC 24
Finished Sep 18 07:56:45 AM UTC 24
Peak memory 215244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4042005
052 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_tx_stretch_ctrl.4042005052
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/6.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/7.i2c_alert_test.199791716
Short name T350
Test name
Test status
Simulation time 56297170 ps
CPU time 0.84 seconds
Started Sep 18 07:57:03 AM UTC 24
Finished Sep 18 07:57:05 AM UTC 24
Peak memory 214812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=199791716 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_alert_test.199791716
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/7.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/7.i2c_host_error_intr.3299285178
Short name T379
Test name
Test status
Simulation time 2461418133 ps
CPU time 9.38 seconds
Started Sep 18 07:56:47 AM UTC 24
Finished Sep 18 07:56:58 AM UTC 24
Peak memory 308220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3299285178 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 7.i2c_host_error_intr.3299285178
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/7.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/7.i2c_host_fifo_fmt_empty.2682814236
Short name T384
Test name
Test status
Simulation time 579828246 ps
CPU time 14.87 seconds
Started Sep 18 07:56:46 AM UTC 24
Finished Sep 18 07:57:02 AM UTC 24
Peak memory 277396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2682814236 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_fmt_empty.2682814236
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/7.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/7.i2c_host_fifo_full.3141743231
Short name T172
Test name
Test status
Simulation time 18144027712 ps
CPU time 48.04 seconds
Started Sep 18 07:56:46 AM UTC 24
Finished Sep 18 07:57:36 AM UTC 24
Peak memory 428892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3141743231 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_full.3141743231
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/7.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/7.i2c_host_fifo_overflow.4234787778
Short name T427
Test name
Test status
Simulation time 2204867422 ps
CPU time 57.14 seconds
Started Sep 18 07:56:45 AM UTC 24
Finished Sep 18 07:57:44 AM UTC 24
Peak memory 670480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4234787778 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_overflow.4234787778
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/7.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/7.i2c_host_fifo_reset_fmt.2198410424
Short name T375
Test name
Test status
Simulation time 523942815 ps
CPU time 1.42 seconds
Started Sep 18 07:56:46 AM UTC 24
Finished Sep 18 07:56:49 AM UTC 24
Peak memory 214908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2198410424 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_fmt.2198410424
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/7.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/7.i2c_host_fifo_reset_rx.2227517129
Short name T100
Test name
Test status
Simulation time 2436363929 ps
CPU time 7.45 seconds
Started Sep 18 07:56:46 AM UTC 24
Finished Sep 18 07:56:55 AM UTC 24
Peak memory 215580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2227517129 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_rx.2227517129
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/7.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/7.i2c_host_fifo_watermark.4049239151
Short name T543
Test name
Test status
Simulation time 13630969084 ps
CPU time 176.15 seconds
Started Sep 18 07:56:43 AM UTC 24
Finished Sep 18 07:59:42 AM UTC 24
Peak memory 1086292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4049239151 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_watermark.4049239151
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/7.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/7.i2c_host_override.719147624
Short name T147
Test name
Test status
Simulation time 27558356 ps
CPU time 1.03 seconds
Started Sep 18 07:56:43 AM UTC 24
Finished Sep 18 07:56:45 AM UTC 24
Peak memory 214112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=719147624 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 7.i2c_host_override.719147624
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/7.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/7.i2c_host_perf.1291422254
Short name T170
Test name
Test status
Simulation time 3132667658 ps
CPU time 16.99 seconds
Started Sep 18 07:56:46 AM UTC 24
Finished Sep 18 07:57:05 AM UTC 24
Peak memory 394004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1291422254 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 7.i2c_host_perf.1291422254
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/7.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/7.i2c_host_perf_precise.3132148087
Short name T93
Test name
Test status
Simulation time 220930820 ps
CPU time 3.39 seconds
Started Sep 18 07:56:46 AM UTC 24
Finished Sep 18 07:56:51 AM UTC 24
Peak memory 215124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3132148087 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_perf_precise.3132148087
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/7.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/7.i2c_host_smoke.4247773815
Short name T412
Test name
Test status
Simulation time 3295086350 ps
CPU time 81.07 seconds
Started Sep 18 07:56:43 AM UTC 24
Finished Sep 18 07:58:06 AM UTC 24
Peak memory 357216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4247773815 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.i2c_host_smoke.4247773815
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/7.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/7.i2c_host_stretch_timeout.3715505476
Short name T410
Test name
Test status
Simulation time 992275831 ps
CPU time 38.87 seconds
Started Sep 18 07:56:46 AM UTC 24
Finished Sep 18 07:57:27 AM UTC 24
Peak memory 225504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3715505476 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_stretch_timeout.3715505476
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/7.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/7.i2c_target_bad_addr.1892458855
Short name T355
Test name
Test status
Simulation time 1906379238 ps
CPU time 7.56 seconds
Started Sep 18 07:56:56 AM UTC 24
Finished Sep 18 07:57:05 AM UTC 24
Peak memory 225568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=1892458855 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_bad_addr.1892458855
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/7.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/7.i2c_target_fifo_reset_acq.3388740221
Short name T378
Test name
Test status
Simulation time 151822620 ps
CPU time 1.79 seconds
Started Sep 18 07:56:55 AM UTC 24
Finished Sep 18 07:56:58 AM UTC 24
Peak memory 224764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3388740
221 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_fifo_reset_acq.3388740221
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/7.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/7.i2c_target_fifo_reset_tx.3725569356
Short name T380
Test name
Test status
Simulation time 194466074 ps
CPU time 1.61 seconds
Started Sep 18 07:56:56 AM UTC 24
Finished Sep 18 07:56:59 AM UTC 24
Peak memory 214780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3725569
356 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_fifo_reset_tx.3725569356
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/7.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/7.i2c_target_fifo_watermarks_acq.2421992146
Short name T268
Test name
Test status
Simulation time 1968065983 ps
CPU time 5.08 seconds
Started Sep 18 07:56:59 AM UTC 24
Finished Sep 18 07:57:05 AM UTC 24
Peak memory 215392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2421992
146 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_fifo_watermark
s_acq.2421992146
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/7.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/7.i2c_target_fifo_watermarks_tx.3901439686
Short name T386
Test name
Test status
Simulation time 254084023 ps
CPU time 2.11 seconds
Started Sep 18 07:57:00 AM UTC 24
Finished Sep 18 07:57:03 AM UTC 24
Peak memory 215052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3901439
686 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_fifo_watermarks
_tx.3901439686
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/7.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/7.i2c_target_intr_smoke.3448730697
Short name T381
Test name
Test status
Simulation time 6580936108 ps
CPU time 7.62 seconds
Started Sep 18 07:56:52 AM UTC 24
Finished Sep 18 07:57:00 AM UTC 24
Peak memory 232208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=344873
0697 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_intr_smoke.3448730697
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/7.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/7.i2c_target_intr_stress_wr.2607582588
Short name T411
Test name
Test status
Simulation time 32813577017 ps
CPU time 34.16 seconds
Started Sep 18 07:56:53 AM UTC 24
Finished Sep 18 07:57:28 AM UTC 24
Peak memory 840676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2607582588 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_intr_stress
_wr.2607582588
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/7.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/7.i2c_target_nack_acqfull.1756978780
Short name T389
Test name
Test status
Simulation time 1989020309 ps
CPU time 3.67 seconds
Started Sep 18 07:57:02 AM UTC 24
Finished Sep 18 07:57:07 AM UTC 24
Peak memory 225620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1756978
780 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_nack_acqfull.1756978780
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/7.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/7.i2c_target_nack_acqfull_addr.3506337826
Short name T385
Test name
Test status
Simulation time 494788272 ps
CPU time 2.68 seconds
Started Sep 18 07:57:02 AM UTC 24
Finished Sep 18 07:57:06 AM UTC 24
Peak memory 215264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3506337
826 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_nack_acqfull_addr.3506337826
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/7.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/7.i2c_target_nack_txstretch.718034792
Short name T183
Test name
Test status
Simulation time 169892291 ps
CPU time 2.49 seconds
Started Sep 18 07:57:03 AM UTC 24
Finished Sep 18 07:57:06 AM UTC 24
Peak memory 232200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7180347
92 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_nack_txstretch.718034792
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/7.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/7.i2c_target_perf.1467833260
Short name T382
Test name
Test status
Simulation time 1912471811 ps
CPU time 4.41 seconds
Started Sep 18 07:56:56 AM UTC 24
Finished Sep 18 07:57:01 AM UTC 24
Peak memory 225636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1467833
260 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_perf.1467833260
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/7.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/7.i2c_target_smbus_maxlen.194452686
Short name T357
Test name
Test status
Simulation time 1905863152 ps
CPU time 4.2 seconds
Started Sep 18 07:57:01 AM UTC 24
Finished Sep 18 07:57:06 AM UTC 24
Peak memory 215232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1944526
86 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_smbus_maxlen.194452686
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/7.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/7.i2c_target_smoke.1245106325
Short name T377
Test name
Test status
Simulation time 2695860358 ps
CPU time 6.51 seconds
Started Sep 18 07:56:49 AM UTC 24
Finished Sep 18 07:56:57 AM UTC 24
Peak memory 225820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1245106325 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_smoke.1245106325
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/7.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/7.i2c_target_stress_all.2498693001
Short name T267
Test name
Test status
Simulation time 60594887118 ps
CPU time 190.7 seconds
Started Sep 18 07:56:56 AM UTC 24
Finished Sep 18 08:00:10 AM UTC 24
Peak memory 2673700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=249869
3001 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_stress_all.2498693001
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/7.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/7.i2c_target_stress_rd.2497094532
Short name T450
Test name
Test status
Simulation time 1638785063 ps
CPU time 67.33 seconds
Started Sep 18 07:56:51 AM UTC 24
Finished Sep 18 07:58:00 AM UTC 24
Peak memory 227668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2497094532 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_stress_rd.2497094532
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/7.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/7.i2c_target_stress_wr.2194901434
Short name T624
Test name
Test status
Simulation time 70840594419 ps
CPU time 256.6 seconds
Started Sep 18 07:56:51 AM UTC 24
Finished Sep 18 08:01:11 AM UTC 24
Peak memory 3353568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2194901434 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_stress_wr.2194901434
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/7.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/7.i2c_target_stretch.3115598684
Short name T396
Test name
Test status
Simulation time 2842108127 ps
CPU time 22.98 seconds
Started Sep 18 07:56:52 AM UTC 24
Finished Sep 18 07:57:16 AM UTC 24
Peak memory 533412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3115598684 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_stretch.3115598684
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/7.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/7.i2c_target_timeout.3410501836
Short name T387
Test name
Test status
Simulation time 5915225054 ps
CPU time 8.59 seconds
Started Sep 18 07:56:54 AM UTC 24
Finished Sep 18 07:57:03 AM UTC 24
Peak memory 232228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3410501
836 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_timeout.3410501836
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/7.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/8.i2c_alert_test.3972942355
Short name T416
Test name
Test status
Simulation time 19548882 ps
CPU time 1.02 seconds
Started Sep 18 07:57:27 AM UTC 24
Finished Sep 18 07:57:29 AM UTC 24
Peak memory 214840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3972942355 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_alert_test.3972942355
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/8.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/8.i2c_host_error_intr.2514463286
Short name T395
Test name
Test status
Simulation time 204923509 ps
CPU time 7.74 seconds
Started Sep 18 07:57:07 AM UTC 24
Finished Sep 18 07:57:16 AM UTC 24
Peak memory 225536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2514463286 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 8.i2c_host_error_intr.2514463286
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/8.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/8.i2c_host_fifo_fmt_empty.1262008821
Short name T392
Test name
Test status
Simulation time 584994514 ps
CPU time 3.32 seconds
Started Sep 18 07:57:05 AM UTC 24
Finished Sep 18 07:57:10 AM UTC 24
Peak memory 240416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1262008821 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_fmt_empty.1262008821
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/8.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/8.i2c_host_fifo_full.2108313928
Short name T493
Test name
Test status
Simulation time 3441079005 ps
CPU time 98.34 seconds
Started Sep 18 07:57:05 AM UTC 24
Finished Sep 18 07:58:46 AM UTC 24
Peak memory 807704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2108313928 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_full.2108313928
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/8.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/8.i2c_host_fifo_overflow.3396025970
Short name T514
Test name
Test status
Simulation time 5705800019 ps
CPU time 123.36 seconds
Started Sep 18 07:57:05 AM UTC 24
Finished Sep 18 07:59:11 AM UTC 24
Peak memory 650004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3396025970 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_overflow.3396025970
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/8.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/8.i2c_host_fifo_reset_fmt.663477130
Short name T391
Test name
Test status
Simulation time 131967773 ps
CPU time 1.67 seconds
Started Sep 18 07:57:05 AM UTC 24
Finished Sep 18 07:57:08 AM UTC 24
Peak memory 213984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=663477130 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_fmt.663477130
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/8.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/8.i2c_host_fifo_reset_rx.1600983734
Short name T393
Test name
Test status
Simulation time 195486797 ps
CPU time 6.53 seconds
Started Sep 18 07:57:05 AM UTC 24
Finished Sep 18 07:57:13 AM UTC 24
Peak memory 240332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1600983734 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_rx.1600983734
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/8.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/8.i2c_host_fifo_watermark.1644219420
Short name T552
Test name
Test status
Simulation time 5892767562 ps
CPU time 160.35 seconds
Started Sep 18 07:57:04 AM UTC 24
Finished Sep 18 07:59:47 AM UTC 24
Peak memory 924644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1644219420 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_watermark.1644219420
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/8.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/8.i2c_host_may_nack.2731403775
Short name T433
Test name
Test status
Simulation time 695701718 ps
CPU time 29.86 seconds
Started Sep 18 07:57:20 AM UTC 24
Finished Sep 18 07:57:51 AM UTC 24
Peak memory 215364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2731403775 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.i2c_host_may_nack.2731403775
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/8.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/8.i2c_host_override.2483514259
Short name T383
Test name
Test status
Simulation time 37388812 ps
CPU time 0.93 seconds
Started Sep 18 07:57:04 AM UTC 24
Finished Sep 18 07:57:06 AM UTC 24
Peak memory 214108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2483514259 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.i2c_host_override.2483514259
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/8.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/8.i2c_host_perf.682027897
Short name T17
Test name
Test status
Simulation time 12644677655 ps
CPU time 91.37 seconds
Started Sep 18 07:57:06 AM UTC 24
Finished Sep 18 07:58:40 AM UTC 24
Peak memory 215456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=682027897 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 8.i2c_host_perf.682027897
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/8.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/8.i2c_host_perf_precise.1212739348
Short name T401
Test name
Test status
Simulation time 234261211 ps
CPU time 11.69 seconds
Started Sep 18 07:57:07 AM UTC 24
Finished Sep 18 07:57:19 AM UTC 24
Peak memory 215192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1212739348 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_perf_precise.1212739348
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/8.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/8.i2c_host_smoke.3156596949
Short name T424
Test name
Test status
Simulation time 3552137203 ps
CPU time 36.39 seconds
Started Sep 18 07:57:04 AM UTC 24
Finished Sep 18 07:57:42 AM UTC 24
Peak memory 467928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3156596949 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.i2c_host_smoke.3156596949
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/8.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/8.i2c_host_stretch_timeout.3228414589
Short name T405
Test name
Test status
Simulation time 13761935792 ps
CPU time 15.67 seconds
Started Sep 18 07:57:07 AM UTC 24
Finished Sep 18 07:57:23 AM UTC 24
Peak memory 231852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3228414589 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_stretch_timeout.3228414589
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/8.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/8.i2c_target_bad_addr.3463451737
Short name T408
Test name
Test status
Simulation time 3623065595 ps
CPU time 7.59 seconds
Started Sep 18 07:57:18 AM UTC 24
Finished Sep 18 07:57:26 AM UTC 24
Peak memory 225628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=3463451737 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_bad_addr.3463451737
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/8.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/8.i2c_target_fifo_reset_acq.2148212699
Short name T398
Test name
Test status
Simulation time 145903308 ps
CPU time 1.69 seconds
Started Sep 18 07:57:14 AM UTC 24
Finished Sep 18 07:57:17 AM UTC 24
Peak memory 214784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2148212
699 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_fifo_reset_acq.2148212699
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/8.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/8.i2c_target_fifo_reset_tx.751087966
Short name T400
Test name
Test status
Simulation time 588885407 ps
CPU time 2.22 seconds
Started Sep 18 07:57:15 AM UTC 24
Finished Sep 18 07:57:19 AM UTC 24
Peak memory 225496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7510879
66 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_fifo_reset_tx.751087966
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/8.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/8.i2c_target_fifo_watermarks_acq.4043696815
Short name T409
Test name
Test status
Simulation time 2150654885 ps
CPU time 4.84 seconds
Started Sep 18 07:57:21 AM UTC 24
Finished Sep 18 07:57:27 AM UTC 24
Peak memory 215372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4043696
815 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_fifo_watermark
s_acq.4043696815
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/8.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/8.i2c_target_fifo_watermarks_tx.4150630288
Short name T406
Test name
Test status
Simulation time 109864756 ps
CPU time 1.96 seconds
Started Sep 18 07:57:22 AM UTC 24
Finished Sep 18 07:57:25 AM UTC 24
Peak memory 214856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4150630
288 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_fifo_watermarks
_tx.4150630288
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/8.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/8.i2c_target_intr_smoke.1528302726
Short name T402
Test name
Test status
Simulation time 1263050547 ps
CPU time 9.65 seconds
Started Sep 18 07:57:10 AM UTC 24
Finished Sep 18 07:57:21 AM UTC 24
Peak memory 232424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=152830
2726 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_intr_smoke.1528302726
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/8.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/8.i2c_target_intr_stress_wr.4007445347
Short name T453
Test name
Test status
Simulation time 18020701816 ps
CPU time 52.65 seconds
Started Sep 18 07:57:10 AM UTC 24
Finished Sep 18 07:58:04 AM UTC 24
Peak memory 1199072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=4007445347 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_intr_stress
_wr.4007445347
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/8.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/8.i2c_target_nack_acqfull.3844198273
Short name T417
Test name
Test status
Simulation time 1053658003 ps
CPU time 4.56 seconds
Started Sep 18 07:57:24 AM UTC 24
Finished Sep 18 07:57:30 AM UTC 24
Peak memory 225632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3844198
273 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_nack_acqfull.3844198273
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/8.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/8.i2c_target_nack_acqfull_addr.609476521
Short name T418
Test name
Test status
Simulation time 2464838686 ps
CPU time 5.12 seconds
Started Sep 18 07:57:25 AM UTC 24
Finished Sep 18 07:57:31 AM UTC 24
Peak memory 215320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6094765
21 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_nack_acqfull_addr.609476521
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/8.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/8.i2c_target_nack_txstretch.2072896638
Short name T184
Test name
Test status
Simulation time 133020105 ps
CPU time 2.37 seconds
Started Sep 18 07:57:26 AM UTC 24
Finished Sep 18 07:57:30 AM UTC 24
Peak memory 232228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2072896
638 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_nack_txstretch.2072896638
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/8.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/8.i2c_target_perf.1265802124
Short name T407
Test name
Test status
Simulation time 815862818 ps
CPU time 8.22 seconds
Started Sep 18 07:57:16 AM UTC 24
Finished Sep 18 07:57:26 AM UTC 24
Peak memory 232160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1265802
124 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_perf.1265802124
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/8.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/8.i2c_target_smbus_maxlen.2439935882
Short name T415
Test name
Test status
Simulation time 1850517120 ps
CPU time 3.84 seconds
Started Sep 18 07:57:24 AM UTC 24
Finished Sep 18 07:57:29 AM UTC 24
Peak memory 215220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2439935
882 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_smbus_maxlen.2439935882
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/8.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/8.i2c_target_smoke.2281254345
Short name T86
Test name
Test status
Simulation time 5237616910 ps
CPU time 30.78 seconds
Started Sep 18 07:57:08 AM UTC 24
Finished Sep 18 07:57:40 AM UTC 24
Peak memory 225696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2281254345 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_smoke.2281254345
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/8.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/8.i2c_target_stress_all.1662513526
Short name T265
Test name
Test status
Simulation time 24398799805 ps
CPU time 36.86 seconds
Started Sep 18 07:57:16 AM UTC 24
Finished Sep 18 07:57:55 AM UTC 24
Peak memory 232480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=166251
3526 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_stress_all.1662513526
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/8.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/8.i2c_target_stress_rd.2417259592
Short name T413
Test name
Test status
Simulation time 955104582 ps
CPU time 18.66 seconds
Started Sep 18 07:57:09 AM UTC 24
Finished Sep 18 07:57:29 AM UTC 24
Peak memory 232416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2417259592 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_stress_rd.2417259592
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/8.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/8.i2c_target_stress_wr.2731376819
Short name T507
Test name
Test status
Simulation time 26039607057 ps
CPU time 109.3 seconds
Started Sep 18 07:57:08 AM UTC 24
Finished Sep 18 07:58:59 AM UTC 24
Peak memory 1669984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2731376819 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_stress_wr.2731376819
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/8.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/8.i2c_target_stretch.1906721919
Short name T394
Test name
Test status
Simulation time 677314183 ps
CPU time 3 seconds
Started Sep 18 07:57:09 AM UTC 24
Finished Sep 18 07:57:13 AM UTC 24
Peak memory 215392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1906721919 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_stretch.1906721919
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/8.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/8.i2c_target_timeout.3325649918
Short name T403
Test name
Test status
Simulation time 5985089648 ps
CPU time 9.45 seconds
Started Sep 18 07:57:11 AM UTC 24
Finished Sep 18 07:57:22 AM UTC 24
Peak memory 231760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3325649
918 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_timeout.3325649918
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/8.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/8.i2c_target_tx_stretch_ctrl.4042961691
Short name T414
Test name
Test status
Simulation time 200476528 ps
CPU time 5.84 seconds
Started Sep 18 07:57:22 AM UTC 24
Finished Sep 18 07:57:29 AM UTC 24
Peak memory 215320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4042961
691 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_tx_stretch_ctrl.4042961691
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/8.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/9.i2c_alert_test.987553616
Short name T441
Test name
Test status
Simulation time 30040643 ps
CPU time 0.88 seconds
Started Sep 18 07:57:54 AM UTC 24
Finished Sep 18 07:57:56 AM UTC 24
Peak memory 214844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=987553616 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_alert_test.987553616
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/9.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/9.i2c_host_error_intr.79984070
Short name T420
Test name
Test status
Simulation time 551359251 ps
CPU time 1.98 seconds
Started Sep 18 07:57:31 AM UTC 24
Finished Sep 18 07:57:34 AM UTC 24
Peak memory 226668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=79984070 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ho
st_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.i2c_host_error_intr.79984070
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/9.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/9.i2c_host_fifo_fmt_empty.138981375
Short name T431
Test name
Test status
Simulation time 323593989 ps
CPU time 17.28 seconds
Started Sep 18 07:57:30 AM UTC 24
Finished Sep 18 07:57:48 AM UTC 24
Peak memory 275240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=138981375 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_fmt_empty.138981375
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/9.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/9.i2c_host_fifo_full.173065941
Short name T520
Test name
Test status
Simulation time 14460520258 ps
CPU time 107.95 seconds
Started Sep 18 07:57:30 AM UTC 24
Finished Sep 18 07:59:20 AM UTC 24
Peak memory 797680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=173065941 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_full.173065941
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/9.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/9.i2c_host_fifo_overflow.3185092273
Short name T468
Test name
Test status
Simulation time 2052628524 ps
CPU time 53.33 seconds
Started Sep 18 07:57:30 AM UTC 24
Finished Sep 18 07:58:25 AM UTC 24
Peak memory 664280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3185092273 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_overflow.3185092273
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/9.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/9.i2c_host_fifo_reset_fmt.2882916865
Short name T419
Test name
Test status
Simulation time 206151279 ps
CPU time 1.71 seconds
Started Sep 18 07:57:30 AM UTC 24
Finished Sep 18 07:57:33 AM UTC 24
Peak memory 214904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2882916865 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_fmt.2882916865
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/9.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/9.i2c_host_fifo_reset_rx.2235058885
Short name T422
Test name
Test status
Simulation time 616377825 ps
CPU time 5.47 seconds
Started Sep 18 07:57:30 AM UTC 24
Finished Sep 18 07:57:36 AM UTC 24
Peak memory 236196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2235058885 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_rx.2235058885
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/9.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/9.i2c_host_fifo_watermark.3124048759
Short name T571
Test name
Test status
Simulation time 22597517494 ps
CPU time 153.71 seconds
Started Sep 18 07:57:29 AM UTC 24
Finished Sep 18 08:00:05 AM UTC 24
Peak memory 934820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3124048759 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_watermark.3124048759
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/9.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/9.i2c_host_may_nack.1759586212
Short name T451
Test name
Test status
Simulation time 2029335907 ps
CPU time 9.63 seconds
Started Sep 18 07:57:49 AM UTC 24
Finished Sep 18 07:58:00 AM UTC 24
Peak memory 215452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1759586212 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.i2c_host_may_nack.1759586212
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/9.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/9.i2c_host_mode_toggle.2200158406
Short name T24
Test name
Test status
Simulation time 91567784 ps
CPU time 2.18 seconds
Started Sep 18 07:57:47 AM UTC 24
Finished Sep 18 07:57:50 AM UTC 24
Peak memory 225640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2200158406 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_mode_toggle.2200158406
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/9.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/9.i2c_host_override.1602190669
Short name T148
Test name
Test status
Simulation time 92143825 ps
CPU time 1.06 seconds
Started Sep 18 07:57:28 AM UTC 24
Finished Sep 18 07:57:29 AM UTC 24
Peak memory 214108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1602190669 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.i2c_host_override.1602190669
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/9.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/9.i2c_host_perf.4253251460
Short name T564
Test name
Test status
Simulation time 13649872291 ps
CPU time 141.53 seconds
Started Sep 18 07:57:31 AM UTC 24
Finished Sep 18 07:59:55 AM UTC 24
Peak memory 225556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4253251460 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 9.i2c_host_perf.4253251460
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/9.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/9.i2c_host_perf_precise.1023800579
Short name T421
Test name
Test status
Simulation time 92244424 ps
CPU time 2.55 seconds
Started Sep 18 07:57:31 AM UTC 24
Finished Sep 18 07:57:35 AM UTC 24
Peak memory 215452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1023800579 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_perf_precise.1023800579
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/9.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/9.i2c_host_smoke.2920022786
Short name T437
Test name
Test status
Simulation time 1317086825 ps
CPU time 24.53 seconds
Started Sep 18 07:57:27 AM UTC 24
Finished Sep 18 07:57:53 AM UTC 24
Peak memory 361120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2920022786 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.i2c_host_smoke.2920022786
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/9.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/9.i2c_host_stretch_timeout.2583388497
Short name T438
Test name
Test status
Simulation time 933896080 ps
CPU time 22.69 seconds
Started Sep 18 07:57:31 AM UTC 24
Finished Sep 18 07:57:55 AM UTC 24
Peak memory 232028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2583388497 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_stretch_timeout.2583388497
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/9.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/9.i2c_target_bad_addr.2375968619
Short name T435
Test name
Test status
Simulation time 6107784261 ps
CPU time 6.33 seconds
Started Sep 18 07:57:45 AM UTC 24
Finished Sep 18 07:57:52 AM UTC 24
Peak memory 231844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=2375968619 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_bad_addr.2375968619
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/9.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/9.i2c_target_fifo_reset_acq.1615304500
Short name T428
Test name
Test status
Simulation time 257849674 ps
CPU time 1.27 seconds
Started Sep 18 07:57:42 AM UTC 24
Finished Sep 18 07:57:44 AM UTC 24
Peak memory 214784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1615304
500 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_fifo_reset_acq.1615304500
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/9.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/9.i2c_target_fifo_reset_tx.967848391
Short name T429
Test name
Test status
Simulation time 208119621 ps
CPU time 2.09 seconds
Started Sep 18 07:57:43 AM UTC 24
Finished Sep 18 07:57:46 AM UTC 24
Peak memory 215244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9678483
91 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_fifo_reset_tx.967848391
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/9.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/9.i2c_target_fifo_watermarks_acq.3846767872
Short name T442
Test name
Test status
Simulation time 603644959 ps
CPU time 4.28 seconds
Started Sep 18 07:57:51 AM UTC 24
Finished Sep 18 07:57:56 AM UTC 24
Peak memory 215336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3846767
872 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_fifo_watermark
s_acq.3846767872
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/9.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/9.i2c_target_fifo_watermarks_tx.3940435120
Short name T185
Test name
Test status
Simulation time 568416822 ps
CPU time 2.12 seconds
Started Sep 18 07:57:52 AM UTC 24
Finished Sep 18 07:57:55 AM UTC 24
Peak memory 215048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3940435
120 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_fifo_watermarks
_tx.3940435120
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/9.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/9.i2c_target_hrst.967754882
Short name T432
Test name
Test status
Simulation time 1224027802 ps
CPU time 3.73 seconds
Started Sep 18 07:57:45 AM UTC 24
Finished Sep 18 07:57:50 AM UTC 24
Peak memory 227740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9677548
82 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_hrst.967754882
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/9.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/9.i2c_target_intr_smoke.2805486672
Short name T430
Test name
Test status
Simulation time 2255063080 ps
CPU time 9.38 seconds
Started Sep 18 07:57:37 AM UTC 24
Finished Sep 18 07:57:47 AM UTC 24
Peak memory 242592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=280548
6672 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_intr_smoke.2805486672
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/9.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/9.i2c_target_intr_stress_wr.2701365689
Short name T57
Test name
Test status
Simulation time 14280022114 ps
CPU time 27.27 seconds
Started Sep 18 07:57:38 AM UTC 24
Finished Sep 18 07:58:06 AM UTC 24
Peak memory 516884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2701365689 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_intr_stress
_wr.2701365689
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/9.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/9.i2c_target_nack_acqfull.3244509998
Short name T446
Test name
Test status
Simulation time 460808912 ps
CPU time 3.73 seconds
Started Sep 18 07:57:53 AM UTC 24
Finished Sep 18 07:57:57 AM UTC 24
Peak memory 225752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3244509
998 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_nack_acqfull.3244509998
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/9.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/9.i2c_target_nack_acqfull_addr.3934501216
Short name T448
Test name
Test status
Simulation time 409150289 ps
CPU time 3.26 seconds
Started Sep 18 07:57:54 AM UTC 24
Finished Sep 18 07:57:58 AM UTC 24
Peak memory 215468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3934501
216 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_nack_acqfull_addr.3934501216
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/9.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/9.i2c_target_perf.1827591924
Short name T440
Test name
Test status
Simulation time 1924017992 ps
CPU time 10.51 seconds
Started Sep 18 07:57:44 AM UTC 24
Finished Sep 18 07:57:56 AM UTC 24
Peak memory 232168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1827591
924 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_perf.1827591924
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/9.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/9.i2c_target_smbus_maxlen.141163562
Short name T447
Test name
Test status
Simulation time 518048109 ps
CPU time 3.97 seconds
Started Sep 18 07:57:53 AM UTC 24
Finished Sep 18 07:57:58 AM UTC 24
Peak memory 215148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1411635
62 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_smbus_maxlen.141163562
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/9.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/9.i2c_target_smoke.2219706663
Short name T426
Test name
Test status
Simulation time 1992462488 ps
CPU time 9.24 seconds
Started Sep 18 07:57:33 AM UTC 24
Finished Sep 18 07:57:44 AM UTC 24
Peak memory 225692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2219706663 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_smoke.2219706663
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/9.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/9.i2c_target_stress_all.2562491406
Short name T678
Test name
Test status
Simulation time 55460159344 ps
CPU time 258.6 seconds
Started Sep 18 07:57:44 AM UTC 24
Finished Sep 18 08:02:06 AM UTC 24
Peak memory 2507608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=256249
1406 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_stress_all.2562491406
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/9.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/9.i2c_target_stress_rd.547072603
Short name T397
Test name
Test status
Simulation time 746646902 ps
CPU time 38.38 seconds
Started Sep 18 07:57:35 AM UTC 24
Finished Sep 18 07:58:15 AM UTC 24
Peak memory 225496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=547072603 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_stress_rd.547072603
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/9.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/9.i2c_target_stress_wr.23484384
Short name T1392
Test name
Test status
Simulation time 57841586241 ps
CPU time 1065.99 seconds
Started Sep 18 07:57:35 AM UTC 24
Finished Sep 18 08:15:32 AM UTC 24
Peak memory 9978856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=23484384 -assert nopostpro
c +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_stress_wr.23484384
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/9.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/9.i2c_target_stretch.3615105483
Short name T423
Test name
Test status
Simulation time 1148861460 ps
CPU time 3.12 seconds
Started Sep 18 07:57:37 AM UTC 24
Finished Sep 18 07:57:41 AM UTC 24
Peak memory 232224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3615105483 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_stretch.3615105483
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/9.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/9.i2c_target_timeout.2068762914
Short name T436
Test name
Test status
Simulation time 1172589109 ps
CPU time 12.37 seconds
Started Sep 18 07:57:40 AM UTC 24
Finished Sep 18 07:57:53 AM UTC 24
Peak memory 231972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2068762
914 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_timeout.2068762914
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/9.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default/9.i2c_target_tx_stretch_ctrl.4245876646
Short name T444
Test name
Test status
Simulation time 99755337 ps
CPU time 3.99 seconds
Started Sep 18 07:57:52 AM UTC 24
Finished Sep 18 07:57:57 AM UTC 24
Peak memory 215372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4245876
646 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_tx_stretch_ctrl.4245876646
Directory /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/9.i2c_target_tx_stretch_ctrl/latest
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