| T1568 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/46.i2c_target_stress_wr.2292996095 |
|
|
Sep 24 08:38:16 AM UTC 24 |
Sep 24 08:38:27 AM UTC 24 |
8196708586 ps |
| T1569 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/46.i2c_host_perf_precise.138470381 |
|
|
Sep 24 08:38:07 AM UTC 24 |
Sep 24 08:38:27 AM UTC 24 |
2670310825 ps |
| T1570 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/46.i2c_target_stress_rd.4194388465 |
|
|
Sep 24 08:38:21 AM UTC 24 |
Sep 24 08:38:28 AM UTC 24 |
848364224 ps |
| T1571 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/42.i2c_host_fifo_full.1754734831 |
|
|
Sep 24 08:35:26 AM UTC 24 |
Sep 24 08:38:28 AM UTC 24 |
15318810433 ps |
| T1572 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/45.i2c_host_fifo_overflow.2150526775 |
|
|
Sep 24 08:37:25 AM UTC 24 |
Sep 24 08:38:29 AM UTC 24 |
9613824569 ps |
| T1573 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/45.i2c_target_stress_wr.194155163 |
|
|
Sep 24 08:37:35 AM UTC 24 |
Sep 24 08:38:30 AM UTC 24 |
43112756445 ps |
| T1574 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/46.i2c_host_stretch_timeout.1177874280 |
|
|
Sep 24 08:38:08 AM UTC 24 |
Sep 24 08:38:30 AM UTC 24 |
1032374630 ps |
| T1575 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/46.i2c_target_fifo_reset_tx.2425961940 |
|
|
Sep 24 08:38:28 AM UTC 24 |
Sep 24 08:38:31 AM UTC 24 |
457264338 ps |
| T1576 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/46.i2c_target_fifo_reset_acq.1053565053 |
|
|
Sep 24 08:38:28 AM UTC 24 |
Sep 24 08:38:32 AM UTC 24 |
630881214 ps |
| T1577 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/46.i2c_target_intr_smoke.420163677 |
|
|
Sep 24 08:38:26 AM UTC 24 |
Sep 24 08:38:33 AM UTC 24 |
3393657652 ps |
| T1578 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/46.i2c_host_mode_toggle.1621509883 |
|
|
Sep 24 08:38:31 AM UTC 24 |
Sep 24 08:38:34 AM UTC 24 |
1161817543 ps |
| T1579 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/46.i2c_target_smoke.774485717 |
|
|
Sep 24 08:38:15 AM UTC 24 |
Sep 24 08:38:35 AM UTC 24 |
3890781080 ps |
| T1580 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/46.i2c_target_fifo_watermarks_tx.1001548312 |
|
|
Sep 24 08:38:34 AM UTC 24 |
Sep 24 08:38:37 AM UTC 24 |
104487496 ps |
| T1581 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/46.i2c_target_timeout.124575293 |
|
|
Sep 24 08:38:27 AM UTC 24 |
Sep 24 08:38:37 AM UTC 24 |
5620455814 ps |
| T1582 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_fmt_empty.1712681663 |
|
|
Sep 24 08:39:28 AM UTC 24 |
Sep 24 08:39:40 AM UTC 24 |
744915856 ps |
| T1583 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/46.i2c_target_fifo_watermarks_acq.1258888061 |
|
|
Sep 24 08:38:33 AM UTC 24 |
Sep 24 08:38:38 AM UTC 24 |
478433680 ps |
| T1584 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/46.i2c_target_bad_addr.280102077 |
|
|
Sep 24 08:38:31 AM UTC 24 |
Sep 24 08:38:38 AM UTC 24 |
4578464585 ps |
| T1585 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/46.i2c_target_perf.1429279462 |
|
|
Sep 24 08:38:30 AM UTC 24 |
Sep 24 08:38:38 AM UTC 24 |
670103688 ps |
| T1586 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/46.i2c_target_intr_stress_wr.2964600266 |
|
|
Sep 24 08:38:26 AM UTC 24 |
Sep 24 08:38:38 AM UTC 24 |
3756716677 ps |
| T1587 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/46.i2c_target_smbus_maxlen.3003572217 |
|
|
Sep 24 08:38:36 AM UTC 24 |
Sep 24 08:38:40 AM UTC 24 |
1852613775 ps |
| T1588 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/46.i2c_alert_test.2478473149 |
|
|
Sep 24 08:38:39 AM UTC 24 |
Sep 24 08:38:41 AM UTC 24 |
31232200 ps |
| T1589 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/47.i2c_host_override.4160671070 |
|
|
Sep 24 08:38:40 AM UTC 24 |
Sep 24 08:38:42 AM UTC 24 |
98761465 ps |
| T1590 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_overflow.3437787269 |
|
|
Sep 24 08:38:41 AM UTC 24 |
Sep 24 08:39:51 AM UTC 24 |
8765601613 ps |
| T1591 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/46.i2c_target_nack_acqfull.582730958 |
|
|
Sep 24 08:38:37 AM UTC 24 |
Sep 24 08:38:42 AM UTC 24 |
1109079135 ps |
| T1592 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/46.i2c_target_nack_acqfull_addr.2613162220 |
|
|
Sep 24 08:38:38 AM UTC 24 |
Sep 24 08:38:44 AM UTC 24 |
1523030453 ps |
| T1593 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_reset_fmt.3621529361 |
|
|
Sep 24 08:38:42 AM UTC 24 |
Sep 24 08:38:45 AM UTC 24 |
573498142 ps |
| T1594 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/47.i2c_host_perf_precise.3011819188 |
|
|
Sep 24 08:38:45 AM UTC 24 |
Sep 24 08:38:49 AM UTC 24 |
110192901 ps |
| T1595 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_reset_rx.2995752968 |
|
|
Sep 24 08:38:43 AM UTC 24 |
Sep 24 08:38:54 AM UTC 24 |
599341517 ps |
| T1596 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/46.i2c_host_may_nack.3559442522 |
|
|
Sep 24 08:38:32 AM UTC 24 |
Sep 24 08:38:55 AM UTC 24 |
1597149506 ps |
| T1597 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/46.i2c_host_smoke.2275595770 |
|
|
Sep 24 08:38:02 AM UTC 24 |
Sep 24 08:38:57 AM UTC 24 |
4707403076 ps |
| T1598 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_overflow.2262128239 |
|
|
Sep 24 08:38:04 AM UTC 24 |
Sep 24 08:38:59 AM UTC 24 |
1928121477 ps |
| T1599 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/44.i2c_host_fifo_full.1978916177 |
|
|
Sep 24 08:36:40 AM UTC 24 |
Sep 24 08:38:59 AM UTC 24 |
17085720776 ps |
| T1600 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/47.i2c_host_stretch_timeout.2425526593 |
|
|
Sep 24 08:38:50 AM UTC 24 |
Sep 24 08:39:02 AM UTC 24 |
476723317 ps |
| T1601 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/47.i2c_target_smoke.181764863 |
|
|
Sep 24 08:38:56 AM UTC 24 |
Sep 24 08:39:03 AM UTC 24 |
427722342 ps |
| T1602 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/42.i2c_host_perf.3618019308 |
|
|
Sep 24 08:35:27 AM UTC 24 |
Sep 24 08:39:06 AM UTC 24 |
5682393706 ps |
| T1603 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_fmt_empty.1180817715 |
|
|
Sep 24 08:38:43 AM UTC 24 |
Sep 24 08:39:06 AM UTC 24 |
328160041 ps |
| T1604 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/47.i2c_target_intr_smoke.2794482141 |
|
|
Sep 24 08:39:03 AM UTC 24 |
Sep 24 08:39:08 AM UTC 24 |
1409857464 ps |
| T1605 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/41.i2c_host_perf.1380001217 |
|
|
Sep 24 08:34:53 AM UTC 24 |
Sep 24 08:39:09 AM UTC 24 |
18040899560 ps |
| T1606 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/47.i2c_host_perf.108518216 |
|
|
Sep 24 08:38:44 AM UTC 24 |
Sep 24 08:39:10 AM UTC 24 |
7020531691 ps |
| T1607 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/47.i2c_target_stretch.3313343991 |
|
|
Sep 24 08:39:00 AM UTC 24 |
Sep 24 08:39:11 AM UTC 24 |
927091414 ps |
| T1608 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/47.i2c_target_fifo_reset_acq.2523714346 |
|
|
Sep 24 08:39:09 AM UTC 24 |
Sep 24 08:39:13 AM UTC 24 |
343488067 ps |
| T1609 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/47.i2c_target_fifo_reset_tx.3407604220 |
|
|
Sep 24 08:39:10 AM UTC 24 |
Sep 24 08:39:13 AM UTC 24 |
138721910 ps |
| T1610 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/41.i2c_target_stress_all.1920409831 |
|
|
Sep 24 08:35:08 AM UTC 24 |
Sep 24 08:39:13 AM UTC 24 |
33191394687 ps |
| T1611 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/47.i2c_target_stress_rd.550075012 |
|
|
Sep 24 08:39:00 AM UTC 24 |
Sep 24 08:39:17 AM UTC 24 |
1844052133 ps |
| T1612 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/47.i2c_target_hrst.2526735057 |
|
|
Sep 24 08:39:14 AM UTC 24 |
Sep 24 08:39:17 AM UTC 24 |
353158743 ps |
| T1613 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/47.i2c_target_timeout.1397786451 |
|
|
Sep 24 08:39:07 AM UTC 24 |
Sep 24 08:39:18 AM UTC 24 |
1536933361 ps |
| T1614 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/47.i2c_target_fifo_watermarks_tx.1000736716 |
|
|
Sep 24 08:39:18 AM UTC 24 |
Sep 24 08:39:22 AM UTC 24 |
651176665 ps |
| T1615 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/47.i2c_target_perf.3890281695 |
|
|
Sep 24 08:39:11 AM UTC 24 |
Sep 24 08:39:22 AM UTC 24 |
2117246751 ps |
| T1616 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/47.i2c_host_may_nack.944839918 |
|
|
Sep 24 08:39:15 AM UTC 24 |
Sep 24 08:39:23 AM UTC 24 |
1059679424 ps |
| T1617 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/47.i2c_target_fifo_watermarks_acq.2184643930 |
|
|
Sep 24 08:39:18 AM UTC 24 |
Sep 24 08:39:23 AM UTC 24 |
938233989 ps |
| T1618 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/47.i2c_target_smbus_maxlen.4275473316 |
|
|
Sep 24 08:39:19 AM UTC 24 |
Sep 24 08:39:24 AM UTC 24 |
514306142 ps |
| T1619 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/47.i2c_host_smoke.2477859362 |
|
|
Sep 24 08:38:39 AM UTC 24 |
Sep 24 08:39:26 AM UTC 24 |
2092691908 ps |
| T1620 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/47.i2c_target_bad_addr.22009317 |
|
|
Sep 24 08:39:13 AM UTC 24 |
Sep 24 08:39:26 AM UTC 24 |
5184869924 ps |
| T1621 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/47.i2c_alert_test.1936610165 |
|
|
Sep 24 08:39:24 AM UTC 24 |
Sep 24 08:39:26 AM UTC 24 |
28779990 ps |
| T1622 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/47.i2c_target_nack_acqfull_addr.3121868368 |
|
|
Sep 24 08:39:22 AM UTC 24 |
Sep 24 08:39:26 AM UTC 24 |
2910249947 ps |
| T1623 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/47.i2c_target_nack_txstretch.3606289126 |
|
|
Sep 24 08:39:23 AM UTC 24 |
Sep 24 08:39:27 AM UTC 24 |
534319603 ps |
| T1624 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/47.i2c_target_nack_acqfull.1552335323 |
|
|
Sep 24 08:39:22 AM UTC 24 |
Sep 24 08:39:27 AM UTC 24 |
494712045 ps |
| T1625 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/47.i2c_target_tx_stretch_ctrl.689679175 |
|
|
Sep 24 08:39:18 AM UTC 24 |
Sep 24 08:39:27 AM UTC 24 |
446416419 ps |
| T1626 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/48.i2c_host_override.1338678478 |
|
|
Sep 24 08:39:27 AM UTC 24 |
Sep 24 08:39:28 AM UTC 24 |
36854302 ps |
| T1627 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_reset_fmt.2540325623 |
|
|
Sep 24 08:39:28 AM UTC 24 |
Sep 24 08:39:30 AM UTC 24 |
185382433 ps |
| T1628 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/48.i2c_host_perf_precise.3840821405 |
|
|
Sep 24 08:39:31 AM UTC 24 |
Sep 24 08:39:34 AM UTC 24 |
143566727 ps |
| T1629 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_reset_rx.993185683 |
|
|
Sep 24 08:39:28 AM UTC 24 |
Sep 24 08:39:34 AM UTC 24 |
360325338 ps |
| T1630 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/45.i2c_target_stress_all.2957096756 |
|
|
Sep 24 08:37:49 AM UTC 24 |
Sep 24 08:39:38 AM UTC 24 |
11453073829 ps |
| T1631 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/48.i2c_host_stretch_timeout.3486635110 |
|
|
Sep 24 08:39:35 AM UTC 24 |
Sep 24 08:39:53 AM UTC 24 |
747166017 ps |
| T1632 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/48.i2c_target_stress_rd.2699065577 |
|
|
Sep 24 08:39:53 AM UTC 24 |
Sep 24 08:40:01 AM UTC 24 |
297130976 ps |
| T1633 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/42.i2c_host_fifo_watermark.1457799647 |
|
|
Sep 24 08:35:23 AM UTC 24 |
Sep 24 08:40:04 AM UTC 24 |
4392256192 ps |
| T1634 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/42.i2c_target_intr_stress_wr.2063504219 |
|
|
Sep 24 08:35:35 AM UTC 24 |
Sep 24 08:40:06 AM UTC 24 |
20429337194 ps |
| T1635 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/37.i2c_target_intr_stress_wr.240581988 |
|
|
Sep 24 08:32:58 AM UTC 24 |
Sep 24 08:40:09 AM UTC 24 |
22781158977 ps |
| T1636 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/48.i2c_target_smoke.417533114 |
|
|
Sep 24 08:39:39 AM UTC 24 |
Sep 24 08:40:15 AM UTC 24 |
954183487 ps |
| T1637 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/48.i2c_target_intr_smoke.1444512637 |
|
|
Sep 24 08:40:02 AM UTC 24 |
Sep 24 08:40:15 AM UTC 24 |
1408517720 ps |
| T1638 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_overflow.519572645 |
|
|
Sep 24 08:39:28 AM UTC 24 |
Sep 24 08:40:16 AM UTC 24 |
5515081621 ps |
| T1639 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/48.i2c_target_timeout.1293190857 |
|
|
Sep 24 08:40:06 AM UTC 24 |
Sep 24 08:40:16 AM UTC 24 |
3940462886 ps |
| T1640 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/48.i2c_target_fifo_reset_acq.4218873139 |
|
|
Sep 24 08:40:14 AM UTC 24 |
Sep 24 08:40:17 AM UTC 24 |
434965403 ps |
| T1641 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/48.i2c_target_fifo_reset_tx.1750156043 |
|
|
Sep 24 08:40:15 AM UTC 24 |
Sep 24 08:40:18 AM UTC 24 |
736098687 ps |
| T1642 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/48.i2c_target_hrst.3018701559 |
|
|
Sep 24 08:40:18 AM UTC 24 |
Sep 24 08:40:22 AM UTC 24 |
5258097381 ps |
| T1643 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/48.i2c_target_perf.3894161584 |
|
|
Sep 24 08:40:16 AM UTC 24 |
Sep 24 08:40:22 AM UTC 24 |
706795572 ps |
| T1644 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/28.i2c_target_stress_wr.2526884241 |
|
|
Sep 24 08:28:18 AM UTC 24 |
Sep 24 08:43:38 AM UTC 24 |
54338581334 ps |
| T1645 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/48.i2c_target_bad_addr.3833272170 |
|
|
Sep 24 08:40:16 AM UTC 24 |
Sep 24 08:40:23 AM UTC 24 |
505984172 ps |
| T1646 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/45.i2c_host_perf.763800857 |
|
|
Sep 24 08:37:27 AM UTC 24 |
Sep 24 08:40:24 AM UTC 24 |
51429599202 ps |
| T1647 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/48.i2c_target_fifo_watermarks_tx.2725529865 |
|
|
Sep 24 08:40:23 AM UTC 24 |
Sep 24 08:40:26 AM UTC 24 |
116157724 ps |
| T1648 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/48.i2c_target_fifo_watermarks_acq.3444020892 |
|
|
Sep 24 08:40:20 AM UTC 24 |
Sep 24 08:40:27 AM UTC 24 |
628085695 ps |
| T1649 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/46.i2c_target_stretch.2061948474 |
|
|
Sep 24 08:38:23 AM UTC 24 |
Sep 24 08:40:27 AM UTC 24 |
2857604235 ps |
| T1650 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/48.i2c_target_nack_acqfull.13006974 |
|
|
Sep 24 08:40:24 AM UTC 24 |
Sep 24 08:40:29 AM UTC 24 |
596136828 ps |
| T1651 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/48.i2c_target_smbus_maxlen.21828996 |
|
|
Sep 24 08:40:24 AM UTC 24 |
Sep 24 08:40:29 AM UTC 24 |
539213870 ps |
| T1652 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/48.i2c_alert_test.1191898166 |
|
|
Sep 24 08:40:27 AM UTC 24 |
Sep 24 08:40:29 AM UTC 24 |
16476293 ps |
| T1653 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/48.i2c_target_tx_stretch_ctrl.3410485930 |
|
|
Sep 24 08:40:23 AM UTC 24 |
Sep 24 08:40:30 AM UTC 24 |
137344271 ps |
| T1654 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/48.i2c_target_nack_acqfull_addr.1086277836 |
|
|
Sep 24 08:40:25 AM UTC 24 |
Sep 24 08:40:30 AM UTC 24 |
879233151 ps |
| T1655 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/48.i2c_target_nack_txstretch.1392462436 |
|
|
Sep 24 08:40:27 AM UTC 24 |
Sep 24 08:40:31 AM UTC 24 |
127231287 ps |
| T250 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/39.i2c_host_stress_all.2939976256 |
|
|
Sep 24 08:33:53 AM UTC 24 |
Sep 24 08:43:49 AM UTC 24 |
14767604980 ps |
| T1656 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/49.i2c_host_override.3662593479 |
|
|
Sep 24 08:40:30 AM UTC 24 |
Sep 24 08:40:31 AM UTC 24 |
68550702 ps |
| T254 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/48.i2c_host_may_nack.3945037011 |
|
|
Sep 24 08:40:20 AM UTC 24 |
Sep 24 08:40:32 AM UTC 24 |
598503811 ps |
| T1657 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_reset_fmt.1085419048 |
|
|
Sep 24 08:40:31 AM UTC 24 |
Sep 24 08:40:33 AM UTC 24 |
242041349 ps |
| T1658 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/48.i2c_target_stretch.4203847474 |
|
|
Sep 24 08:39:54 AM UTC 24 |
Sep 24 08:40:35 AM UTC 24 |
2430475882 ps |
| T1659 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/47.i2c_target_stress_wr.4283456122 |
|
|
Sep 24 08:38:58 AM UTC 24 |
Sep 24 08:40:36 AM UTC 24 |
43357552892 ps |
| T1660 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_reset_rx.1653367156 |
|
|
Sep 24 08:40:32 AM UTC 24 |
Sep 24 08:40:38 AM UTC 24 |
360704000 ps |
| T1661 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/48.i2c_host_smoke.1473873031 |
|
|
Sep 24 08:39:24 AM UTC 24 |
Sep 24 08:40:38 AM UTC 24 |
1328129993 ps |
| T1662 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/49.i2c_host_error_intr.422538042 |
|
|
Sep 24 08:40:36 AM UTC 24 |
Sep 24 08:40:43 AM UTC 24 |
1323114608 ps |
| T1663 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_full.1374965911 |
|
|
Sep 24 08:39:28 AM UTC 24 |
Sep 24 08:40:50 AM UTC 24 |
10593551168 ps |
| T1664 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/49.i2c_target_smoke.1872547117 |
|
|
Sep 24 08:40:38 AM UTC 24 |
Sep 24 08:40:52 AM UTC 24 |
3628845971 ps |
| T1665 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/45.i2c_host_fifo_full.2327267883 |
|
|
Sep 24 08:37:26 AM UTC 24 |
Sep 24 08:40:53 AM UTC 24 |
7131019520 ps |
| T1666 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/48.i2c_target_stress_wr.3208090915 |
|
|
Sep 24 08:39:41 AM UTC 24 |
Sep 24 08:40:54 AM UTC 24 |
33503340082 ps |
| T1667 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_fmt_empty.2563721724 |
|
|
Sep 24 08:40:31 AM UTC 24 |
Sep 24 08:40:57 AM UTC 24 |
566959318 ps |
| T1668 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/49.i2c_host_smoke.2772228023 |
|
|
Sep 24 08:40:28 AM UTC 24 |
Sep 24 08:40:57 AM UTC 24 |
2605766938 ps |
| T1669 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/49.i2c_target_fifo_reset_acq.1845414886 |
|
|
Sep 24 08:40:58 AM UTC 24 |
Sep 24 08:41:01 AM UTC 24 |
141318869 ps |
| T1670 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/49.i2c_target_intr_smoke.785092325 |
|
|
Sep 24 08:40:53 AM UTC 24 |
Sep 24 08:41:02 AM UTC 24 |
920410474 ps |
| T1671 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/49.i2c_host_stretch_timeout.3034567260 |
|
|
Sep 24 08:40:34 AM UTC 24 |
Sep 24 08:41:02 AM UTC 24 |
437023073 ps |
| T1672 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/49.i2c_host_perf.188618998 |
|
|
Sep 24 08:40:32 AM UTC 24 |
Sep 24 08:41:03 AM UTC 24 |
3022526397 ps |
| T1673 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/49.i2c_target_timeout.1223925267 |
|
|
Sep 24 08:40:55 AM UTC 24 |
Sep 24 08:41:04 AM UTC 24 |
6455460606 ps |
| T1674 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/49.i2c_target_fifo_reset_tx.1153469040 |
|
|
Sep 24 08:41:02 AM UTC 24 |
Sep 24 08:41:06 AM UTC 24 |
229731724 ps |
| T1675 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/42.i2c_target_stress_all.1352603780 |
|
|
Sep 24 08:35:43 AM UTC 24 |
Sep 24 08:41:06 AM UTC 24 |
69953308249 ps |
| T1676 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/49.i2c_target_stress_rd.895181568 |
|
|
Sep 24 08:40:45 AM UTC 24 |
Sep 24 08:41:08 AM UTC 24 |
18527216351 ps |
| T1677 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/49.i2c_target_fifo_watermarks_acq.619385433 |
|
|
Sep 24 08:41:07 AM UTC 24 |
Sep 24 08:41:11 AM UTC 24 |
496411998 ps |
| T1678 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/49.i2c_host_perf_precise.4102729664 |
|
|
Sep 24 08:40:33 AM UTC 24 |
Sep 24 08:41:12 AM UTC 24 |
2385779848 ps |
| T1679 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/49.i2c_target_fifo_watermarks_tx.1696802253 |
|
|
Sep 24 08:41:09 AM UTC 24 |
Sep 24 08:41:13 AM UTC 24 |
565360326 ps |
| T1680 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/49.i2c_target_tx_stretch_ctrl.2402807522 |
|
|
Sep 24 08:41:10 AM UTC 24 |
Sep 24 08:41:13 AM UTC 24 |
71069515 ps |
| T1681 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/49.i2c_target_bad_addr.1867941804 |
|
|
Sep 24 08:41:04 AM UTC 24 |
Sep 24 08:41:14 AM UTC 24 |
14726298095 ps |
| T1682 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/49.i2c_target_perf.2827102663 |
|
|
Sep 24 08:41:02 AM UTC 24 |
Sep 24 08:41:15 AM UTC 24 |
820696499 ps |
| T1683 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/49.i2c_target_smbus_maxlen.397220965 |
|
|
Sep 24 08:41:12 AM UTC 24 |
Sep 24 08:41:16 AM UTC 24 |
708570501 ps |
| T1684 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/49.i2c_host_may_nack.2002541752 |
|
|
Sep 24 08:41:07 AM UTC 24 |
Sep 24 08:41:16 AM UTC 24 |
677465373 ps |
| T1685 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/49.i2c_target_nack_txstretch.3991178112 |
|
|
Sep 24 08:41:14 AM UTC 24 |
Sep 24 08:41:17 AM UTC 24 |
269320369 ps |
| T1686 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/49.i2c_alert_test.1235130812 |
|
|
Sep 24 08:41:15 AM UTC 24 |
Sep 24 08:41:17 AM UTC 24 |
25625637 ps |
| T1687 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/49.i2c_target_nack_acqfull.355339774 |
|
|
Sep 24 08:41:13 AM UTC 24 |
Sep 24 08:41:17 AM UTC 24 |
7446320338 ps |
| T1688 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/49.i2c_target_stretch.2363351523 |
|
|
Sep 24 08:40:51 AM UTC 24 |
Sep 24 08:41:18 AM UTC 24 |
2847270218 ps |
| T1689 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/49.i2c_target_nack_acqfull_addr.2829205270 |
|
|
Sep 24 08:41:13 AM UTC 24 |
Sep 24 08:41:20 AM UTC 24 |
3090372053 ps |
| T1690 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_full.956955412 |
|
|
Sep 24 08:38:05 AM UTC 24 |
Sep 24 08:41:24 AM UTC 24 |
11372927810 ps |
| T1691 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_overflow.3474581925 |
|
|
Sep 24 08:40:31 AM UTC 24 |
Sep 24 08:41:26 AM UTC 24 |
1701014955 ps |
| T1692 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/40.i2c_target_stress_all.3242942100 |
|
|
Sep 24 08:34:39 AM UTC 24 |
Sep 24 08:41:40 AM UTC 24 |
106226197874 ps |
| T1693 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/45.i2c_host_fifo_watermark.3461033793 |
|
|
Sep 24 08:37:24 AM UTC 24 |
Sep 24 08:41:43 AM UTC 24 |
8455308290 ps |
| T1694 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/49.i2c_target_stress_wr.3847151010 |
|
|
Sep 24 08:40:39 AM UTC 24 |
Sep 24 08:41:49 AM UTC 24 |
22688867849 ps |
| T1695 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/49.i2c_target_intr_stress_wr.1902923735 |
|
|
Sep 24 08:40:54 AM UTC 24 |
Sep 24 08:41:51 AM UTC 24 |
16616377925 ps |
| T1696 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/35.i2c_target_stress_all.3473534424 |
|
|
Sep 24 08:31:54 AM UTC 24 |
Sep 24 08:41:53 AM UTC 24 |
32984909274 ps |
| T1697 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_full.2793925906 |
|
|
Sep 24 08:40:32 AM UTC 24 |
Sep 24 08:41:55 AM UTC 24 |
11125778585 ps |
| T1698 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/33.i2c_host_perf.3255495892 |
|
|
Sep 24 08:30:42 AM UTC 24 |
Sep 24 08:42:22 AM UTC 24 |
29864689918 ps |
| T1699 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/29.i2c_host_perf.348689300 |
|
|
Sep 24 08:28:40 AM UTC 24 |
Sep 24 08:42:28 AM UTC 24 |
76099254982 ps |
| T1700 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_watermark.4259149268 |
|
|
Sep 24 08:38:03 AM UTC 24 |
Sep 24 08:42:46 AM UTC 24 |
4509211154 ps |
| T1701 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/46.i2c_target_stress_all.2545582945 |
|
|
Sep 24 08:38:30 AM UTC 24 |
Sep 24 08:42:53 AM UTC 24 |
26390968725 ps |
| T1702 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_watermark.4112578593 |
|
|
Sep 24 08:38:40 AM UTC 24 |
Sep 24 08:42:58 AM UTC 24 |
9146479641 ps |
| T1703 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_full.2844264409 |
|
|
Sep 24 08:38:43 AM UTC 24 |
Sep 24 08:42:58 AM UTC 24 |
6624275673 ps |
| T1704 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/38.i2c_target_stress_wr.2701285049 |
|
|
Sep 24 08:33:23 AM UTC 24 |
Sep 24 08:43:12 AM UTC 24 |
59407085639 ps |
| T1705 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/48.i2c_target_intr_stress_wr.111399618 |
|
|
Sep 24 08:40:05 AM UTC 24 |
Sep 24 08:43:28 AM UTC 24 |
16368124637 ps |
| T1706 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/47.i2c_target_intr_stress_wr.2608020447 |
|
|
Sep 24 08:39:04 AM UTC 24 |
Sep 24 08:44:01 AM UTC 24 |
18640236645 ps |
| T1707 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/39.i2c_target_stress_all.94955661 |
|
|
Sep 24 08:34:07 AM UTC 24 |
Sep 24 08:44:08 AM UTC 24 |
24403064576 ps |
| T1708 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_watermark.3581171500 |
|
|
Sep 24 08:39:27 AM UTC 24 |
Sep 24 08:44:16 AM UTC 24 |
4676554628 ps |
| T1709 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/44.i2c_target_intr_stress_wr.3432710236 |
|
|
Sep 24 08:36:58 AM UTC 24 |
Sep 24 08:44:26 AM UTC 24 |
22039853141 ps |
| T1710 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/48.i2c_host_perf.206636917 |
|
|
Sep 24 08:39:29 AM UTC 24 |
Sep 24 08:44:33 AM UTC 24 |
29013703511 ps |
| T1711 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_watermark.1048913473 |
|
|
Sep 24 08:40:30 AM UTC 24 |
Sep 24 08:44:48 AM UTC 24 |
9584757402 ps |
| T238 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/41.i2c_host_stress_all.1248830202 |
|
|
Sep 24 08:34:55 AM UTC 24 |
Sep 24 08:45:20 AM UTC 24 |
65689732352 ps |
| T1712 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/43.i2c_target_stress_all.3387726383 |
|
|
Sep 24 08:36:22 AM UTC 24 |
Sep 24 08:46:34 AM UTC 24 |
45699748862 ps |
| T1713 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/49.i2c_target_stress_all.2552461608 |
|
|
Sep 24 08:41:02 AM UTC 24 |
Sep 24 08:46:54 AM UTC 24 |
24823125391 ps |
| T1714 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/39.i2c_target_stress_wr.3246948741 |
|
|
Sep 24 08:33:54 AM UTC 24 |
Sep 24 08:46:59 AM UTC 24 |
51503188707 ps |
| T1715 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/42.i2c_target_stress_wr.3036102183 |
|
|
Sep 24 08:35:29 AM UTC 24 |
Sep 24 08:47:12 AM UTC 24 |
53539072428 ps |
| T251 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/29.i2c_host_stress_all.1232785299 |
|
|
Sep 24 08:28:42 AM UTC 24 |
Sep 24 08:47:15 AM UTC 24 |
54574236637 ps |
| T1716 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/48.i2c_target_stress_all.2578491081 |
|
|
Sep 24 08:40:16 AM UTC 24 |
Sep 24 08:47:21 AM UTC 24 |
32385534139 ps |
| T1717 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/15.i2c_host_stress_all.3042944288 |
|
|
Sep 24 08:21:33 AM UTC 24 |
Sep 24 08:47:53 AM UTC 24 |
102860149765 ps |
| T1718 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/47.i2c_target_stress_all.361185761 |
|
|
Sep 24 08:39:11 AM UTC 24 |
Sep 24 08:48:43 AM UTC 24 |
49069020938 ps |
| T1719 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/44.i2c_host_stress_all.2130068665 |
|
|
Sep 24 08:36:47 AM UTC 24 |
Sep 24 08:49:44 AM UTC 24 |
53703244418 ps |
| T1720 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/18.i2c_host_perf.2782789535 |
|
|
Sep 24 08:23:07 AM UTC 24 |
Sep 24 08:50:51 AM UTC 24 |
73460428953 ps |
| T1721 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/18.i2c_target_stress_all.2825382739 |
|
|
Sep 24 08:23:28 AM UTC 24 |
Sep 24 08:52:29 AM UTC 24 |
57294783746 ps |
| T37 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/43.i2c_host_perf.1617935611 |
|
|
Sep 24 08:36:01 AM UTC 24 |
Sep 24 08:53:36 AM UTC 24 |
13375714193 ps |
| T1722 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/20.i2c_host_perf.3852103149 |
|
|
Sep 24 08:24:09 AM UTC 24 |
Sep 24 08:55:40 AM UTC 24 |
28945448237 ps |
| T1723 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/32.i2c_target_stress_wr.1043157818 |
|
|
Sep 24 08:30:16 AM UTC 24 |
Sep 24 08:55:53 AM UTC 24 |
63626006923 ps |
| T1724 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/30.i2c_target_stress_all.4185700288 |
|
|
Sep 24 08:29:22 AM UTC 24 |
Sep 24 08:59:12 AM UTC 24 |
80568518419 ps |
| T1725 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/26.i2c_host_perf.2535888041 |
|
|
Sep 24 08:27:23 AM UTC 24 |
Sep 24 09:06:28 AM UTC 24 |
49057258750 ps |
| T1726 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/default/46.i2c_host_perf.4128408618 |
|
|
Sep 24 08:38:07 AM UTC 24 |
Sep 24 09:16:02 AM UTC 24 |
48169505618 ps |
| T102 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_tl_errors.2789473442 |
|
|
Sep 24 08:41:16 AM UTC 24 |
Sep 24 08:41:19 AM UTC 24 |
307157666 ps |
| T192 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_tl_intg_err.2219918681 |
|
|
Sep 24 08:41:17 AM UTC 24 |
Sep 24 08:41:20 AM UTC 24 |
91074127 ps |
| T284 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_intr_test.2796509678 |
|
|
Sep 24 08:41:18 AM UTC 24 |
Sep 24 08:41:20 AM UTC 24 |
18919675 ps |
| T212 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_rw.2319708394 |
|
|
Sep 24 08:41:19 AM UTC 24 |
Sep 24 08:41:21 AM UTC 24 |
46304680 ps |
| T213 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_hw_reset.2505535295 |
|
|
Sep 24 08:41:19 AM UTC 24 |
Sep 24 08:41:21 AM UTC 24 |
61401889 ps |
| T1727 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_aliasing.4206325874 |
|
|
Sep 24 08:41:19 AM UTC 24 |
Sep 24 08:41:22 AM UTC 24 |
88288519 ps |
| T232 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_same_csr_outstanding.2074475230 |
|
|
Sep 24 08:41:20 AM UTC 24 |
Sep 24 08:41:23 AM UTC 24 |
54672339 ps |
| T285 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_intr_test.2916651608 |
|
|
Sep 24 08:41:21 AM UTC 24 |
Sep 24 08:41:23 AM UTC 24 |
18339233 ps |
| T103 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.1540684372 |
|
|
Sep 24 08:41:21 AM UTC 24 |
Sep 24 08:41:23 AM UTC 24 |
238905176 ps |
| T286 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_intr_test.2791122152 |
|
|
Sep 24 08:41:46 AM UTC 24 |
Sep 24 08:41:48 AM UTC 24 |
28467602 ps |
| T104 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_tl_errors.3542340085 |
|
|
Sep 24 08:41:21 AM UTC 24 |
Sep 24 08:41:24 AM UTC 24 |
671706675 ps |
| T1728 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_hw_reset.3216668810 |
|
|
Sep 24 08:41:22 AM UTC 24 |
Sep 24 08:41:25 AM UTC 24 |
18878159 ps |
| T105 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_rw.880526785 |
|
|
Sep 24 08:41:22 AM UTC 24 |
Sep 24 08:41:25 AM UTC 24 |
28212361 ps |
| T198 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_tl_intg_err.46362042 |
|
|
Sep 24 08:41:21 AM UTC 24 |
Sep 24 08:41:25 AM UTC 24 |
85248615 ps |
| T220 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_aliasing.4200244862 |
|
|
Sep 24 08:41:24 AM UTC 24 |
Sep 24 08:41:26 AM UTC 24 |
327789495 ps |
| T106 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_bit_bash.2614920509 |
|
|
Sep 24 08:41:19 AM UTC 24 |
Sep 24 08:41:26 AM UTC 24 |
1119060117 ps |
| T190 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_same_csr_outstanding.3330707967 |
|
|
Sep 24 08:41:25 AM UTC 24 |
Sep 24 08:41:27 AM UTC 24 |
176538290 ps |
| T205 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.151220331 |
|
|
Sep 24 08:41:25 AM UTC 24 |
Sep 24 08:41:28 AM UTC 24 |
98806202 ps |
| T292 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_intr_test.3786175745 |
|
|
Sep 24 08:41:26 AM UTC 24 |
Sep 24 08:41:28 AM UTC 24 |
132417629 ps |
| T1729 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_hw_reset.828236699 |
|
|
Sep 24 08:41:26 AM UTC 24 |
Sep 24 08:41:28 AM UTC 24 |
42178710 ps |
| T233 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_rw.1265295378 |
|
|
Sep 24 08:41:26 AM UTC 24 |
Sep 24 08:41:28 AM UTC 24 |
18398226 ps |
| T107 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_tl_intg_err.407246275 |
|
|
Sep 24 08:41:25 AM UTC 24 |
Sep 24 08:41:29 AM UTC 24 |
462967914 ps |
| T234 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_same_csr_outstanding.3205307694 |
|
|
Sep 24 08:41:27 AM UTC 24 |
Sep 24 08:41:29 AM UTC 24 |
54649583 ps |
| T108 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_tl_errors.2512834294 |
|
|
Sep 24 08:41:25 AM UTC 24 |
Sep 24 08:41:30 AM UTC 24 |
507142001 ps |
| T109 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_aliasing.547963925 |
|
|
Sep 24 08:41:27 AM UTC 24 |
Sep 24 08:41:30 AM UTC 24 |
125464797 ps |
| T227 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_bit_bash.3374112289 |
|
|
Sep 24 08:41:24 AM UTC 24 |
Sep 24 08:41:30 AM UTC 24 |
858549854 ps |
| T289 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_intr_test.2182786585 |
|
|
Sep 24 08:41:29 AM UTC 24 |
Sep 24 08:41:31 AM UTC 24 |
19354721 ps |
| T210 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.1871198078 |
|
|
Sep 24 08:41:29 AM UTC 24 |
Sep 24 08:41:31 AM UTC 24 |
172402786 ps |
| T1730 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_hw_reset.2808862812 |
|
|
Sep 24 08:41:30 AM UTC 24 |
Sep 24 08:41:32 AM UTC 24 |
56275459 ps |
| T199 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_tl_errors.3755498768 |
|
|
Sep 24 08:41:29 AM UTC 24 |
Sep 24 08:41:33 AM UTC 24 |
819331018 ps |
| T127 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_rw.19401244 |
|
|
Sep 24 08:41:31 AM UTC 24 |
Sep 24 08:41:33 AM UTC 24 |
20765886 ps |
| T110 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_tl_intg_err.3031398930 |
|
|
Sep 24 08:41:29 AM UTC 24 |
Sep 24 08:41:33 AM UTC 24 |
256952826 ps |
| T235 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_same_csr_outstanding.338738025 |
|
|
Sep 24 08:41:31 AM UTC 24 |
Sep 24 08:41:33 AM UTC 24 |
21641975 ps |
| T200 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.1108335915 |
|
|
Sep 24 08:41:31 AM UTC 24 |
Sep 24 08:41:34 AM UTC 24 |
58164404 ps |
| T288 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_intr_test.4198025938 |
|
|
Sep 24 08:41:33 AM UTC 24 |
Sep 24 08:41:35 AM UTC 24 |
17570269 ps |
| T221 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_aliasing.205221424 |
|
|
Sep 24 08:41:31 AM UTC 24 |
Sep 24 08:41:35 AM UTC 24 |
42025466 ps |
| T202 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_tl_errors.1217419819 |
|
|
Sep 24 08:41:32 AM UTC 24 |
Sep 24 08:41:35 AM UTC 24 |
73924624 ps |
| T1731 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_bit_bash.4040202183 |
|
|
Sep 24 08:41:27 AM UTC 24 |
Sep 24 08:41:35 AM UTC 24 |
1392635454 ps |
| T222 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_hw_reset.2499753684 |
|
|
Sep 24 08:41:34 AM UTC 24 |
Sep 24 08:41:36 AM UTC 24 |
74158342 ps |
| T1732 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_rw.2803169015 |
|
|
Sep 24 08:41:34 AM UTC 24 |
Sep 24 08:41:36 AM UTC 24 |
92948397 ps |
| T111 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_tl_intg_err.4255624665 |
|
|
Sep 24 08:41:32 AM UTC 24 |
Sep 24 08:41:37 AM UTC 24 |
266456743 ps |
| T1733 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.963165446 |
|
|
Sep 24 08:41:35 AM UTC 24 |
Sep 24 08:41:37 AM UTC 24 |
24927758 ps |
| T236 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_same_csr_outstanding.568532824 |
|
|
Sep 24 08:41:35 AM UTC 24 |
Sep 24 08:41:38 AM UTC 24 |
46581122 ps |
| T290 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_intr_test.1938823730 |
|
|
Sep 24 08:41:36 AM UTC 24 |
Sep 24 08:41:38 AM UTC 24 |
33308549 ps |
| T223 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_aliasing.3648204123 |
|
|
Sep 24 08:41:35 AM UTC 24 |
Sep 24 08:41:38 AM UTC 24 |
75643413 ps |
| T237 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_same_csr_outstanding.3380154205 |
|
|
Sep 24 08:41:36 AM UTC 24 |
Sep 24 08:41:38 AM UTC 24 |
85699644 ps |
| T224 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_csr_rw.4166378348 |
|
|
Sep 24 08:41:36 AM UTC 24 |
Sep 24 08:41:39 AM UTC 24 |
18549783 ps |
| T228 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_bit_bash.33025585 |
|
|
Sep 24 08:41:31 AM UTC 24 |
Sep 24 08:41:39 AM UTC 24 |
353248685 ps |
| T1734 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_bit_bash.2189215912 |
|
|
Sep 24 08:41:34 AM UTC 24 |
Sep 24 08:41:39 AM UTC 24 |
114063221 ps |
| T1735 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_tl_intg_err.2614890118 |
|
|
Sep 24 08:41:36 AM UTC 24 |
Sep 24 08:41:39 AM UTC 24 |
50840693 ps |
| T1736 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.514962623 |
|
|
Sep 24 08:41:38 AM UTC 24 |
Sep 24 08:41:40 AM UTC 24 |
31304864 ps |
| T201 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_tl_errors.386956724 |
|
|
Sep 24 08:41:36 AM UTC 24 |
Sep 24 08:41:40 AM UTC 24 |
505128703 ps |
| T1737 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_intr_test.798939952 |
|
|
Sep 24 08:41:40 AM UTC 24 |
Sep 24 08:41:42 AM UTC 24 |
22922330 ps |
| T1738 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_tl_errors.2482532852 |
|
|
Sep 24 08:41:39 AM UTC 24 |
Sep 24 08:41:42 AM UTC 24 |
245417668 ps |
| T225 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_csr_rw.673629352 |
|
|
Sep 24 08:41:40 AM UTC 24 |
Sep 24 08:41:42 AM UTC 24 |
25959735 ps |
| T1739 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_same_csr_outstanding.2994000447 |
|
|
Sep 24 08:41:40 AM UTC 24 |
Sep 24 08:41:42 AM UTC 24 |
55449141 ps |
| T294 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_intr_test.1634340226 |
|
|
Sep 24 08:41:40 AM UTC 24 |
Sep 24 08:41:42 AM UTC 24 |
17934418 ps |
| T204 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_tl_intg_err.3228786713 |
|
|
Sep 24 08:41:39 AM UTC 24 |
Sep 24 08:41:43 AM UTC 24 |
554415742 ps |
| T1740 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.2629830104 |
|
|
Sep 24 08:41:40 AM UTC 24 |
Sep 24 08:41:43 AM UTC 24 |
72627192 ps |
| T206 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_tl_intg_err.1928317308 |
|
|
Sep 24 08:41:40 AM UTC 24 |
Sep 24 08:41:43 AM UTC 24 |
679708524 ps |
| T1741 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_tl_errors.2441364575 |
|
|
Sep 24 08:41:40 AM UTC 24 |
Sep 24 08:41:43 AM UTC 24 |
187864139 ps |
| T1742 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_csr_rw.1094622777 |
|
|
Sep 24 08:41:41 AM UTC 24 |
Sep 24 08:41:43 AM UTC 24 |
22033665 ps |
| T1743 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.3355118828 |
|
|
Sep 24 08:41:41 AM UTC 24 |
Sep 24 08:41:44 AM UTC 24 |
46057967 ps |
| T1744 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_same_csr_outstanding.2546990300 |
|
|
Sep 24 08:41:41 AM UTC 24 |
Sep 24 08:41:44 AM UTC 24 |
313337805 ps |
| T295 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_intr_test.2062248951 |
|
|
Sep 24 08:41:43 AM UTC 24 |
Sep 24 08:41:45 AM UTC 24 |
20735680 ps |
| T1745 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_csr_rw.1121412298 |
|
|
Sep 24 08:41:43 AM UTC 24 |
Sep 24 08:41:45 AM UTC 24 |
23496262 ps |
| T1746 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_same_csr_outstanding.4025541278 |
|
|
Sep 24 08:41:43 AM UTC 24 |
Sep 24 08:41:45 AM UTC 24 |
22056853 ps |
| T1747 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_tl_errors.220371374 |
|
|
Sep 24 08:41:43 AM UTC 24 |
Sep 24 08:41:45 AM UTC 24 |
94715510 ps |
| T1748 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_tl_intg_err.3388981235 |
|
|
Sep 24 08:41:43 AM UTC 24 |
Sep 24 08:41:46 AM UTC 24 |
84946415 ps |
| T293 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/9.i2c_intr_test.2336310496 |
|
|
Sep 24 08:41:44 AM UTC 24 |
Sep 24 08:41:46 AM UTC 24 |
99499101 ps |
| T1749 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/9.i2c_csr_rw.1661992112 |
|
|
Sep 24 08:41:44 AM UTC 24 |
Sep 24 08:41:46 AM UTC 24 |
66798239 ps |
| T1750 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.1746293446 |
|
|
Sep 24 08:41:44 AM UTC 24 |
Sep 24 08:41:46 AM UTC 24 |
70566849 ps |
| T1751 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/9.i2c_same_csr_outstanding.3403615048 |
|
|
Sep 24 08:41:44 AM UTC 24 |
Sep 24 08:41:47 AM UTC 24 |
58683649 ps |
| T1752 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.1802849760 |
|
|
Sep 24 08:41:44 AM UTC 24 |
Sep 24 08:41:47 AM UTC 24 |
128979914 ps |
| T1753 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_csr_rw.4177860610 |
|
|
Sep 24 08:41:46 AM UTC 24 |
Sep 24 08:41:48 AM UTC 24 |
18150068 ps |
| T207 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/9.i2c_tl_intg_err.3595050174 |
|
|
Sep 24 08:41:44 AM UTC 24 |
Sep 24 08:41:48 AM UTC 24 |
295261573 ps |
| T1754 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/9.i2c_tl_errors.1694077514 |
|
|
Sep 24 08:41:44 AM UTC 24 |
Sep 24 08:41:48 AM UTC 24 |
481261195 ps |
| T287 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_intr_test.3587465954 |
|
|
Sep 24 08:41:47 AM UTC 24 |
Sep 24 08:41:49 AM UTC 24 |
18366996 ps |
| T1755 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.1311643746 |
|
|
Sep 24 08:41:47 AM UTC 24 |
Sep 24 08:41:49 AM UTC 24 |
39058208 ps |
| T1756 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_same_csr_outstanding.3607090272 |
|
|
Sep 24 08:41:47 AM UTC 24 |
Sep 24 08:41:49 AM UTC 24 |
89281576 ps |
| T208 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_tl_intg_err.2388344137 |
|
|
Sep 24 08:41:46 AM UTC 24 |
Sep 24 08:41:50 AM UTC 24 |
1685374868 ps |
| T1757 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_tl_errors.3741571826 |
|
|
Sep 24 08:41:47 AM UTC 24 |
Sep 24 08:41:50 AM UTC 24 |
48403469 ps |
| T1758 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_tl_intg_err.2239862796 |
|
|
Sep 24 08:41:47 AM UTC 24 |
Sep 24 08:41:50 AM UTC 24 |
1214070944 ps |
| T1759 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_same_csr_outstanding.2477033234 |
|
|
Sep 24 08:41:48 AM UTC 24 |
Sep 24 08:41:50 AM UTC 24 |
33992844 ps |
| T1760 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_tl_errors.3017027590 |
|
|
Sep 24 08:41:46 AM UTC 24 |
Sep 24 08:41:50 AM UTC 24 |
86093605 ps |
| T1761 |
/workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.2117976768 |
|
|
Sep 24 08:41:48 AM UTC 24 |
Sep 24 08:41:51 AM UTC 24 |
36451736 ps |