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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
91.18 97.23 89.50 97.22 72.02 94.23 98.47 89.58


Total test records in report: 1848
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html | tests27.html | tests28.html | tests29.html | tests30.html | tests31.html | tests32.html | tests33.html | tests34.html | tests35.html | tests36.html | tests37.html | tests38.html

T850 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/23.i2c_host_perf_precise.2868812589 Oct 09 08:30:35 AM UTC 24 Oct 09 08:30:39 AM UTC 24 237012131 ps
T851 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/23.i2c_host_error_intr.206780377 Oct 09 08:30:36 AM UTC 24 Oct 09 08:30:40 AM UTC 24 100454322 ps
T852 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/23.i2c_host_perf.3022182859 Oct 09 08:30:35 AM UTC 24 Oct 09 08:30:45 AM UTC 24 288633888 ps
T853 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/23.i2c_host_fifo_fmt_empty.524445561 Oct 09 08:30:34 AM UTC 24 Oct 09 08:30:46 AM UTC 24 514411803 ps
T854 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/16.i2c_host_fifo_watermark.2046958117 Oct 09 08:25:46 AM UTC 24 Oct 09 08:30:51 AM UTC 24 17700234479 ps
T855 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/21.i2c_target_intr_stress_wr.1199447066 Oct 09 08:29:30 AM UTC 24 Oct 09 08:30:53 AM UTC 24 28079251915 ps
T856 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/23.i2c_target_smoke.1105830310 Oct 09 08:30:38 AM UTC 24 Oct 09 08:30:54 AM UTC 24 3307890587 ps
T857 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/23.i2c_target_intr_smoke.1827413373 Oct 09 08:30:46 AM UTC 24 Oct 09 08:30:54 AM UTC 24 1175949615 ps
T858 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/23.i2c_host_smoke.369375926 Oct 09 08:30:31 AM UTC 24 Oct 09 08:30:55 AM UTC 24 9632838068 ps
T859 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/23.i2c_host_stretch_timeout.4030516964 Oct 09 08:30:35 AM UTC 24 Oct 09 08:30:55 AM UTC 24 11451171913 ps
T860 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/22.i2c_target_stress_wr.3389453864 Oct 09 08:29:57 AM UTC 24 Oct 09 08:30:57 AM UTC 24 27863941219 ps
T861 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/23.i2c_target_fifo_reset_acq.987060514 Oct 09 08:30:55 AM UTC 24 Oct 09 08:30:57 AM UTC 24 203508879 ps
T862 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/23.i2c_target_fifo_reset_tx.103293796 Oct 09 08:30:56 AM UTC 24 Oct 09 08:30:59 AM UTC 24 222730446 ps
T863 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/22.i2c_host_fifo_full.1351345299 Oct 09 08:29:51 AM UTC 24 Oct 09 08:31:02 AM UTC 24 19547039465 ps
T864 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/23.i2c_target_fifo_watermarks_tx.647458724 Oct 09 08:31:03 AM UTC 24 Oct 09 08:31:06 AM UTC 24 113373744 ps
T865 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/23.i2c_target_timeout.3682058108 Oct 09 08:30:52 AM UTC 24 Oct 09 08:31:06 AM UTC 24 1389211381 ps
T866 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/24.i2c_host_stretch_timeout.1368115183 Oct 09 08:31:16 AM UTC 24 Oct 09 08:31:46 AM UTC 24 2766852171 ps
T867 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/23.i2c_target_perf.216696746 Oct 09 08:30:56 AM UTC 24 Oct 09 08:31:06 AM UTC 24 3623053057 ps
T868 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/23.i2c_target_stretch.4104068530 Oct 09 08:30:41 AM UTC 24 Oct 09 08:31:07 AM UTC 24 3386247487 ps
T869 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/23.i2c_target_bad_addr.981976530 Oct 09 08:30:57 AM UTC 24 Oct 09 08:31:07 AM UTC 24 2000847871 ps
T870 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/23.i2c_target_fifo_watermarks_acq.307170657 Oct 09 08:31:03 AM UTC 24 Oct 09 08:31:07 AM UTC 24 1756358247 ps
T871 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/23.i2c_target_stress_rd.2764303596 Oct 09 08:30:40 AM UTC 24 Oct 09 08:31:08 AM UTC 24 1429956428 ps
T872 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/23.i2c_alert_test.54868029 Oct 09 08:31:08 AM UTC 24 Oct 09 08:31:11 AM UTC 24 14801480 ps
T873 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/23.i2c_target_nack_txstretch.1637337044 Oct 09 08:31:08 AM UTC 24 Oct 09 08:31:12 AM UTC 24 643077300 ps
T144 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/24.i2c_host_override.1818686923 Oct 09 08:31:10 AM UTC 24 Oct 09 08:31:12 AM UTC 24 85886331 ps
T874 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/23.i2c_target_nack_acqfull.776984581 Oct 09 08:31:07 AM UTC 24 Oct 09 08:31:13 AM UTC 24 2871146173 ps
T875 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/23.i2c_target_smbus_maxlen.3102420173 Oct 09 08:31:07 AM UTC 24 Oct 09 08:31:13 AM UTC 24 561933129 ps
T876 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/23.i2c_target_tx_stretch_ctrl.594855135 Oct 09 08:31:05 AM UTC 24 Oct 09 08:31:13 AM UTC 24 420454966 ps
T877 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/23.i2c_target_nack_acqfull_addr.1970691025 Oct 09 08:31:07 AM UTC 24 Oct 09 08:31:13 AM UTC 24 569404474 ps
T249 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/23.i2c_host_may_nack.416631585 Oct 09 08:31:00 AM UTC 24 Oct 09 08:31:14 AM UTC 24 586876659 ps
T878 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/24.i2c_host_fifo_reset_fmt.2231698631 Oct 09 08:31:13 AM UTC 24 Oct 09 08:31:15 AM UTC 24 122456343 ps
T879 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/12.i2c_target_stress_all.520716787 Oct 09 08:23:00 AM UTC 24 Oct 09 08:31:17 AM UTC 24 28341932287 ps
T880 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/24.i2c_host_error_intr.2486726587 Oct 09 08:31:17 AM UTC 24 Oct 09 08:31:20 AM UTC 24 124427337 ps
T118 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/21.i2c_host_fifo_watermark.3709798105 Oct 09 08:29:20 AM UTC 24 Oct 09 08:31:23 AM UTC 24 6015944337 ps
T881 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/23.i2c_target_stress_wr.3344208512 Oct 09 08:30:40 AM UTC 24 Oct 09 08:31:25 AM UTC 24 19285005083 ps
T882 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/20.i2c_host_fifo_full.1588869846 Oct 09 08:28:48 AM UTC 24 Oct 09 08:31:26 AM UTC 24 3068067997 ps
T883 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/24.i2c_host_fifo_reset_rx.2859376207 Oct 09 08:31:14 AM UTC 24 Oct 09 08:31:29 AM UTC 24 187809952 ps
T884 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/24.i2c_host_fifo_fmt_empty.1819730624 Oct 09 08:31:13 AM UTC 24 Oct 09 08:31:37 AM UTC 24 758518433 ps
T180 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/15.i2c_host_stress_all.987280926 Oct 09 08:25:05 AM UTC 24 Oct 09 08:31:40 AM UTC 24 14154513961 ps
T885 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/23.i2c_host_fifo_overflow.1181213696 Oct 09 08:30:34 AM UTC 24 Oct 09 08:31:42 AM UTC 24 1997365083 ps
T886 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/23.i2c_target_stress_all.3624484255 Oct 09 08:30:56 AM UTC 24 Oct 09 08:31:42 AM UTC 24 17897142456 ps
T887 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/24.i2c_target_intr_smoke.676346710 Oct 09 08:31:30 AM UTC 24 Oct 09 08:31:42 AM UTC 24 5707200790 ps
T888 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/24.i2c_target_intr_stress_wr.3471311514 Oct 09 08:31:38 AM UTC 24 Oct 09 08:31:45 AM UTC 24 9417212396 ps
T889 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/24.i2c_target_fifo_reset_tx.3955014951 Oct 09 08:31:43 AM UTC 24 Oct 09 08:31:47 AM UTC 24 307831547 ps
T890 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/23.i2c_target_intr_stress_wr.1294348302 Oct 09 08:30:46 AM UTC 24 Oct 09 08:31:48 AM UTC 24 23473907893 ps
T891 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/18.i2c_host_fifo_watermark.2113169619 Oct 09 08:27:20 AM UTC 24 Oct 09 08:31:48 AM UTC 24 33108069073 ps
T119 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/22.i2c_host_fifo_watermark.4112231545 Oct 09 08:29:49 AM UTC 24 Oct 09 08:31:49 AM UTC 24 18941112567 ps
T892 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/24.i2c_target_timeout.1025321235 Oct 09 08:31:41 AM UTC 24 Oct 09 08:31:54 AM UTC 24 1362729457 ps
T893 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/24.i2c_target_fifo_watermarks_tx.1153721611 Oct 09 08:31:52 AM UTC 24 Oct 09 08:31:54 AM UTC 24 75857301 ps
T79 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/24.i2c_host_mode_toggle.1798528566 Oct 09 08:31:52 AM UTC 24 Oct 09 08:31:55 AM UTC 24 84545300 ps
T894 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/24.i2c_target_smoke.2744298519 Oct 09 08:31:21 AM UTC 24 Oct 09 08:31:56 AM UTC 24 1062275778 ps
T895 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/24.i2c_target_smbus_maxlen.2978826567 Oct 09 08:31:52 AM UTC 24 Oct 09 08:31:56 AM UTC 24 566352516 ps
T896 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/24.i2c_target_tx_stretch_ctrl.3762294458 Oct 09 08:31:52 AM UTC 24 Oct 09 08:31:57 AM UTC 24 151246585 ps
T897 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/24.i2c_target_perf.3887271717 Oct 09 08:31:50 AM UTC 24 Oct 09 08:31:57 AM UTC 24 3629511107 ps
T898 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/24.i2c_target_fifo_watermarks_acq.1628109578 Oct 09 08:31:52 AM UTC 24 Oct 09 08:31:58 AM UTC 24 2099478641 ps
T899 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/24.i2c_target_nack_txstretch.3241060832 Oct 09 08:31:56 AM UTC 24 Oct 09 08:32:00 AM UTC 24 150617759 ps
T145 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/25.i2c_host_override.2918594187 Oct 09 08:31:58 AM UTC 24 Oct 09 08:32:00 AM UTC 24 30845000 ps
T900 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/24.i2c_alert_test.510902788 Oct 09 08:31:57 AM UTC 24 Oct 09 08:32:00 AM UTC 24 39179212 ps
T901 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/24.i2c_target_bad_addr.4246950566 Oct 09 08:31:51 AM UTC 24 Oct 09 08:32:01 AM UTC 24 1622221345 ps
T902 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/24.i2c_target_nack_acqfull_addr.4066256159 Oct 09 08:31:55 AM UTC 24 Oct 09 08:32:01 AM UTC 24 2371787473 ps
T903 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/24.i2c_target_nack_acqfull.4288371564 Oct 09 08:31:55 AM UTC 24 Oct 09 08:32:01 AM UTC 24 1192525193 ps
T257 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/24.i2c_host_may_nack.3703224136 Oct 09 08:31:52 AM UTC 24 Oct 09 08:32:02 AM UTC 24 394106439 ps
T904 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/20.i2c_host_perf_precise.3084443522 Oct 09 08:28:49 AM UTC 24 Oct 09 08:32:02 AM UTC 24 23575787238 ps
T905 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/25.i2c_host_fifo_reset_fmt.2670562213 Oct 09 08:32:01 AM UTC 24 Oct 09 08:32:04 AM UTC 24 234585619 ps
T906 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/9.i2c_host_perf.2778631751 Oct 09 08:19:14 AM UTC 24 Oct 09 08:32:05 AM UTC 24 50294218751 ps
T907 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/25.i2c_host_perf_precise.2754092019 Oct 09 08:32:03 AM UTC 24 Oct 09 08:32:06 AM UTC 24 222818228 ps
T908 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/25.i2c_host_fifo_reset_rx.650519238 Oct 09 08:32:01 AM UTC 24 Oct 09 08:32:07 AM UTC 24 192796414 ps
T909 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/25.i2c_host_error_intr.1776195138 Oct 09 08:32:04 AM UTC 24 Oct 09 08:32:08 AM UTC 24 544411224 ps
T910 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/25.i2c_target_stretch.2901076284 Oct 09 08:32:09 AM UTC 24 Oct 09 08:32:13 AM UTC 24 1562830027 ps
T911 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/26.i2c_alert_test.2619447081 Oct 09 08:33:02 AM UTC 24 Oct 09 08:33:04 AM UTC 24 44115964 ps
T912 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/21.i2c_host_perf.619045946 Oct 09 08:29:21 AM UTC 24 Oct 09 08:32:15 AM UTC 24 6587205612 ps
T913 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/24.i2c_host_fifo_full.980914493 Oct 09 08:31:14 AM UTC 24 Oct 09 08:32:16 AM UTC 24 4670115650 ps
T914 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/20.i2c_target_stress_all.2248470219 Oct 09 08:29:07 AM UTC 24 Oct 09 08:32:17 AM UTC 24 74766645808 ps
T915 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/23.i2c_host_fifo_full.2912058284 Oct 09 08:30:34 AM UTC 24 Oct 09 08:32:19 AM UTC 24 3859238885 ps
T916 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/24.i2c_host_smoke.2929588404 Oct 09 08:31:08 AM UTC 24 Oct 09 08:32:19 AM UTC 24 24647464513 ps
T917 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/7.i2c_host_perf_precise.4180023967 Oct 09 08:17:23 AM UTC 24 Oct 09 08:32:19 AM UTC 24 24336339162 ps
T918 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/25.i2c_target_smoke.1654572381 Oct 09 08:32:06 AM UTC 24 Oct 09 08:32:20 AM UTC 24 3406331510 ps
T919 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/25.i2c_target_fifo_reset_tx.3096323174 Oct 09 08:32:18 AM UTC 24 Oct 09 08:32:20 AM UTC 24 278313929 ps
T920 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/25.i2c_target_fifo_reset_acq.4239172635 Oct 09 08:32:17 AM UTC 24 Oct 09 08:32:21 AM UTC 24 244344904 ps
T921 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/25.i2c_host_fifo_fmt_empty.2171327121 Oct 09 08:32:01 AM UTC 24 Oct 09 08:32:21 AM UTC 24 284173692 ps
T922 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/25.i2c_target_intr_smoke.587617425 Oct 09 08:32:10 AM UTC 24 Oct 09 08:32:21 AM UTC 24 11631984896 ps
T923 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/25.i2c_host_smoke.530379814 Oct 09 08:31:58 AM UTC 24 Oct 09 08:32:23 AM UTC 24 3389678340 ps
T924 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/17.i2c_target_intr_stress_wr.580882568 Oct 09 08:26:54 AM UTC 24 Oct 09 08:32:23 AM UTC 24 20761504734 ps
T925 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/25.i2c_target_fifo_watermarks_tx.1651024110 Oct 09 08:32:22 AM UTC 24 Oct 09 08:32:25 AM UTC 24 164647333 ps
T926 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/25.i2c_target_tx_stretch_ctrl.3056089500 Oct 09 08:32:22 AM UTC 24 Oct 09 08:32:25 AM UTC 24 48558183 ps
T927 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/22.i2c_host_fifo_overflow.3387923847 Oct 09 08:29:49 AM UTC 24 Oct 09 08:32:25 AM UTC 24 9676923711 ps
T928 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/24.i2c_host_fifo_overflow.3648983391 Oct 09 08:31:13 AM UTC 24 Oct 09 08:32:25 AM UTC 24 7061922167 ps
T929 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/25.i2c_target_perf.4111849951 Oct 09 08:32:19 AM UTC 24 Oct 09 08:32:26 AM UTC 24 1108915934 ps
T930 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/25.i2c_target_bad_addr.3214660238 Oct 09 08:32:20 AM UTC 24 Oct 09 08:32:28 AM UTC 24 2129866108 ps
T931 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/25.i2c_target_timeout.1612547325 Oct 09 08:32:17 AM UTC 24 Oct 09 08:32:28 AM UTC 24 2524819851 ps
T932 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/25.i2c_alert_test.3716960916 Oct 09 08:32:27 AM UTC 24 Oct 09 08:32:29 AM UTC 24 43874395 ps
T933 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/26.i2c_host_override.1200314414 Oct 09 08:32:27 AM UTC 24 Oct 09 08:32:29 AM UTC 24 26181926 ps
T934 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/25.i2c_target_nack_txstretch.826925046 Oct 09 08:32:25 AM UTC 24 Oct 09 08:32:29 AM UTC 24 147345100 ps
T935 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/25.i2c_target_fifo_watermarks_acq.3933237108 Oct 09 08:32:22 AM UTC 24 Oct 09 08:32:29 AM UTC 24 1269087543 ps
T936 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/25.i2c_target_nack_acqfull.3063691202 Oct 09 08:32:24 AM UTC 24 Oct 09 08:32:30 AM UTC 24 1040030644 ps
T937 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/25.i2c_target_stress_rd.450317519 Oct 09 08:32:08 AM UTC 24 Oct 09 08:32:30 AM UTC 24 359616830 ps
T938 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/25.i2c_target_smbus_maxlen.3213385487 Oct 09 08:32:24 AM UTC 24 Oct 09 08:32:30 AM UTC 24 513924312 ps
T939 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/25.i2c_target_nack_acqfull_addr.4101759497 Oct 09 08:32:25 AM UTC 24 Oct 09 08:32:31 AM UTC 24 462758078 ps
T940 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/25.i2c_host_may_nack.1085745845 Oct 09 08:32:22 AM UTC 24 Oct 09 08:32:31 AM UTC 24 519549101 ps
T941 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/25.i2c_host_stretch_timeout.4139549751 Oct 09 08:32:03 AM UTC 24 Oct 09 08:32:31 AM UTC 24 1060396835 ps
T942 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/26.i2c_host_fifo_reset_fmt.760042244 Oct 09 08:32:29 AM UTC 24 Oct 09 08:32:31 AM UTC 24 103108547 ps
T943 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/26.i2c_host_error_intr.3208062495 Oct 09 08:32:32 AM UTC 24 Oct 09 08:32:35 AM UTC 24 68555097 ps
T944 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/26.i2c_host_perf_precise.2326155176 Oct 09 08:32:31 AM UTC 24 Oct 09 08:32:38 AM UTC 24 220557748 ps
T945 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/26.i2c_host_fifo_reset_rx.1207078098 Oct 09 08:32:30 AM UTC 24 Oct 09 08:32:38 AM UTC 24 249549249 ps
T946 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/26.i2c_host_perf.265567034 Oct 09 08:32:31 AM UTC 24 Oct 09 08:32:41 AM UTC 24 662905380 ps
T947 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/26.i2c_target_smoke.71754378 Oct 09 08:32:32 AM UTC 24 Oct 09 08:32:44 AM UTC 24 2467310693 ps
T948 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/26.i2c_target_stretch.1466803281 Oct 09 08:32:36 AM UTC 24 Oct 09 08:32:44 AM UTC 24 2118784882 ps
T949 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/26.i2c_host_stretch_timeout.504777060 Oct 09 08:32:32 AM UTC 24 Oct 09 08:32:47 AM UTC 24 3228377817 ps
T950 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/26.i2c_target_fifo_reset_tx.2598882731 Oct 09 08:32:45 AM UTC 24 Oct 09 08:32:48 AM UTC 24 278432513 ps
T951 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/26.i2c_target_fifo_reset_acq.3977215547 Oct 09 08:32:45 AM UTC 24 Oct 09 08:32:48 AM UTC 24 677349228 ps
T952 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/26.i2c_target_intr_smoke.4003876735 Oct 09 08:32:38 AM UTC 24 Oct 09 08:32:49 AM UTC 24 2423392163 ps
T953 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/26.i2c_host_fifo_fmt_empty.3292854699 Oct 09 08:32:29 AM UTC 24 Oct 09 08:32:49 AM UTC 24 1075113748 ps
T954 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/26.i2c_target_timeout.795581054 Oct 09 08:32:40 AM UTC 24 Oct 09 08:32:53 AM UTC 24 2963335561 ps
T955 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/26.i2c_target_perf.851533366 Oct 09 08:32:47 AM UTC 24 Oct 09 08:32:54 AM UTC 24 1147958692 ps
T956 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/26.i2c_target_fifo_watermarks_tx.1051682629 Oct 09 08:32:54 AM UTC 24 Oct 09 08:32:57 AM UTC 24 565209849 ps
T957 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/26.i2c_target_fifo_watermarks_acq.3021655235 Oct 09 08:32:53 AM UTC 24 Oct 09 08:32:58 AM UTC 24 2567552650 ps
T958 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/26.i2c_target_bad_addr.3344317393 Oct 09 08:32:49 AM UTC 24 Oct 09 08:32:59 AM UTC 24 739596485 ps
T959 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/26.i2c_host_may_nack.3461308863 Oct 09 08:32:50 AM UTC 24 Oct 09 08:33:01 AM UTC 24 633227237 ps
T960 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/26.i2c_target_tx_stretch_ctrl.2337740846 Oct 09 08:32:55 AM UTC 24 Oct 09 08:33:02 AM UTC 24 318007419 ps
T961 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/19.i2c_target_intr_stress_wr.2611501716 Oct 09 08:28:29 AM UTC 24 Oct 09 08:33:03 AM UTC 24 16849548517 ps
T962 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/26.i2c_host_smoke.2181315468 Oct 09 08:32:27 AM UTC 24 Oct 09 08:33:03 AM UTC 24 8921130353 ps
T963 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/26.i2c_target_smbus_maxlen.3877905120 Oct 09 08:32:58 AM UTC 24 Oct 09 08:33:04 AM UTC 24 2101222917 ps
T55 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/26.i2c_target_nack_acqfull.1831416770 Oct 09 08:32:59 AM UTC 24 Oct 09 08:33:04 AM UTC 24 1330759964 ps
T964 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/26.i2c_target_nack_txstretch.1418583013 Oct 09 08:33:01 AM UTC 24 Oct 09 08:33:04 AM UTC 24 269413142 ps
T965 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/26.i2c_target_nack_acqfull_addr.3005921269 Oct 09 08:32:59 AM UTC 24 Oct 09 08:33:05 AM UTC 24 1917945648 ps
T966 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/27.i2c_host_override.3062027354 Oct 09 08:33:04 AM UTC 24 Oct 09 08:33:06 AM UTC 24 82031668 ps
T967 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/27.i2c_host_fifo_reset_fmt.241940167 Oct 09 08:33:05 AM UTC 24 Oct 09 08:33:09 AM UTC 24 143621441 ps
T968 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/26.i2c_target_stress_rd.58358067 Oct 09 08:32:32 AM UTC 24 Oct 09 08:33:09 AM UTC 24 5944008536 ps
T969 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/24.i2c_host_fifo_watermark.3100354372 Oct 09 08:31:12 AM UTC 24 Oct 09 08:33:12 AM UTC 24 4518317975 ps
T970 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/27.i2c_host_fifo_reset_rx.337151940 Oct 09 08:33:05 AM UTC 24 Oct 09 08:33:12 AM UTC 24 144623400 ps
T971 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/22.i2c_host_perf.1893430084 Oct 09 08:29:51 AM UTC 24 Oct 09 08:33:14 AM UTC 24 30164290493 ps
T972 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/27.i2c_host_perf_precise.4036637416 Oct 09 08:33:07 AM UTC 24 Oct 09 08:33:14 AM UTC 24 1220678194 ps
T973 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/25.i2c_host_fifo_overflow.4150599492 Oct 09 08:31:59 AM UTC 24 Oct 09 08:33:16 AM UTC 24 4710983075 ps
T974 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/27.i2c_host_error_intr.645641170 Oct 09 08:33:10 AM UTC 24 Oct 09 08:33:16 AM UTC 24 1430082177 ps
T975 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/21.i2c_host_fifo_full.3141741916 Oct 09 08:29:21 AM UTC 24 Oct 09 08:33:18 AM UTC 24 3636730293 ps
T976 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/25.i2c_target_stress_all.806168385 Oct 09 08:32:20 AM UTC 24 Oct 09 08:33:21 AM UTC 24 27164126869 ps
T181 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/4.i2c_host_stress_all.816242366 Oct 09 08:13:59 AM UTC 24 Oct 09 08:33:22 AM UTC 24 130555969006 ps
T977 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/27.i2c_host_fifo_fmt_empty.75324990 Oct 09 08:33:05 AM UTC 24 Oct 09 08:33:22 AM UTC 24 426070664 ps
T978 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/26.i2c_target_intr_stress_wr.239735577 Oct 09 08:32:40 AM UTC 24 Oct 09 08:33:24 AM UTC 24 10636868883 ps
T979 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/27.i2c_target_intr_smoke.2383085269 Oct 09 08:33:18 AM UTC 24 Oct 09 08:33:27 AM UTC 24 809605881 ps
T980 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/27.i2c_target_fifo_reset_acq.1111118477 Oct 09 08:33:23 AM UTC 24 Oct 09 08:33:27 AM UTC 24 223416661 ps
T981 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/27.i2c_target_fifo_reset_tx.1737466454 Oct 09 08:33:23 AM UTC 24 Oct 09 08:33:27 AM UTC 24 2122680339 ps
T982 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/27.i2c_host_stretch_timeout.3687470662 Oct 09 08:33:10 AM UTC 24 Oct 09 08:33:28 AM UTC 24 1413062981 ps
T983 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/27.i2c_target_stress_rd.750202578 Oct 09 08:33:14 AM UTC 24 Oct 09 08:33:30 AM UTC 24 834898501 ps
T984 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/25.i2c_host_perf.3137255293 Oct 09 08:32:02 AM UTC 24 Oct 09 08:33:30 AM UTC 24 8439439412 ps
T985 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/27.i2c_target_timeout.583899380 Oct 09 08:33:19 AM UTC 24 Oct 09 08:33:31 AM UTC 24 1637521212 ps
T986 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/27.i2c_target_hrst.272307606 Oct 09 08:33:28 AM UTC 24 Oct 09 08:33:32 AM UTC 24 1033152411 ps
T987 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/27.i2c_target_bad_addr.116997003 Oct 09 08:33:28 AM UTC 24 Oct 09 08:33:32 AM UTC 24 1825078125 ps
T988 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/9.i2c_target_stress_all.2641828550 Oct 09 08:20:02 AM UTC 24 Oct 09 08:33:33 AM UTC 24 45452519594 ps
T989 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/27.i2c_target_fifo_watermarks_acq.1122999136 Oct 09 08:33:30 AM UTC 24 Oct 09 08:33:34 AM UTC 24 342236485 ps
T990 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/27.i2c_target_perf.1361681045 Oct 09 08:33:25 AM UTC 24 Oct 09 08:33:34 AM UTC 24 4229059822 ps
T991 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/27.i2c_target_fifo_watermarks_tx.2480982160 Oct 09 08:33:31 AM UTC 24 Oct 09 08:33:35 AM UTC 24 162484138 ps
T992 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/27.i2c_alert_test.3870644746 Oct 09 08:33:35 AM UTC 24 Oct 09 08:33:37 AM UTC 24 23244933 ps
T993 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/27.i2c_target_nack_txstretch.171658023 Oct 09 08:33:34 AM UTC 24 Oct 09 08:33:37 AM UTC 24 137025672 ps
T994 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/25.i2c_host_fifo_full.1189147541 Oct 09 08:32:02 AM UTC 24 Oct 09 08:33:37 AM UTC 24 3166822788 ps
T995 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/27.i2c_target_smbus_maxlen.315943694 Oct 09 08:33:32 AM UTC 24 Oct 09 08:33:38 AM UTC 24 4745287449 ps
T996 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/27.i2c_target_nack_acqfull_addr.1912581006 Oct 09 08:33:34 AM UTC 24 Oct 09 08:33:38 AM UTC 24 516946333 ps
T997 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/28.i2c_host_override.40228388 Oct 09 08:33:36 AM UTC 24 Oct 09 08:33:38 AM UTC 24 46117241 ps
T998 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/27.i2c_target_stretch.3352421692 Oct 09 08:33:15 AM UTC 24 Oct 09 08:33:39 AM UTC 24 2878496881 ps
T999 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/27.i2c_target_nack_acqfull.3374780601 Oct 09 08:33:33 AM UTC 24 Oct 09 08:33:39 AM UTC 24 2676337338 ps
T1000 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/27.i2c_target_tx_stretch_ctrl.483780548 Oct 09 08:33:31 AM UTC 24 Oct 09 08:33:39 AM UTC 24 354722250 ps
T1001 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/27.i2c_target_intr_stress_wr.2194161426 Oct 09 08:33:18 AM UTC 24 Oct 09 08:33:41 AM UTC 24 4479853623 ps
T1002 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/28.i2c_host_fifo_reset_fmt.4104453720 Oct 09 08:33:38 AM UTC 24 Oct 09 08:33:41 AM UTC 24 291081156 ps
T1003 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/28.i2c_host_fifo_reset_rx.921324395 Oct 09 08:33:40 AM UTC 24 Oct 09 08:33:48 AM UTC 24 608218655 ps
T236 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/2.i2c_host_stress_all.14193991 Oct 09 08:10:29 AM UTC 24 Oct 09 08:33:50 AM UTC 24 82805101566 ps
T250 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/27.i2c_host_may_nack.3769098128 Oct 09 08:33:29 AM UTC 24 Oct 09 08:33:50 AM UTC 24 1525676149 ps
T1004 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/28.i2c_host_error_intr.1341433376 Oct 09 08:33:42 AM UTC 24 Oct 09 08:33:51 AM UTC 24 984634206 ps
T1005 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/28.i2c_host_perf.2846192201 Oct 09 08:33:40 AM UTC 24 Oct 09 08:33:51 AM UTC 24 422382764 ps
T1006 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/26.i2c_target_stress_wr.158719116 Oct 09 08:32:32 AM UTC 24 Oct 09 08:33:55 AM UTC 24 37299914363 ps
T1007 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/28.i2c_target_intr_stress_wr.3838723511 Oct 09 08:33:53 AM UTC 24 Oct 09 08:33:57 AM UTC 24 913934597 ps
T1008 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/28.i2c_host_perf_precise.1330876353 Oct 09 08:33:40 AM UTC 24 Oct 09 08:33:57 AM UTC 24 702546559 ps
T1009 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/27.i2c_target_smoke.1613467221 Oct 09 08:33:13 AM UTC 24 Oct 09 08:33:58 AM UTC 24 1320107415 ps
T1010 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/27.i2c_host_smoke.1454810942 Oct 09 08:33:03 AM UTC 24 Oct 09 08:33:59 AM UTC 24 5548561876 ps
T1011 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/28.i2c_target_fifo_reset_acq.3743933913 Oct 09 08:33:58 AM UTC 24 Oct 09 08:34:01 AM UTC 24 388949389 ps
T1012 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/28.i2c_host_stretch_timeout.1775423886 Oct 09 08:33:40 AM UTC 24 Oct 09 08:34:01 AM UTC 24 2154171955 ps
T1013 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/27.i2c_host_fifo_full.2480482605 Oct 09 08:33:06 AM UTC 24 Oct 09 08:34:02 AM UTC 24 4320130368 ps
T1014 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/28.i2c_host_fifo_fmt_empty.2289522563 Oct 09 08:33:38 AM UTC 24 Oct 09 08:34:02 AM UTC 24 918259807 ps
T87 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/28.i2c_target_fifo_reset_tx.3318355773 Oct 09 08:33:59 AM UTC 24 Oct 09 08:34:03 AM UTC 24 286658895 ps
T1015 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/28.i2c_target_intr_smoke.2443848079 Oct 09 08:33:52 AM UTC 24 Oct 09 08:34:04 AM UTC 24 950139992 ps
T1016 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/27.i2c_host_fifo_overflow.2384285397 Oct 09 08:33:04 AM UTC 24 Oct 09 08:34:04 AM UTC 24 13386628655 ps
T1017 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/28.i2c_target_smoke.3650240693 Oct 09 08:33:49 AM UTC 24 Oct 09 08:34:05 AM UTC 24 941778694 ps
T1018 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/28.i2c_target_timeout.2353810438 Oct 09 08:33:56 AM UTC 24 Oct 09 08:34:06 AM UTC 24 1159101988 ps
T1019 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/28.i2c_target_fifo_watermarks_tx.2980251256 Oct 09 08:34:04 AM UTC 24 Oct 09 08:34:07 AM UTC 24 372317724 ps
T1020 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/28.i2c_host_mode_toggle.2797827689 Oct 09 08:34:03 AM UTC 24 Oct 09 08:34:07 AM UTC 24 82210578 ps
T1021 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/28.i2c_target_perf.500731726 Oct 09 08:34:00 AM UTC 24 Oct 09 08:34:08 AM UTC 24 1328904054 ps
T1022 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/28.i2c_target_tx_stretch_ctrl.4176508390 Oct 09 08:34:06 AM UTC 24 Oct 09 08:34:10 AM UTC 24 152774994 ps
T120 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/26.i2c_host_fifo_watermark.3900576338 Oct 09 08:32:28 AM UTC 24 Oct 09 08:34:10 AM UTC 24 4275496852 ps
T1023 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/28.i2c_target_bad_addr.3559410686 Oct 09 08:34:02 AM UTC 24 Oct 09 08:34:11 AM UTC 24 4030966717 ps
T1024 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/28.i2c_target_fifo_watermarks_acq.713117641 Oct 09 08:34:04 AM UTC 24 Oct 09 08:34:11 AM UTC 24 2844862273 ps
T1025 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/28.i2c_alert_test.1619824235 Oct 09 08:34:09 AM UTC 24 Oct 09 08:34:11 AM UTC 24 49389308 ps
T1026 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/29.i2c_host_error_intr.2378265399 Oct 09 08:34:16 AM UTC 24 Oct 09 08:34:20 AM UTC 24 93522702 ps
T1027 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/28.i2c_target_smbus_maxlen.3102376589 Oct 09 08:34:07 AM UTC 24 Oct 09 08:34:12 AM UTC 24 514055933 ps
T1028 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/28.i2c_target_nack_acqfull.3651592521 Oct 09 08:34:07 AM UTC 24 Oct 09 08:34:12 AM UTC 24 543326854 ps
T1029 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/28.i2c_target_nack_acqfull_addr.2762381350 Oct 09 08:34:08 AM UTC 24 Oct 09 08:34:12 AM UTC 24 1930796180 ps
T291 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/22.i2c_target_stress_all.3115167069 Oct 09 08:30:18 AM UTC 24 Oct 09 08:34:13 AM UTC 24 62301019150 ps
T1030 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/29.i2c_host_override.599697810 Oct 09 08:34:11 AM UTC 24 Oct 09 08:34:14 AM UTC 24 37115411 ps
T1031 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/29.i2c_host_fifo_reset_fmt.458785211 Oct 09 08:34:13 AM UTC 24 Oct 09 08:34:15 AM UTC 24 96723230 ps
T1032 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/26.i2c_host_fifo_overflow.1824813590 Oct 09 08:32:29 AM UTC 24 Oct 09 08:34:17 AM UTC 24 5484088015 ps
T1033 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/29.i2c_host_fifo_fmt_empty.1643337641 Oct 09 08:34:13 AM UTC 24 Oct 09 08:34:23 AM UTC 24 1273374433 ps
T1034 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/29.i2c_host_fifo_reset_rx.3467649335 Oct 09 08:34:13 AM UTC 24 Oct 09 08:34:23 AM UTC 24 236358540 ps
T1035 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/28.i2c_host_may_nack.2941585838 Oct 09 08:34:03 AM UTC 24 Oct 09 08:34:23 AM UTC 24 735083788 ps
T1036 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/29.i2c_host_stretch_timeout.3476218526 Oct 09 08:34:14 AM UTC 24 Oct 09 08:34:25 AM UTC 24 1770728306 ps
T1037 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/14.i2c_target_stress_wr.3137332180 Oct 09 08:24:33 AM UTC 24 Oct 09 08:34:30 AM UTC 24 63410890967 ps
T1038 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/29.i2c_target_stress_wr.3565784645 Oct 09 08:34:24 AM UTC 24 Oct 09 08:34:33 AM UTC 24 16942039186 ps
T1039 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/28.i2c_host_smoke.3239380929 Oct 09 08:33:36 AM UTC 24 Oct 09 08:34:33 AM UTC 24 2753110091 ps
T1040 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/23.i2c_host_fifo_watermark.757874599 Oct 09 08:30:32 AM UTC 24 Oct 09 08:34:34 AM UTC 24 4288637686 ps
T1041 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/29.i2c_target_fifo_reset_acq.2067039358 Oct 09 08:34:35 AM UTC 24 Oct 09 08:34:37 AM UTC 24 152402802 ps
T1042 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/29.i2c_target_stress_rd.3623392911 Oct 09 08:34:24 AM UTC 24 Oct 09 08:34:38 AM UTC 24 502023073 ps
T1043 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/29.i2c_target_smoke.1537906929 Oct 09 08:34:21 AM UTC 24 Oct 09 08:34:38 AM UTC 24 889066516 ps
T1044 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/29.i2c_target_fifo_reset_tx.994514156 Oct 09 08:34:36 AM UTC 24 Oct 09 08:34:39 AM UTC 24 766405963 ps
T1045 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/28.i2c_target_stress_rd.2480979674 Oct 09 08:33:51 AM UTC 24 Oct 09 08:34:40 AM UTC 24 3771961610 ps
T1046 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/29.i2c_target_intr_smoke.481095692 Oct 09 08:34:25 AM UTC 24 Oct 09 08:34:40 AM UTC 24 10178575342 ps
T1047 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/24.i2c_target_stretch.2258869656 Oct 09 08:31:27 AM UTC 24 Oct 09 08:34:41 AM UTC 24 4328932484 ps
T1048 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/24.i2c_host_perf_precise.3222424167 Oct 09 08:31:14 AM UTC 24 Oct 09 08:34:44 AM UTC 24 24577627879 ps
T1049 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/29.i2c_target_fifo_watermarks_acq.767313167 Oct 09 08:34:41 AM UTC 24 Oct 09 08:34:44 AM UTC 24 157275440 ps
T1050 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/29.i2c_target_fifo_watermarks_tx.1025393549 Oct 09 08:34:42 AM UTC 24 Oct 09 08:34:45 AM UTC 24 102814272 ps
T1051 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/29.i2c_target_timeout.2342161241 Oct 09 08:34:34 AM UTC 24 Oct 09 08:34:46 AM UTC 24 25750128690 ps
T1052 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/29.i2c_target_nack_acqfull_addr.2424756021 Oct 09 08:34:45 AM UTC 24 Oct 09 08:34:50 AM UTC 24 1065372260 ps
T1053 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/29.i2c_target_bad_addr.3500127956 Oct 09 08:34:39 AM UTC 24 Oct 09 08:34:50 AM UTC 24 2546155525 ps
T1054 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/29.i2c_target_perf.47739097 Oct 09 08:34:38 AM UTC 24 Oct 09 08:34:50 AM UTC 24 2115881974 ps
T1055 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/29.i2c_target_nack_txstretch.4143999840 Oct 09 08:34:47 AM UTC 24 Oct 09 08:34:50 AM UTC 24 506710720 ps
T1056 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/29.i2c_target_smbus_maxlen.1745811628 Oct 09 08:34:45 AM UTC 24 Oct 09 08:34:51 AM UTC 24 536753965 ps
T1057 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/29.i2c_target_tx_stretch_ctrl.3849444802 Oct 09 08:34:45 AM UTC 24 Oct 09 08:34:51 AM UTC 24 262631071 ps
T1058 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/29.i2c_target_nack_acqfull.2115283079 Oct 09 08:34:45 AM UTC 24 Oct 09 08:34:52 AM UTC 24 3180553824 ps
T1059 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/29.i2c_alert_test.2719195571 Oct 09 08:34:51 AM UTC 24 Oct 09 08:34:53 AM UTC 24 34120089 ps
T1060 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/30.i2c_host_override.2195774817 Oct 09 08:34:51 AM UTC 24 Oct 09 08:34:53 AM UTC 24 82884823 ps
T1061 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/29.i2c_host_may_nack.2987740295 Oct 09 08:34:41 AM UTC 24 Oct 09 08:34:55 AM UTC 24 1112610325 ps
T1062 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/30.i2c_host_fifo_reset_fmt.2574507554 Oct 09 08:34:52 AM UTC 24 Oct 09 08:34:56 AM UTC 24 718397759 ps
T1063 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/28.i2c_target_stretch.3608171293 Oct 09 08:33:52 AM UTC 24 Oct 09 08:34:58 AM UTC 24 5683991999 ps
T1064 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/30.i2c_host_perf_precise.2541612972 Oct 09 08:34:56 AM UTC 24 Oct 09 08:35:01 AM UTC 24 266158472 ps
T1065 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/30.i2c_host_fifo_reset_rx.1534704815 Oct 09 08:34:54 AM UTC 24 Oct 09 08:35:05 AM UTC 24 134840583 ps
T1066 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/28.i2c_host_fifo_overflow.3150302234 Oct 09 08:33:38 AM UTC 24 Oct 09 08:35:08 AM UTC 24 1398552322 ps
T1067 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/30.i2c_host_error_intr.3375868759 Oct 09 08:34:59 AM UTC 24 Oct 09 08:35:08 AM UTC 24 309438209 ps
T1068 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/29.i2c_target_stretch.2408101732 Oct 09 08:34:24 AM UTC 24 Oct 09 08:35:12 AM UTC 24 3836912496 ps
T1069 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/29.i2c_target_intr_stress_wr.1887263710 Oct 09 08:34:31 AM UTC 24 Oct 09 08:35:13 AM UTC 24 9422011784 ps
T1070 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/30.i2c_target_stretch.4161667475 Oct 09 08:35:13 AM UTC 24 Oct 09 08:35:16 AM UTC 24 297060695 ps
T1071 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/30.i2c_target_stress_wr.139315389 Oct 09 08:35:09 AM UTC 24 Oct 09 08:35:18 AM UTC 24 12762703194 ps
T1072 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/29.i2c_host_fifo_overflow.7631410 Oct 09 08:34:12 AM UTC 24 Oct 09 08:36:00 AM UTC 24 10622770690 ps
T1073 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/30.i2c_target_smoke.1343428690 Oct 09 08:35:05 AM UTC 24 Oct 09 08:35:19 AM UTC 24 807626624 ps
T1074 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/30.i2c_host_fifo_fmt_empty.2644802871 Oct 09 08:34:52 AM UTC 24 Oct 09 08:35:19 AM UTC 24 940277959 ps
T1075 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/27.i2c_target_stress_all.523854144 Oct 09 08:33:25 AM UTC 24 Oct 09 08:35:24 AM UTC 24 53733658778 ps
T1076 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/30.i2c_target_fifo_reset_acq.1497300230 Oct 09 08:35:21 AM UTC 24 Oct 09 08:35:24 AM UTC 24 390699759 ps
T1077 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/30.i2c_target_intr_smoke.1855290524 Oct 09 08:35:14 AM UTC 24 Oct 09 08:35:24 AM UTC 24 5137778986 ps
T1078 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/29.i2c_target_stress_all.1005200376 Oct 09 08:34:38 AM UTC 24 Oct 09 08:35:26 AM UTC 24 17329179170 ps
T1079 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/30.i2c_target_fifo_reset_tx.3519170481 Oct 09 08:35:24 AM UTC 24 Oct 09 08:35:26 AM UTC 24 299962855 ps
T121 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/29.i2c_host_fifo_watermark.1066815217 Oct 09 08:34:12 AM UTC 24 Oct 09 08:35:27 AM UTC 24 15044993808 ps
T1080 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/30.i2c_target_timeout.2266294604 Oct 09 08:35:19 AM UTC 24 Oct 09 08:35:31 AM UTC 24 16750915643 ps
T1081 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/31.i2c_target_smoke.457094209 Oct 09 08:35:47 AM UTC 24 Oct 09 08:36:04 AM UTC 24 4362641053 ps
T1082 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/30.i2c_host_smoke.2381597698 Oct 09 08:34:51 AM UTC 24 Oct 09 08:35:32 AM UTC 24 1994197250 ps
T1083 /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/30.i2c_target_perf.3863934803 Oct 09 08:35:25 AM UTC 24 Oct 09 08:35:32 AM UTC 24 2892876540 ps
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