| T1570 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/45.i2c_target_fifo_reset_tx.2603183293 |
|
|
Oct 09 08:46:09 AM UTC 24 |
Oct 09 08:46:12 AM UTC 24 |
426241200 ps |
| T1571 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/42.i2c_host_perf.2589098120 |
|
|
Oct 09 08:43:41 AM UTC 24 |
Oct 09 08:46:15 AM UTC 24 |
4916828807 ps |
| T1572 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/45.i2c_target_intr_smoke.103991686 |
|
|
Oct 09 08:46:04 AM UTC 24 |
Oct 09 08:46:17 AM UTC 24 |
5132822623 ps |
| T1573 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/45.i2c_target_bad_addr.1274592573 |
|
|
Oct 09 08:46:11 AM UTC 24 |
Oct 09 08:46:17 AM UTC 24 |
1922937715 ps |
| T1574 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/44.i2c_host_fifo_full.164196635 |
|
|
Oct 09 08:45:19 AM UTC 24 |
Oct 09 08:46:17 AM UTC 24 |
1803086487 ps |
| T1575 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/45.i2c_host_smoke.244923645 |
|
|
Oct 09 08:45:51 AM UTC 24 |
Oct 09 08:46:18 AM UTC 24 |
5010480525 ps |
| T1576 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/45.i2c_target_hrst.1302038808 |
|
|
Oct 09 08:46:12 AM UTC 24 |
Oct 09 08:46:18 AM UTC 24 |
1203138653 ps |
| T1577 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/44.i2c_target_stress_wr.3783292055 |
|
|
Oct 09 08:45:29 AM UTC 24 |
Oct 09 08:46:19 AM UTC 24 |
35323162898 ps |
| T1578 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/45.i2c_target_stress_rd.4190818661 |
|
|
Oct 09 08:46:01 AM UTC 24 |
Oct 09 08:46:19 AM UTC 24 |
798521544 ps |
| T1579 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/45.i2c_target_timeout.21848998 |
|
|
Oct 09 08:46:05 AM UTC 24 |
Oct 09 08:46:20 AM UTC 24 |
3221715576 ps |
| T1580 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/45.i2c_target_perf.1717463081 |
|
|
Oct 09 08:46:10 AM UTC 24 |
Oct 09 08:46:20 AM UTC 24 |
3871511521 ps |
| T1581 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/45.i2c_target_fifo_watermarks_tx.1983288947 |
|
|
Oct 09 08:46:18 AM UTC 24 |
Oct 09 08:46:20 AM UTC 24 |
114576162 ps |
| T1582 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/45.i2c_alert_test.1413618228 |
|
|
Oct 09 08:46:20 AM UTC 24 |
Oct 09 08:46:23 AM UTC 24 |
130710906 ps |
| T1583 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/45.i2c_host_stretch_timeout.1565239318 |
|
|
Oct 09 08:45:56 AM UTC 24 |
Oct 09 08:46:23 AM UTC 24 |
2237181752 ps |
| T1584 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/45.i2c_target_nack_txstretch.1159040832 |
|
|
Oct 09 08:46:20 AM UTC 24 |
Oct 09 08:46:23 AM UTC 24 |
252344920 ps |
| T1585 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/46.i2c_host_override.1768072169 |
|
|
Oct 09 08:46:22 AM UTC 24 |
Oct 09 08:46:24 AM UTC 24 |
18034082 ps |
| T1586 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/45.i2c_target_fifo_watermarks_acq.1073815174 |
|
|
Oct 09 08:46:18 AM UTC 24 |
Oct 09 08:46:24 AM UTC 24 |
557398744 ps |
| T1587 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/45.i2c_target_smbus_maxlen.3115653746 |
|
|
Oct 09 08:46:19 AM UTC 24 |
Oct 09 08:46:24 AM UTC 24 |
635491796 ps |
| T1588 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/45.i2c_target_nack_acqfull.2339736567 |
|
|
Oct 09 08:46:19 AM UTC 24 |
Oct 09 08:46:26 AM UTC 24 |
3884835061 ps |
| T1589 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/44.i2c_target_intr_stress_wr.2165939243 |
|
|
Oct 09 08:45:37 AM UTC 24 |
Oct 09 08:46:26 AM UTC 24 |
19733010492 ps |
| T1590 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/45.i2c_target_tx_stretch_ctrl.1280007536 |
|
|
Oct 09 08:46:19 AM UTC 24 |
Oct 09 08:46:26 AM UTC 24 |
232281310 ps |
| T1591 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/45.i2c_target_nack_acqfull_addr.2757300120 |
|
|
Oct 09 08:46:20 AM UTC 24 |
Oct 09 08:46:26 AM UTC 24 |
622240401 ps |
| T1592 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_reset_fmt.4008379720 |
|
|
Oct 09 08:46:24 AM UTC 24 |
Oct 09 08:46:27 AM UTC 24 |
169970507 ps |
| T1593 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/45.i2c_host_may_nack.715693021 |
|
|
Oct 09 08:46:16 AM UTC 24 |
Oct 09 08:46:27 AM UTC 24 |
463045671 ps |
| T1594 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/46.i2c_host_perf_precise.2897638545 |
|
|
Oct 09 08:46:27 AM UTC 24 |
Oct 09 08:46:31 AM UTC 24 |
99621862 ps |
| T1595 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_reset_rx.171443355 |
|
|
Oct 09 08:46:25 AM UTC 24 |
Oct 09 08:46:32 AM UTC 24 |
603668541 ps |
| T1596 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/46.i2c_host_error_intr.144332980 |
|
|
Oct 09 08:46:27 AM UTC 24 |
Oct 09 08:46:36 AM UTC 24 |
612877464 ps |
| T1597 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/45.i2c_target_smoke.2351038231 |
|
|
Oct 09 08:46:00 AM UTC 24 |
Oct 09 08:46:41 AM UTC 24 |
4643659330 ps |
| T1598 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/46.i2c_target_smoke.100266447 |
|
|
Oct 09 08:46:28 AM UTC 24 |
Oct 09 08:46:43 AM UTC 24 |
3592554330 ps |
| T1599 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/46.i2c_target_stress_rd.3831267011 |
|
|
Oct 09 08:46:31 AM UTC 24 |
Oct 09 08:46:43 AM UTC 24 |
374215445 ps |
| T1600 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/16.i2c_target_stress_all.525978394 |
|
|
Oct 09 08:26:26 AM UTC 24 |
Oct 09 08:46:46 AM UTC 24 |
77596369802 ps |
| T1601 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/46.i2c_host_smoke.1042253399 |
|
|
Oct 09 08:46:22 AM UTC 24 |
Oct 09 08:46:47 AM UTC 24 |
6620662335 ps |
| T1602 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/46.i2c_target_intr_smoke.3106854970 |
|
|
Oct 09 08:46:37 AM UTC 24 |
Oct 09 08:46:47 AM UTC 24 |
1020043892 ps |
| T1603 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/46.i2c_target_stress_wr.2848872633 |
|
|
Oct 09 08:46:28 AM UTC 24 |
Oct 09 08:46:48 AM UTC 24 |
30156447599 ps |
| T1604 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_fmt_empty.224532054 |
|
|
Oct 09 08:46:25 AM UTC 24 |
Oct 09 08:46:49 AM UTC 24 |
450962877 ps |
| T1605 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/46.i2c_target_fifo_reset_acq.2371225316 |
|
|
Oct 09 08:46:46 AM UTC 24 |
Oct 09 08:46:49 AM UTC 24 |
178756524 ps |
| T1606 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/46.i2c_target_fifo_reset_tx.3851227827 |
|
|
Oct 09 08:46:47 AM UTC 24 |
Oct 09 08:46:50 AM UTC 24 |
197195640 ps |
| T1607 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/46.i2c_target_hrst.2088660419 |
|
|
Oct 09 08:46:50 AM UTC 24 |
Oct 09 08:46:53 AM UTC 24 |
522364499 ps |
| T1608 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/46.i2c_target_timeout.4167157460 |
|
|
Oct 09 08:46:44 AM UTC 24 |
Oct 09 08:46:55 AM UTC 24 |
5502376810 ps |
| T1609 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/46.i2c_target_fifo_watermarks_acq.4155116245 |
|
|
Oct 09 08:46:51 AM UTC 24 |
Oct 09 08:46:56 AM UTC 24 |
818453584 ps |
| T1610 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/46.i2c_target_bad_addr.2032786734 |
|
|
Oct 09 08:46:49 AM UTC 24 |
Oct 09 08:46:57 AM UTC 24 |
4870314455 ps |
| T1611 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/45.i2c_target_stress_all.1093442421 |
|
|
Oct 09 08:46:10 AM UTC 24 |
Oct 09 08:46:57 AM UTC 24 |
10652341021 ps |
| T1612 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/46.i2c_target_fifo_watermarks_tx.985072085 |
|
|
Oct 09 08:46:54 AM UTC 24 |
Oct 09 08:46:58 AM UTC 24 |
158737112 ps |
| T1613 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/46.i2c_target_intr_stress_wr.3564719199 |
|
|
Oct 09 08:46:42 AM UTC 24 |
Oct 09 08:46:59 AM UTC 24 |
20651434240 ps |
| T1614 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/46.i2c_host_may_nack.4139644190 |
|
|
Oct 09 08:46:50 AM UTC 24 |
Oct 09 08:47:00 AM UTC 24 |
1116890971 ps |
| T1615 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/46.i2c_target_tx_stretch_ctrl.1633434266 |
|
|
Oct 09 08:46:55 AM UTC 24 |
Oct 09 08:47:01 AM UTC 24 |
113869360 ps |
| T1616 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/46.i2c_target_perf.874443269 |
|
|
Oct 09 08:46:49 AM UTC 24 |
Oct 09 08:47:01 AM UTC 24 |
875518638 ps |
| T1617 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/46.i2c_alert_test.1012060787 |
|
|
Oct 09 08:46:59 AM UTC 24 |
Oct 09 08:47:02 AM UTC 24 |
26893861 ps |
| T1618 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/46.i2c_target_nack_txstretch.2418286756 |
|
|
Oct 09 08:46:58 AM UTC 24 |
Oct 09 08:47:02 AM UTC 24 |
679874938 ps |
| T1619 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/46.i2c_target_smbus_maxlen.3936821556 |
|
|
Oct 09 08:46:57 AM UTC 24 |
Oct 09 08:47:02 AM UTC 24 |
2908777780 ps |
| T1620 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/46.i2c_target_nack_acqfull.4265458804 |
|
|
Oct 09 08:46:58 AM UTC 24 |
Oct 09 08:47:04 AM UTC 24 |
5678440235 ps |
| T1621 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/47.i2c_host_override.2227949712 |
|
|
Oct 09 08:47:01 AM UTC 24 |
Oct 09 08:47:04 AM UTC 24 |
41603033 ps |
| T1622 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/46.i2c_target_nack_acqfull_addr.2794385792 |
|
|
Oct 09 08:46:58 AM UTC 24 |
Oct 09 08:47:04 AM UTC 24 |
2268470090 ps |
| T1623 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_reset_fmt.1203079702 |
|
|
Oct 09 08:47:03 AM UTC 24 |
Oct 09 08:47:06 AM UTC 24 |
569080870 ps |
| T1624 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/44.i2c_host_fifo_watermark.3849028671 |
|
|
Oct 09 08:45:16 AM UTC 24 |
Oct 09 08:47:09 AM UTC 24 |
3759492357 ps |
| T1625 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_reset_rx.3023874908 |
|
|
Oct 09 08:47:03 AM UTC 24 |
Oct 09 08:47:10 AM UTC 24 |
310022331 ps |
| T1626 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/46.i2c_host_stretch_timeout.134401638 |
|
|
Oct 09 08:46:27 AM UTC 24 |
Oct 09 08:47:14 AM UTC 24 |
1583153747 ps |
| T1627 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/47.i2c_host_error_intr.3997265033 |
|
|
Oct 09 08:47:09 AM UTC 24 |
Oct 09 08:47:14 AM UTC 24 |
134018428 ps |
| T1628 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_fmt_empty.3418656915 |
|
|
Oct 09 08:47:03 AM UTC 24 |
Oct 09 08:47:15 AM UTC 24 |
412959060 ps |
| T1629 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/43.i2c_host_fifo_watermark.3810168379 |
|
|
Oct 09 08:44:26 AM UTC 24 |
Oct 09 08:47:17 AM UTC 24 |
4338142553 ps |
| T1630 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/24.i2c_target_stress_wr.3971992523 |
|
|
Oct 09 08:31:24 AM UTC 24 |
Oct 09 08:47:17 AM UTC 24 |
53057482674 ps |
| T1631 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/44.i2c_target_stress_all.351357432 |
|
|
Oct 09 08:45:39 AM UTC 24 |
Oct 09 08:47:18 AM UTC 24 |
28950339875 ps |
| T1632 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/47.i2c_host_stretch_timeout.96977384 |
|
|
Oct 09 08:47:06 AM UTC 24 |
Oct 09 08:47:20 AM UTC 24 |
286051627 ps |
| T1633 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/45.i2c_target_intr_stress_wr.2529327020 |
|
|
Oct 09 08:46:04 AM UTC 24 |
Oct 09 08:47:20 AM UTC 24 |
36291011735 ps |
| T1634 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/44.i2c_host_fifo_overflow.2239794656 |
|
|
Oct 09 08:45:16 AM UTC 24 |
Oct 09 08:47:21 AM UTC 24 |
1928858391 ps |
| T1635 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/33.i2c_host_perf.1665505313 |
|
|
Oct 09 08:36:50 AM UTC 24 |
Oct 09 08:47:21 AM UTC 24 |
51273480315 ps |
| T1636 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_watermark.3587708669 |
|
|
Oct 09 08:46:24 AM UTC 24 |
Oct 09 08:47:22 AM UTC 24 |
7088198178 ps |
| T1637 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/47.i2c_target_fifo_reset_tx.1308317088 |
|
|
Oct 09 08:47:22 AM UTC 24 |
Oct 09 08:47:25 AM UTC 24 |
243407243 ps |
| T1638 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/47.i2c_target_fifo_reset_acq.1554885431 |
|
|
Oct 09 08:47:22 AM UTC 24 |
Oct 09 08:47:25 AM UTC 24 |
382924380 ps |
| T1639 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/47.i2c_host_perf_precise.3132406120 |
|
|
Oct 09 08:47:05 AM UTC 24 |
Oct 09 08:47:28 AM UTC 24 |
1742688853 ps |
| T1640 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/47.i2c_target_smoke.1472991148 |
|
|
Oct 09 08:47:15 AM UTC 24 |
Oct 09 08:47:29 AM UTC 24 |
3578189273 ps |
| T1641 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/38.i2c_target_stress_wr.1306598010 |
|
|
Oct 09 08:40:45 AM UTC 24 |
Oct 09 08:47:30 AM UTC 24 |
38190661958 ps |
| T1642 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/47.i2c_target_intr_smoke.323678584 |
|
|
Oct 09 08:47:18 AM UTC 24 |
Oct 09 08:47:30 AM UTC 24 |
2828216826 ps |
| T1643 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/47.i2c_target_perf.3872400832 |
|
|
Oct 09 08:47:23 AM UTC 24 |
Oct 09 08:47:30 AM UTC 24 |
886506421 ps |
| T1644 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/47.i2c_target_timeout.3421403684 |
|
|
Oct 09 08:47:21 AM UTC 24 |
Oct 09 08:47:31 AM UTC 24 |
2168265229 ps |
| T1645 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_overflow.3416131012 |
|
|
Oct 09 08:46:24 AM UTC 24 |
Oct 09 08:47:31 AM UTC 24 |
4192527492 ps |
| T1646 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/47.i2c_target_bad_addr.2429174941 |
|
|
Oct 09 08:47:26 AM UTC 24 |
Oct 09 08:47:32 AM UTC 24 |
729103799 ps |
| T1647 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/47.i2c_target_fifo_watermarks_acq.3351092418 |
|
|
Oct 09 08:47:31 AM UTC 24 |
Oct 09 08:47:35 AM UTC 24 |
1754752796 ps |
| T1648 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/47.i2c_alert_test.410830337 |
|
|
Oct 09 08:47:34 AM UTC 24 |
Oct 09 08:47:36 AM UTC 24 |
41244991 ps |
| T1649 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/47.i2c_target_nack_txstretch.943427308 |
|
|
Oct 09 08:47:33 AM UTC 24 |
Oct 09 08:47:36 AM UTC 24 |
809428728 ps |
| T1650 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/45.i2c_host_fifo_watermark.3880780560 |
|
|
Oct 09 08:45:52 AM UTC 24 |
Oct 09 08:47:36 AM UTC 24 |
5518035741 ps |
| T1651 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/47.i2c_target_tx_stretch_ctrl.3060417599 |
|
|
Oct 09 08:47:31 AM UTC 24 |
Oct 09 08:47:36 AM UTC 24 |
155709534 ps |
| T1652 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/47.i2c_host_may_nack.355411931 |
|
|
Oct 09 08:47:30 AM UTC 24 |
Oct 09 08:47:37 AM UTC 24 |
387604790 ps |
| T1653 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/47.i2c_target_smbus_maxlen.2324255349 |
|
|
Oct 09 08:47:32 AM UTC 24 |
Oct 09 08:47:38 AM UTC 24 |
402399546 ps |
| T1654 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/47.i2c_target_nack_acqfull_addr.3357390743 |
|
|
Oct 09 08:47:33 AM UTC 24 |
Oct 09 08:47:38 AM UTC 24 |
1240869551 ps |
| T1655 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/47.i2c_target_nack_acqfull.252266414 |
|
|
Oct 09 08:47:32 AM UTC 24 |
Oct 09 08:47:39 AM UTC 24 |
1394883264 ps |
| T1656 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/48.i2c_host_override.2419523750 |
|
|
Oct 09 08:47:37 AM UTC 24 |
Oct 09 08:47:39 AM UTC 24 |
51625494 ps |
| T1657 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_reset_fmt.1835979587 |
|
|
Oct 09 08:47:37 AM UTC 24 |
Oct 09 08:47:40 AM UTC 24 |
891472469 ps |
| T1658 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/43.i2c_target_stress_all.1254590773 |
|
|
Oct 09 08:45:02 AM UTC 24 |
Oct 09 08:47:42 AM UTC 24 |
54015399115 ps |
| T1659 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_fmt_empty.3554389064 |
|
|
Oct 09 08:47:39 AM UTC 24 |
Oct 09 08:47:46 AM UTC 24 |
348104543 ps |
| T1660 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/48.i2c_host_error_intr.1025276913 |
|
|
Oct 09 08:47:43 AM UTC 24 |
Oct 09 08:47:47 AM UTC 24 |
108786565 ps |
| T1661 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/48.i2c_host_perf_precise.1314839406 |
|
|
Oct 09 08:47:40 AM UTC 24 |
Oct 09 08:47:47 AM UTC 24 |
245667762 ps |
| T1662 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_reset_rx.2408787754 |
|
|
Oct 09 08:47:39 AM UTC 24 |
Oct 09 08:47:50 AM UTC 24 |
610078550 ps |
| T1663 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/47.i2c_host_smoke.412099766 |
|
|
Oct 09 08:47:00 AM UTC 24 |
Oct 09 08:47:54 AM UTC 24 |
6067054371 ps |
| T1664 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/47.i2c_target_stress_all.567576434 |
|
|
Oct 09 08:47:26 AM UTC 24 |
Oct 09 08:47:54 AM UTC 24 |
43631104862 ps |
| T1665 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/48.i2c_target_stretch.1497035805 |
|
|
Oct 09 08:47:51 AM UTC 24 |
Oct 09 08:47:56 AM UTC 24 |
2171899220 ps |
| T1666 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/47.i2c_target_intr_stress_wr.3707535700 |
|
|
Oct 09 08:47:18 AM UTC 24 |
Oct 09 08:47:56 AM UTC 24 |
16949924548 ps |
| T1667 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/48.i2c_target_stress_wr.2359605342 |
|
|
Oct 09 08:47:49 AM UTC 24 |
Oct 09 08:47:57 AM UTC 24 |
12220504097 ps |
| T1668 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/47.i2c_target_stress_rd.2546358737 |
|
|
Oct 09 08:47:16 AM UTC 24 |
Oct 09 08:48:00 AM UTC 24 |
4286321419 ps |
| T1669 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/48.i2c_target_fifo_reset_acq.75735063 |
|
|
Oct 09 08:47:58 AM UTC 24 |
Oct 09 08:48:00 AM UTC 24 |
279004347 ps |
| T1670 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/48.i2c_target_intr_smoke.3354369330 |
|
|
Oct 09 08:47:55 AM UTC 24 |
Oct 09 08:48:03 AM UTC 24 |
606634496 ps |
| T1671 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/48.i2c_host_smoke.1933491019 |
|
|
Oct 09 08:47:36 AM UTC 24 |
Oct 09 08:48:03 AM UTC 24 |
1735773712 ps |
| T1672 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/48.i2c_target_fifo_reset_tx.1109220385 |
|
|
Oct 09 08:48:01 AM UTC 24 |
Oct 09 08:48:03 AM UTC 24 |
617248918 ps |
| T1673 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_full.1160238501 |
|
|
Oct 09 08:47:05 AM UTC 24 |
Oct 09 08:48:05 AM UTC 24 |
6972414588 ps |
| T1674 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_overflow.510871330 |
|
|
Oct 09 08:47:02 AM UTC 24 |
Oct 09 08:48:05 AM UTC 24 |
9625880591 ps |
| T1675 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/48.i2c_target_perf.4015320857 |
|
|
Oct 09 08:48:01 AM UTC 24 |
Oct 09 08:48:07 AM UTC 24 |
2801457385 ps |
| T1676 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/45.i2c_host_perf.991989814 |
|
|
Oct 09 08:45:55 AM UTC 24 |
Oct 09 08:48:08 AM UTC 24 |
27845628987 ps |
| T1677 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/48.i2c_target_hrst.908005856 |
|
|
Oct 09 08:48:03 AM UTC 24 |
Oct 09 08:48:08 AM UTC 24 |
1036819954 ps |
| T1678 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/49.i2c_host_may_nack.368654192 |
|
|
Oct 09 08:48:30 AM UTC 24 |
Oct 09 08:48:37 AM UTC 24 |
689116882 ps |
| T1679 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/47.i2c_target_stress_wr.1718208429 |
|
|
Oct 09 08:47:15 AM UTC 24 |
Oct 09 08:48:09 AM UTC 24 |
32900905516 ps |
| T1680 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/48.i2c_target_bad_addr.1474858405 |
|
|
Oct 09 08:48:02 AM UTC 24 |
Oct 09 08:48:10 AM UTC 24 |
3373076091 ps |
| T1681 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/48.i2c_target_fifo_watermarks_tx.2101182242 |
|
|
Oct 09 08:48:07 AM UTC 24 |
Oct 09 08:48:10 AM UTC 24 |
102271377 ps |
| T1682 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/48.i2c_target_timeout.3719384290 |
|
|
Oct 09 08:47:57 AM UTC 24 |
Oct 09 08:48:10 AM UTC 24 |
1216255682 ps |
| T1683 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/48.i2c_host_may_nack.2102741603 |
|
|
Oct 09 08:48:04 AM UTC 24 |
Oct 09 08:48:11 AM UTC 24 |
2091148527 ps |
| T1684 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/48.i2c_alert_test.3331433035 |
|
|
Oct 09 08:48:10 AM UTC 24 |
Oct 09 08:48:13 AM UTC 24 |
42491082 ps |
| T1685 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/48.i2c_target_fifo_watermarks_acq.694145727 |
|
|
Oct 09 08:48:06 AM UTC 24 |
Oct 09 08:48:13 AM UTC 24 |
3026577250 ps |
| T1686 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/48.i2c_target_smoke.2642238212 |
|
|
Oct 09 08:47:49 AM UTC 24 |
Oct 09 08:48:13 AM UTC 24 |
2739267461 ps |
| T1687 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/48.i2c_target_tx_stretch_ctrl.1312746848 |
|
|
Oct 09 08:48:09 AM UTC 24 |
Oct 09 08:48:14 AM UTC 24 |
162792202 ps |
| T1688 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/49.i2c_host_override.808833558 |
|
|
Oct 09 08:48:12 AM UTC 24 |
Oct 09 08:48:14 AM UTC 24 |
18005817 ps |
| T1689 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/49.i2c_target_fifo_watermarks_acq.1617376042 |
|
|
Oct 09 08:48:32 AM UTC 24 |
Oct 09 08:48:35 AM UTC 24 |
963482345 ps |
| T1690 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/48.i2c_target_smbus_maxlen.877293874 |
|
|
Oct 09 08:48:09 AM UTC 24 |
Oct 09 08:48:14 AM UTC 24 |
485350219 ps |
| T1691 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/48.i2c_target_nack_acqfull_addr.1114964018 |
|
|
Oct 09 08:48:10 AM UTC 24 |
Oct 09 08:48:15 AM UTC 24 |
435183077 ps |
| T1692 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/48.i2c_target_nack_acqfull.4258635597 |
|
|
Oct 09 08:48:09 AM UTC 24 |
Oct 09 08:48:15 AM UTC 24 |
1169358529 ps |
| T1693 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_reset_fmt.1871880541 |
|
|
Oct 09 08:48:14 AM UTC 24 |
Oct 09 08:48:17 AM UTC 24 |
126732990 ps |
| T1694 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/45.i2c_host_fifo_overflow.1490987156 |
|
|
Oct 09 08:45:52 AM UTC 24 |
Oct 09 08:48:18 AM UTC 24 |
4468981625 ps |
| T1695 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/49.i2c_host_perf_precise.1441814392 |
|
|
Oct 09 08:48:16 AM UTC 24 |
Oct 09 08:48:18 AM UTC 24 |
85581684 ps |
| T1696 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/47.i2c_target_stretch.1064010649 |
|
|
Oct 09 08:47:18 AM UTC 24 |
Oct 09 08:48:18 AM UTC 24 |
2687659449 ps |
| T1697 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/48.i2c_target_stress_rd.2462464505 |
|
|
Oct 09 08:47:49 AM UTC 24 |
Oct 09 08:48:18 AM UTC 24 |
604679095 ps |
| T1698 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_reset_rx.1782404589 |
|
|
Oct 09 08:48:14 AM UTC 24 |
Oct 09 08:48:19 AM UTC 24 |
132039970 ps |
| T1699 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/24.i2c_target_stress_all.375881464 |
|
|
Oct 09 08:31:51 AM UTC 24 |
Oct 09 08:48:21 AM UTC 24 |
42637613106 ps |
| T1700 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/49.i2c_target_stretch.2492129422 |
|
|
Oct 09 08:48:19 AM UTC 24 |
Oct 09 08:48:22 AM UTC 24 |
192104509 ps |
| T1701 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/48.i2c_host_stretch_timeout.2819402196 |
|
|
Oct 09 08:47:41 AM UTC 24 |
Oct 09 08:48:22 AM UTC 24 |
3111816310 ps |
| T1702 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_fmt_empty.2327672731 |
|
|
Oct 09 08:48:14 AM UTC 24 |
Oct 09 08:48:24 AM UTC 24 |
178062407 ps |
| T1703 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/46.i2c_host_perf.3639045842 |
|
|
Oct 09 08:46:25 AM UTC 24 |
Oct 09 08:48:25 AM UTC 24 |
24276710687 ps |
| T1704 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/49.i2c_host_error_intr.3675591062 |
|
|
Oct 09 08:48:17 AM UTC 24 |
Oct 09 08:48:26 AM UTC 24 |
2809837408 ps |
| T1705 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/49.i2c_target_stress_rd.2534025997 |
|
|
Oct 09 08:48:19 AM UTC 24 |
Oct 09 08:48:38 AM UTC 24 |
320855780 ps |
| T1706 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/49.i2c_target_fifo_reset_acq.1157007127 |
|
|
Oct 09 08:48:25 AM UTC 24 |
Oct 09 08:48:28 AM UTC 24 |
220148026 ps |
| T1707 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/49.i2c_target_bad_addr.2786097873 |
|
|
Oct 09 08:48:29 AM UTC 24 |
Oct 09 08:48:38 AM UTC 24 |
6184598915 ps |
| T1708 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/45.i2c_host_fifo_full.1051382 |
|
|
Oct 09 08:45:55 AM UTC 24 |
Oct 09 08:48:29 AM UTC 24 |
18648637229 ps |
| T1709 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/49.i2c_target_fifo_reset_tx.1938122090 |
|
|
Oct 09 08:48:26 AM UTC 24 |
Oct 09 08:48:29 AM UTC 24 |
201533278 ps |
| T1710 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/49.i2c_target_intr_smoke.4190849298 |
|
|
Oct 09 08:48:21 AM UTC 24 |
Oct 09 08:48:31 AM UTC 24 |
2068050504 ps |
| T1711 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/49.i2c_target_timeout.36566631 |
|
|
Oct 09 08:48:23 AM UTC 24 |
Oct 09 08:48:34 AM UTC 24 |
5335892800 ps |
| T1712 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/49.i2c_target_smoke.2566897660 |
|
|
Oct 09 08:48:19 AM UTC 24 |
Oct 09 08:48:34 AM UTC 24 |
1484537670 ps |
| T1713 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/49.i2c_host_mode_toggle.2503584039 |
|
|
Oct 09 08:48:30 AM UTC 24 |
Oct 09 08:48:35 AM UTC 24 |
1201429743 ps |
| T1714 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/49.i2c_target_perf.2305234059 |
|
|
Oct 09 08:48:27 AM UTC 24 |
Oct 09 08:48:35 AM UTC 24 |
778153458 ps |
| T1715 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/49.i2c_target_fifo_watermarks_tx.46371922 |
|
|
Oct 09 08:48:35 AM UTC 24 |
Oct 09 08:48:39 AM UTC 24 |
529450435 ps |
| T1716 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/29.i2c_host_perf_precise.2277282014 |
|
|
Oct 09 08:34:14 AM UTC 24 |
Oct 09 08:48:40 AM UTC 24 |
23195573870 ps |
| T1717 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/49.i2c_target_tx_stretch_ctrl.2447761383 |
|
|
Oct 09 08:48:35 AM UTC 24 |
Oct 09 08:48:41 AM UTC 24 |
148572877 ps |
| T1718 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/49.i2c_target_smbus_maxlen.3905545238 |
|
|
Oct 09 08:48:35 AM UTC 24 |
Oct 09 08:48:41 AM UTC 24 |
481721537 ps |
| T1719 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/49.i2c_target_nack_acqfull_addr.2405509343 |
|
|
Oct 09 08:48:37 AM UTC 24 |
Oct 09 08:48:41 AM UTC 24 |
414116797 ps |
| T1720 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/49.i2c_alert_test.776722769 |
|
|
Oct 09 08:48:39 AM UTC 24 |
Oct 09 08:48:41 AM UTC 24 |
14578819 ps |
| T1721 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/49.i2c_target_nack_txstretch.1738552766 |
|
|
Oct 09 08:48:38 AM UTC 24 |
Oct 09 08:48:41 AM UTC 24 |
519771448 ps |
| T1722 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/49.i2c_target_nack_acqfull.2807678273 |
|
|
Oct 09 08:48:35 AM UTC 24 |
Oct 09 08:48:41 AM UTC 24 |
1960559657 ps |
| T1723 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/48.i2c_target_stress_all.4002647220 |
|
|
Oct 09 08:48:01 AM UTC 24 |
Oct 09 08:48:42 AM UTC 24 |
4773287296 ps |
| T1724 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/48.i2c_host_perf.1127840463 |
|
|
Oct 09 08:47:40 AM UTC 24 |
Oct 09 08:48:47 AM UTC 24 |
6550994147 ps |
| T1725 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/49.i2c_host_stretch_timeout.1750293373 |
|
|
Oct 09 08:48:16 AM UTC 24 |
Oct 09 08:48:48 AM UTC 24 |
2371958097 ps |
| T1726 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/46.i2c_target_stress_all.3601421164 |
|
|
Oct 09 08:46:49 AM UTC 24 |
Oct 09 08:48:50 AM UTC 24 |
17461753800 ps |
| T1727 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_full.1815862438 |
|
|
Oct 09 08:46:25 AM UTC 24 |
Oct 09 08:48:54 AM UTC 24 |
2636529594 ps |
| T1728 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/49.i2c_target_intr_stress_wr.2268543841 |
|
|
Oct 09 08:48:22 AM UTC 24 |
Oct 09 08:48:55 AM UTC 24 |
29367970406 ps |
| T1729 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_watermark.32517385 |
|
|
Oct 09 08:47:37 AM UTC 24 |
Oct 09 08:48:56 AM UTC 24 |
6352475769 ps |
| T1730 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_overflow.693183073 |
|
|
Oct 09 08:47:37 AM UTC 24 |
Oct 09 08:48:57 AM UTC 24 |
2884958930 ps |
| T1731 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/48.i2c_target_intr_stress_wr.1059860370 |
|
|
Oct 09 08:47:55 AM UTC 24 |
Oct 09 08:48:59 AM UTC 24 |
13226103006 ps |
| T1732 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/49.i2c_host_perf.621766356 |
|
|
Oct 09 08:48:16 AM UTC 24 |
Oct 09 08:49:22 AM UTC 24 |
6100526318 ps |
| T1733 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_watermark.476918184 |
|
|
Oct 09 08:47:01 AM UTC 24 |
Oct 09 08:49:23 AM UTC 24 |
9805755750 ps |
| T1734 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/33.i2c_host_stress_all.656924944 |
|
|
Oct 09 08:36:52 AM UTC 24 |
Oct 09 08:49:26 AM UTC 24 |
20519296311 ps |
| T1735 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_full.1810930087 |
|
|
Oct 09 08:47:39 AM UTC 24 |
Oct 09 08:49:29 AM UTC 24 |
3678908999 ps |
| T1736 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/49.i2c_host_smoke.548646753 |
|
|
Oct 09 08:48:10 AM UTC 24 |
Oct 09 08:49:41 AM UTC 24 |
6420868187 ps |
| T1737 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_overflow.2664987412 |
|
|
Oct 09 08:48:14 AM UTC 24 |
Oct 09 08:49:57 AM UTC 24 |
2531176736 ps |
| T1738 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/47.i2c_host_perf.1363284397 |
|
|
Oct 09 08:47:05 AM UTC 24 |
Oct 09 08:50:00 AM UTC 24 |
14248096857 ps |
| T1739 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_watermark.4196613089 |
|
|
Oct 09 08:48:12 AM UTC 24 |
Oct 09 08:50:07 AM UTC 24 |
4907715332 ps |
| T1740 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_full.657613077 |
|
|
Oct 09 08:48:15 AM UTC 24 |
Oct 09 08:50:14 AM UTC 24 |
9342798549 ps |
| T1741 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/42.i2c_target_stress_wr.3582206040 |
|
|
Oct 09 08:43:55 AM UTC 24 |
Oct 09 08:50:26 AM UTC 24 |
40501168213 ps |
| T1742 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/49.i2c_target_stress_wr.988314208 |
|
|
Oct 09 08:48:19 AM UTC 24 |
Oct 09 08:51:04 AM UTC 24 |
29126292322 ps |
| T1743 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/38.i2c_host_stress_all.1882290109 |
|
|
Oct 09 08:40:45 AM UTC 24 |
Oct 09 08:52:08 AM UTC 24 |
39573859398 ps |
| T1744 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/39.i2c_target_stress_wr.1724713328 |
|
|
Oct 09 08:41:35 AM UTC 24 |
Oct 09 08:53:06 AM UTC 24 |
46330106325 ps |
| T1745 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/27.i2c_target_stress_wr.3083802925 |
|
|
Oct 09 08:33:13 AM UTC 24 |
Oct 09 08:53:12 AM UTC 24 |
57567863867 ps |
| T1746 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/41.i2c_host_perf.1854494990 |
|
|
Oct 09 08:43:07 AM UTC 24 |
Oct 09 08:54:27 AM UTC 24 |
53441791325 ps |
| T1747 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/40.i2c_target_stress_all.1171440352 |
|
|
Oct 09 08:42:54 AM UTC 24 |
Oct 09 08:54:34 AM UTC 24 |
39250665669 ps |
| T1748 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/45.i2c_target_stress_wr.1650732513 |
|
|
Oct 09 08:46:01 AM UTC 24 |
Oct 09 08:58:39 AM UTC 24 |
51177936438 ps |
| T1749 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/21.i2c_target_stress_wr.1460626774 |
|
|
Oct 09 08:29:24 AM UTC 24 |
Oct 09 09:00:20 AM UTC 24 |
68001471954 ps |
| T276 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/32.i2c_host_stress_all.1935733518 |
|
|
Oct 09 08:36:20 AM UTC 24 |
Oct 09 09:03:36 AM UTC 24 |
46493537771 ps |
| T1750 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/49.i2c_target_stress_all.248642931 |
|
|
Oct 09 08:48:27 AM UTC 24 |
Oct 09 09:19:07 AM UTC 24 |
64154669451 ps |
| T1751 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/35.i2c_target_stress_wr.83589170 |
|
|
Oct 09 08:38:27 AM UTC 24 |
Oct 09 09:20:04 AM UTC 24 |
75637474035 ps |
| T284 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_intr_test.3857426837 |
|
|
Oct 09 07:25:13 AM UTC 24 |
Oct 09 07:25:15 AM UTC 24 |
54848154 ps |
| T183 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_tl_errors.2913626171 |
|
|
Oct 09 07:25:12 AM UTC 24 |
Oct 09 07:25:16 AM UTC 24 |
144151390 ps |
| T184 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_tl_intg_err.3997899685 |
|
|
Oct 09 07:25:13 AM UTC 24 |
Oct 09 07:25:16 AM UTC 24 |
69425664 ps |
| T207 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_hw_reset.1234186290 |
|
|
Oct 09 07:25:15 AM UTC 24 |
Oct 09 07:25:17 AM UTC 24 |
60120970 ps |
| T104 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_rw.3436580714 |
|
|
Oct 09 07:25:16 AM UTC 24 |
Oct 09 07:25:18 AM UTC 24 |
96697741 ps |
| T227 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_same_csr_outstanding.2691027847 |
|
|
Oct 09 07:25:17 AM UTC 24 |
Oct 09 07:25:19 AM UTC 24 |
36275382 ps |
| T1752 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_bit_bash.262404167 |
|
|
Oct 09 07:25:16 AM UTC 24 |
Oct 09 07:25:20 AM UTC 24 |
242592242 ps |
| T185 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.2646044429 |
|
|
Oct 09 07:25:18 AM UTC 24 |
Oct 09 07:25:20 AM UTC 24 |
93123626 ps |
| T215 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_aliasing.3214821087 |
|
|
Oct 09 07:25:17 AM UTC 24 |
Oct 09 07:25:21 AM UTC 24 |
138728747 ps |
| T105 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_tl_errors.1080175107 |
|
|
Oct 09 07:25:18 AM UTC 24 |
Oct 09 07:25:21 AM UTC 24 |
251413304 ps |
| T277 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_intr_test.3568507533 |
|
|
Oct 09 07:25:20 AM UTC 24 |
Oct 09 07:25:22 AM UTC 24 |
42263904 ps |
| T190 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_tl_intg_err.1891189240 |
|
|
Oct 09 07:25:19 AM UTC 24 |
Oct 09 07:25:22 AM UTC 24 |
125388995 ps |
| T106 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_hw_reset.2716315976 |
|
|
Oct 09 07:25:21 AM UTC 24 |
Oct 09 07:25:24 AM UTC 24 |
22875687 ps |
| T216 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_rw.678510219 |
|
|
Oct 09 07:25:21 AM UTC 24 |
Oct 09 07:25:24 AM UTC 24 |
16713821 ps |
| T217 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_aliasing.843522017 |
|
|
Oct 09 07:25:23 AM UTC 24 |
Oct 09 07:25:25 AM UTC 24 |
27204844 ps |
| T195 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.129456944 |
|
|
Oct 09 07:25:24 AM UTC 24 |
Oct 09 07:25:26 AM UTC 24 |
72712968 ps |
| T228 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_same_csr_outstanding.3045834776 |
|
|
Oct 09 07:25:24 AM UTC 24 |
Oct 09 07:25:27 AM UTC 24 |
88372155 ps |
| T1753 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_bit_bash.4095284171 |
|
|
Oct 09 07:25:22 AM UTC 24 |
Oct 09 07:25:27 AM UTC 24 |
185475381 ps |
| T135 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_intr_test.3839714296 |
|
|
Oct 09 07:25:25 AM UTC 24 |
Oct 09 07:25:27 AM UTC 24 |
20347764 ps |
| T191 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_tl_intg_err.1576583010 |
|
|
Oct 09 07:25:25 AM UTC 24 |
Oct 09 07:25:28 AM UTC 24 |
128554940 ps |
| T1754 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_hw_reset.2360120033 |
|
|
Oct 09 07:25:26 AM UTC 24 |
Oct 09 07:25:29 AM UTC 24 |
18606084 ps |
| T107 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_tl_errors.3523584887 |
|
|
Oct 09 07:25:25 AM UTC 24 |
Oct 09 07:25:29 AM UTC 24 |
887456294 ps |
| T108 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_rw.1349762504 |
|
|
Oct 09 07:25:27 AM UTC 24 |
Oct 09 07:25:29 AM UTC 24 |
35647436 ps |
| T109 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_aliasing.3504384576 |
|
|
Oct 09 07:25:27 AM UTC 24 |
Oct 09 07:25:31 AM UTC 24 |
186888383 ps |
| T229 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_same_csr_outstanding.3359739142 |
|
|
Oct 09 07:25:29 AM UTC 24 |
Oct 09 07:25:31 AM UTC 24 |
192577182 ps |
| T1755 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_bit_bash.2197320353 |
|
|
Oct 09 07:25:27 AM UTC 24 |
Oct 09 07:25:31 AM UTC 24 |
746622641 ps |
| T136 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_intr_test.3472720713 |
|
|
Oct 09 07:25:30 AM UTC 24 |
Oct 09 07:25:32 AM UTC 24 |
168207914 ps |
| T192 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.836776181 |
|
|
Oct 09 07:25:29 AM UTC 24 |
Oct 09 07:25:32 AM UTC 24 |
32560291 ps |
| T230 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_rw.2704934106 |
|
|
Oct 09 07:25:30 AM UTC 24 |
Oct 09 07:25:32 AM UTC 24 |
22162782 ps |
| T110 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_hw_reset.3306011428 |
|
|
Oct 09 07:25:30 AM UTC 24 |
Oct 09 07:25:32 AM UTC 24 |
27019201 ps |
| T193 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_tl_errors.1208088301 |
|
|
Oct 09 07:25:29 AM UTC 24 |
Oct 09 07:25:33 AM UTC 24 |
81429941 ps |
| T202 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_tl_intg_err.2569777685 |
|
|
Oct 09 07:25:30 AM UTC 24 |
Oct 09 07:25:34 AM UTC 24 |
214551129 ps |
| T231 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_same_csr_outstanding.3400938986 |
|
|
Oct 09 07:25:32 AM UTC 24 |
Oct 09 07:25:35 AM UTC 24 |
33640905 ps |
| T218 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_aliasing.3631465965 |
|
|
Oct 09 07:25:31 AM UTC 24 |
Oct 09 07:25:35 AM UTC 24 |
39876648 ps |
| T213 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.4031827398 |
|
|
Oct 09 07:25:32 AM UTC 24 |
Oct 09 07:25:35 AM UTC 24 |
25347790 ps |
| T1756 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_bit_bash.586281371 |
|
|
Oct 09 07:25:31 AM UTC 24 |
Oct 09 07:25:35 AM UTC 24 |
737870171 ps |
| T278 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_intr_test.1313134258 |
|
|
Oct 09 07:25:34 AM UTC 24 |
Oct 09 07:25:36 AM UTC 24 |
41744690 ps |
| T232 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_rw.101610935 |
|
|
Oct 09 07:25:34 AM UTC 24 |
Oct 09 07:25:36 AM UTC 24 |
195120215 ps |
| T219 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_hw_reset.3268560880 |
|
|
Oct 09 07:25:34 AM UTC 24 |
Oct 09 07:25:36 AM UTC 24 |
42368842 ps |
| T111 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_tl_errors.4109564688 |
|
|
Oct 09 07:25:33 AM UTC 24 |
Oct 09 07:25:37 AM UTC 24 |
145895032 ps |
| T112 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_tl_intg_err.2228425111 |
|
|
Oct 09 07:25:34 AM UTC 24 |
Oct 09 07:25:37 AM UTC 24 |
275682085 ps |
| T220 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_aliasing.1574503750 |
|
|
Oct 09 07:25:35 AM UTC 24 |
Oct 09 07:25:38 AM UTC 24 |
47148941 ps |
| T233 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_same_csr_outstanding.204491629 |
|
|
Oct 09 07:25:35 AM UTC 24 |
Oct 09 07:25:38 AM UTC 24 |
27496595 ps |
| T214 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.3783586687 |
|
|
Oct 09 07:25:35 AM UTC 24 |
Oct 09 07:25:38 AM UTC 24 |
70357773 ps |
| T1757 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_intr_test.2042197186 |
|
|
Oct 09 07:25:36 AM UTC 24 |
Oct 09 07:25:38 AM UTC 24 |
18200327 ps |
| T113 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_csr_rw.85877044 |
|
|
Oct 09 07:25:38 AM UTC 24 |
Oct 09 07:25:40 AM UTC 24 |
23386106 ps |
| T1758 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_same_csr_outstanding.1210259146 |
|
|
Oct 09 07:25:38 AM UTC 24 |
Oct 09 07:25:40 AM UTC 24 |
56873533 ps |
| T279 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_intr_test.871197854 |
|
|
Oct 09 07:25:38 AM UTC 24 |
Oct 09 07:25:40 AM UTC 24 |
140675497 ps |
| T194 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_tl_errors.3429124509 |
|
|
Oct 09 07:25:36 AM UTC 24 |
Oct 09 07:25:40 AM UTC 24 |
195073225 ps |
| T1759 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_bit_bash.1175168999 |
|
|
Oct 09 07:25:34 AM UTC 24 |
Oct 09 07:25:40 AM UTC 24 |
357260144 ps |
| T1760 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_csr_rw.3553718850 |
|
|
Oct 09 07:25:38 AM UTC 24 |
Oct 09 07:25:40 AM UTC 24 |
19041827 ps |
| T204 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_tl_intg_err.245775212 |
|
|
Oct 09 07:25:36 AM UTC 24 |
Oct 09 07:25:40 AM UTC 24 |
123936645 ps |
| T1761 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.2323330038 |
|
|
Oct 09 07:25:38 AM UTC 24 |
Oct 09 07:25:41 AM UTC 24 |
44323239 ps |
| T133 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_tl_intg_err.858920611 |
|
|
Oct 09 07:25:38 AM UTC 24 |
Oct 09 07:25:41 AM UTC 24 |
75470151 ps |
| T1762 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_same_csr_outstanding.4278335802 |
|
|
Oct 09 07:25:39 AM UTC 24 |
Oct 09 07:25:42 AM UTC 24 |
68215647 ps |
| T1763 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_tl_errors.4169001339 |
|
|
Oct 09 07:25:38 AM UTC 24 |
Oct 09 07:25:42 AM UTC 24 |
120282027 ps |
| T134 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.884431608 |
|
|
Oct 09 07:25:39 AM UTC 24 |
Oct 09 07:25:42 AM UTC 24 |
43861379 ps |
| T1764 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_tl_errors.2698244876 |
|
|
Oct 09 07:25:39 AM UTC 24 |
Oct 09 07:25:42 AM UTC 24 |
275532281 ps |
| T1765 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_csr_rw.132891593 |
|
|
Oct 09 07:25:41 AM UTC 24 |
Oct 09 07:25:43 AM UTC 24 |
72375812 ps |
| T283 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_intr_test.3106222672 |
|
|
Oct 09 07:25:41 AM UTC 24 |
Oct 09 07:25:43 AM UTC 24 |
18932150 ps |
| T1766 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.3409424687 |
|
|
Oct 09 07:25:41 AM UTC 24 |
Oct 09 07:25:43 AM UTC 24 |
82759348 ps |
| T1767 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_same_csr_outstanding.892573850 |
|
|
Oct 09 07:25:41 AM UTC 24 |
Oct 09 07:25:43 AM UTC 24 |
72705700 ps |
| T282 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_intr_test.3583770015 |
|
|
Oct 09 07:25:41 AM UTC 24 |
Oct 09 07:25:43 AM UTC 24 |
43949375 ps |
| T196 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_tl_intg_err.2968089498 |
|
|
Oct 09 07:25:41 AM UTC 24 |
Oct 09 07:25:43 AM UTC 24 |
447075456 ps |
| T1768 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.55812481 |
|
|
Oct 09 07:25:42 AM UTC 24 |
Oct 09 07:25:44 AM UTC 24 |
116301644 ps |
| T221 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_csr_rw.1298312105 |
|
|
Oct 09 07:25:42 AM UTC 24 |
Oct 09 07:25:44 AM UTC 24 |
24261773 ps |
| T1769 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_tl_errors.4292506174 |
|
|
Oct 09 07:25:41 AM UTC 24 |
Oct 09 07:25:44 AM UTC 24 |
68003716 ps |