T1328 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/36.i2c_target_stress_wr.3089919722 |
|
|
Oct 09 08:39:15 AM UTC 24 |
Oct 09 08:40:42 AM UTC 24 |
30823086995 ps |
T1329 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/38.i2c_host_fifo_reset_rx.219450364 |
|
|
Oct 09 08:40:36 AM UTC 24 |
Oct 09 08:40:43 AM UTC 24 |
329018161 ps |
T1330 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/38.i2c_host_perf.805863799 |
|
|
Oct 09 08:40:37 AM UTC 24 |
Oct 09 08:40:44 AM UTC 24 |
424123504 ps |
T1331 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/35.i2c_host_fifo_full.3044346716 |
|
|
Oct 09 08:38:18 AM UTC 24 |
Oct 09 08:40:44 AM UTC 24 |
8123917662 ps |
T1332 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/37.i2c_target_stress_wr.519718189 |
|
|
Oct 09 08:39:57 AM UTC 24 |
Oct 09 08:40:45 AM UTC 24 |
34780184009 ps |
T1333 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/38.i2c_host_fifo_fmt_empty.3197721206 |
|
|
Oct 09 08:40:35 AM UTC 24 |
Oct 09 08:40:53 AM UTC 24 |
3479009283 ps |
T1334 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/38.i2c_host_error_intr.801236782 |
|
|
Oct 09 08:40:44 AM UTC 24 |
Oct 09 08:40:56 AM UTC 24 |
1070592258 ps |
T1335 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/38.i2c_target_smoke.4029931590 |
|
|
Oct 09 08:40:45 AM UTC 24 |
Oct 09 08:40:58 AM UTC 24 |
14721628451 ps |
T1336 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/38.i2c_target_stretch.2642527881 |
|
|
Oct 09 08:40:53 AM UTC 24 |
Oct 09 08:40:59 AM UTC 24 |
861381117 ps |
T1337 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/38.i2c_target_intr_stress_wr.2884788175 |
|
|
Oct 09 08:40:59 AM UTC 24 |
Oct 09 08:41:11 AM UTC 24 |
16081548854 ps |
T1338 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/38.i2c_target_timeout.3219454506 |
|
|
Oct 09 08:41:00 AM UTC 24 |
Oct 09 08:41:12 AM UTC 24 |
1234459927 ps |
T1339 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/34.i2c_host_fifo_watermark.780791608 |
|
|
Oct 09 08:37:29 AM UTC 24 |
Oct 09 08:41:14 AM UTC 24 |
8129683845 ps |
T1340 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/38.i2c_target_fifo_reset_acq.3121043741 |
|
|
Oct 09 08:41:11 AM UTC 24 |
Oct 09 08:41:14 AM UTC 24 |
405087776 ps |
T1341 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/38.i2c_target_fifo_reset_tx.1653842252 |
|
|
Oct 09 08:41:12 AM UTC 24 |
Oct 09 08:41:16 AM UTC 24 |
193293819 ps |
T1342 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/38.i2c_target_stress_rd.1723925220 |
|
|
Oct 09 08:40:46 AM UTC 24 |
Oct 09 08:41:16 AM UTC 24 |
4281064243 ps |
T1343 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/37.i2c_target_intr_stress_wr.3926842470 |
|
|
Oct 09 08:40:03 AM UTC 24 |
Oct 09 08:41:17 AM UTC 24 |
18785126775 ps |
T1344 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/33.i2c_target_intr_stress_wr.2221722792 |
|
|
Oct 09 08:36:58 AM UTC 24 |
Oct 09 08:41:17 AM UTC 24 |
16024279956 ps |
T1345 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/37.i2c_target_stress_all.142365934 |
|
|
Oct 09 08:40:23 AM UTC 24 |
Oct 09 08:41:19 AM UTC 24 |
52429064001 ps |
T123 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/40.i2c_host_fifo_watermark.106065195 |
|
|
Oct 09 08:42:19 AM UTC 24 |
Oct 09 08:44:25 AM UTC 24 |
4978117853 ps |
T1346 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/38.i2c_target_hrst.4285590573 |
|
|
Oct 09 08:41:17 AM UTC 24 |
Oct 09 08:41:20 AM UTC 24 |
740865752 ps |
T1347 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/38.i2c_target_perf.624609719 |
|
|
Oct 09 08:41:14 AM UTC 24 |
Oct 09 08:41:21 AM UTC 24 |
4072822417 ps |
T1348 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/21.i2c_host_stress_all.4039404837 |
|
|
Oct 09 08:29:23 AM UTC 24 |
Oct 09 08:41:21 AM UTC 24 |
18630306770 ps |
T1349 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/38.i2c_host_mode_toggle.867519037 |
|
|
Oct 09 08:41:17 AM UTC 24 |
Oct 09 08:41:22 AM UTC 24 |
381081294 ps |
T1350 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/38.i2c_target_fifo_watermarks_acq.3131079286 |
|
|
Oct 09 08:41:18 AM UTC 24 |
Oct 09 08:41:22 AM UTC 24 |
453860442 ps |
T1351 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/38.i2c_target_fifo_watermarks_tx.3386742165 |
|
|
Oct 09 08:41:20 AM UTC 24 |
Oct 09 08:41:23 AM UTC 24 |
268238806 ps |
T1352 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/38.i2c_host_stretch_timeout.4293954948 |
|
|
Oct 09 08:40:43 AM UTC 24 |
Oct 09 08:41:24 AM UTC 24 |
910962761 ps |
T1353 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/38.i2c_target_tx_stretch_ctrl.1891875818 |
|
|
Oct 09 08:41:20 AM UTC 24 |
Oct 09 08:41:24 AM UTC 24 |
175542221 ps |
T1354 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/38.i2c_target_bad_addr.1156511268 |
|
|
Oct 09 08:41:16 AM UTC 24 |
Oct 09 08:41:25 AM UTC 24 |
971687965 ps |
T1355 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/38.i2c_host_may_nack.1023435390 |
|
|
Oct 09 08:41:18 AM UTC 24 |
Oct 09 08:41:26 AM UTC 24 |
541709358 ps |
T1356 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/38.i2c_alert_test.1072117711 |
|
|
Oct 09 08:41:24 AM UTC 24 |
Oct 09 08:41:26 AM UTC 24 |
114479766 ps |
T1357 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/42.i2c_target_smbus_maxlen.1644743537 |
|
|
Oct 09 08:44:19 AM UTC 24 |
Oct 09 08:44:25 AM UTC 24 |
1170274317 ps |
T1358 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/38.i2c_host_smoke.3890739609 |
|
|
Oct 09 08:40:33 AM UTC 24 |
Oct 09 08:41:27 AM UTC 24 |
8129857589 ps |
T1359 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/39.i2c_host_override.2249636668 |
|
|
Oct 09 08:41:25 AM UTC 24 |
Oct 09 08:41:28 AM UTC 24 |
15261000 ps |
T1360 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/38.i2c_target_smbus_maxlen.2278068921 |
|
|
Oct 09 08:41:23 AM UTC 24 |
Oct 09 08:41:28 AM UTC 24 |
1970053317 ps |
T51 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/38.i2c_target_nack_acqfull_addr.1461942941 |
|
|
Oct 09 08:41:24 AM UTC 24 |
Oct 09 08:41:29 AM UTC 24 |
3873095085 ps |
T1361 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/38.i2c_target_nack_acqfull.1898156802 |
|
|
Oct 09 08:41:23 AM UTC 24 |
Oct 09 08:41:29 AM UTC 24 |
1125962826 ps |
T1362 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/39.i2c_host_fifo_reset_fmt.3022331452 |
|
|
Oct 09 08:41:27 AM UTC 24 |
Oct 09 08:41:29 AM UTC 24 |
85503419 ps |
T1363 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/36.i2c_host_fifo_watermark.1358186095 |
|
|
Oct 09 08:38:57 AM UTC 24 |
Oct 09 08:41:31 AM UTC 24 |
47113687182 ps |
T1364 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/39.i2c_host_fifo_reset_rx.2327520412 |
|
|
Oct 09 08:41:28 AM UTC 24 |
Oct 09 08:41:33 AM UTC 24 |
140316048 ps |
T1365 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/39.i2c_host_error_intr.2634734769 |
|
|
Oct 09 08:41:31 AM UTC 24 |
Oct 09 08:41:34 AM UTC 24 |
297773379 ps |
T1366 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/39.i2c_host_perf_precise.2914279930 |
|
|
Oct 09 08:41:29 AM UTC 24 |
Oct 09 08:41:40 AM UTC 24 |
818672978 ps |
T1367 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/39.i2c_host_fifo_fmt_empty.2975582563 |
|
|
Oct 09 08:41:28 AM UTC 24 |
Oct 09 08:41:51 AM UTC 24 |
676972979 ps |
T1368 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/38.i2c_host_perf_precise.250548335 |
|
|
Oct 09 08:40:40 AM UTC 24 |
Oct 09 08:41:53 AM UTC 24 |
6039782136 ps |
T1369 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/37.i2c_host_fifo_full.259171951 |
|
|
Oct 09 08:39:44 AM UTC 24 |
Oct 09 08:41:54 AM UTC 24 |
6089882301 ps |
T1370 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/39.i2c_host_stretch_timeout.2416007123 |
|
|
Oct 09 08:41:31 AM UTC 24 |
Oct 09 08:41:55 AM UTC 24 |
916987221 ps |
T1371 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/38.i2c_host_fifo_overflow.3987017928 |
|
|
Oct 09 08:40:35 AM UTC 24 |
Oct 09 08:42:02 AM UTC 24 |
3796237620 ps |
T1372 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/39.i2c_target_intr_smoke.1382611023 |
|
|
Oct 09 08:41:54 AM UTC 24 |
Oct 09 08:42:02 AM UTC 24 |
571237166 ps |
T1373 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/39.i2c_target_stress_rd.3115797376 |
|
|
Oct 09 08:41:41 AM UTC 24 |
Oct 09 08:42:04 AM UTC 24 |
3807358743 ps |
T1374 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/37.i2c_host_fifo_watermark.2259946046 |
|
|
Oct 09 08:39:41 AM UTC 24 |
Oct 09 08:42:06 AM UTC 24 |
11102343514 ps |
T1375 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/39.i2c_target_fifo_reset_acq.1566862647 |
|
|
Oct 09 08:42:03 AM UTC 24 |
Oct 09 08:42:06 AM UTC 24 |
306265364 ps |
T1376 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/39.i2c_target_timeout.3923009385 |
|
|
Oct 09 08:41:57 AM UTC 24 |
Oct 09 08:42:07 AM UTC 24 |
1235635722 ps |
T1377 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/38.i2c_target_stress_all.2122100378 |
|
|
Oct 09 08:41:15 AM UTC 24 |
Oct 09 08:42:08 AM UTC 24 |
16910368602 ps |
T1378 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/39.i2c_target_fifo_reset_tx.1025282710 |
|
|
Oct 09 08:42:05 AM UTC 24 |
Oct 09 08:42:08 AM UTC 24 |
220338582 ps |
T88 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/39.i2c_target_smoke.2560958152 |
|
|
Oct 09 08:41:35 AM UTC 24 |
Oct 09 08:42:10 AM UTC 24 |
1884130672 ps |
T1379 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/39.i2c_host_mode_toggle.2580561170 |
|
|
Oct 09 08:42:09 AM UTC 24 |
Oct 09 08:42:12 AM UTC 24 |
214347948 ps |
T1380 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/39.i2c_target_hrst.2085963535 |
|
|
Oct 09 08:42:08 AM UTC 24 |
Oct 09 08:42:13 AM UTC 24 |
270568137 ps |
T1381 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/39.i2c_target_bad_addr.787414124 |
|
|
Oct 09 08:42:08 AM UTC 24 |
Oct 09 08:42:14 AM UTC 24 |
706814982 ps |
T1382 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/39.i2c_target_tx_stretch_ctrl.2297466362 |
|
|
Oct 09 08:42:13 AM UTC 24 |
Oct 09 08:42:16 AM UTC 24 |
37650898 ps |
T1383 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/39.i2c_target_fifo_watermarks_acq.2746134420 |
|
|
Oct 09 08:42:11 AM UTC 24 |
Oct 09 08:42:16 AM UTC 24 |
1817145849 ps |
T1384 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/39.i2c_target_stretch.2524557784 |
|
|
Oct 09 08:41:52 AM UTC 24 |
Oct 09 08:42:17 AM UTC 24 |
1261251330 ps |
T1385 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/39.i2c_target_fifo_watermarks_tx.1784419726 |
|
|
Oct 09 08:42:13 AM UTC 24 |
Oct 09 08:42:17 AM UTC 24 |
151523815 ps |
T1386 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/39.i2c_target_perf.547196775 |
|
|
Oct 09 08:42:07 AM UTC 24 |
Oct 09 08:42:18 AM UTC 24 |
4739020878 ps |
T1387 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/39.i2c_host_may_nack.555076979 |
|
|
Oct 09 08:42:09 AM UTC 24 |
Oct 09 08:42:18 AM UTC 24 |
1601201666 ps |
T1388 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/35.i2c_host_fifo_watermark.42961738 |
|
|
Oct 09 08:38:16 AM UTC 24 |
Oct 09 08:42:18 AM UTC 24 |
3759263674 ps |
T1389 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/39.i2c_target_smbus_maxlen.1652915631 |
|
|
Oct 09 08:42:14 AM UTC 24 |
Oct 09 08:42:19 AM UTC 24 |
1800478472 ps |
T1390 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/39.i2c_host_fifo_watermark.393487069 |
|
|
Oct 09 08:41:27 AM UTC 24 |
Oct 09 08:42:19 AM UTC 24 |
2688116610 ps |
T1391 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/39.i2c_alert_test.3054843462 |
|
|
Oct 09 08:42:18 AM UTC 24 |
Oct 09 08:42:20 AM UTC 24 |
16126272 ps |
T234 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/16.i2c_host_stress_all.1024225485 |
|
|
Oct 09 08:25:57 AM UTC 24 |
Oct 09 08:42:20 AM UTC 24 |
44112580631 ps |
T1392 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/39.i2c_target_nack_txstretch.2221932540 |
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|
Oct 09 08:42:18 AM UTC 24 |
Oct 09 08:42:21 AM UTC 24 |
295321939 ps |
T1393 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/40.i2c_host_override.3040210190 |
|
|
Oct 09 08:42:19 AM UTC 24 |
Oct 09 08:42:21 AM UTC 24 |
92271492 ps |
T1394 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/39.i2c_target_nack_acqfull.1757798269 |
|
|
Oct 09 08:42:16 AM UTC 24 |
Oct 09 08:42:22 AM UTC 24 |
1884894052 ps |
T1395 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/39.i2c_target_nack_acqfull_addr.1821416845 |
|
|
Oct 09 08:42:18 AM UTC 24 |
Oct 09 08:42:23 AM UTC 24 |
2001673230 ps |
T1396 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/40.i2c_host_fifo_reset_fmt.2975146196 |
|
|
Oct 09 08:42:21 AM UTC 24 |
Oct 09 08:42:23 AM UTC 24 |
394845624 ps |
T1397 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/40.i2c_host_perf_precise.1907883077 |
|
|
Oct 09 08:42:23 AM UTC 24 |
Oct 09 08:42:27 AM UTC 24 |
53670923 ps |
T1398 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/40.i2c_host_error_intr.1115338920 |
|
|
Oct 09 08:42:24 AM UTC 24 |
Oct 09 08:42:28 AM UTC 24 |
94469165 ps |
T1399 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/39.i2c_host_fifo_overflow.3663977597 |
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|
Oct 09 08:41:27 AM UTC 24 |
Oct 09 08:42:29 AM UTC 24 |
10288547982 ps |
T1400 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/40.i2c_host_fifo_reset_rx.100139712 |
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|
Oct 09 08:42:21 AM UTC 24 |
Oct 09 08:42:30 AM UTC 24 |
150718816 ps |
T1401 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/39.i2c_host_fifo_full.1972152002 |
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|
Oct 09 08:41:29 AM UTC 24 |
Oct 09 08:42:31 AM UTC 24 |
9740128089 ps |
T1402 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/40.i2c_target_stretch.3740757755 |
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|
Oct 09 08:42:32 AM UTC 24 |
Oct 09 08:42:39 AM UTC 24 |
1201293491 ps |
T275 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/27.i2c_host_stress_all.3301057320 |
|
|
Oct 09 08:33:13 AM UTC 24 |
Oct 09 08:42:44 AM UTC 24 |
17345384175 ps |
T1403 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/40.i2c_target_intr_smoke.2369458222 |
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|
Oct 09 08:42:40 AM UTC 24 |
Oct 09 08:42:48 AM UTC 24 |
7137895723 ps |
T1404 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/40.i2c_host_stretch_timeout.1668147663 |
|
|
Oct 09 08:42:24 AM UTC 24 |
Oct 09 08:42:49 AM UTC 24 |
967801954 ps |
T1405 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/40.i2c_host_fifo_fmt_empty.2035824962 |
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|
Oct 09 08:42:21 AM UTC 24 |
Oct 09 08:42:50 AM UTC 24 |
468596819 ps |
T1406 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/39.i2c_target_stress_all.1556513978 |
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|
Oct 09 08:42:07 AM UTC 24 |
Oct 09 08:42:50 AM UTC 24 |
38256427041 ps |
T1407 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/40.i2c_host_smoke.427703115 |
|
|
Oct 09 08:42:19 AM UTC 24 |
Oct 09 08:42:51 AM UTC 24 |
9045971807 ps |
T1408 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/4.i2c_target_stress_all.1873498314 |
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|
Oct 09 08:14:30 AM UTC 24 |
Oct 09 08:42:53 AM UTC 24 |
57980479637 ps |
T1409 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/40.i2c_target_fifo_reset_acq.1415975069 |
|
|
Oct 09 08:42:51 AM UTC 24 |
Oct 09 08:42:54 AM UTC 24 |
181465788 ps |
T1410 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/40.i2c_target_fifo_reset_tx.1233707694 |
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|
Oct 09 08:42:51 AM UTC 24 |
Oct 09 08:42:55 AM UTC 24 |
179125431 ps |
T1411 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/32.i2c_target_stress_wr.3951913748 |
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|
Oct 09 08:36:23 AM UTC 24 |
Oct 09 08:42:56 AM UTC 24 |
52787675581 ps |
T1412 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/33.i2c_host_fifo_watermark.1992256174 |
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|
Oct 09 08:36:48 AM UTC 24 |
Oct 09 08:42:57 AM UTC 24 |
21807734585 ps |
T1413 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/40.i2c_host_perf.1645585761 |
|
|
Oct 09 08:42:22 AM UTC 24 |
Oct 09 08:42:57 AM UTC 24 |
4817270953 ps |
T1414 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/40.i2c_target_smoke.161652400 |
|
|
Oct 09 08:42:29 AM UTC 24 |
Oct 09 08:42:57 AM UTC 24 |
3439053782 ps |
T89 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/42.i2c_target_smoke.1714702161 |
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|
Oct 09 08:43:54 AM UTC 24 |
Oct 09 08:44:24 AM UTC 24 |
17383472354 ps |
T1415 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/32.i2c_target_intr_stress_wr.1457494844 |
|
|
Oct 09 08:36:27 AM UTC 24 |
Oct 09 08:42:58 AM UTC 24 |
19280090271 ps |
T1416 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/40.i2c_target_intr_stress_wr.3892154492 |
|
|
Oct 09 08:42:44 AM UTC 24 |
Oct 09 08:42:59 AM UTC 24 |
5987192371 ps |
T1417 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/40.i2c_target_hrst.3900756611 |
|
|
Oct 09 08:42:55 AM UTC 24 |
Oct 09 08:42:59 AM UTC 24 |
1188167528 ps |
T1418 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/40.i2c_target_perf.1147808647 |
|
|
Oct 09 08:42:52 AM UTC 24 |
Oct 09 08:43:00 AM UTC 24 |
1193200404 ps |
T1419 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/40.i2c_target_timeout.3448909921 |
|
|
Oct 09 08:42:50 AM UTC 24 |
Oct 09 08:43:01 AM UTC 24 |
1528519778 ps |
T1420 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/40.i2c_target_fifo_watermarks_tx.3597055670 |
|
|
Oct 09 08:42:58 AM UTC 24 |
Oct 09 08:43:01 AM UTC 24 |
467821726 ps |
T1421 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/40.i2c_alert_test.4059506692 |
|
|
Oct 09 08:43:01 AM UTC 24 |
Oct 09 08:43:03 AM UTC 24 |
48845256 ps |
T1422 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/40.i2c_target_smbus_maxlen.1644599160 |
|
|
Oct 09 08:42:59 AM UTC 24 |
Oct 09 08:43:03 AM UTC 24 |
406399008 ps |
T1423 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/40.i2c_target_fifo_watermarks_acq.886145773 |
|
|
Oct 09 08:42:58 AM UTC 24 |
Oct 09 08:43:04 AM UTC 24 |
752940340 ps |
T1424 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/41.i2c_host_override.2481918426 |
|
|
Oct 09 08:43:02 AM UTC 24 |
Oct 09 08:43:04 AM UTC 24 |
93707494 ps |
T1425 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/40.i2c_target_stress_rd.1380179440 |
|
|
Oct 09 08:42:31 AM UTC 24 |
Oct 09 08:43:04 AM UTC 24 |
5436903115 ps |
T1426 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/40.i2c_target_nack_txstretch.2576158245 |
|
|
Oct 09 08:43:01 AM UTC 24 |
Oct 09 08:43:05 AM UTC 24 |
272641645 ps |
T1427 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/40.i2c_target_bad_addr.258919687 |
|
|
Oct 09 08:42:55 AM UTC 24 |
Oct 09 08:43:05 AM UTC 24 |
967295481 ps |
T1428 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/40.i2c_target_nack_acqfull.4192222919 |
|
|
Oct 09 08:42:59 AM UTC 24 |
Oct 09 08:43:05 AM UTC 24 |
2879984515 ps |
T1429 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/40.i2c_target_tx_stretch_ctrl.3412238424 |
|
|
Oct 09 08:42:59 AM UTC 24 |
Oct 09 08:43:06 AM UTC 24 |
264771830 ps |
T1430 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/42.i2c_alert_test.3727561124 |
|
|
Oct 09 08:44:23 AM UTC 24 |
Oct 09 08:44:25 AM UTC 24 |
43152015 ps |
T1431 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/40.i2c_target_nack_acqfull_addr.731833553 |
|
|
Oct 09 08:43:01 AM UTC 24 |
Oct 09 08:43:06 AM UTC 24 |
1556055294 ps |
T1432 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/39.i2c_host_perf.3038460346 |
|
|
Oct 09 08:41:29 AM UTC 24 |
Oct 09 08:43:06 AM UTC 24 |
6698920764 ps |
T261 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/40.i2c_host_may_nack.2302787504 |
|
|
Oct 09 08:42:57 AM UTC 24 |
Oct 09 08:43:08 AM UTC 24 |
1948553687 ps |
T1433 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/41.i2c_host_fifo_reset_fmt.3868171432 |
|
|
Oct 09 08:43:05 AM UTC 24 |
Oct 09 08:43:08 AM UTC 24 |
110755440 ps |
T1434 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/35.i2c_target_intr_stress_wr.3767077683 |
|
|
Oct 09 08:38:32 AM UTC 24 |
Oct 09 08:43:08 AM UTC 24 |
16984793267 ps |
T1435 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/38.i2c_host_fifo_watermark.4096312093 |
|
|
Oct 09 08:40:34 AM UTC 24 |
Oct 09 08:43:12 AM UTC 24 |
3096482767 ps |
T1436 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/39.i2c_host_smoke.3965817243 |
|
|
Oct 09 08:41:25 AM UTC 24 |
Oct 09 08:43:14 AM UTC 24 |
2221630486 ps |
T1437 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/41.i2c_target_stretch.3765074985 |
|
|
Oct 09 08:43:13 AM UTC 24 |
Oct 09 08:43:17 AM UTC 24 |
316021536 ps |
T1438 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/41.i2c_host_error_intr.3674353884 |
|
|
Oct 09 08:43:07 AM UTC 24 |
Oct 09 08:43:17 AM UTC 24 |
349132250 ps |
T1439 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/41.i2c_host_fifo_reset_rx.1824773779 |
|
|
Oct 09 08:43:06 AM UTC 24 |
Oct 09 08:43:18 AM UTC 24 |
405063823 ps |
T1440 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/41.i2c_target_stress_rd.1249729516 |
|
|
Oct 09 08:43:09 AM UTC 24 |
Oct 09 08:43:21 AM UTC 24 |
3334558152 ps |
T1441 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/38.i2c_host_fifo_full.1125703891 |
|
|
Oct 09 08:40:36 AM UTC 24 |
Oct 09 08:43:22 AM UTC 24 |
2779690746 ps |
T1442 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/41.i2c_host_fifo_fmt_empty.367908375 |
|
|
Oct 09 08:43:06 AM UTC 24 |
Oct 09 08:43:23 AM UTC 24 |
540761936 ps |
T1443 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/41.i2c_target_fifo_reset_acq.3957481708 |
|
|
Oct 09 08:43:23 AM UTC 24 |
Oct 09 08:43:25 AM UTC 24 |
389152203 ps |
T1444 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/41.i2c_target_fifo_reset_tx.27923714 |
|
|
Oct 09 08:43:23 AM UTC 24 |
Oct 09 08:43:26 AM UTC 24 |
175710770 ps |
T1445 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/41.i2c_target_intr_smoke.487985185 |
|
|
Oct 09 08:43:15 AM UTC 24 |
Oct 09 08:43:26 AM UTC 24 |
4438549839 ps |
T1446 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/41.i2c_target_smoke.2664154664 |
|
|
Oct 09 08:43:09 AM UTC 24 |
Oct 09 08:43:29 AM UTC 24 |
1190701401 ps |
T1447 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/41.i2c_target_perf.1276784230 |
|
|
Oct 09 08:43:24 AM UTC 24 |
Oct 09 08:43:29 AM UTC 24 |
2787263263 ps |
T1448 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/41.i2c_target_hrst.7547485 |
|
|
Oct 09 08:43:27 AM UTC 24 |
Oct 09 08:43:30 AM UTC 24 |
376495005 ps |
T1449 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/41.i2c_target_timeout.2403734794 |
|
|
Oct 09 08:43:17 AM UTC 24 |
Oct 09 08:43:31 AM UTC 24 |
1645635630 ps |
T1450 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/41.i2c_host_stretch_timeout.2781248802 |
|
|
Oct 09 08:43:07 AM UTC 24 |
Oct 09 08:43:32 AM UTC 24 |
1644669264 ps |
T1451 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/41.i2c_target_bad_addr.3117988444 |
|
|
Oct 09 08:43:26 AM UTC 24 |
Oct 09 08:43:35 AM UTC 24 |
872488515 ps |
T1452 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/41.i2c_target_fifo_watermarks_tx.3249098677 |
|
|
Oct 09 08:43:32 AM UTC 24 |
Oct 09 08:43:35 AM UTC 24 |
576318654 ps |
T1453 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/41.i2c_target_stress_wr.3717831415 |
|
|
Oct 09 08:43:09 AM UTC 24 |
Oct 09 08:43:35 AM UTC 24 |
9950968967 ps |
T1454 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/41.i2c_target_smbus_maxlen.1744883320 |
|
|
Oct 09 08:43:33 AM UTC 24 |
Oct 09 08:43:37 AM UTC 24 |
882973776 ps |
T1455 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/41.i2c_target_fifo_watermarks_acq.336794364 |
|
|
Oct 09 08:43:30 AM UTC 24 |
Oct 09 08:43:37 AM UTC 24 |
6010025009 ps |
T1456 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/41.i2c_target_tx_stretch_ctrl.1047638474 |
|
|
Oct 09 08:43:32 AM UTC 24 |
Oct 09 08:43:38 AM UTC 24 |
177345708 ps |
T1457 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/41.i2c_host_may_nack.3976836483 |
|
|
Oct 09 08:43:29 AM UTC 24 |
Oct 09 08:43:38 AM UTC 24 |
480443481 ps |
T1458 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/41.i2c_alert_test.2055333297 |
|
|
Oct 09 08:43:36 AM UTC 24 |
Oct 09 08:43:39 AM UTC 24 |
46747493 ps |
T1459 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/41.i2c_target_nack_txstretch.2831272567 |
|
|
Oct 09 08:43:35 AM UTC 24 |
Oct 09 08:43:39 AM UTC 24 |
380373651 ps |
T1460 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/42.i2c_host_override.2950629863 |
|
|
Oct 09 08:43:38 AM UTC 24 |
Oct 09 08:43:40 AM UTC 24 |
20413706 ps |
T1461 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/41.i2c_target_nack_acqfull.4223492331 |
|
|
Oct 09 08:43:34 AM UTC 24 |
Oct 09 08:43:41 AM UTC 24 |
2229208851 ps |
T1462 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/41.i2c_target_nack_acqfull_addr.2907539481 |
|
|
Oct 09 08:43:35 AM UTC 24 |
Oct 09 08:43:41 AM UTC 24 |
542508726 ps |
T1463 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/42.i2c_host_fifo_reset_fmt.4016259198 |
|
|
Oct 09 08:43:40 AM UTC 24 |
Oct 09 08:43:43 AM UTC 24 |
199592218 ps |
T1464 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/42.i2c_host_perf_precise.2666426119 |
|
|
Oct 09 08:43:44 AM UTC 24 |
Oct 09 08:43:46 AM UTC 24 |
103612776 ps |
T1465 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/41.i2c_host_smoke.3082924948 |
|
|
Oct 09 08:43:02 AM UTC 24 |
Oct 09 08:43:48 AM UTC 24 |
3486865720 ps |
T1466 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/42.i2c_host_fifo_fmt_empty.3922054440 |
|
|
Oct 09 08:43:40 AM UTC 24 |
Oct 09 08:43:50 AM UTC 24 |
581271453 ps |
T1467 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/42.i2c_host_fifo_reset_rx.1184186497 |
|
|
Oct 09 08:43:41 AM UTC 24 |
Oct 09 08:43:54 AM UTC 24 |
192134560 ps |
T1468 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/40.i2c_host_fifo_full.2764413986 |
|
|
Oct 09 08:42:22 AM UTC 24 |
Oct 09 08:43:54 AM UTC 24 |
12402752786 ps |
T1469 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/41.i2c_host_perf_precise.2299379477 |
|
|
Oct 09 08:43:07 AM UTC 24 |
Oct 09 08:43:56 AM UTC 24 |
2692084113 ps |
T1470 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/37.i2c_host_perf_precise.2936758496 |
|
|
Oct 09 08:39:49 AM UTC 24 |
Oct 09 08:43:57 AM UTC 24 |
23216284648 ps |
T1471 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/42.i2c_host_error_intr.2091445443 |
|
|
Oct 09 08:43:49 AM UTC 24 |
Oct 09 08:43:58 AM UTC 24 |
3174435006 ps |
T1472 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/34.i2c_target_stress_all.2223521894 |
|
|
Oct 09 08:38:04 AM UTC 24 |
Oct 09 08:43:59 AM UTC 24 |
67572668893 ps |
T1473 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/41.i2c_host_fifo_overflow.1477104640 |
|
|
Oct 09 08:43:04 AM UTC 24 |
Oct 09 08:44:00 AM UTC 24 |
1930291077 ps |
T1474 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/42.i2c_host_stretch_timeout.487659298 |
|
|
Oct 09 08:43:47 AM UTC 24 |
Oct 09 08:44:05 AM UTC 24 |
1709544483 ps |
T1475 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/42.i2c_target_intr_smoke.3756923124 |
|
|
Oct 09 08:43:59 AM UTC 24 |
Oct 09 08:44:08 AM UTC 24 |
1106538599 ps |
T1476 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/41.i2c_host_fifo_full.3216084660 |
|
|
Oct 09 08:43:06 AM UTC 24 |
Oct 09 08:44:08 AM UTC 24 |
2426986436 ps |
T1477 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/42.i2c_target_stretch.2850054290 |
|
|
Oct 09 08:43:58 AM UTC 24 |
Oct 09 08:44:10 AM UTC 24 |
666081673 ps |
T1478 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/42.i2c_target_fifo_reset_acq.2447180833 |
|
|
Oct 09 08:44:08 AM UTC 24 |
Oct 09 08:44:12 AM UTC 24 |
1052236917 ps |
T1479 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/42.i2c_target_fifo_reset_tx.3215810832 |
|
|
Oct 09 08:44:09 AM UTC 24 |
Oct 09 08:44:13 AM UTC 24 |
1932164645 ps |
T1480 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/42.i2c_target_bad_addr.3197054030 |
|
|
Oct 09 08:44:11 AM UTC 24 |
Oct 09 08:44:15 AM UTC 24 |
535899769 ps |
T1481 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/42.i2c_target_hrst.1065769690 |
|
|
Oct 09 08:44:13 AM UTC 24 |
Oct 09 08:44:17 AM UTC 24 |
691373567 ps |
T1482 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/42.i2c_target_timeout.2587812399 |
|
|
Oct 09 08:44:01 AM UTC 24 |
Oct 09 08:44:17 AM UTC 24 |
5674308962 ps |
T1483 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/42.i2c_target_perf.4123496183 |
|
|
Oct 09 08:44:09 AM UTC 24 |
Oct 09 08:44:17 AM UTC 24 |
5443209344 ps |
T1484 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/42.i2c_host_fifo_overflow.1439796585 |
|
|
Oct 09 08:43:39 AM UTC 24 |
Oct 09 08:44:21 AM UTC 24 |
1621516964 ps |
T1485 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/42.i2c_host_may_nack.1686542424 |
|
|
Oct 09 08:44:16 AM UTC 24 |
Oct 09 08:44:21 AM UTC 24 |
489404163 ps |
T1486 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/42.i2c_target_fifo_watermarks_acq.1476089070 |
|
|
Oct 09 08:44:17 AM UTC 24 |
Oct 09 08:44:22 AM UTC 24 |
411087614 ps |
T1487 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/42.i2c_target_fifo_watermarks_tx.3542792386 |
|
|
Oct 09 08:44:18 AM UTC 24 |
Oct 09 08:44:22 AM UTC 24 |
145923485 ps |
T1488 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/42.i2c_target_nack_acqfull.3780202431 |
|
|
Oct 09 08:44:22 AM UTC 24 |
Oct 09 08:44:27 AM UTC 24 |
2014727727 ps |
T1489 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/44.i2c_target_smoke.4142305282 |
|
|
Oct 09 08:45:27 AM UTC 24 |
Oct 09 08:45:56 AM UTC 24 |
731108100 ps |
T1490 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/43.i2c_host_override.4285454634 |
|
|
Oct 09 08:44:25 AM UTC 24 |
Oct 09 08:44:27 AM UTC 24 |
54705564 ps |
T1491 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/42.i2c_target_nack_acqfull_addr.260491874 |
|
|
Oct 09 08:44:22 AM UTC 24 |
Oct 09 08:44:27 AM UTC 24 |
497574390 ps |
T1492 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/42.i2c_host_smoke.3875358399 |
|
|
Oct 09 08:43:38 AM UTC 24 |
Oct 09 08:44:28 AM UTC 24 |
1130406623 ps |
T1493 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/42.i2c_target_tx_stretch_ctrl.3132517068 |
|
|
Oct 09 08:44:18 AM UTC 24 |
Oct 09 08:44:28 AM UTC 24 |
361416555 ps |
T1494 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/43.i2c_host_fifo_reset_fmt.4063184492 |
|
|
Oct 09 08:44:28 AM UTC 24 |
Oct 09 08:44:31 AM UTC 24 |
227476016 ps |
T1495 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/43.i2c_host_perf_precise.1598642344 |
|
|
Oct 09 08:44:29 AM UTC 24 |
Oct 09 08:44:32 AM UTC 24 |
53757950 ps |
T1496 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/42.i2c_host_fifo_watermark.2327705343 |
|
|
Oct 09 08:43:39 AM UTC 24 |
Oct 09 08:44:35 AM UTC 24 |
42298619609 ps |
T1497 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/43.i2c_host_fifo_reset_rx.3869201405 |
|
|
Oct 09 08:44:28 AM UTC 24 |
Oct 09 08:44:36 AM UTC 24 |
358159532 ps |
T1498 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/43.i2c_host_fifo_fmt_empty.2924622499 |
|
|
Oct 09 08:44:28 AM UTC 24 |
Oct 09 08:44:36 AM UTC 24 |
2037502733 ps |
T1499 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/43.i2c_host_error_intr.826828409 |
|
|
Oct 09 08:44:32 AM UTC 24 |
Oct 09 08:44:41 AM UTC 24 |
760387161 ps |
T1500 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/43.i2c_host_stretch_timeout.2552485504 |
|
|
Oct 09 08:44:29 AM UTC 24 |
Oct 09 08:44:43 AM UTC 24 |
577666123 ps |
T1501 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/42.i2c_target_stress_rd.3392488670 |
|
|
Oct 09 08:43:57 AM UTC 24 |
Oct 09 08:44:54 AM UTC 24 |
4147110835 ps |
T1502 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/43.i2c_target_smoke.1635370422 |
|
|
Oct 09 08:44:36 AM UTC 24 |
Oct 09 08:44:55 AM UTC 24 |
4332534461 ps |
T1503 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/43.i2c_host_smoke.538433916 |
|
|
Oct 09 08:44:25 AM UTC 24 |
Oct 09 08:44:56 AM UTC 24 |
2555869259 ps |
T1504 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/42.i2c_host_fifo_full.3609949338 |
|
|
Oct 09 08:43:41 AM UTC 24 |
Oct 09 08:44:57 AM UTC 24 |
2793904798 ps |
T1505 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/43.i2c_target_intr_smoke.3720153487 |
|
|
Oct 09 08:44:43 AM UTC 24 |
Oct 09 08:45:00 AM UTC 24 |
1509960889 ps |
T1506 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/43.i2c_target_fifo_reset_acq.2789230321 |
|
|
Oct 09 08:44:59 AM UTC 24 |
Oct 09 08:45:02 AM UTC 24 |
743806716 ps |
T1507 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/40.i2c_host_fifo_overflow.1631214711 |
|
|
Oct 09 08:42:19 AM UTC 24 |
Oct 09 08:45:03 AM UTC 24 |
2187558499 ps |
T1508 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/42.i2c_target_intr_stress_wr.1126211989 |
|
|
Oct 09 08:44:00 AM UTC 24 |
Oct 09 08:45:03 AM UTC 24 |
22145886131 ps |
T1509 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/43.i2c_target_fifo_reset_tx.2459898998 |
|
|
Oct 09 08:45:01 AM UTC 24 |
Oct 09 08:45:04 AM UTC 24 |
316160158 ps |
T1510 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/43.i2c_target_stress_rd.742223367 |
|
|
Oct 09 08:44:37 AM UTC 24 |
Oct 09 08:45:08 AM UTC 24 |
6643352628 ps |
T1511 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/43.i2c_target_hrst.914302303 |
|
|
Oct 09 08:45:05 AM UTC 24 |
Oct 09 08:45:08 AM UTC 24 |
178889438 ps |
T1512 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/43.i2c_target_perf.2829731045 |
|
|
Oct 09 08:45:01 AM UTC 24 |
Oct 09 08:45:10 AM UTC 24 |
7006890610 ps |
T1513 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/43.i2c_target_timeout.958744739 |
|
|
Oct 09 08:44:57 AM UTC 24 |
Oct 09 08:45:10 AM UTC 24 |
4825310889 ps |
T1514 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/43.i2c_target_fifo_watermarks_tx.1625663199 |
|
|
Oct 09 08:45:09 AM UTC 24 |
Oct 09 08:45:12 AM UTC 24 |
154742501 ps |
T1515 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/43.i2c_target_bad_addr.3015359022 |
|
|
Oct 09 08:45:03 AM UTC 24 |
Oct 09 08:45:13 AM UTC 24 |
846457769 ps |
T1516 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/43.i2c_target_fifo_watermarks_acq.2113725608 |
|
|
Oct 09 08:45:09 AM UTC 24 |
Oct 09 08:45:14 AM UTC 24 |
1521791342 ps |
T1517 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/41.i2c_host_fifo_watermark.743462103 |
|
|
Oct 09 08:43:04 AM UTC 24 |
Oct 09 08:45:14 AM UTC 24 |
34407002787 ps |
T1518 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/43.i2c_target_tx_stretch_ctrl.27242905 |
|
|
Oct 09 08:45:11 AM UTC 24 |
Oct 09 08:45:15 AM UTC 24 |
142246790 ps |
T1519 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/43.i2c_target_smbus_maxlen.2317061055 |
|
|
Oct 09 08:45:11 AM UTC 24 |
Oct 09 08:45:15 AM UTC 24 |
3141646524 ps |
T1520 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/43.i2c_alert_test.913093061 |
|
|
Oct 09 08:45:14 AM UTC 24 |
Oct 09 08:45:16 AM UTC 24 |
24838912 ps |
T1521 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/43.i2c_target_nack_acqfull.1479616829 |
|
|
Oct 09 08:45:11 AM UTC 24 |
Oct 09 08:45:16 AM UTC 24 |
8335963248 ps |
T1522 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/43.i2c_host_perf.1066374378 |
|
|
Oct 09 08:44:29 AM UTC 24 |
Oct 09 08:45:16 AM UTC 24 |
2874977160 ps |
T1523 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/43.i2c_target_nack_txstretch.406762991 |
|
|
Oct 09 08:45:14 AM UTC 24 |
Oct 09 08:45:17 AM UTC 24 |
194724027 ps |
T1524 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/43.i2c_target_nack_acqfull_addr.2860349692 |
|
|
Oct 09 08:45:12 AM UTC 24 |
Oct 09 08:45:18 AM UTC 24 |
611824621 ps |
T1525 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/44.i2c_host_override.3018247252 |
|
|
Oct 09 08:45:16 AM UTC 24 |
Oct 09 08:45:18 AM UTC 24 |
80840580 ps |
T1526 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/44.i2c_host_fifo_reset_fmt.1924898251 |
|
|
Oct 09 08:45:17 AM UTC 24 |
Oct 09 08:45:20 AM UTC 24 |
1362184975 ps |
T1527 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/41.i2c_target_intr_stress_wr.2273520357 |
|
|
Oct 09 08:43:17 AM UTC 24 |
Oct 09 08:45:24 AM UTC 24 |
14132715591 ps |
T1528 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/43.i2c_host_may_nack.2831881708 |
|
|
Oct 09 08:45:06 AM UTC 24 |
Oct 09 08:45:26 AM UTC 24 |
3523111537 ps |
T1529 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/40.i2c_target_stress_wr.1286137064 |
|
|
Oct 09 08:42:30 AM UTC 24 |
Oct 09 08:45:26 AM UTC 24 |
30396849649 ps |
T1530 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/44.i2c_host_fifo_reset_rx.3677976129 |
|
|
Oct 09 08:45:18 AM UTC 24 |
Oct 09 08:45:27 AM UTC 24 |
194069861 ps |
T1531 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/43.i2c_target_stress_wr.977609426 |
|
|
Oct 09 08:44:37 AM UTC 24 |
Oct 09 08:45:28 AM UTC 24 |
70713918882 ps |
T1532 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/43.i2c_target_stretch.3873323608 |
|
|
Oct 09 08:44:42 AM UTC 24 |
Oct 09 08:45:29 AM UTC 24 |
2370119070 ps |
T1533 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/43.i2c_target_intr_stress_wr.4200582230 |
|
|
Oct 09 08:44:54 AM UTC 24 |
Oct 09 08:45:30 AM UTC 24 |
11995888768 ps |
T1534 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/44.i2c_host_perf_precise.2700672962 |
|
|
Oct 09 08:45:20 AM UTC 24 |
Oct 09 08:45:30 AM UTC 24 |
232560331 ps |
T1535 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/44.i2c_host_fifo_fmt_empty.293660533 |
|
|
Oct 09 08:45:17 AM UTC 24 |
Oct 09 08:45:32 AM UTC 24 |
1436978718 ps |
T1536 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/44.i2c_host_error_intr.2222436105 |
|
|
Oct 09 08:45:25 AM UTC 24 |
Oct 09 08:45:36 AM UTC 24 |
5472101830 ps |
T1537 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/20.i2c_target_stress_wr.2507431528 |
|
|
Oct 09 08:28:51 AM UTC 24 |
Oct 09 08:45:38 AM UTC 24 |
54466207546 ps |
T1538 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/44.i2c_target_stress_rd.4269045162 |
|
|
Oct 09 08:45:29 AM UTC 24 |
Oct 09 08:45:38 AM UTC 24 |
404521690 ps |
T1539 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/44.i2c_target_fifo_reset_acq.2273574599 |
|
|
Oct 09 08:45:38 AM UTC 24 |
Oct 09 08:45:41 AM UTC 24 |
677156246 ps |
T1540 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/44.i2c_target_fifo_reset_tx.340851275 |
|
|
Oct 09 08:45:39 AM UTC 24 |
Oct 09 08:45:42 AM UTC 24 |
1632072117 ps |
T1541 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/44.i2c_target_intr_smoke.2167291583 |
|
|
Oct 09 08:45:37 AM UTC 24 |
Oct 09 08:45:45 AM UTC 24 |
763612422 ps |
T1542 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/41.i2c_target_stress_all.379356591 |
|
|
Oct 09 08:43:24 AM UTC 24 |
Oct 09 08:45:46 AM UTC 24 |
71732491420 ps |
T1543 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/44.i2c_target_hrst.2801341649 |
|
|
Oct 09 08:45:43 AM UTC 24 |
Oct 09 08:45:46 AM UTC 24 |
143212981 ps |
T1544 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/44.i2c_target_perf.1685529758 |
|
|
Oct 09 08:45:39 AM UTC 24 |
Oct 09 08:45:47 AM UTC 24 |
591707976 ps |
T1545 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/44.i2c_host_smoke.1574996095 |
|
|
Oct 09 08:45:15 AM UTC 24 |
Oct 09 08:45:47 AM UTC 24 |
1560722633 ps |
T1546 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/44.i2c_target_fifo_watermarks_tx.2864415395 |
|
|
Oct 09 08:45:46 AM UTC 24 |
Oct 09 08:45:49 AM UTC 24 |
160188019 ps |
T1547 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/44.i2c_target_timeout.4150338427 |
|
|
Oct 09 08:45:37 AM UTC 24 |
Oct 09 08:45:49 AM UTC 24 |
1404811976 ps |
T1548 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/43.i2c_host_fifo_overflow.2179488939 |
|
|
Oct 09 08:44:27 AM UTC 24 |
Oct 09 08:45:50 AM UTC 24 |
2437930313 ps |
T1549 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/44.i2c_target_bad_addr.3346565098 |
|
|
Oct 09 08:45:42 AM UTC 24 |
Oct 09 08:45:51 AM UTC 24 |
971791976 ps |
T1550 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/44.i2c_target_smbus_maxlen.1285428078 |
|
|
Oct 09 08:45:47 AM UTC 24 |
Oct 09 08:45:51 AM UTC 24 |
354544685 ps |
T1551 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/45.i2c_host_fifo_reset_fmt.3664343607 |
|
|
Oct 09 08:45:54 AM UTC 24 |
Oct 09 08:45:56 AM UTC 24 |
531689855 ps |
T1552 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/42.i2c_target_stress_all.3409535905 |
|
|
Oct 09 08:44:11 AM UTC 24 |
Oct 09 08:45:52 AM UTC 24 |
108031042607 ps |
T1553 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/44.i2c_alert_test.3409940023 |
|
|
Oct 09 08:45:50 AM UTC 24 |
Oct 09 08:45:52 AM UTC 24 |
27668578 ps |
T1554 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/44.i2c_target_fifo_watermarks_acq.370223082 |
|
|
Oct 09 08:45:46 AM UTC 24 |
Oct 09 08:45:52 AM UTC 24 |
458152900 ps |
T1555 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/44.i2c_host_may_nack.611334874 |
|
|
Oct 09 08:45:44 AM UTC 24 |
Oct 09 08:45:53 AM UTC 24 |
947865016 ps |
T1556 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/44.i2c_target_nack_acqfull.3964386335 |
|
|
Oct 09 08:45:48 AM UTC 24 |
Oct 09 08:45:53 AM UTC 24 |
1133476969 ps |
T1557 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/45.i2c_host_perf_precise.1760301968 |
|
|
Oct 09 08:45:55 AM UTC 24 |
Oct 09 08:45:58 AM UTC 24 |
98583071 ps |
T1558 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/45.i2c_host_override.3190161104 |
|
|
Oct 09 08:45:52 AM UTC 24 |
Oct 09 08:45:54 AM UTC 24 |
83627557 ps |
T1559 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/44.i2c_target_nack_acqfull_addr.866311618 |
|
|
Oct 09 08:45:49 AM UTC 24 |
Oct 09 08:45:55 AM UTC 24 |
602299548 ps |
T1560 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/44.i2c_target_tx_stretch_ctrl.3821450438 |
|
|
Oct 09 08:45:47 AM UTC 24 |
Oct 09 08:45:59 AM UTC 24 |
416401670 ps |
T1561 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/44.i2c_host_stretch_timeout.1069750824 |
|
|
Oct 09 08:45:21 AM UTC 24 |
Oct 09 08:46:00 AM UTC 24 |
846144695 ps |
T1562 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/45.i2c_host_error_intr.2350841641 |
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|
Oct 09 08:45:57 AM UTC 24 |
Oct 09 08:46:01 AM UTC 24 |
60523243 ps |
T1563 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/43.i2c_host_fifo_full.2102903146 |
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|
Oct 09 08:44:29 AM UTC 24 |
Oct 09 08:46:03 AM UTC 24 |
10952916418 ps |
T1564 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/45.i2c_host_fifo_fmt_empty.3481537900 |
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|
Oct 09 08:45:54 AM UTC 24 |
Oct 09 08:46:03 AM UTC 24 |
1672589374 ps |
T1565 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/39.i2c_target_intr_stress_wr.2084246741 |
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|
Oct 09 08:41:55 AM UTC 24 |
Oct 09 08:46:04 AM UTC 24 |
17285109183 ps |
T274 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/30.i2c_host_stress_all.4067397852 |
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|
Oct 09 08:35:01 AM UTC 24 |
Oct 09 08:46:04 AM UTC 24 |
10102881767 ps |
T1566 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/45.i2c_host_fifo_reset_rx.3550489842 |
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|
Oct 09 08:45:54 AM UTC 24 |
Oct 09 08:46:05 AM UTC 24 |
179859381 ps |
T1567 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/44.i2c_host_perf.1938980122 |
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|
Oct 09 08:45:19 AM UTC 24 |
Oct 09 08:46:08 AM UTC 24 |
7197454442 ps |
T1568 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/45.i2c_target_fifo_reset_acq.1034098944 |
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|
Oct 09 08:46:07 AM UTC 24 |
Oct 09 08:46:11 AM UTC 24 |
282562428 ps |
T1569 |
/workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/coverage/default/45.i2c_target_stretch.4066881457 |
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Oct 09 08:46:02 AM UTC 24 |
Oct 09 08:46:11 AM UTC 24 |
1442873267 ps |