| T1564 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/45.i2c_target_fifo_watermarks_tx.240352850 |
|
|
Oct 12 06:25:24 AM UTC 24 |
Oct 12 06:25:27 AM UTC 24 |
213701876 ps |
| T1565 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/45.i2c_target_timeout.468571913 |
|
|
Oct 12 06:25:15 AM UTC 24 |
Oct 12 06:25:27 AM UTC 24 |
2270705701 ps |
| T1566 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/43.i2c_host_smoke.1850525423 |
|
|
Oct 12 06:23:43 AM UTC 24 |
Oct 12 06:25:27 AM UTC 24 |
24055054118 ps |
| T1567 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/45.i2c_target_perf.904016284 |
|
|
Oct 12 06:25:20 AM UTC 24 |
Oct 12 06:25:28 AM UTC 24 |
2344659001 ps |
| T1568 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/45.i2c_target_fifo_watermarks_acq.2134223253 |
|
|
Oct 12 06:25:24 AM UTC 24 |
Oct 12 06:25:29 AM UTC 24 |
483630455 ps |
| T1569 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/45.i2c_target_tx_stretch_ctrl.1153770030 |
|
|
Oct 12 06:25:26 AM UTC 24 |
Oct 12 06:25:30 AM UTC 24 |
90859053 ps |
| T1570 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/45.i2c_target_smoke.3417714590 |
|
|
Oct 12 06:25:09 AM UTC 24 |
Oct 12 06:25:30 AM UTC 24 |
1120699108 ps |
| T1571 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/45.i2c_target_bad_addr.4072651089 |
|
|
Oct 12 06:25:20 AM UTC 24 |
Oct 12 06:25:30 AM UTC 24 |
6456119067 ps |
| T1572 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/44.i2c_host_fifo_overflow.1927730481 |
|
|
Oct 12 06:24:21 AM UTC 24 |
Oct 12 06:25:31 AM UTC 24 |
4296779168 ps |
| T1573 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/43.i2c_host_fifo_full.445592136 |
|
|
Oct 12 06:23:47 AM UTC 24 |
Oct 12 06:25:31 AM UTC 24 |
3828172473 ps |
| T1574 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/45.i2c_target_smbus_maxlen.2744996325 |
|
|
Oct 12 06:25:28 AM UTC 24 |
Oct 12 06:25:31 AM UTC 24 |
1715675423 ps |
| T1575 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/45.i2c_alert_test.469300640 |
|
|
Oct 12 06:25:29 AM UTC 24 |
Oct 12 06:25:31 AM UTC 24 |
18259481 ps |
| T1576 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/45.i2c_target_nack_txstretch.3270135237 |
|
|
Oct 12 06:25:28 AM UTC 24 |
Oct 12 06:25:32 AM UTC 24 |
349203064 ps |
| T1577 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/46.i2c_host_override.1785416616 |
|
|
Oct 12 06:25:31 AM UTC 24 |
Oct 12 06:25:33 AM UTC 24 |
15247876 ps |
| T1578 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/45.i2c_host_stretch_timeout.3077557081 |
|
|
Oct 12 06:25:02 AM UTC 24 |
Oct 12 06:25:33 AM UTC 24 |
1180149759 ps |
| T1579 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/45.i2c_target_nack_acqfull.1041783272 |
|
|
Oct 12 06:25:28 AM UTC 24 |
Oct 12 06:25:33 AM UTC 24 |
845211946 ps |
| T1580 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/45.i2c_target_nack_acqfull_addr.2009829490 |
|
|
Oct 12 06:25:28 AM UTC 24 |
Oct 12 06:25:34 AM UTC 24 |
545358499 ps |
| T1581 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_reset_fmt.25243359 |
|
|
Oct 12 06:25:32 AM UTC 24 |
Oct 12 06:25:34 AM UTC 24 |
152642038 ps |
| T123 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/43.i2c_host_fifo_watermark.3910269117 |
|
|
Oct 12 06:23:44 AM UTC 24 |
Oct 12 06:25:36 AM UTC 24 |
9962274735 ps |
| T1582 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/45.i2c_host_may_nack.2038236255 |
|
|
Oct 12 06:25:23 AM UTC 24 |
Oct 12 06:25:38 AM UTC 24 |
788430306 ps |
| T1583 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/46.i2c_host_error_intr.448095860 |
|
|
Oct 12 06:25:34 AM UTC 24 |
Oct 12 06:25:38 AM UTC 24 |
222726893 ps |
| T277 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/40.i2c_host_stress_all.2305220082 |
|
|
Oct 12 06:22:03 AM UTC 24 |
Oct 12 06:25:42 AM UTC 24 |
5570068438 ps |
| T1584 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/44.i2c_host_fifo_full.2473454438 |
|
|
Oct 12 06:24:24 AM UTC 24 |
Oct 12 06:25:43 AM UTC 24 |
2951955978 ps |
| T1585 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_fmt_empty.312589736 |
|
|
Oct 12 06:25:33 AM UTC 24 |
Oct 12 06:25:44 AM UTC 24 |
1465842790 ps |
| T1586 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_reset_rx.34404728 |
|
|
Oct 12 06:25:33 AM UTC 24 |
Oct 12 06:25:46 AM UTC 24 |
172077057 ps |
| T1587 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/45.i2c_target_stress_rd.3049743871 |
|
|
Oct 12 06:25:10 AM UTC 24 |
Oct 12 06:25:46 AM UTC 24 |
14137438007 ps |
| T1588 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/46.i2c_target_smoke.2967596484 |
|
|
Oct 12 06:25:36 AM UTC 24 |
Oct 12 06:25:47 AM UTC 24 |
6858739339 ps |
| T1589 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/46.i2c_host_stretch_timeout.3762690116 |
|
|
Oct 12 06:25:34 AM UTC 24 |
Oct 12 06:25:47 AM UTC 24 |
1213107530 ps |
| T1590 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/48.i2c_host_override.2521511739 |
|
|
Oct 12 06:26:38 AM UTC 24 |
Oct 12 06:26:40 AM UTC 24 |
25258638 ps |
| T1591 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/46.i2c_target_stress_rd.1346997528 |
|
|
Oct 12 06:25:39 AM UTC 24 |
Oct 12 06:25:48 AM UTC 24 |
737953396 ps |
| T1592 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/46.i2c_target_fifo_reset_acq.1842202271 |
|
|
Oct 12 06:25:47 AM UTC 24 |
Oct 12 06:25:50 AM UTC 24 |
243599684 ps |
| T1593 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/46.i2c_target_fifo_reset_tx.3635727177 |
|
|
Oct 12 06:25:47 AM UTC 24 |
Oct 12 06:25:50 AM UTC 24 |
578652733 ps |
| T1594 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/46.i2c_host_smoke.1965511676 |
|
|
Oct 12 06:25:29 AM UTC 24 |
Oct 12 06:25:53 AM UTC 24 |
5714979448 ps |
| T1595 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/46.i2c_target_intr_smoke.2653785077 |
|
|
Oct 12 06:25:42 AM UTC 24 |
Oct 12 06:25:54 AM UTC 24 |
4396589862 ps |
| T1596 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/46.i2c_target_timeout.1949857316 |
|
|
Oct 12 06:25:45 AM UTC 24 |
Oct 12 06:25:54 AM UTC 24 |
2855352136 ps |
| T1597 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/46.i2c_target_hrst.2553428657 |
|
|
Oct 12 06:25:50 AM UTC 24 |
Oct 12 06:25:54 AM UTC 24 |
381429108 ps |
| T1598 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/46.i2c_target_perf.108785389 |
|
|
Oct 12 06:25:49 AM UTC 24 |
Oct 12 06:25:55 AM UTC 24 |
1157743435 ps |
| T1599 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/46.i2c_target_bad_addr.2789298923 |
|
|
Oct 12 06:25:49 AM UTC 24 |
Oct 12 06:25:55 AM UTC 24 |
2306442236 ps |
| T1600 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/42.i2c_host_fifo_overflow.2045148223 |
|
|
Oct 12 06:23:09 AM UTC 24 |
Oct 12 06:25:55 AM UTC 24 |
16405855816 ps |
| T1601 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/41.i2c_host_fifo_watermark.1722055633 |
|
|
Oct 12 06:22:37 AM UTC 24 |
Oct 12 06:25:56 AM UTC 24 |
71720747037 ps |
| T1602 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/46.i2c_target_fifo_watermarks_tx.2847992633 |
|
|
Oct 12 06:25:54 AM UTC 24 |
Oct 12 06:25:57 AM UTC 24 |
115643256 ps |
| T1603 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/46.i2c_target_fifo_watermarks_acq.976628996 |
|
|
Oct 12 06:25:54 AM UTC 24 |
Oct 12 06:25:58 AM UTC 24 |
793187060 ps |
| T1604 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/46.i2c_alert_test.316744306 |
|
|
Oct 12 06:25:57 AM UTC 24 |
Oct 12 06:25:59 AM UTC 24 |
41049962 ps |
| T1605 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/46.i2c_target_nack_acqfull.1783001435 |
|
|
Oct 12 06:25:55 AM UTC 24 |
Oct 12 06:26:00 AM UTC 24 |
558794587 ps |
| T1606 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/46.i2c_host_may_nack.2757458305 |
|
|
Oct 12 06:25:51 AM UTC 24 |
Oct 12 06:26:00 AM UTC 24 |
469983263 ps |
| T1607 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/46.i2c_target_smbus_maxlen.1558446101 |
|
|
Oct 12 06:25:55 AM UTC 24 |
Oct 12 06:26:00 AM UTC 24 |
1882299948 ps |
| T1608 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/47.i2c_host_override.2858333064 |
|
|
Oct 12 06:25:58 AM UTC 24 |
Oct 12 06:26:00 AM UTC 24 |
18396230 ps |
| T1609 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/46.i2c_target_tx_stretch_ctrl.1234800721 |
|
|
Oct 12 06:25:55 AM UTC 24 |
Oct 12 06:26:00 AM UTC 24 |
135176233 ps |
| T1610 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/49.i2c_target_intr_stress_wr.3119836546 |
|
|
Oct 12 06:27:12 AM UTC 24 |
Oct 12 06:28:07 AM UTC 24 |
29137546471 ps |
| T1611 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/42.i2c_target_stress_wr.2976471710 |
|
|
Oct 12 06:23:18 AM UTC 24 |
Oct 12 06:26:01 AM UTC 24 |
28986988783 ps |
| T1612 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/46.i2c_target_nack_acqfull_addr.339509493 |
|
|
Oct 12 06:25:57 AM UTC 24 |
Oct 12 06:26:02 AM UTC 24 |
2025340653 ps |
| T1613 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_reset_fmt.866406317 |
|
|
Oct 12 06:26:00 AM UTC 24 |
Oct 12 06:26:03 AM UTC 24 |
189127758 ps |
| T1614 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/47.i2c_host_error_intr.3304164218 |
|
|
Oct 12 06:26:03 AM UTC 24 |
Oct 12 06:26:06 AM UTC 24 |
355649891 ps |
| T1615 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/41.i2c_host_perf.523618748 |
|
|
Oct 12 06:22:38 AM UTC 24 |
Oct 12 06:26:08 AM UTC 24 |
52530735327 ps |
| T1616 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_reset_rx.2681846736 |
|
|
Oct 12 06:26:02 AM UTC 24 |
Oct 12 06:26:08 AM UTC 24 |
138967827 ps |
| T1617 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/46.i2c_target_stretch.1085242439 |
|
|
Oct 12 06:25:39 AM UTC 24 |
Oct 12 06:26:10 AM UTC 24 |
2708539927 ps |
| T1618 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_fmt_empty.2313546864 |
|
|
Oct 12 06:26:01 AM UTC 24 |
Oct 12 06:26:11 AM UTC 24 |
621209456 ps |
| T1619 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/41.i2c_target_stress_wr.4170757248 |
|
|
Oct 12 06:22:45 AM UTC 24 |
Oct 12 06:26:11 AM UTC 24 |
44788307895 ps |
| T1620 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/45.i2c_host_fifo_full.3232461228 |
|
|
Oct 12 06:25:00 AM UTC 24 |
Oct 12 06:26:17 AM UTC 24 |
3583422146 ps |
| T1621 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/47.i2c_host_stretch_timeout.668341371 |
|
|
Oct 12 06:26:02 AM UTC 24 |
Oct 12 06:26:18 AM UTC 24 |
787238989 ps |
| T1622 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/47.i2c_target_intr_smoke.406545440 |
|
|
Oct 12 06:26:12 AM UTC 24 |
Oct 12 06:26:19 AM UTC 24 |
5193395797 ps |
| T1623 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/47.i2c_host_smoke.1839376330 |
|
|
Oct 12 06:25:57 AM UTC 24 |
Oct 12 06:26:21 AM UTC 24 |
1146185314 ps |
| T1624 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/47.i2c_target_fifo_reset_acq.2326242925 |
|
|
Oct 12 06:26:20 AM UTC 24 |
Oct 12 06:26:23 AM UTC 24 |
1117373739 ps |
| T1625 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/47.i2c_target_fifo_reset_tx.2277082331 |
|
|
Oct 12 06:26:22 AM UTC 24 |
Oct 12 06:26:25 AM UTC 24 |
200274331 ps |
| T1626 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/47.i2c_target_perf.1496740612 |
|
|
Oct 12 06:26:23 AM UTC 24 |
Oct 12 06:26:28 AM UTC 24 |
8038925880 ps |
| T1627 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/47.i2c_target_timeout.1861328094 |
|
|
Oct 12 06:26:18 AM UTC 24 |
Oct 12 06:26:30 AM UTC 24 |
1408198108 ps |
| T1628 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/46.i2c_target_stress_wr.1909564181 |
|
|
Oct 12 06:25:37 AM UTC 24 |
Oct 12 06:26:31 AM UTC 24 |
35973794863 ps |
| T1629 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/47.i2c_target_smoke.1787332943 |
|
|
Oct 12 06:26:07 AM UTC 24 |
Oct 12 06:26:31 AM UTC 24 |
596723553 ps |
| T1630 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/47.i2c_target_intr_stress_wr.3583858199 |
|
|
Oct 12 06:26:13 AM UTC 24 |
Oct 12 06:26:31 AM UTC 24 |
9644384067 ps |
| T1631 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/45.i2c_host_smoke.435755767 |
|
|
Oct 12 06:24:56 AM UTC 24 |
Oct 12 06:26:32 AM UTC 24 |
1877971090 ps |
| T1632 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/47.i2c_target_fifo_watermarks_acq.741644200 |
|
|
Oct 12 06:26:32 AM UTC 24 |
Oct 12 06:26:35 AM UTC 24 |
193865771 ps |
| T1633 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/47.i2c_target_bad_addr.3365821821 |
|
|
Oct 12 06:26:26 AM UTC 24 |
Oct 12 06:26:35 AM UTC 24 |
4831486568 ps |
| T1634 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/47.i2c_target_fifo_watermarks_tx.1084720376 |
|
|
Oct 12 06:26:33 AM UTC 24 |
Oct 12 06:26:35 AM UTC 24 |
374554525 ps |
| T1635 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/47.i2c_target_tx_stretch_ctrl.2132974466 |
|
|
Oct 12 06:26:33 AM UTC 24 |
Oct 12 06:26:36 AM UTC 24 |
67634217 ps |
| T1636 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/47.i2c_target_stress_rd.399406397 |
|
|
Oct 12 06:26:09 AM UTC 24 |
Oct 12 06:26:37 AM UTC 24 |
423291490 ps |
| T1637 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/45.i2c_target_stress_wr.2387682298 |
|
|
Oct 12 06:25:10 AM UTC 24 |
Oct 12 06:26:37 AM UTC 24 |
30034122908 ps |
| T1638 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/47.i2c_target_smbus_maxlen.210637453 |
|
|
Oct 12 06:26:34 AM UTC 24 |
Oct 12 06:26:38 AM UTC 24 |
539629121 ps |
| T1639 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/46.i2c_target_intr_stress_wr.840199942 |
|
|
Oct 12 06:25:44 AM UTC 24 |
Oct 12 06:26:39 AM UTC 24 |
19102670562 ps |
| T1640 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/47.i2c_alert_test.794815223 |
|
|
Oct 12 06:26:37 AM UTC 24 |
Oct 12 06:26:39 AM UTC 24 |
49439099 ps |
| T1641 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/43.i2c_target_intr_stress_wr.1554314977 |
|
|
Oct 12 06:23:57 AM UTC 24 |
Oct 12 06:26:40 AM UTC 24 |
13288724664 ps |
| T1642 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/47.i2c_target_nack_acqfull.1833455713 |
|
|
Oct 12 06:26:36 AM UTC 24 |
Oct 12 06:26:41 AM UTC 24 |
515781451 ps |
| T1643 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/47.i2c_target_nack_acqfull_addr.2451886240 |
|
|
Oct 12 06:26:36 AM UTC 24 |
Oct 12 06:26:41 AM UTC 24 |
516405266 ps |
| T1644 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/47.i2c_target_stretch.1593920104 |
|
|
Oct 12 06:26:11 AM UTC 24 |
Oct 12 06:26:42 AM UTC 24 |
1892733638 ps |
| T1645 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/47.i2c_host_may_nack.4283163043 |
|
|
Oct 12 06:26:32 AM UTC 24 |
Oct 12 06:26:42 AM UTC 24 |
2458273328 ps |
| T1646 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/46.i2c_host_perf_precise.1449058938 |
|
|
Oct 12 06:25:33 AM UTC 24 |
Oct 12 06:26:43 AM UTC 24 |
5865289042 ps |
| T1647 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_overflow.2825785044 |
|
|
Oct 12 06:25:32 AM UTC 24 |
Oct 12 06:26:43 AM UTC 24 |
31456358505 ps |
| T1648 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_reset_fmt.3790618561 |
|
|
Oct 12 06:26:41 AM UTC 24 |
Oct 12 06:26:44 AM UTC 24 |
346113873 ps |
| T1649 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/34.i2c_target_stress_wr.2831838410 |
|
|
Oct 12 06:18:40 AM UTC 24 |
Oct 12 06:28:15 AM UTC 24 |
44638922510 ps |
| T1650 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/45.i2c_host_fifo_overflow.2091191996 |
|
|
Oct 12 06:24:58 AM UTC 24 |
Oct 12 06:26:44 AM UTC 24 |
3129975646 ps |
| T1651 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/47.i2c_host_perf_precise.1753408059 |
|
|
Oct 12 06:26:02 AM UTC 24 |
Oct 12 06:26:46 AM UTC 24 |
2593229890 ps |
| T1652 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_reset_rx.71895554 |
|
|
Oct 12 06:26:41 AM UTC 24 |
Oct 12 06:26:47 AM UTC 24 |
606635995 ps |
| T245 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/39.i2c_host_stress_all.4119429663 |
|
|
Oct 12 06:21:15 AM UTC 24 |
Oct 12 06:26:49 AM UTC 24 |
209910216596 ps |
| T1653 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/46.i2c_target_stress_all.895179947 |
|
|
Oct 12 06:25:49 AM UTC 24 |
Oct 12 06:26:49 AM UTC 24 |
65440950470 ps |
| T1654 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/48.i2c_host_error_intr.2301360288 |
|
|
Oct 12 06:26:44 AM UTC 24 |
Oct 12 06:26:50 AM UTC 24 |
135426351 ps |
| T1655 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/48.i2c_target_stretch.542137170 |
|
|
Oct 12 06:26:47 AM UTC 24 |
Oct 12 06:26:50 AM UTC 24 |
188549044 ps |
| T1656 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/48.i2c_target_stress_rd.3739584756 |
|
|
Oct 12 06:26:45 AM UTC 24 |
Oct 12 06:26:52 AM UTC 24 |
297941249 ps |
| T1657 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/48.i2c_target_fifo_reset_acq.2859975675 |
|
|
Oct 12 06:26:52 AM UTC 24 |
Oct 12 06:26:55 AM UTC 24 |
618581661 ps |
| T1658 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/48.i2c_target_fifo_reset_tx.2255232407 |
|
|
Oct 12 06:26:53 AM UTC 24 |
Oct 12 06:26:55 AM UTC 24 |
506314902 ps |
| T1659 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_fmt_empty.884337685 |
|
|
Oct 12 06:26:41 AM UTC 24 |
Oct 12 06:26:55 AM UTC 24 |
1066775539 ps |
| T1660 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/48.i2c_target_intr_stress_wr.362884428 |
|
|
Oct 12 06:26:49 AM UTC 24 |
Oct 12 06:26:57 AM UTC 24 |
3946550172 ps |
| T1661 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_overflow.1885042608 |
|
|
Oct 12 06:25:59 AM UTC 24 |
Oct 12 06:26:58 AM UTC 24 |
8832342015 ps |
| T1662 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/48.i2c_target_intr_smoke.2239147085 |
|
|
Oct 12 06:26:48 AM UTC 24 |
Oct 12 06:26:58 AM UTC 24 |
2448147120 ps |
| T1663 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/48.i2c_host_smoke.1839626870 |
|
|
Oct 12 06:26:37 AM UTC 24 |
Oct 12 06:26:59 AM UTC 24 |
1467552853 ps |
| T1664 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/48.i2c_host_stretch_timeout.2932255525 |
|
|
Oct 12 06:26:42 AM UTC 24 |
Oct 12 06:26:59 AM UTC 24 |
3885554204 ps |
| T1665 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/44.i2c_target_stress_all.1319494781 |
|
|
Oct 12 06:24:45 AM UTC 24 |
Oct 12 06:27:00 AM UTC 24 |
46335790368 ps |
| T1666 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/48.i2c_host_mode_toggle.3819830054 |
|
|
Oct 12 06:26:57 AM UTC 24 |
Oct 12 06:27:00 AM UTC 24 |
423458794 ps |
| T1667 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/48.i2c_target_bad_addr.2876209940 |
|
|
Oct 12 06:26:56 AM UTC 24 |
Oct 12 06:27:01 AM UTC 24 |
615736097 ps |
| T1668 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/48.i2c_target_hrst.2824000526 |
|
|
Oct 12 06:26:56 AM UTC 24 |
Oct 12 06:27:02 AM UTC 24 |
752295952 ps |
| T1669 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/48.i2c_target_timeout.1207028184 |
|
|
Oct 12 06:26:50 AM UTC 24 |
Oct 12 06:27:03 AM UTC 24 |
1203833679 ps |
| T1670 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/48.i2c_target_fifo_watermarks_tx.3219843511 |
|
|
Oct 12 06:27:00 AM UTC 24 |
Oct 12 06:27:03 AM UTC 24 |
196719994 ps |
| T1671 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/48.i2c_target_perf.178659780 |
|
|
Oct 12 06:26:55 AM UTC 24 |
Oct 12 06:27:03 AM UTC 24 |
1850909302 ps |
| T1672 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/45.i2c_host_fifo_watermark.1660786727 |
|
|
Oct 12 06:24:58 AM UTC 24 |
Oct 12 06:27:04 AM UTC 24 |
2510718453 ps |
| T1673 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/48.i2c_alert_test.470661471 |
|
|
Oct 12 06:27:03 AM UTC 24 |
Oct 12 06:27:04 AM UTC 24 |
16392145 ps |
| T1674 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/48.i2c_target_fifo_watermarks_acq.358078685 |
|
|
Oct 12 06:26:59 AM UTC 24 |
Oct 12 06:27:05 AM UTC 24 |
1557573749 ps |
| T1675 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/48.i2c_target_smbus_maxlen.3706164325 |
|
|
Oct 12 06:27:00 AM UTC 24 |
Oct 12 06:27:05 AM UTC 24 |
4642481407 ps |
| T1676 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/48.i2c_target_nack_txstretch.2609118858 |
|
|
Oct 12 06:27:01 AM UTC 24 |
Oct 12 06:27:05 AM UTC 24 |
519268874 ps |
| T1677 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/48.i2c_target_tx_stretch_ctrl.526995263 |
|
|
Oct 12 06:27:00 AM UTC 24 |
Oct 12 06:27:05 AM UTC 24 |
156042446 ps |
| T1678 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/49.i2c_host_override.2106638877 |
|
|
Oct 12 06:27:04 AM UTC 24 |
Oct 12 06:27:06 AM UTC 24 |
49570640 ps |
| T1679 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/48.i2c_host_may_nack.3028061958 |
|
|
Oct 12 06:26:58 AM UTC 24 |
Oct 12 06:27:06 AM UTC 24 |
5461838398 ps |
| T1680 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/48.i2c_target_nack_acqfull.4188434439 |
|
|
Oct 12 06:27:00 AM UTC 24 |
Oct 12 06:27:06 AM UTC 24 |
2197319927 ps |
| T1681 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/48.i2c_target_smoke.356949649 |
|
|
Oct 12 06:26:44 AM UTC 24 |
Oct 12 06:27:06 AM UTC 24 |
1858260195 ps |
| T1682 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/48.i2c_target_nack_acqfull_addr.4212041950 |
|
|
Oct 12 06:27:01 AM UTC 24 |
Oct 12 06:27:07 AM UTC 24 |
4750209719 ps |
| T1683 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_reset_fmt.142348539 |
|
|
Oct 12 06:27:05 AM UTC 24 |
Oct 12 06:27:08 AM UTC 24 |
704261617 ps |
| T1684 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/40.i2c_host_perf.3983163035 |
|
|
Oct 12 06:22:02 AM UTC 24 |
Oct 12 06:27:08 AM UTC 24 |
7200933029 ps |
| T1685 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/49.i2c_host_error_intr.165100782 |
|
|
Oct 12 06:27:07 AM UTC 24 |
Oct 12 06:27:11 AM UTC 24 |
183846896 ps |
| T1686 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/48.i2c_host_perf_precise.331358838 |
|
|
Oct 12 06:26:42 AM UTC 24 |
Oct 12 06:27:16 AM UTC 24 |
6138872012 ps |
| T1687 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/49.i2c_target_intr_smoke.352545172 |
|
|
Oct 12 06:27:09 AM UTC 24 |
Oct 12 06:27:17 AM UTC 24 |
2567138915 ps |
| T1688 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_fmt_empty.855431615 |
|
|
Oct 12 06:27:05 AM UTC 24 |
Oct 12 06:27:20 AM UTC 24 |
547983569 ps |
| T1689 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_full.4011745331 |
|
|
Oct 12 06:26:02 AM UTC 24 |
Oct 12 06:27:21 AM UTC 24 |
12366388344 ps |
| T1690 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_overflow.766671975 |
|
|
Oct 12 06:26:41 AM UTC 24 |
Oct 12 06:27:24 AM UTC 24 |
2754671767 ps |
| T1691 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_reset_rx.1177042092 |
|
|
Oct 12 06:27:06 AM UTC 24 |
Oct 12 06:27:25 AM UTC 24 |
1496808962 ps |
| T1692 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/49.i2c_target_fifo_reset_acq.299706726 |
|
|
Oct 12 06:27:22 AM UTC 24 |
Oct 12 06:27:25 AM UTC 24 |
594577709 ps |
| T1693 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/49.i2c_target_fifo_reset_tx.1223055326 |
|
|
Oct 12 06:27:22 AM UTC 24 |
Oct 12 06:27:26 AM UTC 24 |
963869697 ps |
| T1694 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/49.i2c_target_stress_wr.3052024480 |
|
|
Oct 12 06:27:08 AM UTC 24 |
Oct 12 06:27:26 AM UTC 24 |
10773907833 ps |
| T1695 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/49.i2c_target_stretch.543991735 |
|
|
Oct 12 06:27:09 AM UTC 24 |
Oct 12 06:27:27 AM UTC 24 |
1528840682 ps |
| T1696 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/48.i2c_target_stress_wr.1443567727 |
|
|
Oct 12 06:26:45 AM UTC 24 |
Oct 12 06:27:28 AM UTC 24 |
35898078088 ps |
| T1697 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/49.i2c_target_timeout.644744919 |
|
|
Oct 12 06:27:16 AM UTC 24 |
Oct 12 06:27:28 AM UTC 24 |
6947895268 ps |
| T1698 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/49.i2c_target_hrst.654154745 |
|
|
Oct 12 06:27:26 AM UTC 24 |
Oct 12 06:27:30 AM UTC 24 |
1475823123 ps |
| T1699 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/49.i2c_target_fifo_watermarks_tx.696739689 |
|
|
Oct 12 06:27:29 AM UTC 24 |
Oct 12 06:27:31 AM UTC 24 |
268410782 ps |
| T1700 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/49.i2c_target_perf.3995010882 |
|
|
Oct 12 06:27:23 AM UTC 24 |
Oct 12 06:27:32 AM UTC 24 |
1522603535 ps |
| T1701 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/49.i2c_target_stress_rd.3075027135 |
|
|
Oct 12 06:27:08 AM UTC 24 |
Oct 12 06:27:33 AM UTC 24 |
5949447348 ps |
| T1702 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/49.i2c_target_fifo_watermarks_acq.2886942782 |
|
|
Oct 12 06:27:27 AM UTC 24 |
Oct 12 06:27:33 AM UTC 24 |
1337224672 ps |
| T1703 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/49.i2c_target_tx_stretch_ctrl.1229161416 |
|
|
Oct 12 06:27:29 AM UTC 24 |
Oct 12 06:27:33 AM UTC 24 |
87757637 ps |
| T1704 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/49.i2c_target_bad_addr.1193689946 |
|
|
Oct 12 06:27:25 AM UTC 24 |
Oct 12 06:27:34 AM UTC 24 |
5089580117 ps |
| T1705 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/49.i2c_alert_test.919353980 |
|
|
Oct 12 06:27:33 AM UTC 24 |
Oct 12 06:27:35 AM UTC 24 |
38489509 ps |
| T1706 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/49.i2c_target_smbus_maxlen.2439668703 |
|
|
Oct 12 06:27:31 AM UTC 24 |
Oct 12 06:27:36 AM UTC 24 |
471746080 ps |
| T1707 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/49.i2c_target_nack_txstretch.1575923574 |
|
|
Oct 12 06:27:33 AM UTC 24 |
Oct 12 06:27:36 AM UTC 24 |
507503549 ps |
| T1708 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/49.i2c_target_nack_acqfull.1705078067 |
|
|
Oct 12 06:27:31 AM UTC 24 |
Oct 12 06:27:37 AM UTC 24 |
2017627346 ps |
| T1709 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/49.i2c_target_nack_acqfull_addr.3100915024 |
|
|
Oct 12 06:27:32 AM UTC 24 |
Oct 12 06:27:39 AM UTC 24 |
634571396 ps |
| T1710 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_watermark.2952443814 |
|
|
Oct 12 06:25:59 AM UTC 24 |
Oct 12 06:27:40 AM UTC 24 |
14932191031 ps |
| T1711 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/49.i2c_host_may_nack.424602601 |
|
|
Oct 12 06:27:27 AM UTC 24 |
Oct 12 06:27:41 AM UTC 24 |
329212213 ps |
| T1712 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/42.i2c_host_perf.2556383877 |
|
|
Oct 12 06:23:10 AM UTC 24 |
Oct 12 06:27:42 AM UTC 24 |
25632586566 ps |
| T1713 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_watermark.4194655054 |
|
|
Oct 12 06:25:32 AM UTC 24 |
Oct 12 06:27:42 AM UTC 24 |
21943534518 ps |
| T1714 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/48.i2c_target_stress_all.1629485649 |
|
|
Oct 12 06:26:55 AM UTC 24 |
Oct 12 06:27:44 AM UTC 24 |
29920893359 ps |
| T1715 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/49.i2c_target_smoke.1988726159 |
|
|
Oct 12 06:27:07 AM UTC 24 |
Oct 12 06:27:53 AM UTC 24 |
1128320246 ps |
| T1716 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/49.i2c_host_stretch_timeout.3831050654 |
|
|
Oct 12 06:27:07 AM UTC 24 |
Oct 12 06:27:57 AM UTC 24 |
2043276032 ps |
| T1717 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_watermark.2393637190 |
|
|
Oct 12 06:27:04 AM UTC 24 |
Oct 12 06:28:17 AM UTC 24 |
13532554470 ps |
| T1718 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/49.i2c_host_perf_precise.2148124162 |
|
|
Oct 12 06:27:07 AM UTC 24 |
Oct 12 06:28:19 AM UTC 24 |
6177353340 ps |
| T1719 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/49.i2c_host_smoke.1641608059 |
|
|
Oct 12 06:27:03 AM UTC 24 |
Oct 12 06:28:27 AM UTC 24 |
1774475759 ps |
| T1720 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/44.i2c_host_fifo_watermark.2694535433 |
|
|
Oct 12 06:24:20 AM UTC 24 |
Oct 12 06:28:34 AM UTC 24 |
24296619963 ps |
| T1721 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_watermark.3342493687 |
|
|
Oct 12 06:26:39 AM UTC 24 |
Oct 12 06:28:50 AM UTC 24 |
41467313137 ps |
| T1722 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_full.2838767177 |
|
|
Oct 12 06:26:41 AM UTC 24 |
Oct 12 06:28:56 AM UTC 24 |
3221194632 ps |
| T1723 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/47.i2c_target_stress_wr.4187040397 |
|
|
Oct 12 06:26:09 AM UTC 24 |
Oct 12 06:29:03 AM UTC 24 |
40349881728 ps |
| T1724 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_full.2840404644 |
|
|
Oct 12 06:25:33 AM UTC 24 |
Oct 12 06:29:09 AM UTC 24 |
21118474366 ps |
| T1725 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_full.2633690101 |
|
|
Oct 12 06:27:06 AM UTC 24 |
Oct 12 06:29:12 AM UTC 24 |
2100364637 ps |
| T1726 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/39.i2c_target_stress_all.1831831195 |
|
|
Oct 12 06:21:42 AM UTC 24 |
Oct 12 06:29:14 AM UTC 24 |
26469506034 ps |
| T1727 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/49.i2c_target_stress_all.2484388060 |
|
|
Oct 12 06:27:25 AM UTC 24 |
Oct 12 06:29:18 AM UTC 24 |
26401803216 ps |
| T1728 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/43.i2c_target_stress_all.1370823285 |
|
|
Oct 12 06:24:05 AM UTC 24 |
Oct 12 06:29:33 AM UTC 24 |
23636843043 ps |
| T1729 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_overflow.2522174735 |
|
|
Oct 12 06:27:04 AM UTC 24 |
Oct 12 06:29:44 AM UTC 24 |
2365428341 ps |
| T1730 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/47.i2c_host_perf.3037000417 |
|
|
Oct 12 06:26:02 AM UTC 24 |
Oct 12 06:30:07 AM UTC 24 |
24941999710 ps |
| T1731 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/45.i2c_host_perf.2334247910 |
|
|
Oct 12 06:25:00 AM UTC 24 |
Oct 12 06:30:24 AM UTC 24 |
7418913425 ps |
| T1732 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/47.i2c_target_stress_all.412703499 |
|
|
Oct 12 06:26:24 AM UTC 24 |
Oct 12 06:30:26 AM UTC 24 |
74667049536 ps |
| T1733 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/44.i2c_host_perf.1787992750 |
|
|
Oct 12 06:24:24 AM UTC 24 |
Oct 12 06:30:29 AM UTC 24 |
6970232188 ps |
| T246 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/44.i2c_host_stress_all.4123727147 |
|
|
Oct 12 06:24:28 AM UTC 24 |
Oct 12 06:31:30 AM UTC 24 |
6649402243 ps |
| T1734 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/48.i2c_host_perf.4273792561 |
|
|
Oct 12 06:26:42 AM UTC 24 |
Oct 12 06:32:50 AM UTC 24 |
6594899987 ps |
| T1735 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/46.i2c_host_perf.670590507 |
|
|
Oct 12 06:25:33 AM UTC 24 |
Oct 12 06:32:52 AM UTC 24 |
12795451009 ps |
| T280 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/24.i2c_host_stress_all.103981814 |
|
|
Oct 12 06:11:48 AM UTC 24 |
Oct 12 06:34:35 AM UTC 24 |
60008531067 ps |
| T1736 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/45.i2c_target_stress_all.994553159 |
|
|
Oct 12 06:25:20 AM UTC 24 |
Oct 12 06:36:33 AM UTC 24 |
53049427348 ps |
| T283 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/38.i2c_host_stress_all.3543107282 |
|
|
Oct 12 06:20:42 AM UTC 24 |
Oct 12 06:37:20 AM UTC 24 |
103718848732 ps |
| T1737 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/44.i2c_target_stress_wr.6029436 |
|
|
Oct 12 06:24:31 AM UTC 24 |
Oct 12 06:37:46 AM UTC 24 |
52361310755 ps |
| T278 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/41.i2c_host_stress_all.2079189863 |
|
|
Oct 12 06:22:40 AM UTC 24 |
Oct 12 06:38:05 AM UTC 24 |
40262089562 ps |
| T1738 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/37.i2c_host_perf.1088898803 |
|
|
Oct 12 06:20:15 AM UTC 24 |
Oct 12 06:41:53 AM UTC 24 |
50150982110 ps |
| T1739 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/25.i2c_target_stress_all.3525682267 |
|
|
Oct 12 06:12:56 AM UTC 24 |
Oct 12 06:43:31 AM UTC 24 |
66534504399 ps |
| T1740 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/36.i2c_target_stress_all.3326042263 |
|
|
Oct 12 06:20:06 AM UTC 24 |
Oct 12 06:43:48 AM UTC 24 |
75995865508 ps |
| T279 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/47.i2c_host_stress_all.3808134224 |
|
|
Oct 12 06:26:04 AM UTC 24 |
Oct 12 06:51:25 AM UTC 24 |
101756640789 ps |
| T1741 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/49.i2c_host_perf.3393417214 |
|
|
Oct 12 06:27:07 AM UTC 24 |
Oct 12 06:54:50 AM UTC 24 |
50153134839 ps |
| T1742 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_intr_test.2996435197 |
|
|
Oct 12 02:21:59 AM UTC 24 |
Oct 12 02:22:01 AM UTC 24 |
47921171 ps |
| T105 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_rw.3169277881 |
|
|
Oct 12 02:21:59 AM UTC 24 |
Oct 12 02:22:01 AM UTC 24 |
51028884 ps |
| T208 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_hw_reset.4254589828 |
|
|
Oct 12 02:21:59 AM UTC 24 |
Oct 12 02:22:01 AM UTC 24 |
58712102 ps |
| T187 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_tl_intg_err.34775466 |
|
|
Oct 12 02:21:59 AM UTC 24 |
Oct 12 02:22:02 AM UTC 24 |
95301339 ps |
| T106 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_same_csr_outstanding.2650066547 |
|
|
Oct 12 02:22:00 AM UTC 24 |
Oct 12 02:22:02 AM UTC 24 |
39799142 ps |
| T188 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_tl_errors.3036736238 |
|
|
Oct 12 02:21:59 AM UTC 24 |
Oct 12 02:22:02 AM UTC 24 |
43607107 ps |
| T107 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_aliasing.525421256 |
|
|
Oct 12 02:21:59 AM UTC 24 |
Oct 12 02:22:03 AM UTC 24 |
396625591 ps |
| T189 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.77869256 |
|
|
Oct 12 02:22:00 AM UTC 24 |
Oct 12 02:22:03 AM UTC 24 |
88148288 ps |
| T194 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_tl_intg_err.1337603506 |
|
|
Oct 12 02:22:00 AM UTC 24 |
Oct 12 02:22:03 AM UTC 24 |
159174346 ps |
| T1743 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_intr_test.2806018538 |
|
|
Oct 12 02:22:01 AM UTC 24 |
Oct 12 02:22:03 AM UTC 24 |
29020252 ps |
| T227 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_rw.2865560506 |
|
|
Oct 12 02:22:01 AM UTC 24 |
Oct 12 02:22:03 AM UTC 24 |
77057041 ps |
| T1744 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_hw_reset.4140285501 |
|
|
Oct 12 02:22:01 AM UTC 24 |
Oct 12 02:22:03 AM UTC 24 |
18880045 ps |
| T108 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_same_csr_outstanding.2717310565 |
|
|
Oct 12 02:22:02 AM UTC 24 |
Oct 12 02:22:04 AM UTC 24 |
259126429 ps |
| T109 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_aliasing.3337612501 |
|
|
Oct 12 02:22:02 AM UTC 24 |
Oct 12 02:22:04 AM UTC 24 |
130512873 ps |
| T193 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_tl_errors.2875549594 |
|
|
Oct 12 02:22:00 AM UTC 24 |
Oct 12 02:22:04 AM UTC 24 |
98050431 ps |
| T110 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.455885931 |
|
|
Oct 12 02:22:02 AM UTC 24 |
Oct 12 02:22:04 AM UTC 24 |
74031614 ps |
| T111 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_bit_bash.3681815783 |
|
|
Oct 12 02:21:59 AM UTC 24 |
Oct 12 02:22:04 AM UTC 24 |
546671184 ps |
| T281 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_intr_test.2266342736 |
|
|
Oct 12 02:22:03 AM UTC 24 |
Oct 12 02:22:05 AM UTC 24 |
28746400 ps |
| T112 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_tl_intg_err.3258374227 |
|
|
Oct 12 02:22:03 AM UTC 24 |
Oct 12 02:22:06 AM UTC 24 |
78786188 ps |
| T216 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_hw_reset.2030731011 |
|
|
Oct 12 02:22:04 AM UTC 24 |
Oct 12 02:22:06 AM UTC 24 |
21878628 ps |
| T1745 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_bit_bash.3050322126 |
|
|
Oct 12 02:22:02 AM UTC 24 |
Oct 12 02:22:06 AM UTC 24 |
113733662 ps |
| T217 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_rw.44905884 |
|
|
Oct 12 02:22:04 AM UTC 24 |
Oct 12 02:22:06 AM UTC 24 |
58965398 ps |
| T113 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_same_csr_outstanding.527027700 |
|
|
Oct 12 02:22:04 AM UTC 24 |
Oct 12 02:22:07 AM UTC 24 |
140644324 ps |
| T218 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_aliasing.1305296299 |
|
|
Oct 12 02:22:04 AM UTC 24 |
Oct 12 02:22:07 AM UTC 24 |
91852361 ps |
| T114 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_tl_errors.3358041212 |
|
|
Oct 12 02:22:03 AM UTC 24 |
Oct 12 02:22:07 AM UTC 24 |
136605134 ps |
| T211 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.228941115 |
|
|
Oct 12 02:22:04 AM UTC 24 |
Oct 12 02:22:07 AM UTC 24 |
72427748 ps |
| T1746 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_intr_test.3233348544 |
|
|
Oct 12 02:22:05 AM UTC 24 |
Oct 12 02:22:08 AM UTC 24 |
17822711 ps |
| T151 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_hw_reset.2064115075 |
|
|
Oct 12 02:22:06 AM UTC 24 |
Oct 12 02:22:08 AM UTC 24 |
64732803 ps |
| T228 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_rw.4038789027 |
|
|
Oct 12 02:22:06 AM UTC 24 |
Oct 12 02:22:08 AM UTC 24 |
26073273 ps |
| T205 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_tl_intg_err.199303562 |
|
|
Oct 12 02:22:05 AM UTC 24 |
Oct 12 02:22:08 AM UTC 24 |
76271353 ps |
| T196 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_tl_errors.2362699617 |
|
|
Oct 12 02:22:05 AM UTC 24 |
Oct 12 02:22:09 AM UTC 24 |
32985535 ps |
| T212 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.859547389 |
|
|
Oct 12 02:22:07 AM UTC 24 |
Oct 12 02:22:09 AM UTC 24 |
30429548 ps |
| T229 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_same_csr_outstanding.3222114179 |
|
|
Oct 12 02:22:07 AM UTC 24 |
Oct 12 02:22:09 AM UTC 24 |
21553192 ps |
| T1747 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_intr_test.2264441999 |
|
|
Oct 12 02:22:08 AM UTC 24 |
Oct 12 02:22:10 AM UTC 24 |
37780640 ps |
| T219 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_aliasing.3464316558 |
|
|
Oct 12 02:22:07 AM UTC 24 |
Oct 12 02:22:10 AM UTC 24 |
73902556 ps |
| T127 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_hw_reset.1943740784 |
|
|
Oct 12 02:22:08 AM UTC 24 |
Oct 12 02:22:10 AM UTC 24 |
77562738 ps |
| T230 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_rw.783840083 |
|
|
Oct 12 02:22:08 AM UTC 24 |
Oct 12 02:22:10 AM UTC 24 |
29985025 ps |
| T195 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_tl_intg_err.506134642 |
|
|
Oct 12 02:22:08 AM UTC 24 |
Oct 12 02:22:11 AM UTC 24 |
260514688 ps |
| T1748 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_bit_bash.3678090393 |
|
|
Oct 12 02:22:04 AM UTC 24 |
Oct 12 02:22:11 AM UTC 24 |
707158519 ps |
| T197 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_tl_errors.1997546645 |
|
|
Oct 12 02:22:07 AM UTC 24 |
Oct 12 02:22:11 AM UTC 24 |
325511657 ps |
| T223 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_bit_bash.1048832862 |
|
|
Oct 12 02:22:06 AM UTC 24 |
Oct 12 02:22:11 AM UTC 24 |
452133204 ps |
| T213 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.4119495882 |
|
|
Oct 12 02:22:09 AM UTC 24 |
Oct 12 02:22:12 AM UTC 24 |
47270994 ps |
| T231 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_same_csr_outstanding.3272821341 |
|
|
Oct 12 02:22:09 AM UTC 24 |
Oct 12 02:22:12 AM UTC 24 |
58092373 ps |
| T214 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_tl_errors.1878313759 |
|
|
Oct 12 02:22:09 AM UTC 24 |
Oct 12 02:22:12 AM UTC 24 |
97478244 ps |
| T1749 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_intr_test.2295190942 |
|
|
Oct 12 02:22:11 AM UTC 24 |
Oct 12 02:22:12 AM UTC 24 |
27914971 ps |
| T220 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_aliasing.1207514342 |
|
|
Oct 12 02:22:09 AM UTC 24 |
Oct 12 02:22:13 AM UTC 24 |
41230735 ps |
| T232 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_csr_rw.3166885021 |
|
|
Oct 12 02:22:11 AM UTC 24 |
Oct 12 02:22:13 AM UTC 24 |
17040801 ps |
| T1750 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_bit_bash.1460431103 |
|
|
Oct 12 02:22:08 AM UTC 24 |
Oct 12 02:22:13 AM UTC 24 |
1756953327 ps |
| T198 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_tl_intg_err.553813480 |
|
|
Oct 12 02:22:09 AM UTC 24 |
Oct 12 02:22:13 AM UTC 24 |
78112160 ps |
| T1751 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_same_csr_outstanding.163180281 |
|
|
Oct 12 02:22:11 AM UTC 24 |
Oct 12 02:22:13 AM UTC 24 |
56367246 ps |
| T1752 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.2675524748 |
|
|
Oct 12 02:22:11 AM UTC 24 |
Oct 12 02:22:13 AM UTC 24 |
26045448 ps |
| T1753 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_intr_test.1377576212 |
|
|
Oct 12 02:22:12 AM UTC 24 |
Oct 12 02:22:14 AM UTC 24 |
33980050 ps |
| T1754 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_csr_rw.1621474884 |
|
|
Oct 12 02:22:12 AM UTC 24 |
Oct 12 02:22:14 AM UTC 24 |
28880399 ps |
| T1755 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_same_csr_outstanding.1623211553 |
|
|
Oct 12 02:22:12 AM UTC 24 |
Oct 12 02:22:14 AM UTC 24 |
104404053 ps |
| T1756 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_tl_errors.4252851787 |
|
|
Oct 12 02:22:11 AM UTC 24 |
Oct 12 02:22:14 AM UTC 24 |
156958347 ps |
| T200 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_tl_intg_err.1136003642 |
|
|
Oct 12 02:22:12 AM UTC 24 |
Oct 12 02:22:15 AM UTC 24 |
47383668 ps |
| T1757 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_intr_test.2028940707 |
|
|
Oct 12 02:22:13 AM UTC 24 |
Oct 12 02:22:15 AM UTC 24 |
19889488 ps |
| T221 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_csr_rw.995003482 |
|
|
Oct 12 02:22:13 AM UTC 24 |
Oct 12 02:22:15 AM UTC 24 |
26003569 ps |
| T1758 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_same_csr_outstanding.253678493 |
|
|
Oct 12 02:22:13 AM UTC 24 |
Oct 12 02:22:15 AM UTC 24 |
148130614 ps |
| T1759 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.4233552861 |
|
|
Oct 12 02:22:13 AM UTC 24 |
Oct 12 02:22:15 AM UTC 24 |
35050695 ps |
| T1760 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.3354769127 |
|
|
Oct 12 02:22:13 AM UTC 24 |
Oct 12 02:22:15 AM UTC 24 |
37482799 ps |
| T1761 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_intr_test.3218457036 |
|
|
Oct 12 02:22:14 AM UTC 24 |
Oct 12 02:22:16 AM UTC 24 |
16209288 ps |
| T1762 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_tl_errors.644104588 |
|
|
Oct 12 02:22:13 AM UTC 24 |
Oct 12 02:22:17 AM UTC 24 |
65957205 ps |
| T222 |
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_csr_rw.2687504143 |
|
|
Oct 12 02:22:15 AM UTC 24 |
Oct 12 02:22:17 AM UTC 24 |
20055402 ps |