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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
91.28 97.26 89.57 97.22 72.02 94.30 98.47 90.11


Total test records in report: 1851
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T203 /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_tl_intg_err.1943223475 Oct 12 02:22:13 AM UTC 24 Oct 12 02:22:17 AM UTC 24 284948977 ps
T1763 /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_same_csr_outstanding.657533916 Oct 12 02:22:15 AM UTC 24 Oct 12 02:22:17 AM UTC 24 107101387 ps
T1764 /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_tl_intg_err.2264340852 Oct 12 02:22:14 AM UTC 24 Oct 12 02:22:17 AM UTC 24 83374035 ps
T1765 /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/9.i2c_tl_intg_err.2225328842 Oct 12 02:22:16 AM UTC 24 Oct 12 02:22:18 AM UTC 24 162589747 ps
T1766 /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_tl_errors.1109990890 Oct 12 02:22:14 AM UTC 24 Oct 12 02:22:17 AM UTC 24 123132331 ps
T1767 /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.3487010378 Oct 12 02:22:16 AM UTC 24 Oct 12 02:22:18 AM UTC 24 41148275 ps
T1768 /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/9.i2c_intr_test.3222711142 Oct 12 02:22:16 AM UTC 24 Oct 12 02:22:18 AM UTC 24 15963054 ps
T1769 /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/9.i2c_csr_rw.3638391042 Oct 12 02:22:16 AM UTC 24 Oct 12 02:22:18 AM UTC 24 20482918 ps
T1770 /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/9.i2c_same_csr_outstanding.2371124294 Oct 12 02:22:16 AM UTC 24 Oct 12 02:22:18 AM UTC 24 116768550 ps
T1771 /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.3679499437 Oct 12 02:22:16 AM UTC 24 Oct 12 02:22:18 AM UTC 24 27730690 ps
T1772 /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/9.i2c_tl_errors.2607205361 Oct 12 02:22:16 AM UTC 24 Oct 12 02:22:19 AM UTC 24 228347736 ps
T1773 /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_intr_test.1047492358 Oct 12 02:22:17 AM UTC 24 Oct 12 02:22:20 AM UTC 24 43912982 ps
T1774 /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_same_csr_outstanding.4293727507 Oct 12 02:22:17 AM UTC 24 Oct 12 02:22:20 AM UTC 24 66173398 ps
T1775 /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_csr_rw.1778696966 Oct 12 02:22:17 AM UTC 24 Oct 12 02:22:20 AM UTC 24 49593567 ps
T1776 /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_tl_intg_err.1393310121 Oct 12 02:22:17 AM UTC 24 Oct 12 02:22:21 AM UTC 24 82297770 ps
T1777 /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_tl_errors.3997970977 Oct 12 02:22:17 AM UTC 24 Oct 12 02:22:21 AM UTC 24 65637561 ps
T1778 /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_intr_test.2879628035 Oct 12 02:22:18 AM UTC 24 Oct 12 02:22:21 AM UTC 24 52464459 ps
T1779 /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_csr_rw.2454263503 Oct 12 02:22:19 AM UTC 24 Oct 12 02:22:21 AM UTC 24 17027454 ps
T1780 /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.2612299782 Oct 12 02:22:17 AM UTC 24 Oct 12 02:22:21 AM UTC 24 58207354 ps
T264 /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_same_csr_outstanding.2617549653 Oct 12 02:22:19 AM UTC 24 Oct 12 02:22:21 AM UTC 24 59084728 ps
T1781 /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_tl_intg_err.4045814988 Oct 12 02:22:18 AM UTC 24 Oct 12 02:22:22 AM UTC 24 479262303 ps
T1782 /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_intr_test.226186683 Oct 12 02:22:20 AM UTC 24 Oct 12 02:22:22 AM UTC 24 15248096 ps
T1783 /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_tl_errors.2615864328 Oct 12 02:22:18 AM UTC 24 Oct 12 02:22:22 AM UTC 24 72210841 ps
T226 /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_csr_rw.1217564279 Oct 12 02:22:20 AM UTC 24 Oct 12 02:22:22 AM UTC 24 353497534 ps
T1784 /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.1068985756 Oct 12 02:22:20 AM UTC 24 Oct 12 02:22:22 AM UTC 24 40186522 ps
T206 /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_tl_intg_err.1876858663 Oct 12 02:22:20 AM UTC 24 Oct 12 02:22:23 AM UTC 24 99096781 ps
T1785 /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_same_csr_outstanding.3010441943 Oct 12 02:22:21 AM UTC 24 Oct 12 02:22:23 AM UTC 24 53589049 ps
T1786 /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.2217379131 Oct 12 02:22:21 AM UTC 24 Oct 12 02:22:23 AM UTC 24 67781309 ps
T1787 /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_tl_errors.1436424697 Oct 12 02:22:20 AM UTC 24 Oct 12 02:22:24 AM UTC 24 252192934 ps
T1788 /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_tl_errors.2205448454 Oct 12 02:22:21 AM UTC 24 Oct 12 02:22:24 AM UTC 24 209541748 ps
T201 /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_tl_intg_err.3812307166 Oct 12 02:22:21 AM UTC 24 Oct 12 02:22:24 AM UTC 24 95550577 ps
T1789 /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_intr_test.3613084520 Oct 12 02:22:22 AM UTC 24 Oct 12 02:22:24 AM UTC 24 15287568 ps
T1790 /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_same_csr_outstanding.2729623237 Oct 12 02:22:22 AM UTC 24 Oct 12 02:22:25 AM UTC 24 39439052 ps
T1791 /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_csr_rw.118534399 Oct 12 02:22:22 AM UTC 24 Oct 12 02:22:25 AM UTC 24 50798705 ps
T1792 /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.2156313950 Oct 12 02:22:22 AM UTC 24 Oct 12 02:22:25 AM UTC 24 114498731 ps
T1793 /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_tl_errors.306477897 Oct 12 02:22:22 AM UTC 24 Oct 12 02:22:26 AM UTC 24 37787374 ps
T1794 /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_intr_test.3617705674 Oct 12 02:22:23 AM UTC 24 Oct 12 02:22:27 AM UTC 24 27044094 ps
T225 /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_csr_rw.2580007450 Oct 12 02:22:24 AM UTC 24 Oct 12 02:22:27 AM UTC 24 24155874 ps
T1795 /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_same_csr_outstanding.3604386765 Oct 12 02:22:24 AM UTC 24 Oct 12 02:22:27 AM UTC 24 38362540 ps
T1796 /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/15.i2c_tl_errors.3838019885 Oct 12 02:22:24 AM UTC 24 Oct 12 02:22:28 AM UTC 24 512653619 ps
T282 /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/15.i2c_intr_test.340237853 Oct 12 02:22:25 AM UTC 24 Oct 12 02:22:28 AM UTC 24 27057240 ps
T1797 /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/15.i2c_csr_rw.1249069353 Oct 12 02:22:25 AM UTC 24 Oct 12 02:22:28 AM UTC 24 17344932 ps
T1798 /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.3862378677 Oct 12 02:22:24 AM UTC 24 Oct 12 02:22:28 AM UTC 24 96564270 ps
T1799 /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/15.i2c_same_csr_outstanding.1392487315 Oct 12 02:22:25 AM UTC 24 Oct 12 02:22:28 AM UTC 24 95240325 ps
T207 /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/15.i2c_tl_intg_err.187475950 Oct 12 02:22:24 AM UTC 24 Oct 12 02:22:28 AM UTC 24 289126277 ps
T202 /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_tl_intg_err.1194964279 Oct 12 02:22:23 AM UTC 24 Oct 12 02:22:28 AM UTC 24 593688863 ps
T1800 /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/16.i2c_intr_test.1041656357 Oct 12 02:22:26 AM UTC 24 Oct 12 02:22:29 AM UTC 24 16798782 ps
T1801 /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.2715265046 Oct 12 02:22:26 AM UTC 24 Oct 12 02:22:29 AM UTC 24 415195165 ps
T224 /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/16.i2c_csr_rw.1882863685 Oct 12 02:22:26 AM UTC 24 Oct 12 02:22:29 AM UTC 24 24098661 ps
T199 /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/16.i2c_tl_intg_err.1970532421 Oct 12 02:22:26 AM UTC 24 Oct 12 02:22:29 AM UTC 24 52002174 ps
T1802 /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.3517476037 Oct 12 02:22:27 AM UTC 24 Oct 12 02:22:30 AM UTC 24 83993149 ps
T1803 /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/16.i2c_same_csr_outstanding.3941087993 Oct 12 02:22:27 AM UTC 24 Oct 12 02:22:30 AM UTC 24 21773367 ps
T1804 /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/16.i2c_tl_errors.3583477153 Oct 12 02:22:26 AM UTC 24 Oct 12 02:22:30 AM UTC 24 72972344 ps
T1805 /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/17.i2c_tl_errors.2545894484 Oct 12 02:22:27 AM UTC 24 Oct 12 02:22:30 AM UTC 24 504601466 ps
T1806 /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/17.i2c_intr_test.897059925 Oct 12 02:22:29 AM UTC 24 Oct 12 02:22:31 AM UTC 24 17312657 ps
T1807 /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/17.i2c_csr_rw.3967705280 Oct 12 02:22:29 AM UTC 24 Oct 12 02:22:31 AM UTC 24 38585932 ps
T1808 /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/17.i2c_same_csr_outstanding.1918948995 Oct 12 02:22:29 AM UTC 24 Oct 12 02:22:31 AM UTC 24 21471174 ps
T1809 /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/17.i2c_tl_intg_err.3757941749 Oct 12 02:22:28 AM UTC 24 Oct 12 02:22:31 AM UTC 24 70591703 ps
T1810 /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.2426719938 Oct 12 02:22:29 AM UTC 24 Oct 12 02:22:31 AM UTC 24 526936141 ps
T1811 /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/18.i2c_intr_test.719417646 Oct 12 02:22:30 AM UTC 24 Oct 12 02:22:32 AM UTC 24 24813571 ps
T1812 /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/18.i2c_csr_rw.1417468290 Oct 12 02:22:30 AM UTC 24 Oct 12 02:22:32 AM UTC 24 22259288 ps
T204 /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/18.i2c_tl_intg_err.1576475266 Oct 12 02:22:29 AM UTC 24 Oct 12 02:22:32 AM UTC 24 123361628 ps
T1813 /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/18.i2c_same_csr_outstanding.4097569771 Oct 12 02:22:30 AM UTC 24 Oct 12 02:22:32 AM UTC 24 115592856 ps
T1814 /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.209581886 Oct 12 02:22:30 AM UTC 24 Oct 12 02:22:33 AM UTC 24 27512597 ps
T1815 /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/18.i2c_tl_errors.3536637971 Oct 12 02:22:29 AM UTC 24 Oct 12 02:22:33 AM UTC 24 148598004 ps
T1816 /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/19.i2c_intr_test.1997355558 Oct 12 02:22:31 AM UTC 24 Oct 12 02:22:33 AM UTC 24 25287894 ps
T1817 /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/20.i2c_intr_test.396848891 Oct 12 02:22:31 AM UTC 24 Oct 12 02:22:33 AM UTC 24 14667392 ps
T1818 /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/19.i2c_csr_rw.1115752318 Oct 12 02:22:31 AM UTC 24 Oct 12 02:22:33 AM UTC 24 34527580 ps
T1819 /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/19.i2c_same_csr_outstanding.1210680954 Oct 12 02:22:31 AM UTC 24 Oct 12 02:22:34 AM UTC 24 34598784 ps
T1820 /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.4179373755 Oct 12 02:22:31 AM UTC 24 Oct 12 02:22:34 AM UTC 24 79016683 ps
T1821 /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/19.i2c_tl_errors.98465748 Oct 12 02:22:30 AM UTC 24 Oct 12 02:22:34 AM UTC 24 196837533 ps
T1822 /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/21.i2c_intr_test.2906127578 Oct 12 02:22:32 AM UTC 24 Oct 12 02:22:34 AM UTC 24 28849142 ps
T1823 /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/22.i2c_intr_test.3766989292 Oct 12 02:22:32 AM UTC 24 Oct 12 02:22:34 AM UTC 24 35471880 ps
T1824 /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/25.i2c_intr_test.287762284 Oct 12 02:22:33 AM UTC 24 Oct 12 02:22:34 AM UTC 24 19879827 ps
T1825 /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/24.i2c_intr_test.2966641496 Oct 12 02:22:33 AM UTC 24 Oct 12 02:22:35 AM UTC 24 20729108 ps
T1826 /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/23.i2c_intr_test.1229315643 Oct 12 02:22:33 AM UTC 24 Oct 12 02:22:35 AM UTC 24 16581287 ps
T1827 /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/26.i2c_intr_test.2380168604 Oct 12 02:22:33 AM UTC 24 Oct 12 02:22:35 AM UTC 24 16615510 ps
T1828 /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/19.i2c_tl_intg_err.648579156 Oct 12 02:22:31 AM UTC 24 Oct 12 02:22:35 AM UTC 24 85496470 ps
T1829 /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/28.i2c_intr_test.408064724 Oct 12 02:22:34 AM UTC 24 Oct 12 02:22:36 AM UTC 24 89961788 ps
T1830 /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/30.i2c_intr_test.3333852448 Oct 12 02:22:34 AM UTC 24 Oct 12 02:22:36 AM UTC 24 19677510 ps
T1831 /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/29.i2c_intr_test.139200337 Oct 12 02:22:34 AM UTC 24 Oct 12 02:22:36 AM UTC 24 38684763 ps
T1832 /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/31.i2c_intr_test.895655941 Oct 12 02:22:34 AM UTC 24 Oct 12 02:22:36 AM UTC 24 50101823 ps
T1833 /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/27.i2c_intr_test.2712186437 Oct 12 02:22:34 AM UTC 24 Oct 12 02:22:36 AM UTC 24 18830614 ps
T1834 /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/33.i2c_intr_test.213653025 Oct 12 02:22:34 AM UTC 24 Oct 12 02:22:36 AM UTC 24 30294308 ps
T1835 /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/32.i2c_intr_test.4031134954 Oct 12 02:22:34 AM UTC 24 Oct 12 02:22:36 AM UTC 24 67811286 ps
T1836 /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/34.i2c_intr_test.485482565 Oct 12 02:22:35 AM UTC 24 Oct 12 02:22:37 AM UTC 24 37940471 ps
T1837 /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/35.i2c_intr_test.1106978357 Oct 12 02:22:35 AM UTC 24 Oct 12 02:22:37 AM UTC 24 46721498 ps
T1838 /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/39.i2c_intr_test.3950764295 Oct 12 02:22:35 AM UTC 24 Oct 12 02:22:37 AM UTC 24 26119167 ps
T1839 /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/38.i2c_intr_test.1630462774 Oct 12 02:22:35 AM UTC 24 Oct 12 02:22:37 AM UTC 24 17147218 ps
T1840 /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/40.i2c_intr_test.4189032569 Oct 12 02:22:35 AM UTC 24 Oct 12 02:22:37 AM UTC 24 17847677 ps
T1841 /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/37.i2c_intr_test.2913240149 Oct 12 02:22:35 AM UTC 24 Oct 12 02:22:37 AM UTC 24 45995476 ps
T1842 /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/36.i2c_intr_test.558601471 Oct 12 02:22:35 AM UTC 24 Oct 12 02:22:37 AM UTC 24 19531302 ps
T1843 /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/41.i2c_intr_test.2199086446 Oct 12 02:22:35 AM UTC 24 Oct 12 02:22:37 AM UTC 24 24995150 ps
T1844 /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/42.i2c_intr_test.3145422042 Oct 12 02:22:35 AM UTC 24 Oct 12 02:22:38 AM UTC 24 53936168 ps
T1845 /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/44.i2c_intr_test.2198213646 Oct 12 02:22:37 AM UTC 24 Oct 12 02:22:39 AM UTC 24 42763960 ps
T1846 /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/45.i2c_intr_test.1625663552 Oct 12 02:22:37 AM UTC 24 Oct 12 02:22:39 AM UTC 24 76577742 ps
T1847 /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/47.i2c_intr_test.1622019643 Oct 12 02:22:37 AM UTC 24 Oct 12 02:22:39 AM UTC 24 119995645 ps
T1848 /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/46.i2c_intr_test.3363096038 Oct 12 02:22:37 AM UTC 24 Oct 12 02:22:39 AM UTC 24 34172815 ps
T1849 /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/43.i2c_intr_test.589113623 Oct 12 02:22:37 AM UTC 24 Oct 12 02:22:39 AM UTC 24 35263194 ps
T1850 /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/49.i2c_intr_test.1222437447 Oct 12 02:22:37 AM UTC 24 Oct 12 02:22:39 AM UTC 24 34545504 ps
T1851 /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/48.i2c_intr_test.2566409185 Oct 12 02:22:37 AM UTC 24 Oct 12 02:22:39 AM UTC 24 18014608 ps

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/0.i2c_host_stretch_timeout.613811644
Short name T8
Test name
Test status
Simulation time 853267281 ps
CPU time 22.61 seconds
Started Oct 12 05:53:17 AM UTC 24
Finished Oct 12 05:53:41 AM UTC 24
Peak memory 226084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=613811644 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_stretch_timeout.613811644
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/0.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/0.i2c_target_timeout.1469539228
Short name T47
Test name
Test status
Simulation time 4055338603 ps
CPU time 11.62 seconds
Started Oct 12 05:53:42 AM UTC 24
Finished Oct 12 05:53:55 AM UTC 24
Peak memory 244976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1469539
228 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_timeout.1469539228
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/0.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/0.i2c_target_glitch.2321662958
Short name T6
Test name
Test status
Simulation time 6878803377 ps
CPU time 16.66 seconds
Started Oct 12 05:53:18 AM UTC 24
Finished Oct 12 05:53:36 AM UTC 24
Peak memory 226344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2321662958 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_glitch.2321662958
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/0.i2c_target_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/7.i2c_host_stress_all.3268181653
Short name T35
Test name
Test status
Simulation time 60606836687 ps
CPU time 212.13 seconds
Started Oct 12 05:59:35 AM UTC 24
Finished Oct 12 06:03:11 AM UTC 24
Peak memory 665020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3268181653 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 7.i2c_host_stress_all.3268181653
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/7.i2c_host_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_tl_errors.3358041212
Short name T114
Test name
Test status
Simulation time 136605134 ps
CPU time 2.99 seconds
Started Oct 12 02:22:03 AM UTC 24
Finished Oct 12 02:22:07 AM UTC 24
Peak memory 215304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3358041212 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_errors.3358041212
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/2.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/0.i2c_host_error_intr.3139447076
Short name T4
Test name
Test status
Simulation time 1207362387 ps
CPU time 7.94 seconds
Started Oct 12 05:53:17 AM UTC 24
Finished Oct 12 05:53:26 AM UTC 24
Peak memory 277508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3139447076 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 0.i2c_host_error_intr.3139447076
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/0.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/0.i2c_host_fifo_watermark.1637871209
Short name T38
Test name
Test status
Simulation time 11318089004 ps
CPU time 75.88 seconds
Started Oct 12 05:53:14 AM UTC 24
Finished Oct 12 05:54:31 AM UTC 24
Peak memory 1143868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1637871209 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_watermark.1637871209
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/0.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/1.i2c_target_nack_txstretch.2362902554
Short name T60
Test name
Test status
Simulation time 948627370 ps
CPU time 2.73 seconds
Started Oct 12 05:55:04 AM UTC 24
Finished Oct 12 05:55:08 AM UTC 24
Peak memory 232588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2362902
554 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_nack_txstretch.2362902554
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/1.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/0.i2c_target_stress_all.1982636908
Short name T77
Test name
Test status
Simulation time 43653866863 ps
CPU time 105.65 seconds
Started Oct 12 05:53:55 AM UTC 24
Finished Oct 12 05:55:43 AM UTC 24
Peak memory 574328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=198263
6908 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_stress_all.1982636908
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/0.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/1.i2c_host_may_nack.3249598684
Short name T12
Test name
Test status
Simulation time 10813515366 ps
CPU time 11.98 seconds
Started Oct 12 05:54:58 AM UTC 24
Finished Oct 12 05:55:12 AM UTC 24
Peak memory 215428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3249598684 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.i2c_host_may_nack.3249598684
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/1.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/2.i2c_host_override.475757291
Short name T102
Test name
Test status
Simulation time 100565406 ps
CPU time 0.94 seconds
Started Oct 12 05:55:08 AM UTC 24
Finished Oct 12 05:55:09 AM UTC 24
Peak memory 213208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=475757291 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 2.i2c_host_override.475757291
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/2.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/0.i2c_sec_cm.3838161966
Short name T185
Test name
Test status
Simulation time 129485157 ps
CPU time 1.25 seconds
Started Oct 12 05:54:17 AM UTC 24
Finished Oct 12 05:54:19 AM UTC 24
Peak memory 244936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3838161966 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_sec_cm.3838161966
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/0.i2c_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/5.i2c_target_nack_acqfull_addr.265106960
Short name T48
Test name
Test status
Simulation time 407008658 ps
CPU time 4.64 seconds
Started Oct 12 05:58:17 AM UTC 24
Finished Oct 12 05:58:23 AM UTC 24
Peak memory 215408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2651069
60 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_nack_acqfull_addr.265106960
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/5.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/44.i2c_host_stress_all.4123727147
Short name T246
Test name
Test status
Simulation time 6649402243 ps
CPU time 416.48 seconds
Started Oct 12 06:24:28 AM UTC 24
Finished Oct 12 06:31:30 AM UTC 24
Peak memory 1613264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4123727147 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 44.i2c_host_stress_all.4123727147
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/44.i2c_host_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/0.i2c_host_fifo_reset_fmt.1106290690
Short name T2
Test name
Test status
Simulation time 101423850 ps
CPU time 1.48 seconds
Started Oct 12 05:53:14 AM UTC 24
Finished Oct 12 05:53:16 AM UTC 24
Peak memory 213332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1106290690 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_fmt.1106290690
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/0.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_tl_intg_err.1337603506
Short name T194
Test name
Test status
Simulation time 159174346 ps
CPU time 2.08 seconds
Started Oct 12 02:22:00 AM UTC 24
Finished Oct 12 02:22:03 AM UTC 24
Peak memory 215052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1337603506 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_intg_err.1337603506
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/1.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/5.i2c_host_error_intr.3967964530
Short name T19
Test name
Test status
Simulation time 109464787 ps
CPU time 2.79 seconds
Started Oct 12 05:57:34 AM UTC 24
Finished Oct 12 05:57:38 AM UTC 24
Peak memory 225828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3967964530 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 5.i2c_host_error_intr.3967964530
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/5.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_aliasing.525421256
Short name T107
Test name
Test status
Simulation time 396625591 ps
CPU time 2.76 seconds
Started Oct 12 02:21:59 AM UTC 24
Finished Oct 12 02:22:03 AM UTC 24
Peak memory 214864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=525421256 -assert nopostproc +UVM_TESTNAME=i2c
_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i
2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_aliasing.525421256
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/0.i2c_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/8.i2c_target_stress_all.780766945
Short name T209
Test name
Test status
Simulation time 32198571221 ps
CPU time 169.65 seconds
Started Oct 12 06:00:41 AM UTC 24
Finished Oct 12 06:03:33 AM UTC 24
Peak memory 2225356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=780766
945 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_stress_all.780766945
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/8.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/0.i2c_target_nack_acqfull_addr.1324491771
Short name T64
Test name
Test status
Simulation time 433438778 ps
CPU time 3.86 seconds
Started Oct 12 05:54:14 AM UTC 24
Finished Oct 12 05:54:19 AM UTC 24
Peak memory 215488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1324491
771 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_nack_acqfull_addr.1324491771
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/0.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/27.i2c_target_nack_acqfull.1462857317
Short name T999
Test name
Test status
Simulation time 2817947639 ps
CPU time 3.42 seconds
Started Oct 12 06:14:48 AM UTC 24
Finished Oct 12 06:14:53 AM UTC 24
Peak memory 225928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1462857
317 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_nack_acqfull.1462857317
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/27.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/0.i2c_target_bad_addr.2494466052
Short name T45
Test name
Test status
Simulation time 1618292622 ps
CPU time 8.43 seconds
Started Oct 12 05:53:57 AM UTC 24
Finished Oct 12 05:54:07 AM UTC 24
Peak memory 232164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=2494466052 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_bad_addr.2494466052
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/0.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/9.i2c_host_fifo_overflow.4242294469
Short name T448
Test name
Test status
Simulation time 3237865135 ps
CPU time 45.1 seconds
Started Oct 12 06:00:59 AM UTC 24
Finished Oct 12 06:01:46 AM UTC 24
Peak memory 574656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4242294469 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_overflow.4242294469
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/9.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/0.i2c_target_fifo_watermarks_acq.4278678730
Short name T69
Test name
Test status
Simulation time 673032731 ps
CPU time 4.41 seconds
Started Oct 12 05:54:08 AM UTC 24
Finished Oct 12 05:54:14 AM UTC 24
Peak memory 215524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4278678
730 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_fifo_watermark
s_acq.4278678730
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/0.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/1.i2c_host_fifo_reset_rx.1230377401
Short name T81
Test name
Test status
Simulation time 149234358 ps
CPU time 8.49 seconds
Started Oct 12 05:54:23 AM UTC 24
Finished Oct 12 05:54:33 AM UTC 24
Peak memory 215396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1230377401 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_rx.1230377401
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/1.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/17.i2c_host_stress_all.1081704064
Short name T184
Test name
Test status
Simulation time 67130594070 ps
CPU time 315.25 seconds
Started Oct 12 06:06:54 AM UTC 24
Finished Oct 12 06:12:14 AM UTC 24
Peak memory 1332240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1081704064 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 17.i2c_host_stress_all.1081704064
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/17.i2c_host_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/10.i2c_host_smoke.308573115
Short name T420
Test name
Test status
Simulation time 1775363492 ps
CPU time 38.09 seconds
Started Oct 12 06:01:46 AM UTC 24
Finished Oct 12 06:02:26 AM UTC 24
Peak memory 379832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=308573115 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 10.i2c_host_smoke.308573115
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/10.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/0.i2c_alert_test.2646031723
Short name T99
Test name
Test status
Simulation time 44148885 ps
CPU time 1.05 seconds
Started Oct 12 05:54:18 AM UTC 24
Finished Oct 12 05:54:20 AM UTC 24
Peak memory 213392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2646031723 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_alert_test.2646031723
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/0.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/14.i2c_host_fifo_reset_fmt.2016240002
Short name T243
Test name
Test status
Simulation time 137446881 ps
CPU time 1.94 seconds
Started Oct 12 06:04:21 AM UTC 24
Finished Oct 12 06:04:24 AM UTC 24
Peak memory 215716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2016240002 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_fmt.2016240002
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/14.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/14.i2c_host_may_nack.2665918513
Short name T255
Test name
Test status
Simulation time 934266667 ps
CPU time 10.14 seconds
Started Oct 12 06:05:01 AM UTC 24
Finished Oct 12 06:05:12 AM UTC 24
Peak memory 215692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2665918513 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.i2c_host_may_nack.2665918513
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/14.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/6.i2c_host_stress_all.3226457003
Short name T183
Test name
Test status
Simulation time 10989168620 ps
CPU time 432.71 seconds
Started Oct 12 05:58:39 AM UTC 24
Finished Oct 12 06:05:58 AM UTC 24
Peak memory 1694908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3226457003 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 6.i2c_host_stress_all.3226457003
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/6.i2c_host_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/1.i2c_host_mode_toggle.2734100448
Short name T18
Test name
Test status
Simulation time 235536921 ps
CPU time 5.17 seconds
Started Oct 12 05:54:57 AM UTC 24
Finished Oct 12 05:55:04 AM UTC 24
Peak memory 215392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2734100448 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_mode_toggle.2734100448
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/1.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/9.i2c_host_may_nack.4095658350
Short name T250
Test name
Test status
Simulation time 1175697248 ps
CPU time 16.33 seconds
Started Oct 12 06:01:37 AM UTC 24
Finished Oct 12 06:01:54 AM UTC 24
Peak memory 215464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4095658350 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.i2c_host_may_nack.4095658350
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/9.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_rw.3169277881
Short name T105
Test name
Test status
Simulation time 51028884 ps
CPU time 0.95 seconds
Started Oct 12 02:21:59 AM UTC 24
Finished Oct 12 02:22:01 AM UTC 24
Peak memory 214196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3169277881 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_rw.3169277881
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/0.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/11.i2c_target_smoke.3905696237
Short name T85
Test name
Test status
Simulation time 1133347729 ps
CPU time 41.15 seconds
Started Oct 12 06:02:48 AM UTC 24
Finished Oct 12 06:03:31 AM UTC 24
Peak memory 232396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3905696237 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_smoke.3905696237
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/11.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/0.i2c_host_perf_precise.3406204531
Short name T7
Test name
Test status
Simulation time 519360731 ps
CPU time 19.78 seconds
Started Oct 12 05:53:17 AM UTC 24
Finished Oct 12 05:53:38 AM UTC 24
Peak memory 215528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3406204531 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_perf_precise.3406204531
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/0.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/33.i2c_host_override.4105346446
Short name T262
Test name
Test status
Simulation time 37303712 ps
CPU time 1.07 seconds
Started Oct 12 06:17:56 AM UTC 24
Finished Oct 12 06:17:58 AM UTC 24
Peak memory 213212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4105346446 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.i2c_host_override.4105346446
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/33.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/4.i2c_target_fifo_reset_tx.1842581723
Short name T236
Test name
Test status
Simulation time 168457863 ps
CPU time 1.43 seconds
Started Oct 12 05:56:59 AM UTC 24
Finished Oct 12 05:57:01 AM UTC 24
Peak memory 215572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1842581
723 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_fifo_reset_tx.1842581723
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/4.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/13.i2c_host_error_intr.3057920270
Short name T22
Test name
Test status
Simulation time 230681494 ps
CPU time 2.51 seconds
Started Oct 12 06:03:46 AM UTC 24
Finished Oct 12 06:03:49 AM UTC 24
Peak memory 225788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3057920270 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 13.i2c_host_error_intr.3057920270
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/13.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_tl_errors.3997970977
Short name T1777
Test name
Test status
Simulation time 65637561 ps
CPU time 2.14 seconds
Started Oct 12 02:22:17 AM UTC 24
Finished Oct 12 02:22:21 AM UTC 24
Peak memory 214992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3997970977 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_errors.3997970977
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/10.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/15.i2c_tl_intg_err.187475950
Short name T207
Test name
Test status
Simulation time 289126277 ps
CPU time 1.88 seconds
Started Oct 12 02:22:24 AM UTC 24
Finished Oct 12 02:22:28 AM UTC 24
Peak memory 214024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=187475950 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
1/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_intg_err.187475950
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/15.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_same_csr_outstanding.2617549653
Short name T264
Test name
Test status
Simulation time 59084728 ps
CPU time 1.16 seconds
Started Oct 12 02:22:19 AM UTC 24
Finished Oct 12 02:22:21 AM UTC 24
Peak memory 213780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2617549653 -assert nopostproc +UVM
_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_same_csr_outstanding.2617549653
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/11.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/0.i2c_target_tx_stretch_ctrl.351004132
Short name T70
Test name
Test status
Simulation time 127456798 ps
CPU time 4.12 seconds
Started Oct 12 05:54:11 AM UTC 24
Finished Oct 12 05:54:17 AM UTC 24
Peak memory 215396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3510041
32 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_tx_stretch_ctrl.351004132
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/0.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/11.i2c_target_stress_rd.1015492814
Short name T539
Test name
Test status
Simulation time 6274007288 ps
CPU time 72.76 seconds
Started Oct 12 06:02:49 AM UTC 24
Finished Oct 12 06:04:04 AM UTC 24
Peak memory 229920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1015492814 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_stress_rd.1015492814
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/11.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/13.i2c_target_intr_smoke.4183580799
Short name T271
Test name
Test status
Simulation time 482543520 ps
CPU time 5.69 seconds
Started Oct 12 06:04:00 AM UTC 24
Finished Oct 12 06:04:07 AM UTC 24
Peak memory 225968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=418358
0799 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_intr_smoke.4183580799
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/13.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/15.i2c_host_may_nack.151467738
Short name T247
Test name
Test status
Simulation time 1315753716 ps
CPU time 18.37 seconds
Started Oct 12 06:05:56 AM UTC 24
Finished Oct 12 06:06:16 AM UTC 24
Peak memory 215464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=151467738 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 15.i2c_host_may_nack.151467738
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/15.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/19.i2c_target_fifo_reset_acq.3427260537
Short name T291
Test name
Test status
Simulation time 305302980 ps
CPU time 2.4 seconds
Started Oct 12 06:08:32 AM UTC 24
Finished Oct 12 06:08:35 AM UTC 24
Peak memory 222072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3427260
537 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_fifo_reset_acq.3427260537
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/19.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_tl_intg_err.1136003642
Short name T200
Test name
Test status
Simulation time 47383668 ps
CPU time 1.87 seconds
Started Oct 12 02:22:12 AM UTC 24
Finished Oct 12 02:22:15 AM UTC 24
Peak memory 214224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1136003642 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_intg_err.1136003642
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/6.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/12.i2c_host_error_intr.397439031
Short name T29
Test name
Test status
Simulation time 314661755 ps
CPU time 1.97 seconds
Started Oct 12 06:03:13 AM UTC 24
Finished Oct 12 06:03:16 AM UTC 24
Peak memory 225456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=397439031 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 12.i2c_host_error_intr.397439031
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/12.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/16.i2c_tl_intg_err.1970532421
Short name T199
Test name
Test status
Simulation time 52002174 ps
CPU time 1.6 seconds
Started Oct 12 02:22:26 AM UTC 24
Finished Oct 12 02:22:29 AM UTC 24
Peak memory 214216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1970532421 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_intg_err.1970532421
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/16.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_tl_intg_err.553813480
Short name T198
Test name
Test status
Simulation time 78112160 ps
CPU time 2.64 seconds
Started Oct 12 02:22:09 AM UTC 24
Finished Oct 12 02:22:13 AM UTC 24
Peak memory 215180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=553813480 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
1/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_intg_err.553813480
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/5.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/10.i2c_host_mode_toggle.3896614919
Short name T79
Test name
Test status
Simulation time 132746224 ps
CPU time 6.4 seconds
Started Oct 12 06:02:32 AM UTC 24
Finished Oct 12 06:02:39 AM UTC 24
Peak memory 232648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3896614919 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_mode_toggle.3896614919
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/10.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/10.i2c_target_hrst.1565459695
Short name T465
Test name
Test status
Simulation time 688307896 ps
CPU time 3.64 seconds
Started Oct 12 06:02:31 AM UTC 24
Finished Oct 12 06:02:35 AM UTC 24
Peak memory 225708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1565459
695 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_hrst.1565459695
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/10.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_bit_bash.3681815783
Short name T111
Test name
Test status
Simulation time 546671184 ps
CPU time 4.24 seconds
Started Oct 12 02:21:59 AM UTC 24
Finished Oct 12 02:22:04 AM UTC 24
Peak memory 214980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3681815783 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_bit_bash.3681815783
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/0.i2c_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_hw_reset.4254589828
Short name T208
Test name
Test status
Simulation time 58712102 ps
CPU time 1 seconds
Started Oct 12 02:21:59 AM UTC 24
Finished Oct 12 02:22:01 AM UTC 24
Peak memory 214196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4254589828 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_hw_reset.4254589828
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/0.i2c_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.77869256
Short name T189
Test name
Test status
Simulation time 88148288 ps
CPU time 1.9 seconds
Started Oct 12 02:22:00 AM UTC 24
Finished Oct 12 02:22:03 AM UTC 24
Peak memory 214148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=77869256 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_mem_rw_with_rand_reset.77869256
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/0.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_intr_test.2996435197
Short name T1742
Test name
Test status
Simulation time 47921171 ps
CPU time 0.97 seconds
Started Oct 12 02:21:59 AM UTC 24
Finished Oct 12 02:22:01 AM UTC 24
Peak memory 214200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2996435197 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_intr_test.2996435197
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/0.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_same_csr_outstanding.2650066547
Short name T106
Test name
Test status
Simulation time 39799142 ps
CPU time 1.03 seconds
Started Oct 12 02:22:00 AM UTC 24
Finished Oct 12 02:22:02 AM UTC 24
Peak memory 214264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2650066547 -assert nopostproc +UVM
_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_same_csr_outstanding.2650066547
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/0.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_tl_errors.3036736238
Short name T188
Test name
Test status
Simulation time 43607107 ps
CPU time 2.47 seconds
Started Oct 12 02:21:59 AM UTC 24
Finished Oct 12 02:22:02 AM UTC 24
Peak memory 215112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3036736238 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_errors.3036736238
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/0.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_tl_intg_err.34775466
Short name T187
Test name
Test status
Simulation time 95301339 ps
CPU time 1.89 seconds
Started Oct 12 02:21:59 AM UTC 24
Finished Oct 12 02:22:02 AM UTC 24
Peak memory 214272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=34775466 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_intg_err.34775466
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/0.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_aliasing.3337612501
Short name T109
Test name
Test status
Simulation time 130512873 ps
CPU time 1.52 seconds
Started Oct 12 02:22:02 AM UTC 24
Finished Oct 12 02:22:04 AM UTC 24
Peak memory 214272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3337612501 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_aliasing.3337612501
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/1.i2c_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_bit_bash.3050322126
Short name T1745
Test name
Test status
Simulation time 113733662 ps
CPU time 3.39 seconds
Started Oct 12 02:22:02 AM UTC 24
Finished Oct 12 02:22:06 AM UTC 24
Peak memory 215052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3050322126 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_bit_bash.3050322126
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/1.i2c_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_hw_reset.4140285501
Short name T1744
Test name
Test status
Simulation time 18880045 ps
CPU time 1.05 seconds
Started Oct 12 02:22:01 AM UTC 24
Finished Oct 12 02:22:03 AM UTC 24
Peak memory 214196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4140285501 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_hw_reset.4140285501
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/1.i2c_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.455885931
Short name T110
Test name
Test status
Simulation time 74031614 ps
CPU time 1.44 seconds
Started Oct 12 02:22:02 AM UTC 24
Finished Oct 12 02:22:04 AM UTC 24
Peak memory 214196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=455885931 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_mem_rw_with_rand_reset.455885931
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/1.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_rw.2865560506
Short name T227
Test name
Test status
Simulation time 77057041 ps
CPU time 1.09 seconds
Started Oct 12 02:22:01 AM UTC 24
Finished Oct 12 02:22:03 AM UTC 24
Peak memory 214196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2865560506 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_rw.2865560506
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/1.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_intr_test.2806018538
Short name T1743
Test name
Test status
Simulation time 29020252 ps
CPU time 1 seconds
Started Oct 12 02:22:01 AM UTC 24
Finished Oct 12 02:22:03 AM UTC 24
Peak memory 214072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2806018538 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_intr_test.2806018538
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/1.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_same_csr_outstanding.2717310565
Short name T108
Test name
Test status
Simulation time 259126429 ps
CPU time 1.35 seconds
Started Oct 12 02:22:02 AM UTC 24
Finished Oct 12 02:22:04 AM UTC 24
Peak memory 214216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2717310565 -assert nopostproc +UVM
_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_same_csr_outstanding.2717310565
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/1.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_tl_errors.2875549594
Short name T193
Test name
Test status
Simulation time 98050431 ps
CPU time 2.9 seconds
Started Oct 12 02:22:00 AM UTC 24
Finished Oct 12 02:22:04 AM UTC 24
Peak memory 215368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2875549594 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_errors.2875549594
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/1.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.2612299782
Short name T1780
Test name
Test status
Simulation time 58207354 ps
CPU time 2.07 seconds
Started Oct 12 02:22:17 AM UTC 24
Finished Oct 12 02:22:21 AM UTC 24
Peak memory 227340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=2612299782 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_csr_mem_rw_with_rand_reset.2612299782
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/10.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_csr_rw.1778696966
Short name T1775
Test name
Test status
Simulation time 49593567 ps
CPU time 0.96 seconds
Started Oct 12 02:22:17 AM UTC 24
Finished Oct 12 02:22:20 AM UTC 24
Peak memory 214260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1778696966 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_csr_rw.1778696966
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/10.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_intr_test.1047492358
Short name T1773
Test name
Test status
Simulation time 43912982 ps
CPU time 0.97 seconds
Started Oct 12 02:22:17 AM UTC 24
Finished Oct 12 02:22:20 AM UTC 24
Peak memory 214072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1047492358 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_intr_test.1047492358
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/10.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_same_csr_outstanding.4293727507
Short name T1774
Test name
Test status
Simulation time 66173398 ps
CPU time 1.11 seconds
Started Oct 12 02:22:17 AM UTC 24
Finished Oct 12 02:22:20 AM UTC 24
Peak memory 214324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4293727507 -assert nopostproc +UVM
_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_same_csr_outstanding.4293727507
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/10.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_tl_intg_err.1393310121
Short name T1776
Test name
Test status
Simulation time 82297770 ps
CPU time 1.81 seconds
Started Oct 12 02:22:17 AM UTC 24
Finished Oct 12 02:22:21 AM UTC 24
Peak memory 214212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1393310121 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_intg_err.1393310121
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/10.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.1068985756
Short name T1784
Test name
Test status
Simulation time 40186522 ps
CPU time 1.38 seconds
Started Oct 12 02:22:20 AM UTC 24
Finished Oct 12 02:22:22 AM UTC 24
Peak memory 214264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=1068985756 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_csr_mem_rw_with_rand_reset.1068985756
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/11.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_csr_rw.2454263503
Short name T1779
Test name
Test status
Simulation time 17027454 ps
CPU time 0.97 seconds
Started Oct 12 02:22:19 AM UTC 24
Finished Oct 12 02:22:21 AM UTC 24
Peak memory 214260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2454263503 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_csr_rw.2454263503
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/11.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_intr_test.2879628035
Short name T1778
Test name
Test status
Simulation time 52464459 ps
CPU time 0.9 seconds
Started Oct 12 02:22:18 AM UTC 24
Finished Oct 12 02:22:21 AM UTC 24
Peak memory 214072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2879628035 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_intr_test.2879628035
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/11.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_tl_errors.2615864328
Short name T1783
Test name
Test status
Simulation time 72210841 ps
CPU time 2.05 seconds
Started Oct 12 02:22:18 AM UTC 24
Finished Oct 12 02:22:22 AM UTC 24
Peak memory 215120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2615864328 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_errors.2615864328
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/11.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/11.i2c_tl_intg_err.4045814988
Short name T1781
Test name
Test status
Simulation time 479262303 ps
CPU time 1.86 seconds
Started Oct 12 02:22:18 AM UTC 24
Finished Oct 12 02:22:22 AM UTC 24
Peak memory 213520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4045814988 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_intg_err.4045814988
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/11.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.2217379131
Short name T1786
Test name
Test status
Simulation time 67781309 ps
CPU time 1.18 seconds
Started Oct 12 02:22:21 AM UTC 24
Finished Oct 12 02:22:23 AM UTC 24
Peak memory 214264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=2217379131 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_csr_mem_rw_with_rand_reset.2217379131
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/12.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_csr_rw.1217564279
Short name T226
Test name
Test status
Simulation time 353497534 ps
CPU time 1.13 seconds
Started Oct 12 02:22:20 AM UTC 24
Finished Oct 12 02:22:22 AM UTC 24
Peak memory 214260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1217564279 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_csr_rw.1217564279
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/12.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_intr_test.226186683
Short name T1782
Test name
Test status
Simulation time 15248096 ps
CPU time 0.88 seconds
Started Oct 12 02:22:20 AM UTC 24
Finished Oct 12 02:22:22 AM UTC 24
Peak memory 214072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=226186683 -assert nopostproc +UVM_TESTNAME=i2c_base_tes
t +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_intr_test.226186683
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/12.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_same_csr_outstanding.3010441943
Short name T1785
Test name
Test status
Simulation time 53589049 ps
CPU time 1.02 seconds
Started Oct 12 02:22:21 AM UTC 24
Finished Oct 12 02:22:23 AM UTC 24
Peak memory 214324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3010441943 -assert nopostproc +UVM
_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_same_csr_outstanding.3010441943
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/12.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_tl_errors.1436424697
Short name T1787
Test name
Test status
Simulation time 252192934 ps
CPU time 3.16 seconds
Started Oct 12 02:22:20 AM UTC 24
Finished Oct 12 02:22:24 AM UTC 24
Peak memory 215372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1436424697 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_errors.1436424697
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/12.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_tl_intg_err.1876858663
Short name T206
Test name
Test status
Simulation time 99096781 ps
CPU time 1.6 seconds
Started Oct 12 02:22:20 AM UTC 24
Finished Oct 12 02:22:23 AM UTC 24
Peak memory 214216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1876858663 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_intg_err.1876858663
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/12.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.2156313950
Short name T1792
Test name
Test status
Simulation time 114498731 ps
CPU time 0.93 seconds
Started Oct 12 02:22:22 AM UTC 24
Finished Oct 12 02:22:25 AM UTC 24
Peak memory 214264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=2156313950 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_csr_mem_rw_with_rand_reset.2156313950
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/13.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_csr_rw.118534399
Short name T1791
Test name
Test status
Simulation time 50798705 ps
CPU time 1 seconds
Started Oct 12 02:22:22 AM UTC 24
Finished Oct 12 02:22:25 AM UTC 24
Peak memory 214264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=118534399 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_csr_rw.118534399
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/13.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_intr_test.3613084520
Short name T1789
Test name
Test status
Simulation time 15287568 ps
CPU time 0.94 seconds
Started Oct 12 02:22:22 AM UTC 24
Finished Oct 12 02:22:24 AM UTC 24
Peak memory 214072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3613084520 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_intr_test.3613084520
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/13.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_same_csr_outstanding.2729623237
Short name T1790
Test name
Test status
Simulation time 39439052 ps
CPU time 1.11 seconds
Started Oct 12 02:22:22 AM UTC 24
Finished Oct 12 02:22:25 AM UTC 24
Peak memory 214168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2729623237 -assert nopostproc +UVM
_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_same_csr_outstanding.2729623237
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/13.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_tl_errors.2205448454
Short name T1788
Test name
Test status
Simulation time 209541748 ps
CPU time 1.91 seconds
Started Oct 12 02:22:21 AM UTC 24
Finished Oct 12 02:22:24 AM UTC 24
Peak memory 214148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2205448454 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_errors.2205448454
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/13.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/13.i2c_tl_intg_err.3812307166
Short name T201
Test name
Test status
Simulation time 95550577 ps
CPU time 1.99 seconds
Started Oct 12 02:22:21 AM UTC 24
Finished Oct 12 02:22:24 AM UTC 24
Peak memory 214212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3812307166 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_intg_err.3812307166
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/13.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.3862378677
Short name T1798
Test name
Test status
Simulation time 96564270 ps
CPU time 1.89 seconds
Started Oct 12 02:22:24 AM UTC 24
Finished Oct 12 02:22:28 AM UTC 24
Peak memory 214216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3862378677 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_csr_mem_rw_with_rand_reset.3862378677
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/14.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_csr_rw.2580007450
Short name T225
Test name
Test status
Simulation time 24155874 ps
CPU time 0.91 seconds
Started Oct 12 02:22:24 AM UTC 24
Finished Oct 12 02:22:27 AM UTC 24
Peak memory 214048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2580007450 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_csr_rw.2580007450
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/14.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_intr_test.3617705674
Short name T1794
Test name
Test status
Simulation time 27044094 ps
CPU time 0.93 seconds
Started Oct 12 02:22:23 AM UTC 24
Finished Oct 12 02:22:27 AM UTC 24
Peak memory 214072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3617705674 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_intr_test.3617705674
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/14.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_same_csr_outstanding.3604386765
Short name T1795
Test name
Test status
Simulation time 38362540 ps
CPU time 1.24 seconds
Started Oct 12 02:22:24 AM UTC 24
Finished Oct 12 02:22:27 AM UTC 24
Peak memory 214000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3604386765 -assert nopostproc +UVM
_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_same_csr_outstanding.3604386765
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/14.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_tl_errors.306477897
Short name T1793
Test name
Test status
Simulation time 37787374 ps
CPU time 2.16 seconds
Started Oct 12 02:22:22 AM UTC 24
Finished Oct 12 02:22:26 AM UTC 24
Peak memory 215112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=306477897 -assert nopostproc +UVM_TESTNAME=i2c_base_tes
t +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_errors.306477897
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/14.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/14.i2c_tl_intg_err.1194964279
Short name T202
Test name
Test status
Simulation time 593688863 ps
CPU time 2.72 seconds
Started Oct 12 02:22:23 AM UTC 24
Finished Oct 12 02:22:28 AM UTC 24
Peak memory 214992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1194964279 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_intg_err.1194964279
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/14.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.2715265046
Short name T1801
Test name
Test status
Simulation time 415195165 ps
CPU time 1.17 seconds
Started Oct 12 02:22:26 AM UTC 24
Finished Oct 12 02:22:29 AM UTC 24
Peak memory 214224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=2715265046 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_csr_mem_rw_with_rand_reset.2715265046
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/15.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/15.i2c_csr_rw.1249069353
Short name T1797
Test name
Test status
Simulation time 17344932 ps
CPU time 1 seconds
Started Oct 12 02:22:25 AM UTC 24
Finished Oct 12 02:22:28 AM UTC 24
Peak memory 214260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1249069353 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_csr_rw.1249069353
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/15.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/15.i2c_intr_test.340237853
Short name T282
Test name
Test status
Simulation time 27057240 ps
CPU time 0.89 seconds
Started Oct 12 02:22:25 AM UTC 24
Finished Oct 12 02:22:28 AM UTC 24
Peak memory 214072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=340237853 -assert nopostproc +UVM_TESTNAME=i2c_base_tes
t +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_intr_test.340237853
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/15.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/15.i2c_same_csr_outstanding.1392487315
Short name T1799
Test name
Test status
Simulation time 95240325 ps
CPU time 1.1 seconds
Started Oct 12 02:22:25 AM UTC 24
Finished Oct 12 02:22:28 AM UTC 24
Peak memory 214324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1392487315 -assert nopostproc +UVM
_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_same_csr_outstanding.1392487315
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/15.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/15.i2c_tl_errors.3838019885
Short name T1796
Test name
Test status
Simulation time 512653619 ps
CPU time 1.52 seconds
Started Oct 12 02:22:24 AM UTC 24
Finished Oct 12 02:22:28 AM UTC 24
Peak memory 214156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3838019885 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_errors.3838019885
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/15.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.3517476037
Short name T1802
Test name
Test status
Simulation time 83993149 ps
CPU time 1.15 seconds
Started Oct 12 02:22:27 AM UTC 24
Finished Oct 12 02:22:30 AM UTC 24
Peak memory 214264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3517476037 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_csr_mem_rw_with_rand_reset.3517476037
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/16.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/16.i2c_csr_rw.1882863685
Short name T224
Test name
Test status
Simulation time 24098661 ps
CPU time 1.13 seconds
Started Oct 12 02:22:26 AM UTC 24
Finished Oct 12 02:22:29 AM UTC 24
Peak memory 214260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1882863685 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_csr_rw.1882863685
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/16.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/16.i2c_intr_test.1041656357
Short name T1800
Test name
Test status
Simulation time 16798782 ps
CPU time 1.01 seconds
Started Oct 12 02:22:26 AM UTC 24
Finished Oct 12 02:22:29 AM UTC 24
Peak memory 214072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1041656357 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_intr_test.1041656357
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/16.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/16.i2c_same_csr_outstanding.3941087993
Short name T1803
Test name
Test status
Simulation time 21773367 ps
CPU time 1.2 seconds
Started Oct 12 02:22:27 AM UTC 24
Finished Oct 12 02:22:30 AM UTC 24
Peak memory 214264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3941087993 -assert nopostproc +UVM
_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_same_csr_outstanding.3941087993
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/16.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/16.i2c_tl_errors.3583477153
Short name T1804
Test name
Test status
Simulation time 72972344 ps
CPU time 2.12 seconds
Started Oct 12 02:22:26 AM UTC 24
Finished Oct 12 02:22:30 AM UTC 24
Peak memory 215116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3583477153 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_errors.3583477153
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/16.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.2426719938
Short name T1810
Test name
Test status
Simulation time 526936141 ps
CPU time 1.19 seconds
Started Oct 12 02:22:29 AM UTC 24
Finished Oct 12 02:22:31 AM UTC 24
Peak memory 214264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=2426719938 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_csr_mem_rw_with_rand_reset.2426719938
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/17.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/17.i2c_csr_rw.3967705280
Short name T1807
Test name
Test status
Simulation time 38585932 ps
CPU time 1.13 seconds
Started Oct 12 02:22:29 AM UTC 24
Finished Oct 12 02:22:31 AM UTC 24
Peak memory 214260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3967705280 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_csr_rw.3967705280
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/17.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/17.i2c_intr_test.897059925
Short name T1806
Test name
Test status
Simulation time 17312657 ps
CPU time 1.02 seconds
Started Oct 12 02:22:29 AM UTC 24
Finished Oct 12 02:22:31 AM UTC 24
Peak memory 214016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=897059925 -assert nopostproc +UVM_TESTNAME=i2c_base_tes
t +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_intr_test.897059925
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/17.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/17.i2c_same_csr_outstanding.1918948995
Short name T1808
Test name
Test status
Simulation time 21471174 ps
CPU time 1.12 seconds
Started Oct 12 02:22:29 AM UTC 24
Finished Oct 12 02:22:31 AM UTC 24
Peak memory 214324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1918948995 -assert nopostproc +UVM
_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_same_csr_outstanding.1918948995
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/17.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/17.i2c_tl_errors.2545894484
Short name T1805
Test name
Test status
Simulation time 504601466 ps
CPU time 1.68 seconds
Started Oct 12 02:22:27 AM UTC 24
Finished Oct 12 02:22:30 AM UTC 24
Peak memory 214144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2545894484 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_errors.2545894484
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/17.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/17.i2c_tl_intg_err.3757941749
Short name T1809
Test name
Test status
Simulation time 70591703 ps
CPU time 1.52 seconds
Started Oct 12 02:22:28 AM UTC 24
Finished Oct 12 02:22:31 AM UTC 24
Peak memory 214144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3757941749 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_intg_err.3757941749
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/17.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.209581886
Short name T1814
Test name
Test status
Simulation time 27512597 ps
CPU time 1.56 seconds
Started Oct 12 02:22:30 AM UTC 24
Finished Oct 12 02:22:33 AM UTC 24
Peak memory 224308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=209581886 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_csr_mem_rw_with_rand_reset.209581886
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/18.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/18.i2c_csr_rw.1417468290
Short name T1812
Test name
Test status
Simulation time 22259288 ps
CPU time 1.11 seconds
Started Oct 12 02:22:30 AM UTC 24
Finished Oct 12 02:22:32 AM UTC 24
Peak memory 214260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1417468290 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_csr_rw.1417468290
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/18.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/18.i2c_intr_test.719417646
Short name T1811
Test name
Test status
Simulation time 24813571 ps
CPU time 0.99 seconds
Started Oct 12 02:22:30 AM UTC 24
Finished Oct 12 02:22:32 AM UTC 24
Peak memory 214072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=719417646 -assert nopostproc +UVM_TESTNAME=i2c_base_tes
t +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_intr_test.719417646
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/18.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/18.i2c_same_csr_outstanding.4097569771
Short name T1813
Test name
Test status
Simulation time 115592856 ps
CPU time 1.3 seconds
Started Oct 12 02:22:30 AM UTC 24
Finished Oct 12 02:22:32 AM UTC 24
Peak memory 214324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4097569771 -assert nopostproc +UVM
_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_same_csr_outstanding.4097569771
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/18.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/18.i2c_tl_errors.3536637971
Short name T1815
Test name
Test status
Simulation time 148598004 ps
CPU time 2.8 seconds
Started Oct 12 02:22:29 AM UTC 24
Finished Oct 12 02:22:33 AM UTC 24
Peak memory 215052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3536637971 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_errors.3536637971
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/18.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/18.i2c_tl_intg_err.1576475266
Short name T204
Test name
Test status
Simulation time 123361628 ps
CPU time 1.87 seconds
Started Oct 12 02:22:29 AM UTC 24
Finished Oct 12 02:22:32 AM UTC 24
Peak memory 214212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1576475266 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_intg_err.1576475266
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/18.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.4179373755
Short name T1820
Test name
Test status
Simulation time 79016683 ps
CPU time 1.18 seconds
Started Oct 12 02:22:31 AM UTC 24
Finished Oct 12 02:22:34 AM UTC 24
Peak memory 214264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=4179373755 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_csr_mem_rw_with_rand_reset.4179373755
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/19.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/19.i2c_csr_rw.1115752318
Short name T1818
Test name
Test status
Simulation time 34527580 ps
CPU time 1.08 seconds
Started Oct 12 02:22:31 AM UTC 24
Finished Oct 12 02:22:33 AM UTC 24
Peak memory 214260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1115752318 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_csr_rw.1115752318
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/19.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/19.i2c_intr_test.1997355558
Short name T1816
Test name
Test status
Simulation time 25287894 ps
CPU time 1.01 seconds
Started Oct 12 02:22:31 AM UTC 24
Finished Oct 12 02:22:33 AM UTC 24
Peak memory 214072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1997355558 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_intr_test.1997355558
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/19.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/19.i2c_same_csr_outstanding.1210680954
Short name T1819
Test name
Test status
Simulation time 34598784 ps
CPU time 1.23 seconds
Started Oct 12 02:22:31 AM UTC 24
Finished Oct 12 02:22:34 AM UTC 24
Peak memory 214324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1210680954 -assert nopostproc +UVM
_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_same_csr_outstanding.1210680954
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/19.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/19.i2c_tl_errors.98465748
Short name T1821
Test name
Test status
Simulation time 196837533 ps
CPU time 2.62 seconds
Started Oct 12 02:22:30 AM UTC 24
Finished Oct 12 02:22:34 AM UTC 24
Peak memory 215056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=98465748 -assert nopostproc +UVM_TESTNAME=i2c_base_test
+UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_errors.98465748
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/19.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/19.i2c_tl_intg_err.648579156
Short name T1828
Test name
Test status
Simulation time 85496470 ps
CPU time 2.75 seconds
Started Oct 12 02:22:31 AM UTC 24
Finished Oct 12 02:22:35 AM UTC 24
Peak memory 214924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=648579156 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
1/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_intg_err.648579156
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/19.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_aliasing.1305296299
Short name T218
Test name
Test status
Simulation time 91852361 ps
CPU time 1.51 seconds
Started Oct 12 02:22:04 AM UTC 24
Finished Oct 12 02:22:07 AM UTC 24
Peak memory 214272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1305296299 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_aliasing.1305296299
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/2.i2c_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_bit_bash.3678090393
Short name T1748
Test name
Test status
Simulation time 707158519 ps
CPU time 5.61 seconds
Started Oct 12 02:22:04 AM UTC 24
Finished Oct 12 02:22:11 AM UTC 24
Peak memory 214984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3678090393 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_bit_bash.3678090393
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/2.i2c_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_hw_reset.2030731011
Short name T216
Test name
Test status
Simulation time 21878628 ps
CPU time 1 seconds
Started Oct 12 02:22:04 AM UTC 24
Finished Oct 12 02:22:06 AM UTC 24
Peak memory 214260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2030731011 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_hw_reset.2030731011
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/2.i2c_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.228941115
Short name T211
Test name
Test status
Simulation time 72427748 ps
CPU time 1.73 seconds
Started Oct 12 02:22:04 AM UTC 24
Finished Oct 12 02:22:07 AM UTC 24
Peak memory 224308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=228941115 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_mem_rw_with_rand_reset.228941115
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/2.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_rw.44905884
Short name T217
Test name
Test status
Simulation time 58965398 ps
CPU time 0.92 seconds
Started Oct 12 02:22:04 AM UTC 24
Finished Oct 12 02:22:06 AM UTC 24
Peak memory 214264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=44905884 -assert nopostproc +UVM_TESTNAME=i2c_base_t
est +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-
vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_rw.44905884
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/2.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_intr_test.2266342736
Short name T281
Test name
Test status
Simulation time 28746400 ps
CPU time 0.9 seconds
Started Oct 12 02:22:03 AM UTC 24
Finished Oct 12 02:22:05 AM UTC 24
Peak memory 214072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2266342736 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_intr_test.2266342736
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/2.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_same_csr_outstanding.527027700
Short name T113
Test name
Test status
Simulation time 140644324 ps
CPU time 1.27 seconds
Started Oct 12 02:22:04 AM UTC 24
Finished Oct 12 02:22:07 AM UTC 24
Peak memory 214328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=527027700 -assert nopostproc +UVM_
TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_11/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_same_csr_outstanding.527027700
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/2.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_tl_intg_err.3258374227
Short name T112
Test name
Test status
Simulation time 78786188 ps
CPU time 1.75 seconds
Started Oct 12 02:22:03 AM UTC 24
Finished Oct 12 02:22:06 AM UTC 24
Peak memory 214216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3258374227 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_intg_err.3258374227
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/2.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/20.i2c_intr_test.396848891
Short name T1817
Test name
Test status
Simulation time 14667392 ps
CPU time 0.87 seconds
Started Oct 12 02:22:31 AM UTC 24
Finished Oct 12 02:22:33 AM UTC 24
Peak memory 214072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=396848891 -assert nopostproc +UVM_TESTNAME=i2c_base_tes
t +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.i2c_intr_test.396848891
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/20.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/21.i2c_intr_test.2906127578
Short name T1822
Test name
Test status
Simulation time 28849142 ps
CPU time 0.88 seconds
Started Oct 12 02:22:32 AM UTC 24
Finished Oct 12 02:22:34 AM UTC 24
Peak memory 214072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2906127578 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.i2c_intr_test.2906127578
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/21.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/22.i2c_intr_test.3766989292
Short name T1823
Test name
Test status
Simulation time 35471880 ps
CPU time 0.94 seconds
Started Oct 12 02:22:32 AM UTC 24
Finished Oct 12 02:22:34 AM UTC 24
Peak memory 214072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3766989292 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.i2c_intr_test.3766989292
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/22.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/23.i2c_intr_test.1229315643
Short name T1826
Test name
Test status
Simulation time 16581287 ps
CPU time 1.01 seconds
Started Oct 12 02:22:33 AM UTC 24
Finished Oct 12 02:22:35 AM UTC 24
Peak memory 214072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1229315643 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.i2c_intr_test.1229315643
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/23.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/24.i2c_intr_test.2966641496
Short name T1825
Test name
Test status
Simulation time 20729108 ps
CPU time 0.85 seconds
Started Oct 12 02:22:33 AM UTC 24
Finished Oct 12 02:22:35 AM UTC 24
Peak memory 214052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2966641496 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.i2c_intr_test.2966641496
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/24.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/25.i2c_intr_test.287762284
Short name T1824
Test name
Test status
Simulation time 19879827 ps
CPU time 0.84 seconds
Started Oct 12 02:22:33 AM UTC 24
Finished Oct 12 02:22:34 AM UTC 24
Peak memory 214072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=287762284 -assert nopostproc +UVM_TESTNAME=i2c_base_tes
t +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.i2c_intr_test.287762284
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/25.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/26.i2c_intr_test.2380168604
Short name T1827
Test name
Test status
Simulation time 16615510 ps
CPU time 0.87 seconds
Started Oct 12 02:22:33 AM UTC 24
Finished Oct 12 02:22:35 AM UTC 24
Peak memory 214072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2380168604 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.i2c_intr_test.2380168604
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/26.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/27.i2c_intr_test.2712186437
Short name T1833
Test name
Test status
Simulation time 18830614 ps
CPU time 0.99 seconds
Started Oct 12 02:22:34 AM UTC 24
Finished Oct 12 02:22:36 AM UTC 24
Peak memory 214000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2712186437 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.i2c_intr_test.2712186437
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/27.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/28.i2c_intr_test.408064724
Short name T1829
Test name
Test status
Simulation time 89961788 ps
CPU time 0.74 seconds
Started Oct 12 02:22:34 AM UTC 24
Finished Oct 12 02:22:36 AM UTC 24
Peak memory 214072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=408064724 -assert nopostproc +UVM_TESTNAME=i2c_base_tes
t +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.i2c_intr_test.408064724
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/28.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/29.i2c_intr_test.139200337
Short name T1831
Test name
Test status
Simulation time 38684763 ps
CPU time 0.98 seconds
Started Oct 12 02:22:34 AM UTC 24
Finished Oct 12 02:22:36 AM UTC 24
Peak memory 214072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=139200337 -assert nopostproc +UVM_TESTNAME=i2c_base_tes
t +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.i2c_intr_test.139200337
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/29.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_aliasing.3464316558
Short name T219
Test name
Test status
Simulation time 73902556 ps
CPU time 2.47 seconds
Started Oct 12 02:22:07 AM UTC 24
Finished Oct 12 02:22:10 AM UTC 24
Peak memory 214916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3464316558 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_aliasing.3464316558
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/3.i2c_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_bit_bash.1048832862
Short name T223
Test name
Test status
Simulation time 452133204 ps
CPU time 4.61 seconds
Started Oct 12 02:22:06 AM UTC 24
Finished Oct 12 02:22:11 AM UTC 24
Peak memory 214924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1048832862 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_bit_bash.1048832862
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/3.i2c_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_hw_reset.2064115075
Short name T151
Test name
Test status
Simulation time 64732803 ps
CPU time 1.01 seconds
Started Oct 12 02:22:06 AM UTC 24
Finished Oct 12 02:22:08 AM UTC 24
Peak memory 214196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2064115075 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_hw_reset.2064115075
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/3.i2c_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.859547389
Short name T212
Test name
Test status
Simulation time 30429548 ps
CPU time 1.1 seconds
Started Oct 12 02:22:07 AM UTC 24
Finished Oct 12 02:22:09 AM UTC 24
Peak memory 214196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=859547389 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_mem_rw_with_rand_reset.859547389
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/3.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_rw.4038789027
Short name T228
Test name
Test status
Simulation time 26073273 ps
CPU time 1.1 seconds
Started Oct 12 02:22:06 AM UTC 24
Finished Oct 12 02:22:08 AM UTC 24
Peak memory 214196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4038789027 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_rw.4038789027
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/3.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_intr_test.3233348544
Short name T1746
Test name
Test status
Simulation time 17822711 ps
CPU time 0.99 seconds
Started Oct 12 02:22:05 AM UTC 24
Finished Oct 12 02:22:08 AM UTC 24
Peak memory 214072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3233348544 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_intr_test.3233348544
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/3.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_same_csr_outstanding.3222114179
Short name T229
Test name
Test status
Simulation time 21553192 ps
CPU time 1.27 seconds
Started Oct 12 02:22:07 AM UTC 24
Finished Oct 12 02:22:09 AM UTC 24
Peak memory 214264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3222114179 -assert nopostproc +UVM
_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_same_csr_outstanding.3222114179
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/3.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_tl_errors.2362699617
Short name T196
Test name
Test status
Simulation time 32985535 ps
CPU time 2.16 seconds
Started Oct 12 02:22:05 AM UTC 24
Finished Oct 12 02:22:09 AM UTC 24
Peak memory 215304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2362699617 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_errors.2362699617
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/3.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_tl_intg_err.199303562
Short name T205
Test name
Test status
Simulation time 76271353 ps
CPU time 1.66 seconds
Started Oct 12 02:22:05 AM UTC 24
Finished Oct 12 02:22:08 AM UTC 24
Peak memory 214208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=199303562 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
1/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_intg_err.199303562
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/3.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/30.i2c_intr_test.3333852448
Short name T1830
Test name
Test status
Simulation time 19677510 ps
CPU time 0.85 seconds
Started Oct 12 02:22:34 AM UTC 24
Finished Oct 12 02:22:36 AM UTC 24
Peak memory 214072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3333852448 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.i2c_intr_test.3333852448
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/30.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/31.i2c_intr_test.895655941
Short name T1832
Test name
Test status
Simulation time 50101823 ps
CPU time 0.84 seconds
Started Oct 12 02:22:34 AM UTC 24
Finished Oct 12 02:22:36 AM UTC 24
Peak memory 214072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=895655941 -assert nopostproc +UVM_TESTNAME=i2c_base_tes
t +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.i2c_intr_test.895655941
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/31.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/32.i2c_intr_test.4031134954
Short name T1835
Test name
Test status
Simulation time 67811286 ps
CPU time 0.99 seconds
Started Oct 12 02:22:34 AM UTC 24
Finished Oct 12 02:22:36 AM UTC 24
Peak memory 214072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4031134954 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.i2c_intr_test.4031134954
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/32.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/33.i2c_intr_test.213653025
Short name T1834
Test name
Test status
Simulation time 30294308 ps
CPU time 0.84 seconds
Started Oct 12 02:22:34 AM UTC 24
Finished Oct 12 02:22:36 AM UTC 24
Peak memory 214072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=213653025 -assert nopostproc +UVM_TESTNAME=i2c_base_tes
t +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.i2c_intr_test.213653025
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/33.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/34.i2c_intr_test.485482565
Short name T1836
Test name
Test status
Simulation time 37940471 ps
CPU time 0.92 seconds
Started Oct 12 02:22:35 AM UTC 24
Finished Oct 12 02:22:37 AM UTC 24
Peak memory 213424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=485482565 -assert nopostproc +UVM_TESTNAME=i2c_base_tes
t +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.i2c_intr_test.485482565
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/34.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/35.i2c_intr_test.1106978357
Short name T1837
Test name
Test status
Simulation time 46721498 ps
CPU time 0.92 seconds
Started Oct 12 02:22:35 AM UTC 24
Finished Oct 12 02:22:37 AM UTC 24
Peak memory 214072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1106978357 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.i2c_intr_test.1106978357
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/35.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/36.i2c_intr_test.558601471
Short name T1842
Test name
Test status
Simulation time 19531302 ps
CPU time 1.02 seconds
Started Oct 12 02:22:35 AM UTC 24
Finished Oct 12 02:22:37 AM UTC 24
Peak memory 214072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=558601471 -assert nopostproc +UVM_TESTNAME=i2c_base_tes
t +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.i2c_intr_test.558601471
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/36.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/37.i2c_intr_test.2913240149
Short name T1841
Test name
Test status
Simulation time 45995476 ps
CPU time 0.98 seconds
Started Oct 12 02:22:35 AM UTC 24
Finished Oct 12 02:22:37 AM UTC 24
Peak memory 213932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2913240149 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.i2c_intr_test.2913240149
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/37.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/38.i2c_intr_test.1630462774
Short name T1839
Test name
Test status
Simulation time 17147218 ps
CPU time 0.97 seconds
Started Oct 12 02:22:35 AM UTC 24
Finished Oct 12 02:22:37 AM UTC 24
Peak memory 214072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1630462774 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.i2c_intr_test.1630462774
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/38.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/39.i2c_intr_test.3950764295
Short name T1838
Test name
Test status
Simulation time 26119167 ps
CPU time 0.87 seconds
Started Oct 12 02:22:35 AM UTC 24
Finished Oct 12 02:22:37 AM UTC 24
Peak memory 213820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3950764295 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.i2c_intr_test.3950764295
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/39.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_aliasing.1207514342
Short name T220
Test name
Test status
Simulation time 41230735 ps
CPU time 2.22 seconds
Started Oct 12 02:22:09 AM UTC 24
Finished Oct 12 02:22:13 AM UTC 24
Peak memory 214916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1207514342 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_aliasing.1207514342
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/4.i2c_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_bit_bash.1460431103
Short name T1750
Test name
Test status
Simulation time 1756953327 ps
CPU time 3.46 seconds
Started Oct 12 02:22:08 AM UTC 24
Finished Oct 12 02:22:13 AM UTC 24
Peak memory 214860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1460431103 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_bit_bash.1460431103
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/4.i2c_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_hw_reset.1943740784
Short name T127
Test name
Test status
Simulation time 77562738 ps
CPU time 1.07 seconds
Started Oct 12 02:22:08 AM UTC 24
Finished Oct 12 02:22:10 AM UTC 24
Peak memory 214260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1943740784 -assert nopostproc +UVM_TESTNAME=i2
c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_hw_reset.1943740784
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/4.i2c_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.4119495882
Short name T213
Test name
Test status
Simulation time 47270994 ps
CPU time 1.21 seconds
Started Oct 12 02:22:09 AM UTC 24
Finished Oct 12 02:22:12 AM UTC 24
Peak memory 214152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=4119495882 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_mem_rw_with_rand_reset.4119495882
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/4.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_rw.783840083
Short name T230
Test name
Test status
Simulation time 29985025 ps
CPU time 1.15 seconds
Started Oct 12 02:22:08 AM UTC 24
Finished Oct 12 02:22:10 AM UTC 24
Peak memory 214264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=783840083 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_rw.783840083
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/4.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_intr_test.2264441999
Short name T1747
Test name
Test status
Simulation time 37780640 ps
CPU time 0.95 seconds
Started Oct 12 02:22:08 AM UTC 24
Finished Oct 12 02:22:10 AM UTC 24
Peak memory 214072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2264441999 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_intr_test.2264441999
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/4.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_same_csr_outstanding.3272821341
Short name T231
Test name
Test status
Simulation time 58092373 ps
CPU time 1.32 seconds
Started Oct 12 02:22:09 AM UTC 24
Finished Oct 12 02:22:12 AM UTC 24
Peak memory 214224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3272821341 -assert nopostproc +UVM
_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_same_csr_outstanding.3272821341
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/4.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_tl_errors.1997546645
Short name T197
Test name
Test status
Simulation time 325511657 ps
CPU time 2.91 seconds
Started Oct 12 02:22:07 AM UTC 24
Finished Oct 12 02:22:11 AM UTC 24
Peak memory 215304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1997546645 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_errors.1997546645
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/4.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_tl_intg_err.506134642
Short name T195
Test name
Test status
Simulation time 260514688 ps
CPU time 1.76 seconds
Started Oct 12 02:22:08 AM UTC 24
Finished Oct 12 02:22:11 AM UTC 24
Peak memory 214208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=506134642 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1
1/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_intg_err.506134642
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/4.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/40.i2c_intr_test.4189032569
Short name T1840
Test name
Test status
Simulation time 17847677 ps
CPU time 0.8 seconds
Started Oct 12 02:22:35 AM UTC 24
Finished Oct 12 02:22:37 AM UTC 24
Peak memory 214072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4189032569 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.i2c_intr_test.4189032569
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/40.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/41.i2c_intr_test.2199086446
Short name T1843
Test name
Test status
Simulation time 24995150 ps
CPU time 0.78 seconds
Started Oct 12 02:22:35 AM UTC 24
Finished Oct 12 02:22:37 AM UTC 24
Peak memory 213844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2199086446 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.i2c_intr_test.2199086446
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/41.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/42.i2c_intr_test.3145422042
Short name T1844
Test name
Test status
Simulation time 53936168 ps
CPU time 0.77 seconds
Started Oct 12 02:22:35 AM UTC 24
Finished Oct 12 02:22:38 AM UTC 24
Peak memory 214196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3145422042 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.i2c_intr_test.3145422042
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/42.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/43.i2c_intr_test.589113623
Short name T1849
Test name
Test status
Simulation time 35263194 ps
CPU time 1.02 seconds
Started Oct 12 02:22:37 AM UTC 24
Finished Oct 12 02:22:39 AM UTC 24
Peak memory 213820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=589113623 -assert nopostproc +UVM_TESTNAME=i2c_base_tes
t +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.i2c_intr_test.589113623
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/43.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/44.i2c_intr_test.2198213646
Short name T1845
Test name
Test status
Simulation time 42763960 ps
CPU time 0.91 seconds
Started Oct 12 02:22:37 AM UTC 24
Finished Oct 12 02:22:39 AM UTC 24
Peak memory 214072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2198213646 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.i2c_intr_test.2198213646
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/44.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/45.i2c_intr_test.1625663552
Short name T1846
Test name
Test status
Simulation time 76577742 ps
CPU time 0.83 seconds
Started Oct 12 02:22:37 AM UTC 24
Finished Oct 12 02:22:39 AM UTC 24
Peak memory 213816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1625663552 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.i2c_intr_test.1625663552
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/45.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/46.i2c_intr_test.3363096038
Short name T1848
Test name
Test status
Simulation time 34172815 ps
CPU time 0.96 seconds
Started Oct 12 02:22:37 AM UTC 24
Finished Oct 12 02:22:39 AM UTC 24
Peak memory 214072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3363096038 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.i2c_intr_test.3363096038
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/46.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/47.i2c_intr_test.1622019643
Short name T1847
Test name
Test status
Simulation time 119995645 ps
CPU time 0.84 seconds
Started Oct 12 02:22:37 AM UTC 24
Finished Oct 12 02:22:39 AM UTC 24
Peak memory 214072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1622019643 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.i2c_intr_test.1622019643
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/47.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/48.i2c_intr_test.2566409185
Short name T1851
Test name
Test status
Simulation time 18014608 ps
CPU time 0.99 seconds
Started Oct 12 02:22:37 AM UTC 24
Finished Oct 12 02:22:39 AM UTC 24
Peak memory 214072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2566409185 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.i2c_intr_test.2566409185
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/48.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/49.i2c_intr_test.1222437447
Short name T1850
Test name
Test status
Simulation time 34545504 ps
CPU time 0.89 seconds
Started Oct 12 02:22:37 AM UTC 24
Finished Oct 12 02:22:39 AM UTC 24
Peak memory 214072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1222437447 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.i2c_intr_test.1222437447
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/49.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.2675524748
Short name T1752
Test name
Test status
Simulation time 26045448 ps
CPU time 1.69 seconds
Started Oct 12 02:22:11 AM UTC 24
Finished Oct 12 02:22:13 AM UTC 24
Peak memory 214152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=2675524748 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_csr_mem_rw_with_rand_reset.2675524748
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/5.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_csr_rw.3166885021
Short name T232
Test name
Test status
Simulation time 17040801 ps
CPU time 0.99 seconds
Started Oct 12 02:22:11 AM UTC 24
Finished Oct 12 02:22:13 AM UTC 24
Peak memory 214172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3166885021 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_csr_rw.3166885021
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/5.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_intr_test.2295190942
Short name T1749
Test name
Test status
Simulation time 27914971 ps
CPU time 0.96 seconds
Started Oct 12 02:22:11 AM UTC 24
Finished Oct 12 02:22:12 AM UTC 24
Peak memory 214072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2295190942 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_intr_test.2295190942
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/5.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_same_csr_outstanding.163180281
Short name T1751
Test name
Test status
Simulation time 56367246 ps
CPU time 1.46 seconds
Started Oct 12 02:22:11 AM UTC 24
Finished Oct 12 02:22:13 AM UTC 24
Peak memory 214220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=163180281 -assert nopostproc +UVM_
TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_11/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_same_csr_outstanding.163180281
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/5.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_tl_errors.1878313759
Short name T214
Test name
Test status
Simulation time 97478244 ps
CPU time 1.85 seconds
Started Oct 12 02:22:09 AM UTC 24
Finished Oct 12 02:22:12 AM UTC 24
Peak memory 214120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1878313759 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_errors.1878313759
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/5.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.3354769127
Short name T1760
Test name
Test status
Simulation time 37482799 ps
CPU time 1.39 seconds
Started Oct 12 02:22:13 AM UTC 24
Finished Oct 12 02:22:15 AM UTC 24
Peak memory 214196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3354769127 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_csr_mem_rw_with_rand_reset.3354769127
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/6.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_csr_rw.1621474884
Short name T1754
Test name
Test status
Simulation time 28880399 ps
CPU time 0.93 seconds
Started Oct 12 02:22:12 AM UTC 24
Finished Oct 12 02:22:14 AM UTC 24
Peak memory 214196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1621474884 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_csr_rw.1621474884
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/6.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_intr_test.1377576212
Short name T1753
Test name
Test status
Simulation time 33980050 ps
CPU time 0.96 seconds
Started Oct 12 02:22:12 AM UTC 24
Finished Oct 12 02:22:14 AM UTC 24
Peak memory 214072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1377576212 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_intr_test.1377576212
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/6.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_same_csr_outstanding.1623211553
Short name T1755
Test name
Test status
Simulation time 104404053 ps
CPU time 1.17 seconds
Started Oct 12 02:22:12 AM UTC 24
Finished Oct 12 02:22:14 AM UTC 24
Peak memory 214264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1623211553 -assert nopostproc +UVM
_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_same_csr_outstanding.1623211553
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/6.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_tl_errors.4252851787
Short name T1756
Test name
Test status
Simulation time 156958347 ps
CPU time 2.7 seconds
Started Oct 12 02:22:11 AM UTC 24
Finished Oct 12 02:22:14 AM UTC 24
Peak memory 215304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4252851787 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_errors.4252851787
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/6.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.4233552861
Short name T1759
Test name
Test status
Simulation time 35050695 ps
CPU time 1.03 seconds
Started Oct 12 02:22:13 AM UTC 24
Finished Oct 12 02:22:15 AM UTC 24
Peak memory 214200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=4233552861 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_csr_mem_rw_with_rand_reset.4233552861
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/7.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_csr_rw.995003482
Short name T221
Test name
Test status
Simulation time 26003569 ps
CPU time 0.96 seconds
Started Oct 12 02:22:13 AM UTC 24
Finished Oct 12 02:22:15 AM UTC 24
Peak memory 213956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=995003482 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_csr_rw.995003482
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/7.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_intr_test.2028940707
Short name T1757
Test name
Test status
Simulation time 19889488 ps
CPU time 1.01 seconds
Started Oct 12 02:22:13 AM UTC 24
Finished Oct 12 02:22:15 AM UTC 24
Peak memory 214072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2028940707 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_intr_test.2028940707
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/7.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_same_csr_outstanding.253678493
Short name T1758
Test name
Test status
Simulation time 148130614 ps
CPU time 0.98 seconds
Started Oct 12 02:22:13 AM UTC 24
Finished Oct 12 02:22:15 AM UTC 24
Peak memory 214328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=253678493 -assert nopostproc +UVM_
TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_11/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_same_csr_outstanding.253678493
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/7.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_tl_errors.644104588
Short name T1762
Test name
Test status
Simulation time 65957205 ps
CPU time 2.42 seconds
Started Oct 12 02:22:13 AM UTC 24
Finished Oct 12 02:22:17 AM UTC 24
Peak memory 215256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=644104588 -assert nopostproc +UVM_TESTNAME=i2c_base_tes
t +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_errors.644104588
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/7.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_tl_intg_err.1943223475
Short name T203
Test name
Test status
Simulation time 284948977 ps
CPU time 2.53 seconds
Started Oct 12 02:22:13 AM UTC 24
Finished Oct 12 02:22:17 AM UTC 24
Peak memory 214928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1943223475 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_intg_err.1943223475
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/7.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.3487010378
Short name T1767
Test name
Test status
Simulation time 41148275 ps
CPU time 1.07 seconds
Started Oct 12 02:22:16 AM UTC 24
Finished Oct 12 02:22:18 AM UTC 24
Peak memory 214200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3487010378 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_csr_mem_rw_with_rand_reset.3487010378
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/8.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_csr_rw.2687504143
Short name T222
Test name
Test status
Simulation time 20055402 ps
CPU time 1.08 seconds
Started Oct 12 02:22:15 AM UTC 24
Finished Oct 12 02:22:17 AM UTC 24
Peak memory 214260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2687504143 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_csr_rw.2687504143
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/8.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_intr_test.3218457036
Short name T1761
Test name
Test status
Simulation time 16209288 ps
CPU time 1.01 seconds
Started Oct 12 02:22:14 AM UTC 24
Finished Oct 12 02:22:16 AM UTC 24
Peak memory 214072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3218457036 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_intr_test.3218457036
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/8.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_same_csr_outstanding.657533916
Short name T1763
Test name
Test status
Simulation time 107101387 ps
CPU time 1.12 seconds
Started Oct 12 02:22:15 AM UTC 24
Finished Oct 12 02:22:17 AM UTC 24
Peak memory 214288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=657533916 -assert nopostproc +UVM_
TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_11/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_same_csr_outstanding.657533916
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/8.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_tl_errors.1109990890
Short name T1766
Test name
Test status
Simulation time 123132331 ps
CPU time 1.97 seconds
Started Oct 12 02:22:14 AM UTC 24
Finished Oct 12 02:22:17 AM UTC 24
Peak memory 214156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1109990890 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_errors.1109990890
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/8.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_tl_intg_err.2264340852
Short name T1764
Test name
Test status
Simulation time 83374035 ps
CPU time 1.77 seconds
Started Oct 12 02:22:14 AM UTC 24
Finished Oct 12 02:22:17 AM UTC 24
Peak memory 214280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2264340852 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_intg_err.2264340852
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/8.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.3679499437
Short name T1771
Test name
Test status
Simulation time 27730690 ps
CPU time 1.33 seconds
Started Oct 12 02:22:16 AM UTC 24
Finished Oct 12 02:22:18 AM UTC 24
Peak memory 224312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3679499437 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_csr_mem_rw_with_rand_reset.3679499437
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/9.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/9.i2c_csr_rw.3638391042
Short name T1769
Test name
Test status
Simulation time 20482918 ps
CPU time 1.09 seconds
Started Oct 12 02:22:16 AM UTC 24
Finished Oct 12 02:22:18 AM UTC 24
Peak memory 214196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3638391042 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_csr_rw.3638391042
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/9.i2c_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/9.i2c_intr_test.3222711142
Short name T1768
Test name
Test status
Simulation time 15963054 ps
CPU time 0.96 seconds
Started Oct 12 02:22:16 AM UTC 24
Finished Oct 12 02:22:18 AM UTC 24
Peak memory 214072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3222711142 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_intr_test.3222711142
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/9.i2c_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/9.i2c_same_csr_outstanding.2371124294
Short name T1770
Test name
Test status
Simulation time 116768550 ps
CPU time 1.13 seconds
Started Oct 12 02:22:16 AM UTC 24
Finished Oct 12 02:22:18 AM UTC 24
Peak memory 214264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2371124294 -assert nopostproc +UVM
_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_same_csr_outstanding.2371124294
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/9.i2c_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/9.i2c_tl_errors.2607205361
Short name T1772
Test name
Test status
Simulation time 228347736 ps
CPU time 1.77 seconds
Started Oct 12 02:22:16 AM UTC 24
Finished Oct 12 02:22:19 AM UTC 24
Peak memory 214208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2607205361 -assert nopostproc +UVM_TESTNAME=i2c_base_te
st +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-v
cs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_errors.2607205361
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/9.i2c_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/cover_reg_top/9.i2c_tl_intg_err.2225328842
Short name T1765
Test name
Test status
Simulation time 162589747 ps
CPU time 1.49 seconds
Started Oct 12 02:22:16 AM UTC 24
Finished Oct 12 02:22:18 AM UTC 24
Peak memory 214280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2225328842 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_
11/i2c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_intg_err.2225328842
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/9.i2c_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/0.i2c_host_fifo_fmt_empty.2044266256
Short name T5
Test name
Test status
Simulation time 488471111 ps
CPU time 10.92 seconds
Started Oct 12 05:53:15 AM UTC 24
Finished Oct 12 05:53:27 AM UTC 24
Peak memory 322696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2044266256 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_fmt_empty.2044266256
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/0.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/0.i2c_host_fifo_full.3975270267
Short name T36
Test name
Test status
Simulation time 3303945617 ps
CPU time 106 seconds
Started Oct 12 05:53:17 AM UTC 24
Finished Oct 12 05:55:05 AM UTC 24
Peak memory 758720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3975270267 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_full.3975270267
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/0.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/0.i2c_host_fifo_overflow.3930573720
Short name T39
Test name
Test status
Simulation time 2558649697 ps
CPU time 90.97 seconds
Started Oct 12 05:53:14 AM UTC 24
Finished Oct 12 05:54:47 AM UTC 24
Peak memory 429008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3930573720 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_overflow.3930573720
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/0.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/0.i2c_host_fifo_reset_rx.1550965284
Short name T3
Test name
Test status
Simulation time 314790145 ps
CPU time 5.45 seconds
Started Oct 12 05:53:15 AM UTC 24
Finished Oct 12 05:53:22 AM UTC 24
Peak memory 215448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1550965284 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_rx.1550965284
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/0.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/0.i2c_host_may_nack.4149158644
Short name T11
Test name
Test status
Simulation time 883824894 ps
CPU time 4.25 seconds
Started Oct 12 05:54:05 AM UTC 24
Finished Oct 12 05:54:11 AM UTC 24
Peak memory 215368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4149158644 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.i2c_host_may_nack.4149158644
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/0.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/0.i2c_host_override.3059172341
Short name T1
Test name
Test status
Simulation time 47960192 ps
CPU time 1.07 seconds
Started Oct 12 05:53:14 AM UTC 24
Finished Oct 12 05:53:16 AM UTC 24
Peak memory 214592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3059172341 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.i2c_host_override.3059172341
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/0.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/0.i2c_host_perf.2215174028
Short name T14
Test name
Test status
Simulation time 2469710384 ps
CPU time 63.49 seconds
Started Oct 12 05:53:17 AM UTC 24
Finished Oct 12 05:54:22 AM UTC 24
Peak memory 734220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2215174028 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 0.i2c_host_perf.2215174028
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/0.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/0.i2c_host_smoke.2630884229
Short name T9
Test name
Test status
Simulation time 1627660012 ps
CPU time 35.96 seconds
Started Oct 12 05:53:14 AM UTC 24
Finished Oct 12 05:53:51 AM UTC 24
Peak memory 429124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2630884229 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.i2c_host_smoke.2630884229
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/0.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/0.i2c_target_fifo_reset_acq.3499352710
Short name T75
Test name
Test status
Simulation time 500389110 ps
CPU time 1.33 seconds
Started Oct 12 05:53:54 AM UTC 24
Finished Oct 12 05:53:57 AM UTC 24
Peak memory 215632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3499352
710 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_fifo_reset_acq.3499352710
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/0.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/0.i2c_target_fifo_reset_tx.645216824
Short name T76
Test name
Test status
Simulation time 111617059 ps
CPU time 1.38 seconds
Started Oct 12 05:53:55 AM UTC 24
Finished Oct 12 05:53:58 AM UTC 24
Peak memory 213628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6452168
24 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_fifo_reset_tx.645216824
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/0.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/0.i2c_target_fifo_watermarks_tx.2042588827
Short name T74
Test name
Test status
Simulation time 310072943 ps
CPU time 2.09 seconds
Started Oct 12 05:54:09 AM UTC 24
Finished Oct 12 05:54:13 AM UTC 24
Peak memory 215448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2042588
827 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_fifo_watermarks
_tx.2042588827
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/0.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/0.i2c_target_intr_smoke.822459075
Short name T10
Test name
Test status
Simulation time 12984411623 ps
CPU time 15.1 seconds
Started Oct 12 05:53:37 AM UTC 24
Finished Oct 12 05:53:53 AM UTC 24
Peak memory 232400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=822459
075 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_intr_smoke.822459075
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/0.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/0.i2c_target_intr_stress_wr.596911502
Short name T46
Test name
Test status
Simulation time 22121679075 ps
CPU time 63.4 seconds
Started Oct 12 05:53:39 AM UTC 24
Finished Oct 12 05:54:44 AM UTC 24
Peak memory 1315788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=596911502 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_intr_stress_wr.596911502
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/0.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/0.i2c_target_nack_acqfull.2335571376
Short name T63
Test name
Test status
Simulation time 985223282 ps
CPU time 4.36 seconds
Started Oct 12 05:54:13 AM UTC 24
Finished Oct 12 05:54:18 AM UTC 24
Peak memory 225628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2335571
376 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_nack_acqfull.2335571376
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/0.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/0.i2c_target_perf.976654757
Short name T44
Test name
Test status
Simulation time 951671800 ps
CPU time 6.93 seconds
Started Oct 12 05:53:55 AM UTC 24
Finished Oct 12 05:54:03 AM UTC 24
Peak memory 225940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9766547
57 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_perf.976654757
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/0.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/0.i2c_target_smbus_maxlen.3429977794
Short name T162
Test name
Test status
Simulation time 452933789 ps
CPU time 3.37 seconds
Started Oct 12 05:54:11 AM UTC 24
Finished Oct 12 05:54:16 AM UTC 24
Peak memory 215244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3429977
794 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_smbus_maxlen.3429977794
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/0.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/0.i2c_target_smoke.3170401578
Short name T73
Test name
Test status
Simulation time 9686923486 ps
CPU time 49.26 seconds
Started Oct 12 05:53:19 AM UTC 24
Finished Oct 12 05:54:10 AM UTC 24
Peak memory 226212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3170401578 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_smoke.3170401578
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/0.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/0.i2c_target_stress_rd.3933139190
Short name T42
Test name
Test status
Simulation time 1878138811 ps
CPU time 26.33 seconds
Started Oct 12 05:53:27 AM UTC 24
Finished Oct 12 05:53:54 AM UTC 24
Peak memory 215392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3933139190 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_stress_rd.3933139190
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/0.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/0.i2c_target_stress_wr.2761236625
Short name T56
Test name
Test status
Simulation time 44802547329 ps
CPU time 163.36 seconds
Started Oct 12 05:53:23 AM UTC 24
Finished Oct 12 05:56:08 AM UTC 24
Peak memory 2392956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2761236625 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_stress_wr.2761236625
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/0.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/0.i2c_target_stretch.581721773
Short name T72
Test name
Test status
Simulation time 1629706976 ps
CPU time 35.09 seconds
Started Oct 12 05:53:28 AM UTC 24
Finished Oct 12 05:54:04 AM UTC 24
Peak memory 570552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=581721773 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_stretch.581721773
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/0.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/1.i2c_alert_test.3276619616
Short name T100
Test name
Test status
Simulation time 19315615 ps
CPU time 0.96 seconds
Started Oct 12 05:55:04 AM UTC 24
Finished Oct 12 05:55:06 AM UTC 24
Peak memory 213392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3276619616 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_alert_test.3276619616
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/1.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/1.i2c_host_error_intr.800162578
Short name T17
Test name
Test status
Simulation time 124174279 ps
CPU time 2.32 seconds
Started Oct 12 05:54:31 AM UTC 24
Finished Oct 12 05:54:34 AM UTC 24
Peak memory 226100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=800162578 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 1.i2c_host_error_intr.800162578
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/1.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/1.i2c_host_fifo_fmt_empty.609055739
Short name T41
Test name
Test status
Simulation time 1161978153 ps
CPU time 6.93 seconds
Started Oct 12 05:54:22 AM UTC 24
Finished Oct 12 05:54:30 AM UTC 24
Peak memory 271292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=609055739 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_fmt_empty.609055739
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/1.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/1.i2c_host_fifo_full.282742633
Short name T25
Test name
Test status
Simulation time 13726000122 ps
CPU time 127.26 seconds
Started Oct 12 05:54:24 AM UTC 24
Finished Oct 12 05:56:34 AM UTC 24
Peak memory 953276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=282742633 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_full.282742633
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/1.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/1.i2c_host_fifo_overflow.878642233
Short name T103
Test name
Test status
Simulation time 2704660616 ps
CPU time 64.05 seconds
Started Oct 12 05:54:20 AM UTC 24
Finished Oct 12 05:55:26 AM UTC 24
Peak memory 746832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=878642233 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_overflow.878642233
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/1.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/1.i2c_host_fifo_reset_fmt.749277617
Short name T31
Test name
Test status
Simulation time 164838668 ps
CPU time 1.47 seconds
Started Oct 12 05:54:21 AM UTC 24
Finished Oct 12 05:54:24 AM UTC 24
Peak memory 213268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=749277617 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_fmt.749277617
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/1.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/1.i2c_host_fifo_watermark.514617663
Short name T83
Test name
Test status
Simulation time 9238814677 ps
CPU time 216.11 seconds
Started Oct 12 05:54:19 AM UTC 24
Finished Oct 12 05:57:59 AM UTC 24
Peak memory 1117056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=514617663 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_watermark.514617663
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/1.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/1.i2c_host_override.1412238024
Short name T80
Test name
Test status
Simulation time 27642074 ps
CPU time 1.16 seconds
Started Oct 12 05:54:19 AM UTC 24
Finished Oct 12 05:54:21 AM UTC 24
Peak memory 213208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1412238024 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.i2c_host_override.1412238024
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/1.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/1.i2c_host_perf.2076682859
Short name T160
Test name
Test status
Simulation time 18781008271 ps
CPU time 332.74 seconds
Started Oct 12 05:54:26 AM UTC 24
Finished Oct 12 06:00:03 AM UTC 24
Peak memory 215640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2076682859 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 1.i2c_host_perf.2076682859
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/1.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/1.i2c_host_perf_precise.2063292661
Short name T124
Test name
Test status
Simulation time 2343284336 ps
CPU time 8 seconds
Started Oct 12 05:54:28 AM UTC 24
Finished Oct 12 05:54:37 AM UTC 24
Peak memory 215776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2063292661 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_perf_precise.2063292661
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/1.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/1.i2c_host_smoke.1221678467
Short name T28
Test name
Test status
Simulation time 2023071113 ps
CPU time 20.02 seconds
Started Oct 12 05:54:19 AM UTC 24
Finished Oct 12 05:54:40 AM UTC 24
Peak memory 279624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1221678467 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.i2c_host_smoke.1221678467
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/1.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/1.i2c_host_stretch_timeout.1739824045
Short name T125
Test name
Test status
Simulation time 3538396384 ps
CPU time 12.62 seconds
Started Oct 12 05:54:31 AM UTC 24
Finished Oct 12 05:54:45 AM UTC 24
Peak memory 228200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1739824045 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_stretch_timeout.1739824045
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/1.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/1.i2c_sec_cm.3340136110
Short name T190
Test name
Test status
Simulation time 164796386 ps
CPU time 1.32 seconds
Started Oct 12 05:55:04 AM UTC 24
Finished Oct 12 05:55:07 AM UTC 24
Peak memory 244936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3340136110 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_sec_cm.3340136110
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/1.i2c_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/1.i2c_target_bad_addr.3448238875
Short name T66
Test name
Test status
Simulation time 7612571517 ps
CPU time 8.26 seconds
Started Oct 12 05:54:51 AM UTC 24
Finished Oct 12 05:55:00 AM UTC 24
Peak memory 232656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=3448238875 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_bad_addr.3448238875
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/1.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/1.i2c_target_fifo_reset_acq.1703442736
Short name T238
Test name
Test status
Simulation time 155426572 ps
CPU time 1.55 seconds
Started Oct 12 05:54:48 AM UTC 24
Finished Oct 12 05:54:50 AM UTC 24
Peak memory 215512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1703442
736 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_fifo_reset_acq.1703442736
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/1.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/1.i2c_target_fifo_reset_tx.3887869967
Short name T293
Test name
Test status
Simulation time 361837684 ps
CPU time 2.25 seconds
Started Oct 12 05:54:48 AM UTC 24
Finished Oct 12 05:54:51 AM UTC 24
Peak memory 215396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3887869
967 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_fifo_reset_tx.3887869967
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/1.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/1.i2c_target_fifo_watermarks_acq.3345616654
Short name T215
Test name
Test status
Simulation time 527415337 ps
CPU time 3.29 seconds
Started Oct 12 05:54:58 AM UTC 24
Finished Oct 12 05:55:03 AM UTC 24
Peak memory 215716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3345616
654 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_fifo_watermark
s_acq.3345616654
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/1.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/1.i2c_target_fifo_watermarks_tx.3503557118
Short name T298
Test name
Test status
Simulation time 149056669 ps
CPU time 2.04 seconds
Started Oct 12 05:55:01 AM UTC 24
Finished Oct 12 05:55:04 AM UTC 24
Peak memory 215184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3503557
118 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_fifo_watermarks
_tx.3503557118
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/1.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/1.i2c_target_glitch.4266426918
Short name T51
Test name
Test status
Simulation time 7544677500 ps
CPU time 12.64 seconds
Started Oct 12 05:54:32 AM UTC 24
Finished Oct 12 05:54:46 AM UTC 24
Peak memory 226536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4266426918 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_glitch.4266426918
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/1.i2c_target_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/1.i2c_target_intr_smoke.3287142867
Short name T294
Test name
Test status
Simulation time 4069800354 ps
CPU time 7.67 seconds
Started Oct 12 05:54:42 AM UTC 24
Finished Oct 12 05:54:51 AM UTC 24
Peak memory 226056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=328714
2867 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_intr_smoke.3287142867
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/1.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/1.i2c_target_intr_stress_wr.2094502721
Short name T314
Test name
Test status
Simulation time 8876199042 ps
CPU time 95.82 seconds
Started Oct 12 05:54:45 AM UTC 24
Finished Oct 12 05:56:23 AM UTC 24
Peak memory 2296772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2094502721 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_intr_stress
_wr.2094502721
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/1.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/1.i2c_target_nack_acqfull.4229170513
Short name T154
Test name
Test status
Simulation time 455753428 ps
CPU time 4.54 seconds
Started Oct 12 05:55:03 AM UTC 24
Finished Oct 12 05:55:09 AM UTC 24
Peak memory 225632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4229170
513 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_nack_acqfull.4229170513
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/1.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/1.i2c_target_nack_acqfull_addr.2748321045
Short name T65
Test name
Test status
Simulation time 1929435368 ps
CPU time 3.26 seconds
Started Oct 12 05:55:04 AM UTC 24
Finished Oct 12 05:55:08 AM UTC 24
Peak memory 215412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2748321
045 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_nack_acqfull_addr.2748321045
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/1.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/1.i2c_target_perf.1658590413
Short name T295
Test name
Test status
Simulation time 2380158018 ps
CPU time 6.83 seconds
Started Oct 12 05:54:50 AM UTC 24
Finished Oct 12 05:54:58 AM UTC 24
Peak memory 232324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1658590
413 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_perf.1658590413
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/1.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/1.i2c_target_smbus_maxlen.398312381
Short name T299
Test name
Test status
Simulation time 1726199110 ps
CPU time 3.31 seconds
Started Oct 12 05:55:02 AM UTC 24
Finished Oct 12 05:55:06 AM UTC 24
Peak memory 215176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3983123
81 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_smbus_maxlen.398312381
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/1.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/1.i2c_target_smoke.1110093296
Short name T126
Test name
Test status
Simulation time 806859176 ps
CPU time 13.76 seconds
Started Oct 12 05:54:34 AM UTC 24
Finished Oct 12 05:54:49 AM UTC 24
Peak memory 232340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1110093296 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_smoke.1110093296
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/1.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/1.i2c_target_stress_all.2106418969
Short name T237
Test name
Test status
Simulation time 15255538360 ps
CPU time 62.66 seconds
Started Oct 12 05:54:51 AM UTC 24
Finished Oct 12 05:55:55 AM UTC 24
Peak memory 242568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=210641
8969 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_stress_all.2106418969
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/1.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/1.i2c_target_stress_rd.1431755800
Short name T297
Test name
Test status
Simulation time 1049322210 ps
CPU time 24.24 seconds
Started Oct 12 05:54:37 AM UTC 24
Finished Oct 12 05:55:03 AM UTC 24
Peak memory 232640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1431755800 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_stress_rd.1431755800
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/1.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/1.i2c_target_stress_wr.1674129728
Short name T290
Test name
Test status
Simulation time 21753992987 ps
CPU time 20.38 seconds
Started Oct 12 05:54:35 AM UTC 24
Finished Oct 12 05:54:57 AM UTC 24
Peak memory 226248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1674129728 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_stress_wr.1674129728
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/1.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/1.i2c_target_stretch.1232800363
Short name T170
Test name
Test status
Simulation time 3823215600 ps
CPU time 39.92 seconds
Started Oct 12 05:54:42 AM UTC 24
Finished Oct 12 05:55:23 AM UTC 24
Peak memory 426952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1232800363 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_stretch.1232800363
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/1.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/1.i2c_target_timeout.4178814120
Short name T78
Test name
Test status
Simulation time 1241673535 ps
CPU time 10.49 seconds
Started Oct 12 05:54:46 AM UTC 24
Finished Oct 12 05:54:58 AM UTC 24
Peak memory 242188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4178814
120 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_timeout.4178814120
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/1.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/1.i2c_target_tx_stretch_ctrl.1423939744
Short name T71
Test name
Test status
Simulation time 519516703 ps
CPU time 7.36 seconds
Started Oct 12 05:55:02 AM UTC 24
Finished Oct 12 05:55:10 AM UTC 24
Peak memory 215468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1423939
744 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_tx_stretch_ctrl.1423939744
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/1.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/10.i2c_alert_test.2344869697
Short name T470
Test name
Test status
Simulation time 51539768 ps
CPU time 1 seconds
Started Oct 12 06:02:37 AM UTC 24
Finished Oct 12 06:02:40 AM UTC 24
Peak memory 215628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2344869697 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_alert_test.2344869697
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/10.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/10.i2c_host_error_intr.4205219807
Short name T406
Test name
Test status
Simulation time 302664528 ps
CPU time 1.96 seconds
Started Oct 12 06:01:55 AM UTC 24
Finished Oct 12 06:01:58 AM UTC 24
Peak memory 225392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4205219807 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 10.i2c_host_error_intr.4205219807
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/10.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/10.i2c_host_fifo_fmt_empty.4041217036
Short name T449
Test name
Test status
Simulation time 948145567 ps
CPU time 7.2 seconds
Started Oct 12 06:01:49 AM UTC 24
Finished Oct 12 06:01:57 AM UTC 24
Peak memory 265352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4041217036 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_fmt_empty.4041217036
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/10.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/10.i2c_host_fifo_full.3675030216
Short name T486
Test name
Test status
Simulation time 2317682723 ps
CPU time 60.66 seconds
Started Oct 12 06:01:51 AM UTC 24
Finished Oct 12 06:02:53 AM UTC 24
Peak memory 390456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3675030216 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_full.3675030216
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/10.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/10.i2c_host_fifo_overflow.2149829841
Short name T482
Test name
Test status
Simulation time 34691782602 ps
CPU time 60.05 seconds
Started Oct 12 06:01:48 AM UTC 24
Finished Oct 12 06:02:49 AM UTC 24
Peak memory 621640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2149829841 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_overflow.2149829841
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/10.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/10.i2c_host_fifo_reset_fmt.3027422783
Short name T453
Test name
Test status
Simulation time 123250827 ps
CPU time 1.88 seconds
Started Oct 12 06:01:49 AM UTC 24
Finished Oct 12 06:01:52 AM UTC 24
Peak memory 213332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3027422783 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_fmt.3027422783
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/10.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/10.i2c_host_fifo_reset_rx.597948316
Short name T452
Test name
Test status
Simulation time 599933185 ps
CPU time 4.88 seconds
Started Oct 12 06:01:49 AM UTC 24
Finished Oct 12 06:01:55 AM UTC 24
Peak memory 244864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=597948316 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_rx.597948316
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/10.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/10.i2c_host_fifo_watermark.3434297085
Short name T647
Test name
Test status
Simulation time 97970796899 ps
CPU time 292.2 seconds
Started Oct 12 06:01:48 AM UTC 24
Finished Oct 12 06:06:44 AM UTC 24
Peak memory 1430796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3434297085 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_watermark.3434297085
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/10.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/10.i2c_host_may_nack.2339924131
Short name T478
Test name
Test status
Simulation time 777849029 ps
CPU time 14.34 seconds
Started Oct 12 06:02:32 AM UTC 24
Finished Oct 12 06:02:47 AM UTC 24
Peak memory 215444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2339924131 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.i2c_host_may_nack.2339924131
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/10.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/10.i2c_host_override.1897917783
Short name T139
Test name
Test status
Simulation time 45088195 ps
CPU time 0.98 seconds
Started Oct 12 06:01:48 AM UTC 24
Finished Oct 12 06:01:50 AM UTC 24
Peak memory 213212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1897917783 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.i2c_host_override.1897917783
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/10.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/10.i2c_host_perf.996852962
Short name T593
Test name
Test status
Simulation time 76154882727 ps
CPU time 225.95 seconds
Started Oct 12 06:01:52 AM UTC 24
Finished Oct 12 06:05:42 AM UTC 24
Peak memory 215432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=996852962 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 10.i2c_host_perf.996852962
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/10.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/10.i2c_host_perf_precise.3323327705
Short name T458
Test name
Test status
Simulation time 2337729442 ps
CPU time 31.35 seconds
Started Oct 12 06:01:52 AM UTC 24
Finished Oct 12 06:02:25 AM UTC 24
Peak memory 226096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3323327705 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_perf_precise.3323327705
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/10.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/10.i2c_host_stretch_timeout.140168267
Short name T462
Test name
Test status
Simulation time 3522379643 ps
CPU time 36.89 seconds
Started Oct 12 06:01:52 AM UTC 24
Finished Oct 12 06:02:31 AM UTC 24
Peak memory 225888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=140168267 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_stretch_timeout.140168267
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/10.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/10.i2c_target_bad_addr.3839567981
Short name T287
Test name
Test status
Simulation time 4697550435 ps
CPU time 5.85 seconds
Started Oct 12 06:02:30 AM UTC 24
Finished Oct 12 06:02:37 AM UTC 24
Peak memory 219628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=3839567981 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_bad_ad
dr.3839567981
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/10.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/10.i2c_target_fifo_reset_acq.2091812591
Short name T461
Test name
Test status
Simulation time 229464140 ps
CPU time 2.88 seconds
Started Oct 12 06:02:25 AM UTC 24
Finished Oct 12 06:02:29 AM UTC 24
Peak memory 215256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2091812
591 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_fifo_reset_acq.2091812591
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/10.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/10.i2c_target_fifo_reset_tx.2028064129
Short name T460
Test name
Test status
Simulation time 462095295 ps
CPU time 1.36 seconds
Started Oct 12 06:02:26 AM UTC 24
Finished Oct 12 06:02:29 AM UTC 24
Peak memory 215576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2028064
129 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_fifo_reset_tx.2028064129
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/10.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/10.i2c_target_fifo_watermarks_acq.2413604283
Short name T468
Test name
Test status
Simulation time 720945592 ps
CPU time 3.54 seconds
Started Oct 12 06:02:32 AM UTC 24
Finished Oct 12 06:02:37 AM UTC 24
Peak memory 215240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2413604
283 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_fifo_watermar
ks_acq.2413604283
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/10.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/10.i2c_target_fifo_watermarks_tx.3290108080
Short name T169
Test name
Test status
Simulation time 917302096 ps
CPU time 1.66 seconds
Started Oct 12 06:02:34 AM UTC 24
Finished Oct 12 06:02:37 AM UTC 24
Peak memory 215572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3290108
080 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_fifo_watermark
s_tx.3290108080
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/10.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/10.i2c_target_intr_smoke.2596909889
Short name T457
Test name
Test status
Simulation time 1049875791 ps
CPU time 9.48 seconds
Started Oct 12 06:02:11 AM UTC 24
Finished Oct 12 06:02:22 AM UTC 24
Peak memory 232320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=259690
9889 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_intr_smoke.2596909889
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/10.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/10.i2c_target_intr_stress_wr.2413126521
Short name T134
Test name
Test status
Simulation time 21774200892 ps
CPU time 54.96 seconds
Started Oct 12 06:02:20 AM UTC 24
Finished Oct 12 06:03:17 AM UTC 24
Peak memory 937284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2413126521 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_intr_stres
s_wr.2413126521
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/10.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/10.i2c_target_nack_acqfull.3250153518
Short name T55
Test name
Test status
Simulation time 557320137 ps
CPU time 5.63 seconds
Started Oct 12 06:02:37 AM UTC 24
Finished Oct 12 06:02:44 AM UTC 24
Peak memory 225968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3250153
518 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_nack_acqfull.3250153518
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/10.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/10.i2c_target_nack_acqfull_addr.2236973285
Short name T474
Test name
Test status
Simulation time 2904864005 ps
CPU time 3.98 seconds
Started Oct 12 06:02:37 AM UTC 24
Finished Oct 12 06:02:43 AM UTC 24
Peak memory 215552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2236973
285 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_nack_acqfull_ad
dr.2236973285
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/10.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/10.i2c_target_nack_txstretch.3021181816
Short name T471
Test name
Test status
Simulation time 553135511 ps
CPU time 2.15 seconds
Started Oct 12 06:02:37 AM UTC 24
Finished Oct 12 06:02:41 AM UTC 24
Peak memory 232380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3021181
816 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_nack_txstretch.3021181816
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/10.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/10.i2c_target_perf.1057262315
Short name T466
Test name
Test status
Simulation time 560124368 ps
CPU time 6.23 seconds
Started Oct 12 06:02:28 AM UTC 24
Finished Oct 12 06:02:36 AM UTC 24
Peak memory 229728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1057262
315 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_perf.1057262315
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/10.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/10.i2c_target_smbus_maxlen.3284493439
Short name T472
Test name
Test status
Simulation time 1170149091 ps
CPU time 2.6 seconds
Started Oct 12 06:02:37 AM UTC 24
Finished Oct 12 06:02:41 AM UTC 24
Peak memory 215176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3284493
439 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_smbus_maxlen.3284493439
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/10.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/10.i2c_target_smoke.1817686328
Short name T463
Test name
Test status
Simulation time 864425245 ps
CPU time 31.53 seconds
Started Oct 12 06:01:58 AM UTC 24
Finished Oct 12 06:02:31 AM UTC 24
Peak memory 225768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1817686328 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_smoke.1817686328
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/10.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/10.i2c_target_stress_all.3788072049
Short name T210
Test name
Test status
Simulation time 66104028639 ps
CPU time 134.05 seconds
Started Oct 12 06:02:30 AM UTC 24
Finished Oct 12 06:04:46 AM UTC 24
Peak memory 1328076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=378807
2049 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_stress_all.3788072049
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/10.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/10.i2c_target_stress_rd.2180510681
Short name T455
Test name
Test status
Simulation time 185517754 ps
CPU time 4.7 seconds
Started Oct 12 06:02:05 AM UTC 24
Finished Oct 12 06:02:10 AM UTC 24
Peak memory 215464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2180510681 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_stress_rd.2180510681
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/10.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/10.i2c_target_stress_wr.4132726286
Short name T572
Test name
Test status
Simulation time 58057858398 ps
CPU time 170.31 seconds
Started Oct 12 06:02:00 AM UTC 24
Finished Oct 12 06:04:53 AM UTC 24
Peak memory 2544568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4132726286 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_stress_wr.4132726286
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/10.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/10.i2c_target_stretch.2317179805
Short name T477
Test name
Test status
Simulation time 905279870 ps
CPU time 36.12 seconds
Started Oct 12 06:02:09 AM UTC 24
Finished Oct 12 06:02:46 AM UTC 24
Peak memory 353148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2317179805 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_stretch.2317179805
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/10.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/10.i2c_target_timeout.4011234948
Short name T464
Test name
Test status
Simulation time 3477941939 ps
CPU time 7.5 seconds
Started Oct 12 06:02:22 AM UTC 24
Finished Oct 12 06:02:31 AM UTC 24
Peak memory 232164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4011234
948 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_timeout.4011234948
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/10.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/10.i2c_target_tx_stretch_ctrl.3496742381
Short name T475
Test name
Test status
Simulation time 261004982 ps
CPU time 5.32 seconds
Started Oct 12 06:02:36 AM UTC 24
Finished Oct 12 06:02:43 AM UTC 24
Peak memory 215720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3496742
381 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_target_tx_stretch_ctrl.3496742381
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/10.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/11.i2c_alert_test.954850407
Short name T502
Test name
Test status
Simulation time 16969168 ps
CPU time 0.96 seconds
Started Oct 12 06:03:06 AM UTC 24
Finished Oct 12 06:03:08 AM UTC 24
Peak memory 215628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=954850407 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_alert_test.954850407
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/11.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/11.i2c_host_error_intr.902251701
Short name T481
Test name
Test status
Simulation time 366415222 ps
CPU time 2.96 seconds
Started Oct 12 06:02:45 AM UTC 24
Finished Oct 12 06:02:49 AM UTC 24
Peak memory 227952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=902251701 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 11.i2c_host_error_intr.902251701
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/11.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/11.i2c_host_fifo_fmt_empty.2393267313
Short name T483
Test name
Test status
Simulation time 1257487974 ps
CPU time 6.54 seconds
Started Oct 12 06:02:42 AM UTC 24
Finished Oct 12 06:02:50 AM UTC 24
Peak memory 269444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2393267313 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_fmt_empty.2393267313
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/11.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/11.i2c_host_fifo_full.2966864107
Short name T561
Test name
Test status
Simulation time 1807183975 ps
CPU time 97.53 seconds
Started Oct 12 06:02:43 AM UTC 24
Finished Oct 12 06:04:23 AM UTC 24
Peak memory 347072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2966864107 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_full.2966864107
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/11.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/11.i2c_host_fifo_overflow.2022086302
Short name T533
Test name
Test status
Simulation time 25126100875 ps
CPU time 69.49 seconds
Started Oct 12 06:02:41 AM UTC 24
Finished Oct 12 06:03:52 AM UTC 24
Peak memory 673032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2022086302 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_overflow.2022086302
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/11.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/11.i2c_host_fifo_reset_fmt.1413895858
Short name T476
Test name
Test status
Simulation time 65644185 ps
CPU time 1.32 seconds
Started Oct 12 06:02:42 AM UTC 24
Finished Oct 12 06:02:44 AM UTC 24
Peak memory 213332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1413895858 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_fmt.1413895858
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/11.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/11.i2c_host_fifo_reset_rx.3707772759
Short name T484
Test name
Test status
Simulation time 155427397 ps
CPU time 5.3 seconds
Started Oct 12 06:02:43 AM UTC 24
Finished Oct 12 06:02:50 AM UTC 24
Peak memory 240460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3707772759 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_rx.3707772759
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/11.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/11.i2c_host_fifo_watermark.2971688807
Short name T574
Test name
Test status
Simulation time 40072946860 ps
CPU time 131.92 seconds
Started Oct 12 06:02:40 AM UTC 24
Finished Oct 12 06:04:54 AM UTC 24
Peak memory 1445120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2971688807 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_watermark.2971688807
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/11.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/11.i2c_host_may_nack.372361638
Short name T256
Test name
Test status
Simulation time 6696694437 ps
CPU time 8.17 seconds
Started Oct 12 06:02:58 AM UTC 24
Finished Oct 12 06:03:08 AM UTC 24
Peak memory 215532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=372361638 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 11.i2c_host_may_nack.372361638
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/11.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/11.i2c_host_mode_toggle.2010617613
Short name T500
Test name
Test status
Simulation time 131674077 ps
CPU time 6.21 seconds
Started Oct 12 06:02:58 AM UTC 24
Finished Oct 12 06:03:05 AM UTC 24
Peak memory 249168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2010617613 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_mode_toggle.2010617613
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/11.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/11.i2c_host_override.1164298196
Short name T473
Test name
Test status
Simulation time 105928473 ps
CPU time 1.04 seconds
Started Oct 12 06:02:40 AM UTC 24
Finished Oct 12 06:02:42 AM UTC 24
Peak memory 213212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1164298196 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.i2c_host_override.1164298196
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/11.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/11.i2c_host_perf.2960130627
Short name T131
Test name
Test status
Simulation time 12315682094 ps
CPU time 50.83 seconds
Started Oct 12 06:02:44 AM UTC 24
Finished Oct 12 06:03:36 AM UTC 24
Peak memory 232728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2960130627 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 11.i2c_host_perf.2960130627
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/11.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/11.i2c_host_perf_precise.317680262
Short name T480
Test name
Test status
Simulation time 81341892 ps
CPU time 3.73 seconds
Started Oct 12 06:02:44 AM UTC 24
Finished Oct 12 06:02:48 AM UTC 24
Peak memory 215384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=317680262 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_perf_precise.317680262
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/11.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/11.i2c_host_smoke.158646884
Short name T513
Test name
Test status
Simulation time 1250493269 ps
CPU time 52.8 seconds
Started Oct 12 06:02:38 AM UTC 24
Finished Oct 12 06:03:32 AM UTC 24
Peak memory 330612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=158646884 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 11.i2c_host_smoke.158646884
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/11.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/11.i2c_host_stretch_timeout.2698488334
Short name T491
Test name
Test status
Simulation time 568990425 ps
CPU time 11.31 seconds
Started Oct 12 06:02:45 AM UTC 24
Finished Oct 12 06:02:57 AM UTC 24
Peak memory 225636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2698488334 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_stretch_timeout.2698488334
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/11.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/11.i2c_target_bad_addr.273119838
Short name T496
Test name
Test status
Simulation time 819797982 ps
CPU time 6.04 seconds
Started Oct 12 06:02:57 AM UTC 24
Finished Oct 12 06:03:04 AM UTC 24
Peak memory 228016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=273119838 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_bad_addr.273119838
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/11.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/11.i2c_target_fifo_reset_acq.3839700817
Short name T489
Test name
Test status
Simulation time 276194282 ps
CPU time 1.58 seconds
Started Oct 12 06:02:54 AM UTC 24
Finished Oct 12 06:02:56 AM UTC 24
Peak memory 215636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3839700
817 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_fifo_reset_acq.3839700817
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/11.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/11.i2c_target_fifo_reset_tx.93369718
Short name T490
Test name
Test status
Simulation time 176330480 ps
CPU time 1.82 seconds
Started Oct 12 06:02:54 AM UTC 24
Finished Oct 12 06:02:57 AM UTC 24
Peak memory 215640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9336971
8 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_fifo_reset_tx.93369718
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/11.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/11.i2c_target_fifo_watermarks_acq.3651033647
Short name T497
Test name
Test status
Simulation time 2161592133 ps
CPU time 4.8 seconds
Started Oct 12 06:02:58 AM UTC 24
Finished Oct 12 06:03:04 AM UTC 24
Peak memory 215460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3651033
647 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_fifo_watermar
ks_acq.3651033647
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/11.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/11.i2c_target_fifo_watermarks_tx.1991869959
Short name T499
Test name
Test status
Simulation time 359564122 ps
CPU time 1.41 seconds
Started Oct 12 06:03:02 AM UTC 24
Finished Oct 12 06:03:05 AM UTC 24
Peak memory 213628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1991869
959 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_fifo_watermark
s_tx.1991869959
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/11.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/11.i2c_target_hrst.56903369
Short name T493
Test name
Test status
Simulation time 5126866241 ps
CPU time 3.59 seconds
Started Oct 12 06:02:57 AM UTC 24
Finished Oct 12 06:03:02 AM UTC 24
Peak memory 226084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5690336
9 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_hrst.56903369
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/11.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/11.i2c_target_intr_smoke.2159976523
Short name T492
Test name
Test status
Simulation time 2661877357 ps
CPU time 6.68 seconds
Started Oct 12 06:02:49 AM UTC 24
Finished Oct 12 06:02:57 AM UTC 24
Peak memory 225828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=215997
6523 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_intr_smoke.2159976523
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/11.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/11.i2c_target_intr_stress_wr.3150487204
Short name T488
Test name
Test status
Simulation time 306521301 ps
CPU time 3.39 seconds
Started Oct 12 06:02:50 AM UTC 24
Finished Oct 12 06:02:55 AM UTC 24
Peak memory 215432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3150487204 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_intr_stres
s_wr.3150487204
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/11.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/11.i2c_target_nack_acqfull.1040570856
Short name T130
Test name
Test status
Simulation time 1251730489 ps
CPU time 5.64 seconds
Started Oct 12 06:03:05 AM UTC 24
Finished Oct 12 06:03:11 AM UTC 24
Peak memory 225636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1040570
856 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_nack_acqfull.1040570856
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/11.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/11.i2c_target_nack_acqfull_addr.1158485157
Short name T129
Test name
Test status
Simulation time 596443151 ps
CPU time 5.31 seconds
Started Oct 12 06:03:05 AM UTC 24
Finished Oct 12 06:03:11 AM UTC 24
Peak memory 215488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1158485
157 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_nack_acqfull_ad
dr.1158485157
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/11.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/11.i2c_target_nack_txstretch.795506828
Short name T504
Test name
Test status
Simulation time 132605485 ps
CPU time 2.81 seconds
Started Oct 12 06:03:06 AM UTC 24
Finished Oct 12 06:03:10 AM UTC 24
Peak memory 232252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7955068
28 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_nack_txstretch.795506828
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/11.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/11.i2c_target_perf.4086373808
Short name T495
Test name
Test status
Simulation time 843305012 ps
CPU time 7.73 seconds
Started Oct 12 06:02:55 AM UTC 24
Finished Oct 12 06:03:04 AM UTC 24
Peak memory 227680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4086373
808 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_perf.4086373808
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/11.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/11.i2c_target_smbus_maxlen.272059545
Short name T503
Test name
Test status
Simulation time 3327135770 ps
CPU time 3.15 seconds
Started Oct 12 06:03:05 AM UTC 24
Finished Oct 12 06:03:09 AM UTC 24
Peak memory 215564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2720595
45 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_smbus_maxlen.272059545
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/11.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/11.i2c_target_stress_all.1582061328
Short name T512
Test name
Test status
Simulation time 19779967719 ps
CPU time 34.5 seconds
Started Oct 12 06:02:56 AM UTC 24
Finished Oct 12 06:03:32 AM UTC 24
Peak memory 246784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=158206
1328 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_stress_all.1582061328
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/11.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/11.i2c_target_stress_wr.2160095463
Short name T506
Test name
Test status
Simulation time 9784297668 ps
CPU time 34.62 seconds
Started Oct 12 06:02:48 AM UTC 24
Finished Oct 12 06:03:24 AM UTC 24
Peak memory 215528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2160095463 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_stress_wr.2160095463
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/11.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/11.i2c_target_timeout.1812766980
Short name T494
Test name
Test status
Simulation time 2797569496 ps
CPU time 10.43 seconds
Started Oct 12 06:02:50 AM UTC 24
Finished Oct 12 06:03:02 AM UTC 24
Peak memory 225772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1812766
980 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_timeout.1812766980
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/11.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/11.i2c_target_tx_stretch_ctrl.491414604
Short name T501
Test name
Test status
Simulation time 119043202 ps
CPU time 4.02 seconds
Started Oct 12 06:03:02 AM UTC 24
Finished Oct 12 06:03:07 AM UTC 24
Peak memory 215788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4914146
04 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_target_tx_stretch_ctrl.491414604
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/11.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/12.i2c_alert_test.1346166080
Short name T523
Test name
Test status
Simulation time 40042303 ps
CPU time 0.93 seconds
Started Oct 12 06:03:41 AM UTC 24
Finished Oct 12 06:03:43 AM UTC 24
Peak memory 215628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1346166080 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_alert_test.1346166080
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/12.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/12.i2c_host_fifo_fmt_empty.2660298517
Short name T136
Test name
Test status
Simulation time 296554661 ps
CPU time 6.98 seconds
Started Oct 12 06:03:10 AM UTC 24
Finished Oct 12 06:03:18 AM UTC 24
Peak memory 275328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2660298517 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_fmt_empty.2660298517
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/12.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/12.i2c_host_fifo_full.520384300
Short name T623
Test name
Test status
Simulation time 8119359784 ps
CPU time 181.29 seconds
Started Oct 12 06:03:11 AM UTC 24
Finished Oct 12 06:06:16 AM UTC 24
Peak memory 541952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=520384300 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_full.520384300
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/12.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/12.i2c_host_fifo_overflow.1861852892
Short name T546
Test name
Test status
Simulation time 2204915622 ps
CPU time 60.26 seconds
Started Oct 12 06:03:09 AM UTC 24
Finished Oct 12 06:04:11 AM UTC 24
Peak memory 765200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1861852892 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_overflow.1861852892
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/12.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/12.i2c_host_fifo_reset_fmt.831012453
Short name T132
Test name
Test status
Simulation time 165489143 ps
CPU time 1.91 seconds
Started Oct 12 06:03:09 AM UTC 24
Finished Oct 12 06:03:12 AM UTC 24
Peak memory 213212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=831012453 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_fmt.831012453
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/12.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/12.i2c_host_fifo_reset_rx.339244736
Short name T507
Test name
Test status
Simulation time 1856028001 ps
CPU time 12.94 seconds
Started Oct 12 06:03:11 AM UTC 24
Finished Oct 12 06:03:25 AM UTC 24
Peak memory 215456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=339244736 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_rx.339244736
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/12.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/12.i2c_host_fifo_watermark.2922045527
Short name T549
Test name
Test status
Simulation time 5456229665 ps
CPU time 65.17 seconds
Started Oct 12 06:03:08 AM UTC 24
Finished Oct 12 06:04:15 AM UTC 24
Peak memory 713584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2922045527 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_watermark.2922045527
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/12.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/12.i2c_host_may_nack.3346651199
Short name T526
Test name
Test status
Simulation time 547949590 ps
CPU time 8.3 seconds
Started Oct 12 06:03:34 AM UTC 24
Finished Oct 12 06:03:44 AM UTC 24
Peak memory 215500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3346651199 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.i2c_host_may_nack.3346651199
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/12.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/12.i2c_host_override.3379452933
Short name T505
Test name
Test status
Simulation time 29690392 ps
CPU time 0.99 seconds
Started Oct 12 06:03:08 AM UTC 24
Finished Oct 12 06:03:10 AM UTC 24
Peak memory 213188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3379452933 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.i2c_host_override.3379452933
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/12.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/12.i2c_host_perf.2597508015
Short name T659
Test name
Test status
Simulation time 54801701917 ps
CPU time 229.64 seconds
Started Oct 12 06:03:12 AM UTC 24
Finished Oct 12 06:07:05 AM UTC 24
Peak memory 888080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2597508015 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 12.i2c_host_perf.2597508015
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/12.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/12.i2c_host_perf_precise.1266461968
Short name T133
Test name
Test status
Simulation time 171358503 ps
CPU time 1.5 seconds
Started Oct 12 06:03:13 AM UTC 24
Finished Oct 12 06:03:15 AM UTC 24
Peak memory 239516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1266461968 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_perf_precise.1266461968
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/12.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/12.i2c_host_smoke.1049461761
Short name T469
Test name
Test status
Simulation time 8758898148 ps
CPU time 32.23 seconds
Started Oct 12 06:03:07 AM UTC 24
Finished Oct 12 06:03:41 AM UTC 24
Peak memory 435516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1049461761 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.i2c_host_smoke.1049461761
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/12.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/12.i2c_host_stretch_timeout.3614037249
Short name T530
Test name
Test status
Simulation time 614110841 ps
CPU time 30.51 seconds
Started Oct 12 06:03:13 AM UTC 24
Finished Oct 12 06:03:45 AM UTC 24
Peak memory 225760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3614037249 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_stretch_timeout.3614037249
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/12.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/12.i2c_target_bad_addr.2294112235
Short name T525
Test name
Test status
Simulation time 942535554 ps
CPU time 8.96 seconds
Started Oct 12 06:03:33 AM UTC 24
Finished Oct 12 06:03:43 AM UTC 24
Peak memory 226020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=2294112235 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_bad_ad
dr.2294112235
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/12.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/12.i2c_target_fifo_reset_acq.2648513045
Short name T515
Test name
Test status
Simulation time 133248208 ps
CPU time 1.57 seconds
Started Oct 12 06:03:31 AM UTC 24
Finished Oct 12 06:03:33 AM UTC 24
Peak memory 213512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2648513
045 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_fifo_reset_acq.2648513045
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/12.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/12.i2c_target_fifo_reset_tx.335391558
Short name T516
Test name
Test status
Simulation time 206996917 ps
CPU time 2.49 seconds
Started Oct 12 06:03:31 AM UTC 24
Finished Oct 12 06:03:34 AM UTC 24
Peak memory 215404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3353915
58 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_fifo_reset_tx.335391558
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/12.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/12.i2c_target_fifo_watermarks_acq.2285987913
Short name T520
Test name
Test status
Simulation time 2616446846 ps
CPU time 5.06 seconds
Started Oct 12 06:03:35 AM UTC 24
Finished Oct 12 06:03:41 AM UTC 24
Peak memory 215648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2285987
913 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_fifo_watermar
ks_acq.2285987913
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/12.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/12.i2c_target_fifo_watermarks_tx.2613172676
Short name T519
Test name
Test status
Simulation time 179064013 ps
CPU time 1.91 seconds
Started Oct 12 06:03:36 AM UTC 24
Finished Oct 12 06:03:39 AM UTC 24
Peak memory 215572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2613172
676 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_fifo_watermark
s_tx.2613172676
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/12.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/12.i2c_target_intr_smoke.47536288
Short name T514
Test name
Test status
Simulation time 5077463123 ps
CPU time 9.91 seconds
Started Oct 12 06:03:25 AM UTC 24
Finished Oct 12 06:03:36 AM UTC 24
Peak memory 225712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=475362
88 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_intr_smoke.47536288
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/12.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/12.i2c_target_intr_stress_wr.2947653508
Short name T509
Test name
Test status
Simulation time 834813298 ps
CPU time 2.61 seconds
Started Oct 12 06:03:26 AM UTC 24
Finished Oct 12 06:03:30 AM UTC 24
Peak memory 215508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2947653508 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_intr_stres
s_wr.2947653508
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/12.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/12.i2c_target_nack_acqfull.2175859124
Short name T528
Test name
Test status
Simulation time 781477865 ps
CPU time 4.52 seconds
Started Oct 12 06:03:39 AM UTC 24
Finished Oct 12 06:03:44 AM UTC 24
Peak memory 225768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2175859
124 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_nack_acqfull.2175859124
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/12.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/12.i2c_target_nack_acqfull_addr.1032113249
Short name T527
Test name
Test status
Simulation time 502719974 ps
CPU time 3.33 seconds
Started Oct 12 06:03:40 AM UTC 24
Finished Oct 12 06:03:44 AM UTC 24
Peak memory 215808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1032113
249 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_nack_acqfull_ad
dr.1032113249
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/12.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/12.i2c_target_perf.573001818
Short name T522
Test name
Test status
Simulation time 953249844 ps
CPU time 9.37 seconds
Started Oct 12 06:03:32 AM UTC 24
Finished Oct 12 06:03:42 AM UTC 24
Peak memory 225636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5730018
18 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_perf.573001818
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/12.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/12.i2c_target_smbus_maxlen.3719028484
Short name T521
Test name
Test status
Simulation time 7172271725 ps
CPU time 3.76 seconds
Started Oct 12 06:03:38 AM UTC 24
Finished Oct 12 06:03:42 AM UTC 24
Peak memory 215376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3719028
484 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_smbus_maxlen.3719028484
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/12.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/12.i2c_target_smoke.2122579531
Short name T510
Test name
Test status
Simulation time 833338952 ps
CPU time 12.1 seconds
Started Oct 12 06:03:17 AM UTC 24
Finished Oct 12 06:03:30 AM UTC 24
Peak memory 225900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2122579531 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_smoke.2122579531
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/12.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/12.i2c_target_stress_all.2827016058
Short name T1153
Test name
Test status
Simulation time 48424719178 ps
CPU time 852.02 seconds
Started Oct 12 06:03:33 AM UTC 24
Finished Oct 12 06:17:53 AM UTC 24
Peak memory 6626252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=282701
6058 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_stress_all.2827016058
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/12.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/12.i2c_target_stress_rd.2862185424
Short name T485
Test name
Test status
Simulation time 308877609 ps
CPU time 15.65 seconds
Started Oct 12 06:03:19 AM UTC 24
Finished Oct 12 06:03:36 AM UTC 24
Peak memory 215452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2862185424 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_stress_rd.2862185424
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/12.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/12.i2c_target_stress_wr.1955445034
Short name T511
Test name
Test status
Simulation time 14587553296 ps
CPU time 11 seconds
Started Oct 12 06:03:18 AM UTC 24
Finished Oct 12 06:03:30 AM UTC 24
Peak memory 215528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1955445034 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_stress_wr.1955445034
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/12.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/12.i2c_target_stretch.1578689487
Short name T508
Test name
Test status
Simulation time 1753767112 ps
CPU time 5.88 seconds
Started Oct 12 06:03:19 AM UTC 24
Finished Oct 12 06:03:26 AM UTC 24
Peak memory 265080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1578689487 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_stretch.1578689487
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/12.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/12.i2c_target_timeout.1447586479
Short name T518
Test name
Test status
Simulation time 4887275554 ps
CPU time 9.83 seconds
Started Oct 12 06:03:27 AM UTC 24
Finished Oct 12 06:03:38 AM UTC 24
Peak memory 229852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1447586
479 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_timeout.1447586479
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/12.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/12.i2c_target_tx_stretch_ctrl.2427924908
Short name T529
Test name
Test status
Simulation time 470040625 ps
CPU time 6.87 seconds
Started Oct 12 06:03:36 AM UTC 24
Finished Oct 12 06:03:44 AM UTC 24
Peak memory 215468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2427924
908 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_target_tx_stretch_ctrl.2427924908
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/12.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/13.i2c_alert_test.609950199
Short name T558
Test name
Test status
Simulation time 20054969 ps
CPU time 0.97 seconds
Started Oct 12 06:04:19 AM UTC 24
Finished Oct 12 06:04:21 AM UTC 24
Peak memory 213264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=609950199 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_alert_test.609950199
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/13.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/13.i2c_host_fifo_fmt_empty.2689894639
Short name T535
Test name
Test status
Simulation time 956399325 ps
CPU time 10.84 seconds
Started Oct 12 06:03:44 AM UTC 24
Finished Oct 12 06:03:56 AM UTC 24
Peak memory 265348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2689894639 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_fmt_empty.2689894639
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/13.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/13.i2c_host_fifo_full.2584775026
Short name T688
Test name
Test status
Simulation time 45935510576 ps
CPU time 234.15 seconds
Started Oct 12 06:03:45 AM UTC 24
Finished Oct 12 06:07:43 AM UTC 24
Peak memory 805876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2584775026 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_full.2584775026
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/13.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/13.i2c_host_fifo_overflow.1912221681
Short name T590
Test name
Test status
Simulation time 7297202268 ps
CPU time 106.09 seconds
Started Oct 12 06:03:44 AM UTC 24
Finished Oct 12 06:05:32 AM UTC 24
Peak memory 595160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1912221681 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_overflow.1912221681
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/13.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/13.i2c_host_fifo_reset_fmt.2285384269
Short name T532
Test name
Test status
Simulation time 71163219 ps
CPU time 1.61 seconds
Started Oct 12 06:03:44 AM UTC 24
Finished Oct 12 06:03:47 AM UTC 24
Peak memory 213212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2285384269 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_fmt.2285384269
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/13.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/13.i2c_host_fifo_reset_rx.1218071454
Short name T536
Test name
Test status
Simulation time 188117733 ps
CPU time 13.66 seconds
Started Oct 12 06:03:44 AM UTC 24
Finished Oct 12 06:03:59 AM UTC 24
Peak memory 253120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1218071454 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_rx.1218071454
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/13.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/13.i2c_host_fifo_watermark.2216873164
Short name T116
Test name
Test status
Simulation time 9396213654 ps
CPU time 96.89 seconds
Started Oct 12 06:03:43 AM UTC 24
Finished Oct 12 06:05:22 AM UTC 24
Peak memory 1391944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2216873164 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_watermark.2216873164
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/13.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/13.i2c_host_may_nack.2013401376
Short name T552
Test name
Test status
Simulation time 1309407272 ps
CPU time 6.98 seconds
Started Oct 12 06:04:10 AM UTC 24
Finished Oct 12 06:04:18 AM UTC 24
Peak memory 215652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2013401376 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.i2c_host_may_nack.2013401376
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/13.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/13.i2c_host_mode_toggle.1066375032
Short name T267
Test name
Test status
Simulation time 342523027 ps
CPU time 2.24 seconds
Started Oct 12 06:04:10 AM UTC 24
Finished Oct 12 06:04:13 AM UTC 24
Peak memory 215468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1066375032 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_mode_toggle.1066375032
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/13.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/13.i2c_host_override.761443639
Short name T531
Test name
Test status
Simulation time 18012993 ps
CPU time 0.81 seconds
Started Oct 12 06:03:43 AM UTC 24
Finished Oct 12 06:03:45 AM UTC 24
Peak memory 213212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=761443639 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 13.i2c_host_override.761443639
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/13.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/13.i2c_host_perf.3914431140
Short name T537
Test name
Test status
Simulation time 3376964487 ps
CPU time 13.09 seconds
Started Oct 12 06:03:46 AM UTC 24
Finished Oct 12 06:04:00 AM UTC 24
Peak memory 248900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3914431140 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 13.i2c_host_perf.3914431140
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/13.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/13.i2c_host_perf_precise.2936087783
Short name T534
Test name
Test status
Simulation time 242628895 ps
CPU time 7.77 seconds
Started Oct 12 06:03:46 AM UTC 24
Finished Oct 12 06:03:54 AM UTC 24
Peak memory 225576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2936087783 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_perf_precise.2936087783
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/13.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/13.i2c_host_smoke.3872653968
Short name T543
Test name
Test status
Simulation time 2968468483 ps
CPU time 23.75 seconds
Started Oct 12 06:03:42 AM UTC 24
Finished Oct 12 06:04:07 AM UTC 24
Peak memory 363392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3872653968 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.i2c_host_smoke.3872653968
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/13.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/13.i2c_host_stretch_timeout.1189897961
Short name T541
Test name
Test status
Simulation time 1007402913 ps
CPU time 18.79 seconds
Started Oct 12 06:03:46 AM UTC 24
Finished Oct 12 06:04:06 AM UTC 24
Peak memory 242552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1189897961 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_stretch_timeout.1189897961
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/13.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/13.i2c_target_bad_addr.968933845
Short name T559
Test name
Test status
Simulation time 5381418413 ps
CPU time 11.96 seconds
Started Oct 12 06:04:08 AM UTC 24
Finished Oct 12 06:04:21 AM UTC 24
Peak memory 232712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=968933845 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_bad_addr.968933845
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/13.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/13.i2c_target_fifo_reset_acq.3629552947
Short name T544
Test name
Test status
Simulation time 780384331 ps
CPU time 1.7 seconds
Started Oct 12 06:04:07 AM UTC 24
Finished Oct 12 06:04:09 AM UTC 24
Peak memory 215536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3629552
947 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_fifo_reset_acq.3629552947
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/13.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/13.i2c_target_fifo_reset_tx.2780439653
Short name T545
Test name
Test status
Simulation time 197306990 ps
CPU time 2.09 seconds
Started Oct 12 06:04:07 AM UTC 24
Finished Oct 12 06:04:10 AM UTC 24
Peak memory 215184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2780439
653 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_fifo_reset_tx.2780439653
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/13.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/13.i2c_target_fifo_watermarks_acq.926635418
Short name T550
Test name
Test status
Simulation time 3705148329 ps
CPU time 4.36 seconds
Started Oct 12 06:04:11 AM UTC 24
Finished Oct 12 06:04:17 AM UTC 24
Peak memory 215900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9266354
18 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_fifo_watermark
s_acq.926635418
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/13.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/13.i2c_target_fifo_watermarks_tx.1903086361
Short name T548
Test name
Test status
Simulation time 81428705 ps
CPU time 1.36 seconds
Started Oct 12 06:04:12 AM UTC 24
Finished Oct 12 06:04:15 AM UTC 24
Peak memory 213628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1903086
361 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_fifo_watermark
s_tx.1903086361
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/13.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/13.i2c_target_intr_stress_wr.2132548944
Short name T625
Test name
Test status
Simulation time 19199554661 ps
CPU time 135.33 seconds
Started Oct 12 06:04:00 AM UTC 24
Finished Oct 12 06:06:18 AM UTC 24
Peak memory 2407616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2132548944 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_intr_stres
s_wr.2132548944
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/13.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/13.i2c_target_nack_acqfull.2908009876
Short name T557
Test name
Test status
Simulation time 2467687661 ps
CPU time 4.25 seconds
Started Oct 12 06:04:15 AM UTC 24
Finished Oct 12 06:04:21 AM UTC 24
Peak memory 225832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2908009
876 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_nack_acqfull.2908009876
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/13.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/13.i2c_target_nack_acqfull_addr.2411544889
Short name T555
Test name
Test status
Simulation time 911355408 ps
CPU time 3.85 seconds
Started Oct 12 06:04:16 AM UTC 24
Finished Oct 12 06:04:20 AM UTC 24
Peak memory 215616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2411544
889 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_nack_acqfull_ad
dr.2411544889
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/13.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/13.i2c_target_nack_txstretch.2492603221
Short name T556
Test name
Test status
Simulation time 274713135 ps
CPU time 1.87 seconds
Started Oct 12 06:04:18 AM UTC 24
Finished Oct 12 06:04:20 AM UTC 24
Peak memory 231192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2492603
221 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_nack_txstretch.2492603221
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/13.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/13.i2c_target_perf.2313523897
Short name T551
Test name
Test status
Simulation time 1541536053 ps
CPU time 8.91 seconds
Started Oct 12 06:04:08 AM UTC 24
Finished Oct 12 06:04:18 AM UTC 24
Peak memory 232592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2313523
897 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_perf.2313523897
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/13.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/13.i2c_target_smbus_maxlen.2787664527
Short name T554
Test name
Test status
Simulation time 466302981 ps
CPU time 3.71 seconds
Started Oct 12 06:04:15 AM UTC 24
Finished Oct 12 06:04:20 AM UTC 24
Peak memory 215248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2787664
527 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_smbus_maxlen.2787664527
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/13.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/13.i2c_target_smoke.3227243197
Short name T542
Test name
Test status
Simulation time 6482690968 ps
CPU time 15.11 seconds
Started Oct 12 06:03:50 AM UTC 24
Finished Oct 12 06:04:06 AM UTC 24
Peak memory 232716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3227243197 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_smoke.3227243197
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/13.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/13.i2c_target_stress_all.246938414
Short name T1024
Test name
Test status
Simulation time 34659412288 ps
CPU time 659.44 seconds
Started Oct 12 06:04:08 AM UTC 24
Finished Oct 12 06:15:14 AM UTC 24
Peak memory 7652352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=246938
414 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_stress_all.246938414
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/13.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/13.i2c_target_stress_rd.793133846
Short name T566
Test name
Test status
Simulation time 1618876859 ps
CPU time 35.54 seconds
Started Oct 12 06:03:55 AM UTC 24
Finished Oct 12 06:04:32 AM UTC 24
Peak memory 242496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=793133846 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_stress_rd.793133846
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/13.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/13.i2c_target_stress_wr.1885042777
Short name T610
Test name
Test status
Simulation time 27633845388 ps
CPU time 126.58 seconds
Started Oct 12 06:03:53 AM UTC 24
Finished Oct 12 06:06:02 AM UTC 24
Peak memory 2010044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1885042777 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_stress_wr.1885042777
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/13.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/13.i2c_target_stretch.4272988714
Short name T538
Test name
Test status
Simulation time 2576042268 ps
CPU time 4.87 seconds
Started Oct 12 06:03:57 AM UTC 24
Finished Oct 12 06:04:03 AM UTC 24
Peak memory 225708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4272988714 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_stretch.4272988714
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/13.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/13.i2c_target_timeout.1134391025
Short name T547
Test name
Test status
Simulation time 4699524411 ps
CPU time 8.23 seconds
Started Oct 12 06:04:04 AM UTC 24
Finished Oct 12 06:04:14 AM UTC 24
Peak memory 232460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1134391
025 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_timeout.1134391025
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/13.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/13.i2c_target_tx_stretch_ctrl.3435199962
Short name T553
Test name
Test status
Simulation time 91263821 ps
CPU time 3.28 seconds
Started Oct 12 06:04:14 AM UTC 24
Finished Oct 12 06:04:19 AM UTC 24
Peak memory 215724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3435199
962 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_target_tx_stretch_ctrl.3435199962
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/13.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/14.i2c_alert_test.1961049229
Short name T585
Test name
Test status
Simulation time 26754956 ps
CPU time 1.01 seconds
Started Oct 12 06:05:10 AM UTC 24
Finished Oct 12 06:05:12 AM UTC 24
Peak memory 213392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1961049229 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_alert_test.1961049229
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/14.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/14.i2c_host_error_intr.1347634114
Short name T565
Test name
Test status
Simulation time 375731706 ps
CPU time 4.93 seconds
Started Oct 12 06:04:26 AM UTC 24
Finished Oct 12 06:04:32 AM UTC 24
Peak memory 225792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1347634114 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 14.i2c_host_error_intr.1347634114
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/14.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/14.i2c_host_fifo_fmt_empty.3051772833
Short name T564
Test name
Test status
Simulation time 396440611 ps
CPU time 8.16 seconds
Started Oct 12 06:04:21 AM UTC 24
Finished Oct 12 06:04:31 AM UTC 24
Peak memory 277612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3051772833 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_fmt_empty.3051772833
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/14.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/14.i2c_host_fifo_full.3537736471
Short name T617
Test name
Test status
Simulation time 5602353982 ps
CPU time 101.71 seconds
Started Oct 12 06:04:22 AM UTC 24
Finished Oct 12 06:06:06 AM UTC 24
Peak memory 529396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3537736471 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_full.3537736471
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/14.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/14.i2c_host_fifo_overflow.1368111189
Short name T592
Test name
Test status
Simulation time 2038370556 ps
CPU time 72.01 seconds
Started Oct 12 06:04:21 AM UTC 24
Finished Oct 12 06:05:35 AM UTC 24
Peak memory 732304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1368111189 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_overflow.1368111189
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/14.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/14.i2c_host_fifo_reset_rx.3040223393
Short name T562
Test name
Test status
Simulation time 221200234 ps
CPU time 4.82 seconds
Started Oct 12 06:04:21 AM UTC 24
Finished Oct 12 06:04:27 AM UTC 24
Peak memory 215468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3040223393 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_rx.3040223393
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/14.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/14.i2c_host_fifo_watermark.3179172508
Short name T734
Test name
Test status
Simulation time 4227260876 ps
CPU time 252.46 seconds
Started Oct 12 06:04:20 AM UTC 24
Finished Oct 12 06:08:37 AM UTC 24
Peak memory 1274888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3179172508 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_watermark.3179172508
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/14.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/14.i2c_host_mode_toggle.1758805933
Short name T578
Test name
Test status
Simulation time 140124376 ps
CPU time 3.12 seconds
Started Oct 12 06:05:00 AM UTC 24
Finished Oct 12 06:05:04 AM UTC 24
Peak memory 226088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1758805933 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_mode_toggle.1758805933
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/14.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/14.i2c_host_override.1042141857
Short name T560
Test name
Test status
Simulation time 49355137 ps
CPU time 0.97 seconds
Started Oct 12 06:04:20 AM UTC 24
Finished Oct 12 06:04:22 AM UTC 24
Peak memory 213212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1042141857 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.i2c_host_override.1042141857
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/14.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/14.i2c_host_perf.1365482428
Short name T1079
Test name
Test status
Simulation time 75176864999 ps
CPU time 704.68 seconds
Started Oct 12 06:04:22 AM UTC 24
Finished Oct 12 06:16:15 AM UTC 24
Peak memory 3476548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1365482428 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 14.i2c_host_perf.1365482428
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/14.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/14.i2c_host_perf_precise.172353761
Short name T563
Test name
Test status
Simulation time 240627347 ps
CPU time 3.1 seconds
Started Oct 12 06:04:23 AM UTC 24
Finished Oct 12 06:04:28 AM UTC 24
Peak memory 215712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=172353761 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_perf_precise.172353761
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/14.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/14.i2c_host_smoke.4083467081
Short name T600
Test name
Test status
Simulation time 1950555568 ps
CPU time 89.27 seconds
Started Oct 12 06:04:20 AM UTC 24
Finished Oct 12 06:05:51 AM UTC 24
Peak memory 441228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4083467081 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 14.i2c_host_smoke.4083467081
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/14.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/14.i2c_host_stretch_timeout.395286945
Short name T567
Test name
Test status
Simulation time 765442978 ps
CPU time 12.33 seconds
Started Oct 12 06:04:25 AM UTC 24
Finished Oct 12 06:04:38 AM UTC 24
Peak memory 231980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=395286945 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_stretch_timeout.395286945
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/14.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/14.i2c_target_bad_addr.3187127285
Short name T576
Test name
Test status
Simulation time 12003974592 ps
CPU time 5.8 seconds
Started Oct 12 06:04:55 AM UTC 24
Finished Oct 12 06:05:02 AM UTC 24
Peak memory 225772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=3187127285 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_bad_ad
dr.3187127285
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/14.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/14.i2c_target_fifo_reset_acq.2379628347
Short name T571
Test name
Test status
Simulation time 392186511 ps
CPU time 1.52 seconds
Started Oct 12 06:04:49 AM UTC 24
Finished Oct 12 06:04:52 AM UTC 24
Peak memory 213512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2379628
347 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_fifo_reset_acq.2379628347
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/14.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/14.i2c_target_fifo_reset_tx.1072734092
Short name T573
Test name
Test status
Simulation time 350286033 ps
CPU time 1.4 seconds
Started Oct 12 06:04:52 AM UTC 24
Finished Oct 12 06:04:54 AM UTC 24
Peak memory 215576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1072734
092 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_fifo_reset_tx.1072734092
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/14.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/14.i2c_target_fifo_watermarks_acq.2939290526
Short name T581
Test name
Test status
Simulation time 710430543 ps
CPU time 3.86 seconds
Started Oct 12 06:05:01 AM UTC 24
Finished Oct 12 06:05:06 AM UTC 24
Peak memory 215716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2939290
526 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_fifo_watermar
ks_acq.2939290526
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/14.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/14.i2c_target_fifo_watermarks_tx.775727089
Short name T579
Test name
Test status
Simulation time 46258090 ps
CPU time 1.27 seconds
Started Oct 12 06:05:02 AM UTC 24
Finished Oct 12 06:05:05 AM UTC 24
Peak memory 213632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7757270
89 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_fifo_watermarks
_tx.775727089
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/14.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/14.i2c_target_intr_smoke.3085023803
Short name T569
Test name
Test status
Simulation time 8908856328 ps
CPU time 7.67 seconds
Started Oct 12 06:04:39 AM UTC 24
Finished Oct 12 06:04:48 AM UTC 24
Peak memory 232328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=308502
3803 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_intr_smoke.3085023803
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/14.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/14.i2c_target_intr_stress_wr.2569039672
Short name T596
Test name
Test status
Simulation time 15889644728 ps
CPU time 64.37 seconds
Started Oct 12 06:04:43 AM UTC 24
Finished Oct 12 06:05:49 AM UTC 24
Peak memory 1969352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2569039672 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_intr_stres
s_wr.2569039672
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/14.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/14.i2c_target_nack_acqfull.247673468
Short name T586
Test name
Test status
Simulation time 563039031 ps
CPU time 5.85 seconds
Started Oct 12 06:05:05 AM UTC 24
Finished Oct 12 06:05:12 AM UTC 24
Peak memory 225828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2476734
68 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_nack_acqfull.247673468
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/14.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/14.i2c_target_nack_acqfull_addr.3776065082
Short name T524
Test name
Test status
Simulation time 1188420464 ps
CPU time 5.53 seconds
Started Oct 12 06:05:07 AM UTC 24
Finished Oct 12 06:05:13 AM UTC 24
Peak memory 215600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3776065
082 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_nack_acqfull_ad
dr.3776065082
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/14.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/14.i2c_target_nack_txstretch.2508132151
Short name T582
Test name
Test status
Simulation time 131935420 ps
CPU time 2.33 seconds
Started Oct 12 06:05:07 AM UTC 24
Finished Oct 12 06:05:10 AM UTC 24
Peak memory 232320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2508132
151 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_nack_txstretch.2508132151
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/14.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/14.i2c_target_perf.4035632464
Short name T577
Test name
Test status
Simulation time 3369891020 ps
CPU time 9.69 seconds
Started Oct 12 06:04:53 AM UTC 24
Finished Oct 12 06:05:03 AM UTC 24
Peak memory 228188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4035632
464 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_perf.4035632464
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/14.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/14.i2c_target_smbus_maxlen.3416032031
Short name T583
Test name
Test status
Simulation time 788646184 ps
CPU time 3.88 seconds
Started Oct 12 06:05:05 AM UTC 24
Finished Oct 12 06:05:10 AM UTC 24
Peak memory 215176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3416032
031 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_smbus_maxlen.3416032031
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/14.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/14.i2c_target_smoke.3892983146
Short name T568
Test name
Test status
Simulation time 3150995992 ps
CPU time 12.63 seconds
Started Oct 12 06:04:29 AM UTC 24
Finished Oct 12 06:04:43 AM UTC 24
Peak memory 225760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3892983146 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_smoke.3892983146
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/14.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/14.i2c_target_stress_all.3346264208
Short name T656
Test name
Test status
Simulation time 45948276858 ps
CPU time 120.42 seconds
Started Oct 12 06:04:54 AM UTC 24
Finished Oct 12 06:06:57 AM UTC 24
Peak memory 1244224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=334626
4208 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_stress_all.3346264208
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/14.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/14.i2c_target_stress_rd.4083787204
Short name T570
Test name
Test status
Simulation time 540991858 ps
CPU time 14.03 seconds
Started Oct 12 06:04:33 AM UTC 24
Finished Oct 12 06:04:48 AM UTC 24
Peak memory 225632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4083787204 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_stress_rd.4083787204
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/14.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/14.i2c_target_stress_wr.2630045292
Short name T626
Test name
Test status
Simulation time 46360556183 ps
CPU time 109.42 seconds
Started Oct 12 06:04:32 AM UTC 24
Finished Oct 12 06:06:23 AM UTC 24
Peak memory 1788788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2630045292 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_stress_wr.2630045292
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/14.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/14.i2c_target_timeout.95208102
Short name T575
Test name
Test status
Simulation time 5034185419 ps
CPU time 11.53 seconds
Started Oct 12 06:04:47 AM UTC 24
Finished Oct 12 06:05:00 AM UTC 24
Peak memory 225700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9520810
2 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_timeout.95208102
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/14.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/14.i2c_target_tx_stretch_ctrl.105918536
Short name T584
Test name
Test status
Simulation time 230811347 ps
CPU time 5.88 seconds
Started Oct 12 06:05:04 AM UTC 24
Finished Oct 12 06:05:11 AM UTC 24
Peak memory 215404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1059185
36 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_target_tx_stretch_ctrl.105918536
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/14.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/15.i2c_alert_test.687469523
Short name T614
Test name
Test status
Simulation time 16674388 ps
CPU time 0.96 seconds
Started Oct 12 06:06:02 AM UTC 24
Finished Oct 12 06:06:04 AM UTC 24
Peak memory 215628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=687469523 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_alert_test.687469523
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/15.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/15.i2c_host_error_intr.845149730
Short name T589
Test name
Test status
Simulation time 368374171 ps
CPU time 2.63 seconds
Started Oct 12 06:05:23 AM UTC 24
Finished Oct 12 06:05:26 AM UTC 24
Peak memory 225716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=845149730 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 15.i2c_host_error_intr.845149730
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/15.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/15.i2c_host_fifo_fmt_empty.881552324
Short name T540
Test name
Test status
Simulation time 4652019647 ps
CPU time 7.63 seconds
Started Oct 12 06:05:13 AM UTC 24
Finished Oct 12 06:05:22 AM UTC 24
Peak memory 287684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=881552324 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_fmt_empty.881552324
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/15.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/15.i2c_host_fifo_full.3688259081
Short name T624
Test name
Test status
Simulation time 8220703401 ps
CPU time 61.29 seconds
Started Oct 12 06:05:15 AM UTC 24
Finished Oct 12 06:06:17 AM UTC 24
Peak memory 541900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3688259081 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_full.3688259081
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/15.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/15.i2c_host_fifo_overflow.1633492541
Short name T655
Test name
Test status
Simulation time 3483503081 ps
CPU time 100.67 seconds
Started Oct 12 06:05:13 AM UTC 24
Finished Oct 12 06:06:56 AM UTC 24
Peak memory 639872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1633492541 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_overflow.1633492541
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/15.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/15.i2c_host_fifo_reset_fmt.3333740973
Short name T588
Test name
Test status
Simulation time 255778834 ps
CPU time 1.33 seconds
Started Oct 12 06:05:13 AM UTC 24
Finished Oct 12 06:05:16 AM UTC 24
Peak memory 213332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3333740973 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_fmt.3333740973
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/15.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/15.i2c_host_fifo_reset_rx.714729707
Short name T517
Test name
Test status
Simulation time 474865239 ps
CPU time 10.8 seconds
Started Oct 12 06:05:14 AM UTC 24
Finished Oct 12 06:05:26 AM UTC 24
Peak memory 245048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=714729707 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_rx.714729707
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/15.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/15.i2c_host_fifo_watermark.2580086912
Short name T117
Test name
Test status
Simulation time 17335760607 ps
CPU time 70.59 seconds
Started Oct 12 06:05:12 AM UTC 24
Finished Oct 12 06:06:24 AM UTC 24
Peak memory 896004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2580086912 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_watermark.2580086912
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/15.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/15.i2c_host_override.1428742731
Short name T587
Test name
Test status
Simulation time 25272855 ps
CPU time 1.11 seconds
Started Oct 12 06:05:11 AM UTC 24
Finished Oct 12 06:05:13 AM UTC 24
Peak memory 213208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1428742731 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.i2c_host_override.1428742731
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/15.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/15.i2c_host_perf.1739481865
Short name T591
Test name
Test status
Simulation time 2718452095 ps
CPU time 17.39 seconds
Started Oct 12 06:05:17 AM UTC 24
Finished Oct 12 06:05:35 AM UTC 24
Peak memory 215784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1739481865 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 15.i2c_host_perf.1739481865
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/15.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/15.i2c_host_perf_precise.2925202716
Short name T1018
Test name
Test status
Simulation time 23153011488 ps
CPU time 581.49 seconds
Started Oct 12 06:05:21 AM UTC 24
Finished Oct 12 06:15:09 AM UTC 24
Peak memory 2249644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2925202716 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_perf_precise.2925202716
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/15.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/15.i2c_host_smoke.2987967536
Short name T580
Test name
Test status
Simulation time 1360667503 ps
CPU time 21.94 seconds
Started Oct 12 06:05:11 AM UTC 24
Finished Oct 12 06:05:34 AM UTC 24
Peak memory 281472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2987967536 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 15.i2c_host_smoke.2987967536
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/15.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/15.i2c_host_stretch_timeout.4252448089
Short name T620
Test name
Test status
Simulation time 3680754409 ps
CPU time 47.15 seconds
Started Oct 12 06:05:23 AM UTC 24
Finished Oct 12 06:06:11 AM UTC 24
Peak memory 227872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4252448089 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_stretch_timeout.4252448089
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/15.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/15.i2c_target_bad_addr.2340125623
Short name T609
Test name
Test status
Simulation time 1236353226 ps
CPU time 8.03 seconds
Started Oct 12 06:05:52 AM UTC 24
Finished Oct 12 06:06:02 AM UTC 24
Peak memory 232532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=2340125623 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_bad_ad
dr.2340125623
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/15.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/15.i2c_target_fifo_reset_acq.1226215010
Short name T598
Test name
Test status
Simulation time 216859502 ps
CPU time 1.26 seconds
Started Oct 12 06:05:49 AM UTC 24
Finished Oct 12 06:05:51 AM UTC 24
Peak memory 213272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1226215
010 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_fifo_reset_acq.1226215010
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/15.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/15.i2c_target_fifo_reset_tx.1861758727
Short name T601
Test name
Test status
Simulation time 377271030 ps
CPU time 1.84 seconds
Started Oct 12 06:05:50 AM UTC 24
Finished Oct 12 06:05:53 AM UTC 24
Peak memory 215536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1861758
727 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_fifo_reset_tx.1861758727
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/15.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/15.i2c_target_fifo_watermarks_acq.2867339751
Short name T608
Test name
Test status
Simulation time 3380142887 ps
CPU time 3.6 seconds
Started Oct 12 06:05:56 AM UTC 24
Finished Oct 12 06:06:01 AM UTC 24
Peak memory 215564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2867339
751 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_fifo_watermar
ks_acq.2867339751
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/15.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/15.i2c_target_fifo_watermarks_tx.548336163
Short name T607
Test name
Test status
Simulation time 563644787 ps
CPU time 1.61 seconds
Started Oct 12 06:05:58 AM UTC 24
Finished Oct 12 06:06:01 AM UTC 24
Peak memory 213632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5483361
63 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_fifo_watermarks
_tx.548336163
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/15.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/15.i2c_target_hrst.3340123861
Short name T605
Test name
Test status
Simulation time 236613738 ps
CPU time 2.88 seconds
Started Oct 12 06:05:53 AM UTC 24
Finished Oct 12 06:05:58 AM UTC 24
Peak memory 225692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3340123
861 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_hrst.3340123861
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/15.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/15.i2c_target_intr_smoke.357009739
Short name T595
Test name
Test status
Simulation time 8450797005 ps
CPU time 7.28 seconds
Started Oct 12 06:05:36 AM UTC 24
Finished Oct 12 06:05:45 AM UTC 24
Peak memory 232224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=357009
739 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_intr_smoke.357009739
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/15.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/15.i2c_target_intr_stress_wr.381109097
Short name T752
Test name
Test status
Simulation time 18136122956 ps
CPU time 202.92 seconds
Started Oct 12 06:05:42 AM UTC 24
Finished Oct 12 06:09:08 AM UTC 24
Peak memory 2897104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=381109097 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_intr_stress
_wr.381109097
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/15.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/15.i2c_target_nack_acqfull.2694315427
Short name T612
Test name
Test status
Simulation time 1965378064 ps
CPU time 3.45 seconds
Started Oct 12 06:05:59 AM UTC 24
Finished Oct 12 06:06:03 AM UTC 24
Peak memory 225832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2694315
427 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_nack_acqfull.2694315427
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/15.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/15.i2c_target_nack_acqfull_addr.1259213161
Short name T616
Test name
Test status
Simulation time 2879405670 ps
CPU time 3.42 seconds
Started Oct 12 06:06:01 AM UTC 24
Finished Oct 12 06:06:06 AM UTC 24
Peak memory 215476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1259213
161 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_nack_acqfull_ad
dr.1259213161
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/15.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/15.i2c_target_nack_txstretch.1562804104
Short name T615
Test name
Test status
Simulation time 144687658 ps
CPU time 2.59 seconds
Started Oct 12 06:06:01 AM UTC 24
Finished Oct 12 06:06:05 AM UTC 24
Peak memory 232184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1562804
104 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_nack_txstretch.1562804104
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/15.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/15.i2c_target_perf.3124433035
Short name T603
Test name
Test status
Simulation time 1917190147 ps
CPU time 5.13 seconds
Started Oct 12 06:05:50 AM UTC 24
Finished Oct 12 06:05:56 AM UTC 24
Peak memory 225688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3124433
035 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_perf.3124433035
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/15.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/15.i2c_target_smbus_maxlen.4128575789
Short name T611
Test name
Test status
Simulation time 1067902206 ps
CPU time 3.32 seconds
Started Oct 12 06:05:59 AM UTC 24
Finished Oct 12 06:06:03 AM UTC 24
Peak memory 215248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4128575
789 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_smbus_maxlen.4128575789
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/15.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/15.i2c_target_smoke.2297883626
Short name T594
Test name
Test status
Simulation time 990517949 ps
CPU time 16.17 seconds
Started Oct 12 06:05:27 AM UTC 24
Finished Oct 12 06:05:44 AM UTC 24
Peak memory 225768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2297883626 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_smoke.2297883626
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/15.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/15.i2c_target_stress_all.2217192491
Short name T737
Test name
Test status
Simulation time 36732311556 ps
CPU time 165.02 seconds
Started Oct 12 06:05:52 AM UTC 24
Finished Oct 12 06:08:40 AM UTC 24
Peak memory 2159492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=221719
2491 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_stress_all.2217192491
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/15.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/15.i2c_target_stress_rd.3707167294
Short name T604
Test name
Test status
Simulation time 2044081233 ps
CPU time 20.72 seconds
Started Oct 12 06:05:35 AM UTC 24
Finished Oct 12 06:05:57 AM UTC 24
Peak memory 232380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3707167294 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_stress_rd.3707167294
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/15.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/15.i2c_target_stress_wr.3811112017
Short name T766
Test name
Test status
Simulation time 47447353299 ps
CPU time 229.5 seconds
Started Oct 12 06:05:33 AM UTC 24
Finished Oct 12 06:09:26 AM UTC 24
Peak memory 3480644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3811112017 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_stress_wr.3811112017
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/15.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/15.i2c_target_stretch.1697609865
Short name T597
Test name
Test status
Simulation time 2600907254 ps
CPU time 12.04 seconds
Started Oct 12 06:05:36 AM UTC 24
Finished Oct 12 06:05:49 AM UTC 24
Peak memory 345040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1697609865 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_stretch.1697609865
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/15.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/15.i2c_target_timeout.1808799093
Short name T606
Test name
Test status
Simulation time 2347053825 ps
CPU time 10.92 seconds
Started Oct 12 06:05:46 AM UTC 24
Finished Oct 12 06:05:58 AM UTC 24
Peak memory 242636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1808799
093 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_timeout.1808799093
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/15.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/15.i2c_target_tx_stretch_ctrl.2422169119
Short name T613
Test name
Test status
Simulation time 213474676 ps
CPU time 3.71 seconds
Started Oct 12 06:05:59 AM UTC 24
Finished Oct 12 06:06:03 AM UTC 24
Peak memory 215768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2422169
119 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_target_tx_stretch_ctrl.2422169119
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/15.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/16.i2c_alert_test.1885877144
Short name T642
Test name
Test status
Simulation time 45361987 ps
CPU time 0.93 seconds
Started Oct 12 06:06:40 AM UTC 24
Finished Oct 12 06:06:42 AM UTC 24
Peak memory 215628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1885877144 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_alert_test.1885877144
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/16.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/16.i2c_host_error_intr.1318969211
Short name T622
Test name
Test status
Simulation time 735189382 ps
CPU time 2.45 seconds
Started Oct 12 06:06:12 AM UTC 24
Finished Oct 12 06:06:16 AM UTC 24
Peak memory 232600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1318969211 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 16.i2c_host_error_intr.1318969211
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/16.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/16.i2c_host_fifo_fmt_empty.3521702969
Short name T630
Test name
Test status
Simulation time 703176514 ps
CPU time 21.43 seconds
Started Oct 12 06:06:06 AM UTC 24
Finished Oct 12 06:06:29 AM UTC 24
Peak memory 277648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3521702969 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_fmt_empty.3521702969
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/16.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/16.i2c_host_fifo_full.1646340925
Short name T679
Test name
Test status
Simulation time 2610157765 ps
CPU time 85.64 seconds
Started Oct 12 06:06:06 AM UTC 24
Finished Oct 12 06:07:34 AM UTC 24
Peak memory 533516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1646340925 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_full.1646340925
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/16.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/16.i2c_host_fifo_overflow.1450899588
Short name T699
Test name
Test status
Simulation time 5975055923 ps
CPU time 110.87 seconds
Started Oct 12 06:06:04 AM UTC 24
Finished Oct 12 06:07:58 AM UTC 24
Peak memory 597324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1450899588 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_overflow.1450899588
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/16.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/16.i2c_host_fifo_reset_fmt.2200738876
Short name T618
Test name
Test status
Simulation time 675259596 ps
CPU time 2.05 seconds
Started Oct 12 06:06:05 AM UTC 24
Finished Oct 12 06:06:08 AM UTC 24
Peak memory 215380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2200738876 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_fmt.2200738876
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/16.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/16.i2c_host_fifo_reset_rx.4222821820
Short name T621
Test name
Test status
Simulation time 346639591 ps
CPU time 6.01 seconds
Started Oct 12 06:06:06 AM UTC 24
Finished Oct 12 06:06:13 AM UTC 24
Peak memory 242560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4222821820 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_rx.4222821820
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/16.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/16.i2c_host_fifo_watermark.3809771117
Short name T825
Test name
Test status
Simulation time 22131216903 ps
CPU time 274.23 seconds
Started Oct 12 06:06:04 AM UTC 24
Finished Oct 12 06:10:43 AM UTC 24
Peak memory 1266636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3809771117 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_watermark.3809771117
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/16.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/16.i2c_host_may_nack.1872586306
Short name T650
Test name
Test status
Simulation time 585194391 ps
CPU time 12.93 seconds
Started Oct 12 06:06:33 AM UTC 24
Finished Oct 12 06:06:47 AM UTC 24
Peak memory 215580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1872586306 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.i2c_host_may_nack.1872586306
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/16.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/16.i2c_host_override.2927527209
Short name T140
Test name
Test status
Simulation time 52316106 ps
CPU time 0.96 seconds
Started Oct 12 06:06:02 AM UTC 24
Finished Oct 12 06:06:04 AM UTC 24
Peak memory 213212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2927527209 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.i2c_host_override.2927527209
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/16.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/16.i2c_host_perf.225828509
Short name T693
Test name
Test status
Simulation time 2588392331 ps
CPU time 105.68 seconds
Started Oct 12 06:06:07 AM UTC 24
Finished Oct 12 06:07:55 AM UTC 24
Peak memory 246704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=225828509 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 16.i2c_host_perf.225828509
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/16.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/16.i2c_host_perf_precise.2512422044
Short name T619
Test name
Test status
Simulation time 64067510 ps
CPU time 2.22 seconds
Started Oct 12 06:06:08 AM UTC 24
Finished Oct 12 06:06:11 AM UTC 24
Peak memory 215584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2512422044 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_perf_precise.2512422044
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/16.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/16.i2c_host_smoke.2619420645
Short name T641
Test name
Test status
Simulation time 3511101229 ps
CPU time 36.28 seconds
Started Oct 12 06:06:02 AM UTC 24
Finished Oct 12 06:06:40 AM UTC 24
Peak memory 377844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2619420645 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.i2c_host_smoke.2619420645
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/16.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/16.i2c_host_stretch_timeout.3636953125
Short name T627
Test name
Test status
Simulation time 700227770 ps
CPU time 13.99 seconds
Started Oct 12 06:06:09 AM UTC 24
Finished Oct 12 06:06:25 AM UTC 24
Peak memory 229856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3636953125 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_stretch_timeout.3636953125
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/16.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/16.i2c_target_bad_addr.694112130
Short name T638
Test name
Test status
Simulation time 4709138761 ps
CPU time 6.9 seconds
Started Oct 12 06:06:29 AM UTC 24
Finished Oct 12 06:06:37 AM UTC 24
Peak memory 225832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=694112130 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_bad_addr.694112130
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/16.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/16.i2c_target_fifo_reset_acq.1744587207
Short name T631
Test name
Test status
Simulation time 155831241 ps
CPU time 1.8 seconds
Started Oct 12 06:06:25 AM UTC 24
Finished Oct 12 06:06:29 AM UTC 24
Peak memory 215276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1744587
207 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_fifo_reset_acq.1744587207
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/16.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/16.i2c_target_fifo_reset_tx.263860957
Short name T629
Test name
Test status
Simulation time 691030047 ps
CPU time 1.67 seconds
Started Oct 12 06:06:25 AM UTC 24
Finished Oct 12 06:06:28 AM UTC 24
Peak memory 213304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2638609
57 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_fifo_reset_tx.263860957
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/16.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/16.i2c_target_fifo_watermarks_acq.2317659648
Short name T639
Test name
Test status
Simulation time 1945616466 ps
CPU time 4.03 seconds
Started Oct 12 06:06:34 AM UTC 24
Finished Oct 12 06:06:39 AM UTC 24
Peak memory 215844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2317659
648 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_fifo_watermar
ks_acq.2317659648
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/16.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/16.i2c_target_fifo_watermarks_tx.515404446
Short name T637
Test name
Test status
Simulation time 125672163 ps
CPU time 1.9 seconds
Started Oct 12 06:06:34 AM UTC 24
Finished Oct 12 06:06:37 AM UTC 24
Peak memory 213632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5154044
46 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_fifo_watermarks
_tx.515404446
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/16.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/16.i2c_target_hrst.2300302231
Short name T634
Test name
Test status
Simulation time 379649339 ps
CPU time 2.33 seconds
Started Oct 12 06:06:29 AM UTC 24
Finished Oct 12 06:06:33 AM UTC 24
Peak memory 225692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2300302
231 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_hrst.2300302231
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/16.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/16.i2c_target_intr_smoke.612197675
Short name T633
Test name
Test status
Simulation time 2801635642 ps
CPU time 12.44 seconds
Started Oct 12 06:06:19 AM UTC 24
Finished Oct 12 06:06:32 AM UTC 24
Peak memory 232172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=612197
675 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_intr_smoke.612197675
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/16.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/16.i2c_target_intr_stress_wr.164037144
Short name T694
Test name
Test status
Simulation time 19406357207 ps
CPU time 94.41 seconds
Started Oct 12 06:06:19 AM UTC 24
Finished Oct 12 06:07:55 AM UTC 24
Peak memory 1844432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=164037144 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_intr_stress
_wr.164037144
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/16.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/16.i2c_target_nack_acqfull.2512176992
Short name T648
Test name
Test status
Simulation time 1982520528 ps
CPU time 5.66 seconds
Started Oct 12 06:06:38 AM UTC 24
Finished Oct 12 06:06:45 AM UTC 24
Peak memory 225700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2512176
992 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_nack_acqfull.2512176992
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/16.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/16.i2c_target_nack_acqfull_addr.2846958088
Short name T646
Test name
Test status
Simulation time 987714020 ps
CPU time 4.43 seconds
Started Oct 12 06:06:38 AM UTC 24
Finished Oct 12 06:06:44 AM UTC 24
Peak memory 215808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2846958
088 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_nack_acqfull_ad
dr.2846958088
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/16.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/16.i2c_target_nack_txstretch.3554695537
Short name T644
Test name
Test status
Simulation time 127327194 ps
CPU time 2.18 seconds
Started Oct 12 06:06:40 AM UTC 24
Finished Oct 12 06:06:43 AM UTC 24
Peak memory 232584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3554695
537 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_nack_txstretch.3554695537
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/16.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/16.i2c_target_perf.2373508878
Short name T640
Test name
Test status
Simulation time 920835427 ps
CPU time 10.28 seconds
Started Oct 12 06:06:28 AM UTC 24
Finished Oct 12 06:06:40 AM UTC 24
Peak memory 234572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2373508
878 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_perf.2373508878
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/16.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/16.i2c_target_smbus_maxlen.323202021
Short name T643
Test name
Test status
Simulation time 530709580 ps
CPU time 4.6 seconds
Started Oct 12 06:06:37 AM UTC 24
Finished Oct 12 06:06:43 AM UTC 24
Peak memory 215168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3232020
21 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_smbus_maxlen.323202021
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/16.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/16.i2c_target_smoke.1074633779
Short name T632
Test name
Test status
Simulation time 1655405972 ps
CPU time 16.22 seconds
Started Oct 12 06:06:14 AM UTC 24
Finished Oct 12 06:06:32 AM UTC 24
Peak memory 226080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1074633779 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_smoke.1074633779
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/16.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/16.i2c_target_stress_all.495337099
Short name T703
Test name
Test status
Simulation time 43750807864 ps
CPU time 92.07 seconds
Started Oct 12 06:06:28 AM UTC 24
Finished Oct 12 06:08:02 AM UTC 24
Peak memory 603012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=495337
099 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_stress_all.495337099
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/16.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/16.i2c_target_stress_rd.809227757
Short name T661
Test name
Test status
Simulation time 1063938792 ps
CPU time 54.19 seconds
Started Oct 12 06:06:16 AM UTC 24
Finished Oct 12 06:07:12 AM UTC 24
Peak memory 225768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=809227757 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_stress_rd.809227757
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/16.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/16.i2c_target_stress_wr.405633874
Short name T675
Test name
Test status
Simulation time 27890472168 ps
CPU time 74.4 seconds
Started Oct 12 06:06:16 AM UTC 24
Finished Oct 12 06:07:33 AM UTC 24
Peak memory 1037220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=405633874 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_stress_wr.405633874
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/16.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/16.i2c_target_stretch.2501934244
Short name T677
Test name
Test status
Simulation time 5455542041 ps
CPU time 73.87 seconds
Started Oct 12 06:06:17 AM UTC 24
Finished Oct 12 06:07:33 AM UTC 24
Peak memory 1436616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2501934244 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_stretch.2501934244
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/16.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/16.i2c_target_timeout.874765092
Short name T635
Test name
Test status
Simulation time 1363319130 ps
CPU time 10.74 seconds
Started Oct 12 06:06:21 AM UTC 24
Finished Oct 12 06:06:33 AM UTC 24
Peak memory 225824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8747650
92 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_timeout.874765092
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/16.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/16.i2c_target_tx_stretch_ctrl.830262886
Short name T645
Test name
Test status
Simulation time 248600550 ps
CPU time 6.49 seconds
Started Oct 12 06:06:36 AM UTC 24
Finished Oct 12 06:06:43 AM UTC 24
Peak memory 225640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8302628
86 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_target_tx_stretch_ctrl.830262886
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/16.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/17.i2c_alert_test.3134204892
Short name T680
Test name
Test status
Simulation time 35133223 ps
CPU time 0.96 seconds
Started Oct 12 06:07:31 AM UTC 24
Finished Oct 12 06:07:34 AM UTC 24
Peak memory 215628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3134204892 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_alert_test.3134204892
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/17.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/17.i2c_host_error_intr.1326868476
Short name T657
Test name
Test status
Simulation time 685912042 ps
CPU time 2.76 seconds
Started Oct 12 06:06:53 AM UTC 24
Finished Oct 12 06:06:57 AM UTC 24
Peak memory 225848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1326868476 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 17.i2c_host_error_intr.1326868476
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/17.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/17.i2c_host_fifo_fmt_empty.153457043
Short name T653
Test name
Test status
Simulation time 498156419 ps
CPU time 7.13 seconds
Started Oct 12 06:06:45 AM UTC 24
Finished Oct 12 06:06:53 AM UTC 24
Peak memory 232444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=153457043 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_fmt_empty.153457043
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/17.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/17.i2c_host_fifo_full.3090161628
Short name T727
Test name
Test status
Simulation time 2905127994 ps
CPU time 100.65 seconds
Started Oct 12 06:06:46 AM UTC 24
Finished Oct 12 06:08:29 AM UTC 24
Peak memory 763092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3090161628 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_full.3090161628
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/17.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/17.i2c_host_fifo_overflow.506226266
Short name T686
Test name
Test status
Simulation time 4957207927 ps
CPU time 56.07 seconds
Started Oct 12 06:06:45 AM UTC 24
Finished Oct 12 06:07:42 AM UTC 24
Peak memory 615688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=506226266 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_overflow.506226266
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/17.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/17.i2c_host_fifo_reset_fmt.948996087
Short name T651
Test name
Test status
Simulation time 1086890850 ps
CPU time 2.03 seconds
Started Oct 12 06:06:45 AM UTC 24
Finished Oct 12 06:06:48 AM UTC 24
Peak memory 215436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=948996087 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_fmt.948996087
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/17.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/17.i2c_host_fifo_reset_rx.3407480705
Short name T654
Test name
Test status
Simulation time 538988390 ps
CPU time 7.47 seconds
Started Oct 12 06:06:45 AM UTC 24
Finished Oct 12 06:06:53 AM UTC 24
Peak memory 215472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3407480705 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_rx.3407480705
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/17.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/17.i2c_host_fifo_watermark.2766191120
Short name T842
Test name
Test status
Simulation time 3866454682 ps
CPU time 246.63 seconds
Started Oct 12 06:06:43 AM UTC 24
Finished Oct 12 06:10:54 AM UTC 24
Peak memory 1201028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2766191120 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_watermark.2766191120
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/17.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/17.i2c_host_may_nack.1890736874
Short name T674
Test name
Test status
Simulation time 346575526 ps
CPU time 8.35 seconds
Started Oct 12 06:07:23 AM UTC 24
Finished Oct 12 06:07:32 AM UTC 24
Peak memory 215208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1890736874 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.i2c_host_may_nack.1890736874
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/17.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/17.i2c_host_override.2882699679
Short name T649
Test name
Test status
Simulation time 61745392 ps
CPU time 0.92 seconds
Started Oct 12 06:06:43 AM UTC 24
Finished Oct 12 06:06:45 AM UTC 24
Peak memory 213212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2882699679 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.i2c_host_override.2882699679
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/17.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/17.i2c_host_perf.29098816
Short name T667
Test name
Test status
Simulation time 7898378553 ps
CPU time 34.38 seconds
Started Oct 12 06:06:46 AM UTC 24
Finished Oct 12 06:07:22 AM UTC 24
Peak memory 279436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=29098816 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ho
st_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 17.i2c_host_perf.29098816
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/17.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/17.i2c_host_perf_precise.670380097
Short name T652
Test name
Test status
Simulation time 93582834 ps
CPU time 2.85 seconds
Started Oct 12 06:06:48 AM UTC 24
Finished Oct 12 06:06:52 AM UTC 24
Peak memory 229740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=670380097 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_perf_precise.670380097
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/17.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/17.i2c_host_smoke.3437656246
Short name T658
Test name
Test status
Simulation time 4195761715 ps
CPU time 16.47 seconds
Started Oct 12 06:06:41 AM UTC 24
Finished Oct 12 06:06:59 AM UTC 24
Peak memory 291716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3437656246 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 17.i2c_host_smoke.3437656246
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/17.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/17.i2c_host_stretch_timeout.836085592
Short name T672
Test name
Test status
Simulation time 4005866390 ps
CPU time 38.29 seconds
Started Oct 12 06:06:49 AM UTC 24
Finished Oct 12 06:07:29 AM UTC 24
Peak memory 226028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=836085592 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_stretch_timeout.836085592
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/17.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/17.i2c_target_bad_addr.2168523150
Short name T668
Test name
Test status
Simulation time 3115403469 ps
CPU time 6.83 seconds
Started Oct 12 06:07:16 AM UTC 24
Finished Oct 12 06:07:24 AM UTC 24
Peak memory 225772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=2168523150 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_bad_ad
dr.2168523150
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/17.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/17.i2c_target_fifo_reset_acq.480780255
Short name T663
Test name
Test status
Simulation time 121254829 ps
CPU time 1.51 seconds
Started Oct 12 06:07:13 AM UTC 24
Finished Oct 12 06:07:15 AM UTC 24
Peak memory 225496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4807802
55 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_fifo_reset_acq.480780255
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/17.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/17.i2c_target_fifo_reset_tx.3110312175
Short name T664
Test name
Test status
Simulation time 257027000 ps
CPU time 2.54 seconds
Started Oct 12 06:07:14 AM UTC 24
Finished Oct 12 06:07:18 AM UTC 24
Peak memory 215404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3110312
175 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_fifo_reset_tx.3110312175
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/17.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/17.i2c_target_fifo_watermarks_acq.535135258
Short name T670
Test name
Test status
Simulation time 1231147263 ps
CPU time 3.5 seconds
Started Oct 12 06:07:23 AM UTC 24
Finished Oct 12 06:07:27 AM UTC 24
Peak memory 214872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5351352
58 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_fifo_watermark
s_acq.535135258
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/17.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/17.i2c_target_fifo_watermarks_tx.3234362411
Short name T669
Test name
Test status
Simulation time 358470483 ps
CPU time 1.35 seconds
Started Oct 12 06:07:25 AM UTC 24
Finished Oct 12 06:07:27 AM UTC 24
Peak memory 213268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3234362
411 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_fifo_watermark
s_tx.3234362411
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/17.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/17.i2c_target_intr_smoke.2333365294
Short name T660
Test name
Test status
Simulation time 780679320 ps
CPU time 6.62 seconds
Started Oct 12 06:07:00 AM UTC 24
Finished Oct 12 06:07:07 AM UTC 24
Peak memory 232344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=233336
5294 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_intr_smoke.2333365294
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/17.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/17.i2c_target_intr_stress_wr.2586088517
Short name T714
Test name
Test status
Simulation time 13276245231 ps
CPU time 62.34 seconds
Started Oct 12 06:07:06 AM UTC 24
Finished Oct 12 06:08:10 AM UTC 24
Peak memory 1766264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2586088517 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_intr_stres
s_wr.2586088517
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/17.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/17.i2c_target_nack_acqfull.2488135034
Short name T678
Test name
Test status
Simulation time 903554600 ps
CPU time 4.35 seconds
Started Oct 12 06:07:28 AM UTC 24
Finished Oct 12 06:07:33 AM UTC 24
Peak memory 225636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2488135
034 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_nack_acqfull.2488135034
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/17.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/17.i2c_target_nack_acqfull_addr.4217416286
Short name T682
Test name
Test status
Simulation time 1982332580 ps
CPU time 3.88 seconds
Started Oct 12 06:07:29 AM UTC 24
Finished Oct 12 06:07:34 AM UTC 24
Peak memory 215924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4217416
286 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_nack_acqfull_ad
dr.4217416286
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/17.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/17.i2c_target_perf.3189135574
Short name T665
Test name
Test status
Simulation time 510577636 ps
CPU time 5.43 seconds
Started Oct 12 06:07:14 AM UTC 24
Finished Oct 12 06:07:21 AM UTC 24
Peak memory 232212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3189135
574 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_perf.3189135574
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/17.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/17.i2c_target_smbus_maxlen.1818058214
Short name T676
Test name
Test status
Simulation time 471900557 ps
CPU time 3.91 seconds
Started Oct 12 06:07:28 AM UTC 24
Finished Oct 12 06:07:33 AM UTC 24
Peak memory 215172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1818058
214 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_smbus_maxlen.1818058214
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/17.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/17.i2c_target_smoke.792869025
Short name T599
Test name
Test status
Simulation time 1227678593 ps
CPU time 17.43 seconds
Started Oct 12 06:06:54 AM UTC 24
Finished Oct 12 06:07:13 AM UTC 24
Peak memory 225696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=792869025 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_smoke.792869025
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/17.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/17.i2c_target_stress_all.3709992752
Short name T882
Test name
Test status
Simulation time 20803270132 ps
CPU time 291.6 seconds
Started Oct 12 06:07:16 AM UTC 24
Finished Oct 12 06:12:12 AM UTC 24
Peak memory 3441672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=370999
2752 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_stress_all.3709992752
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/17.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/17.i2c_target_stress_rd.1818516781
Short name T671
Test name
Test status
Simulation time 3255176932 ps
CPU time 29.11 seconds
Started Oct 12 06:06:57 AM UTC 24
Finished Oct 12 06:07:28 AM UTC 24
Peak memory 225824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1818516781 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_stress_rd.1818516781
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/17.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/17.i2c_target_stress_wr.2955292663
Short name T1070
Test name
Test status
Simulation time 43181032057 ps
CPU time 538.82 seconds
Started Oct 12 06:06:56 AM UTC 24
Finished Oct 12 06:16:01 AM UTC 24
Peak memory 5981476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2955292663 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_stress_wr.2955292663
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/17.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/17.i2c_target_stretch.102739161
Short name T662
Test name
Test status
Simulation time 2780953916 ps
CPU time 13.33 seconds
Started Oct 12 06:06:58 AM UTC 24
Finished Oct 12 06:07:12 AM UTC 24
Peak memory 215236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=102739161 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_stretch.102739161
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/17.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/17.i2c_target_timeout.3528598251
Short name T666
Test name
Test status
Simulation time 5792229135 ps
CPU time 12.42 seconds
Started Oct 12 06:07:08 AM UTC 24
Finished Oct 12 06:07:21 AM UTC 24
Peak memory 243024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3528598
251 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_timeout.3528598251
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/17.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/17.i2c_target_tx_stretch_ctrl.3132845707
Short name T673
Test name
Test status
Simulation time 75949874 ps
CPU time 3.18 seconds
Started Oct 12 06:07:26 AM UTC 24
Finished Oct 12 06:07:30 AM UTC 24
Peak memory 215468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3132845
707 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_target_tx_stretch_ctrl.3132845707
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/17.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/18.i2c_alert_test.2814687885
Short name T713
Test name
Test status
Simulation time 82046390 ps
CPU time 0.89 seconds
Started Oct 12 06:08:08 AM UTC 24
Finished Oct 12 06:08:09 AM UTC 24
Peak memory 215392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2814687885 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_alert_test.2814687885
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/18.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/18.i2c_host_error_intr.1534447866
Short name T689
Test name
Test status
Simulation time 663732453 ps
CPU time 4.44 seconds
Started Oct 12 06:07:38 AM UTC 24
Finished Oct 12 06:07:44 AM UTC 24
Peak memory 225848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1534447866 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 18.i2c_host_error_intr.1534447866
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/18.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/18.i2c_host_fifo_fmt_empty.3070481670
Short name T685
Test name
Test status
Simulation time 247774017 ps
CPU time 5.64 seconds
Started Oct 12 06:07:35 AM UTC 24
Finished Oct 12 06:07:41 AM UTC 24
Peak memory 259320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3070481670 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_fmt_empty.3070481670
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/18.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/18.i2c_host_fifo_full.1254683108
Short name T730
Test name
Test status
Simulation time 2248665783 ps
CPU time 54.68 seconds
Started Oct 12 06:07:35 AM UTC 24
Finished Oct 12 06:08:31 AM UTC 24
Peak memory 562100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1254683108 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_full.1254683108
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/18.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/18.i2c_host_fifo_overflow.2508066508
Short name T815
Test name
Test status
Simulation time 5195595418 ps
CPU time 168.08 seconds
Started Oct 12 06:07:34 AM UTC 24
Finished Oct 12 06:10:25 AM UTC 24
Peak memory 826580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2508066508 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_overflow.2508066508
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/18.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/18.i2c_host_fifo_reset_fmt.697878706
Short name T684
Test name
Test status
Simulation time 226561704 ps
CPU time 1.44 seconds
Started Oct 12 06:07:35 AM UTC 24
Finished Oct 12 06:07:37 AM UTC 24
Peak memory 213332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=697878706 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_fmt.697878706
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/18.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/18.i2c_host_fifo_reset_rx.608403036
Short name T687
Test name
Test status
Simulation time 756985412 ps
CPU time 6.75 seconds
Started Oct 12 06:07:35 AM UTC 24
Finished Oct 12 06:07:43 AM UTC 24
Peak memory 251080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=608403036 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_rx.608403036
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/18.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/18.i2c_host_fifo_watermark.105021783
Short name T716
Test name
Test status
Simulation time 5157730883 ps
CPU time 68.85 seconds
Started Oct 12 06:07:34 AM UTC 24
Finished Oct 12 06:08:44 AM UTC 24
Peak memory 807864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=105021783 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_watermark.105021783
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/18.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/18.i2c_host_may_nack.3617877986
Short name T248
Test name
Test status
Simulation time 6379896280 ps
CPU time 16.21 seconds
Started Oct 12 06:08:00 AM UTC 24
Finished Oct 12 06:08:17 AM UTC 24
Peak memory 215452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3617877986 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.i2c_host_may_nack.3617877986
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/18.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/18.i2c_host_mode_toggle.2392773736
Short name T268
Test name
Test status
Simulation time 299625391 ps
CPU time 1.71 seconds
Started Oct 12 06:08:00 AM UTC 24
Finished Oct 12 06:08:02 AM UTC 24
Peak memory 215596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2392773736 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_mode_toggle.2392773736
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/18.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/18.i2c_host_override.3417779197
Short name T683
Test name
Test status
Simulation time 47275690 ps
CPU time 0.96 seconds
Started Oct 12 06:07:34 AM UTC 24
Finished Oct 12 06:07:36 AM UTC 24
Peak memory 213212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3417779197 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.i2c_host_override.3417779197
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/18.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/18.i2c_host_perf.2258274152
Short name T789
Test name
Test status
Simulation time 2658993545 ps
CPU time 134.24 seconds
Started Oct 12 06:07:35 AM UTC 24
Finished Oct 12 06:09:52 AM UTC 24
Peak memory 820148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2258274152 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 18.i2c_host_perf.2258274152
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/18.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/18.i2c_host_perf_precise.387503114
Short name T697
Test name
Test status
Simulation time 1659275866 ps
CPU time 20.21 seconds
Started Oct 12 06:07:35 AM UTC 24
Finished Oct 12 06:07:57 AM UTC 24
Peak memory 215772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=387503114 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_perf_precise.387503114
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/18.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/18.i2c_host_smoke.2999247793
Short name T706
Test name
Test status
Simulation time 1285349445 ps
CPU time 31.29 seconds
Started Oct 12 06:07:33 AM UTC 24
Finished Oct 12 06:08:06 AM UTC 24
Peak memory 336784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2999247793 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.i2c_host_smoke.2999247793
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/18.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/18.i2c_host_stretch_timeout.1974167395
Short name T690
Test name
Test status
Simulation time 3477222702 ps
CPU time 8.23 seconds
Started Oct 12 06:07:36 AM UTC 24
Finished Oct 12 06:07:46 AM UTC 24
Peak memory 232228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1974167395 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_stretch_timeout.1974167395
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/18.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/18.i2c_target_bad_addr.2671668553
Short name T708
Test name
Test status
Simulation time 3458079372 ps
CPU time 7.31 seconds
Started Oct 12 06:07:59 AM UTC 24
Finished Oct 12 06:08:07 AM UTC 24
Peak memory 225828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=2671668553 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_bad_ad
dr.2671668553
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/18.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/18.i2c_target_fifo_reset_acq.77140023
Short name T702
Test name
Test status
Simulation time 270393377 ps
CPU time 1.48 seconds
Started Oct 12 06:07:56 AM UTC 24
Finished Oct 12 06:07:59 AM UTC 24
Peak memory 215640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7714002
3 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_fifo_reset_acq.77140023
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/18.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/18.i2c_target_fifo_reset_tx.891933164
Short name T701
Test name
Test status
Simulation time 206906619 ps
CPU time 1.41 seconds
Started Oct 12 06:07:56 AM UTC 24
Finished Oct 12 06:07:59 AM UTC 24
Peak memory 213576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8919331
64 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_fifo_reset_tx.891933164
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/18.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/18.i2c_target_fifo_watermarks_acq.58009029
Short name T705
Test name
Test status
Simulation time 1875041801 ps
CPU time 3.91 seconds
Started Oct 12 06:08:00 AM UTC 24
Finished Oct 12 06:08:05 AM UTC 24
Peak memory 215580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5800902
9 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_fifo_watermarks
_acq.58009029
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/18.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/18.i2c_target_fifo_watermarks_tx.3850855130
Short name T704
Test name
Test status
Simulation time 2036274338 ps
CPU time 1.92 seconds
Started Oct 12 06:08:00 AM UTC 24
Finished Oct 12 06:08:03 AM UTC 24
Peak memory 215572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3850855
130 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_fifo_watermark
s_tx.3850855130
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/18.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/18.i2c_target_intr_smoke.3693001065
Short name T696
Test name
Test status
Simulation time 3064188593 ps
CPU time 7.63 seconds
Started Oct 12 06:07:47 AM UTC 24
Finished Oct 12 06:07:56 AM UTC 24
Peak memory 232376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=369300
1065 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_intr_smoke.3693001065
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/18.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/18.i2c_target_intr_stress_wr.3391500351
Short name T698
Test name
Test status
Simulation time 1061767886 ps
CPU time 2.16 seconds
Started Oct 12 06:07:54 AM UTC 24
Finished Oct 12 06:07:57 AM UTC 24
Peak memory 215724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3391500351 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_intr_stres
s_wr.3391500351
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/18.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/18.i2c_target_nack_acqfull.1295617800
Short name T715
Test name
Test status
Simulation time 2164537052 ps
CPU time 5.05 seconds
Started Oct 12 06:08:04 AM UTC 24
Finished Oct 12 06:08:10 AM UTC 24
Peak memory 225752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1295617
800 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_nack_acqfull.1295617800
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/18.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/18.i2c_target_nack_acqfull_addr.3574152129
Short name T719
Test name
Test status
Simulation time 2799555304 ps
CPU time 5.12 seconds
Started Oct 12 06:08:05 AM UTC 24
Finished Oct 12 06:08:12 AM UTC 24
Peak memory 215808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3574152
129 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_nack_acqfull_ad
dr.3574152129
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/18.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/18.i2c_target_nack_txstretch.1798194798
Short name T718
Test name
Test status
Simulation time 1430248506 ps
CPU time 2.43 seconds
Started Oct 12 06:08:07 AM UTC 24
Finished Oct 12 06:08:11 AM UTC 24
Peak memory 232328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1798194
798 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_nack_txstretch.1798194798
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/18.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/18.i2c_target_perf.2507595584
Short name T709
Test name
Test status
Simulation time 2242886627 ps
CPU time 9.83 seconds
Started Oct 12 06:07:56 AM UTC 24
Finished Oct 12 06:08:07 AM UTC 24
Peak memory 246660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2507595
584 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_perf.2507595584
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/18.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/18.i2c_target_smbus_maxlen.769089842
Short name T710
Test name
Test status
Simulation time 826631314 ps
CPU time 3.36 seconds
Started Oct 12 06:08:03 AM UTC 24
Finished Oct 12 06:08:07 AM UTC 24
Peak memory 215504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7690898
42 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_smbus_maxlen.769089842
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/18.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/18.i2c_target_smoke.2179900006
Short name T695
Test name
Test status
Simulation time 721965677 ps
CPU time 11.05 seconds
Started Oct 12 06:07:44 AM UTC 24
Finished Oct 12 06:07:56 AM UTC 24
Peak memory 232396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2179900006 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_smoke.2179900006
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/18.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/18.i2c_target_stress_all.930475268
Short name T909
Test name
Test status
Simulation time 90524512523 ps
CPU time 267.21 seconds
Started Oct 12 06:07:57 AM UTC 24
Finished Oct 12 06:12:28 AM UTC 24
Peak memory 1674232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=930475
268 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_stress_all.930475268
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/18.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/18.i2c_target_stress_rd.4243654405
Short name T721
Test name
Test status
Simulation time 3188407427 ps
CPU time 28.34 seconds
Started Oct 12 06:07:45 AM UTC 24
Finished Oct 12 06:08:15 AM UTC 24
Peak memory 243068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4243654405 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_stress_rd.4243654405
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/18.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/18.i2c_target_stress_wr.595775904
Short name T712
Test name
Test status
Simulation time 24660161830 ps
CPU time 24.07 seconds
Started Oct 12 06:07:44 AM UTC 24
Finished Oct 12 06:08:09 AM UTC 24
Peak memory 367556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=595775904 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_stress_wr.595775904
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/18.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/18.i2c_target_stretch.199608287
Short name T691
Test name
Test status
Simulation time 2434432033 ps
CPU time 6.56 seconds
Started Oct 12 06:07:45 AM UTC 24
Finished Oct 12 06:07:53 AM UTC 24
Peak memory 215568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=199608287 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_stretch.199608287
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/18.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/18.i2c_target_timeout.3381477126
Short name T711
Test name
Test status
Simulation time 1654366115 ps
CPU time 11.72 seconds
Started Oct 12 06:07:55 AM UTC 24
Finished Oct 12 06:08:08 AM UTC 24
Peak memory 232104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3381477
126 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_timeout.3381477126
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/18.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/18.i2c_target_tx_stretch_ctrl.3070871118
Short name T707
Test name
Test status
Simulation time 83505187 ps
CPU time 2.52 seconds
Started Oct 12 06:08:03 AM UTC 24
Finished Oct 12 06:08:07 AM UTC 24
Peak memory 215396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3070871
118 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_target_tx_stretch_ctrl.3070871118
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/18.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/19.i2c_alert_test.2554505677
Short name T740
Test name
Test status
Simulation time 40346136 ps
CPU time 0.9 seconds
Started Oct 12 06:08:44 AM UTC 24
Finished Oct 12 06:08:46 AM UTC 24
Peak memory 215628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2554505677 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_alert_test.2554505677
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/19.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/19.i2c_host_error_intr.1879137434
Short name T731
Test name
Test status
Simulation time 368947189 ps
CPU time 17.18 seconds
Started Oct 12 06:08:14 AM UTC 24
Finished Oct 12 06:08:32 AM UTC 24
Peak memory 247120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1879137434 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 19.i2c_host_error_intr.1879137434
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/19.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/19.i2c_host_fifo_fmt_empty.2329018210
Short name T723
Test name
Test status
Simulation time 295857794 ps
CPU time 8.99 seconds
Started Oct 12 06:08:10 AM UTC 24
Finished Oct 12 06:08:20 AM UTC 24
Peak memory 273784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2329018210 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_fmt_empty.2329018210
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/19.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/19.i2c_host_fifo_full.2748520568
Short name T783
Test name
Test status
Simulation time 6325075319 ps
CPU time 89.59 seconds
Started Oct 12 06:08:11 AM UTC 24
Finished Oct 12 06:09:43 AM UTC 24
Peak memory 623884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2748520568 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_full.2748520568
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/19.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/19.i2c_host_fifo_overflow.2713222106
Short name T781
Test name
Test status
Simulation time 13218163674 ps
CPU time 86.57 seconds
Started Oct 12 06:08:09 AM UTC 24
Finished Oct 12 06:09:37 AM UTC 24
Peak memory 891772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2713222106 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_overflow.2713222106
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/19.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/19.i2c_host_fifo_reset_fmt.413432338
Short name T720
Test name
Test status
Simulation time 360498882 ps
CPU time 2.09 seconds
Started Oct 12 06:08:10 AM UTC 24
Finished Oct 12 06:08:13 AM UTC 24
Peak memory 215180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=413432338 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_fmt.413432338
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/19.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/19.i2c_host_fifo_reset_rx.4067074276
Short name T724
Test name
Test status
Simulation time 144783102 ps
CPU time 9.36 seconds
Started Oct 12 06:08:11 AM UTC 24
Finished Oct 12 06:08:22 AM UTC 24
Peak memory 215524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4067074276 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_rx.4067074276
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/19.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/19.i2c_host_fifo_watermark.2411778504
Short name T794
Test name
Test status
Simulation time 6719375256 ps
CPU time 106.83 seconds
Started Oct 12 06:08:09 AM UTC 24
Finished Oct 12 06:09:58 AM UTC 24
Peak memory 1141768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2411778504 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_watermark.2411778504
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/19.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/19.i2c_host_may_nack.2537403181
Short name T249
Test name
Test status
Simulation time 1710065346 ps
CPU time 7.77 seconds
Started Oct 12 06:08:37 AM UTC 24
Finished Oct 12 06:08:45 AM UTC 24
Peak memory 215716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2537403181 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.i2c_host_may_nack.2537403181
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/19.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/19.i2c_host_override.4026058319
Short name T717
Test name
Test status
Simulation time 38679557 ps
CPU time 0.9 seconds
Started Oct 12 06:08:09 AM UTC 24
Finished Oct 12 06:08:11 AM UTC 24
Peak memory 213212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4026058319 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.i2c_host_override.4026058319
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/19.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/19.i2c_host_perf.3652144852
Short name T754
Test name
Test status
Simulation time 5338374911 ps
CPU time 57.04 seconds
Started Oct 12 06:08:11 AM UTC 24
Finished Oct 12 06:09:10 AM UTC 24
Peak memory 369672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3652144852 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 19.i2c_host_perf.3652144852
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/19.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/19.i2c_host_perf_precise.2474724150
Short name T722
Test name
Test status
Simulation time 153858495 ps
CPU time 1.78 seconds
Started Oct 12 06:08:12 AM UTC 24
Finished Oct 12 06:08:15 AM UTC 24
Peak memory 225624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2474724150 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_perf_precise.2474724150
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/19.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/19.i2c_host_smoke.4226703203
Short name T742
Test name
Test status
Simulation time 9231742627 ps
CPU time 37.52 seconds
Started Oct 12 06:08:08 AM UTC 24
Finished Oct 12 06:08:47 AM UTC 24
Peak memory 304120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4226703203 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.i2c_host_smoke.4226703203
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/19.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/19.i2c_host_stretch_timeout.3813239053
Short name T726
Test name
Test status
Simulation time 718937120 ps
CPU time 15.1 seconds
Started Oct 12 06:08:13 AM UTC 24
Finished Oct 12 06:08:29 AM UTC 24
Peak memory 231964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3813239053 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_stretch_timeout.3813239053
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/19.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/19.i2c_target_bad_addr.745592346
Short name T681
Test name
Test status
Simulation time 5797117777 ps
CPU time 9.38 seconds
Started Oct 12 06:08:33 AM UTC 24
Finished Oct 12 06:08:44 AM UTC 24
Peak memory 227880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=745592346 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_bad_addr.745592346
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/19.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/19.i2c_target_fifo_reset_tx.741391857
Short name T733
Test name
Test status
Simulation time 287988508 ps
CPU time 1.97 seconds
Started Oct 12 06:08:32 AM UTC 24
Finished Oct 12 06:08:35 AM UTC 24
Peak memory 215600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7413918
57 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_fifo_reset_tx.741391857
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/19.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/19.i2c_target_fifo_watermarks_acq.2129281634
Short name T738
Test name
Test status
Simulation time 1324103747 ps
CPU time 3.71 seconds
Started Oct 12 06:08:38 AM UTC 24
Finished Oct 12 06:08:42 AM UTC 24
Peak memory 215460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2129281
634 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_fifo_watermar
ks_acq.2129281634
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/19.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/19.i2c_target_fifo_watermarks_tx.783861570
Short name T700
Test name
Test status
Simulation time 436459302 ps
CPU time 1.77 seconds
Started Oct 12 06:08:39 AM UTC 24
Finished Oct 12 06:08:41 AM UTC 24
Peak memory 213632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7838615
70 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_fifo_watermarks
_tx.783861570
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/19.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/19.i2c_target_hrst.2516794839
Short name T735
Test name
Test status
Simulation time 1084447415 ps
CPU time 2.29 seconds
Started Oct 12 06:08:34 AM UTC 24
Finished Oct 12 06:08:38 AM UTC 24
Peak memory 232396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2516794
839 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_hrst.2516794839
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/19.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/19.i2c_target_intr_smoke.3260826847
Short name T732
Test name
Test status
Simulation time 1673873258 ps
CPU time 6.57 seconds
Started Oct 12 06:08:25 AM UTC 24
Finished Oct 12 06:08:33 AM UTC 24
Peak memory 232568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=326082
6847 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_intr_smoke.3260826847
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/19.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/19.i2c_target_intr_stress_wr.1363429085
Short name T1011
Test name
Test status
Simulation time 19900078193 ps
CPU time 387.92 seconds
Started Oct 12 06:08:28 AM UTC 24
Finished Oct 12 06:15:00 AM UTC 24
Peak memory 4947204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1363429085 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_intr_stres
s_wr.1363429085
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/19.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/19.i2c_target_nack_acqfull.1484417027
Short name T741
Test name
Test status
Simulation time 468664540 ps
CPU time 4.17 seconds
Started Oct 12 06:08:41 AM UTC 24
Finished Oct 12 06:08:46 AM UTC 24
Peak memory 225752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1484417
027 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_nack_acqfull.1484417027
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/19.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/19.i2c_target_nack_acqfull_addr.1624728363
Short name T743
Test name
Test status
Simulation time 869199935 ps
CPU time 3.63 seconds
Started Oct 12 06:08:42 AM UTC 24
Finished Oct 12 06:08:47 AM UTC 24
Peak memory 215552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1624728
363 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_nack_acqfull_ad
dr.1624728363
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/19.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/19.i2c_target_nack_txstretch.2211123944
Short name T744
Test name
Test status
Simulation time 174139395 ps
CPU time 2.61 seconds
Started Oct 12 06:08:43 AM UTC 24
Finished Oct 12 06:08:47 AM UTC 24
Peak memory 232260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2211123
944 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_nack_txstretch.2211123944
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/19.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/19.i2c_target_perf.466310959
Short name T736
Test name
Test status
Simulation time 2453477850 ps
CPU time 5.88 seconds
Started Oct 12 06:08:32 AM UTC 24
Finished Oct 12 06:08:39 AM UTC 24
Peak memory 226032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4663109
59 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_perf.466310959
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/19.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/19.i2c_target_smbus_maxlen.983375966
Short name T628
Test name
Test status
Simulation time 1727661284 ps
CPU time 3.48 seconds
Started Oct 12 06:08:40 AM UTC 24
Finished Oct 12 06:08:44 AM UTC 24
Peak memory 215500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9833759
66 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_smbus_maxlen.983375966
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/19.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/19.i2c_target_smoke.2796175810
Short name T729
Test name
Test status
Simulation time 4214718263 ps
CPU time 13.84 seconds
Started Oct 12 06:08:16 AM UTC 24
Finished Oct 12 06:08:31 AM UTC 24
Peak memory 232520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2796175810 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_smoke.2796175810
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/19.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/19.i2c_target_stress_all.2104032333
Short name T876
Test name
Test status
Simulation time 30802332848 ps
CPU time 188.36 seconds
Started Oct 12 06:08:33 AM UTC 24
Finished Oct 12 06:11:44 AM UTC 24
Peak memory 2100228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=210403
2333 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_stress_all.2104032333
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/19.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/19.i2c_target_stress_rd.589303434
Short name T725
Test name
Test status
Simulation time 241851436 ps
CPU time 5.01 seconds
Started Oct 12 06:08:21 AM UTC 24
Finished Oct 12 06:08:27 AM UTC 24
Peak memory 215524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=589303434 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_stress_rd.589303434
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/19.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/19.i2c_target_stress_wr.3503143801
Short name T773
Test name
Test status
Simulation time 23427656456 ps
CPU time 72.13 seconds
Started Oct 12 06:08:18 AM UTC 24
Finished Oct 12 06:09:32 AM UTC 24
Peak memory 965700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3503143801 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_stress_wr.3503143801
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/19.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/19.i2c_target_stretch.1636350535
Short name T728
Test name
Test status
Simulation time 3469246474 ps
CPU time 7.41 seconds
Started Oct 12 06:08:22 AM UTC 24
Finished Oct 12 06:08:31 AM UTC 24
Peak memory 225900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1636350535 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_stretch.1636350535
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/19.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/19.i2c_target_timeout.3727884
Short name T692
Test name
Test status
Simulation time 1407556995 ps
CPU time 13.49 seconds
Started Oct 12 06:08:30 AM UTC 24
Finished Oct 12 06:08:44 AM UTC 24
Peak memory 244984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3727884
-assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_timeout.3727884
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/19.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/19.i2c_target_tx_stretch_ctrl.1797405522
Short name T739
Test name
Test status
Simulation time 163665720 ps
CPU time 4.45 seconds
Started Oct 12 06:08:40 AM UTC 24
Finished Oct 12 06:08:45 AM UTC 24
Peak memory 215724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1797405
522 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_target_tx_stretch_ctrl.1797405522
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/19.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/2.i2c_alert_test.1933134944
Short name T101
Test name
Test status
Simulation time 16700680 ps
CPU time 0.87 seconds
Started Oct 12 05:55:43 AM UTC 24
Finished Oct 12 05:55:45 AM UTC 24
Peak memory 213392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1933134944 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_alert_test.1933134944
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/2.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/2.i2c_host_fifo_fmt_empty.3978056911
Short name T296
Test name
Test status
Simulation time 337256730 ps
CPU time 11.69 seconds
Started Oct 12 05:55:09 AM UTC 24
Finished Oct 12 05:55:22 AM UTC 24
Peak memory 271240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3978056911 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_fmt_empty.3978056911
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/2.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/2.i2c_host_fifo_full.2456549449
Short name T159
Test name
Test status
Simulation time 5672012376 ps
CPU time 96.1 seconds
Started Oct 12 05:55:11 AM UTC 24
Finished Oct 12 05:56:49 AM UTC 24
Peak memory 486276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2456549449 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_full.2456549449
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/2.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/2.i2c_host_fifo_overflow.3447851431
Short name T104
Test name
Test status
Simulation time 2253153554 ps
CPU time 78.25 seconds
Started Oct 12 05:55:08 AM UTC 24
Finished Oct 12 05:56:28 AM UTC 24
Peak memory 789824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3447851431 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_overflow.3447851431
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/2.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/2.i2c_host_fifo_reset_fmt.1069115940
Short name T32
Test name
Test status
Simulation time 153775608 ps
CPU time 1.4 seconds
Started Oct 12 05:55:09 AM UTC 24
Finished Oct 12 05:55:11 AM UTC 24
Peak memory 213264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1069115940 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_fmt.1069115940
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/2.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/2.i2c_host_fifo_reset_rx.917098827
Short name T40
Test name
Test status
Simulation time 1359977149 ps
CPU time 8.87 seconds
Started Oct 12 05:55:11 AM UTC 24
Finished Oct 12 05:55:20 AM UTC 24
Peak memory 215452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=917098827 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_rx.917098827
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/2.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/2.i2c_host_fifo_watermark.5877703
Short name T82
Test name
Test status
Simulation time 7029621363 ps
CPU time 130.61 seconds
Started Oct 12 05:55:08 AM UTC 24
Finished Oct 12 05:57:21 AM UTC 24
Peak memory 1524608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5877703 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_hos
t_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_watermark.5877703
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/2.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/2.i2c_host_may_nack.3290319207
Short name T13
Test name
Test status
Simulation time 681059456 ps
CPU time 16.31 seconds
Started Oct 12 05:55:37 AM UTC 24
Finished Oct 12 05:55:55 AM UTC 24
Peak memory 215444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3290319207 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.i2c_host_may_nack.3290319207
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/2.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/2.i2c_host_perf.1202666411
Short name T301
Test name
Test status
Simulation time 1143923679 ps
CPU time 20.17 seconds
Started Oct 12 05:55:11 AM UTC 24
Finished Oct 12 05:55:32 AM UTC 24
Peak memory 365708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1202666411 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 2.i2c_host_perf.1202666411
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/2.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/2.i2c_host_perf_precise.3887588322
Short name T146
Test name
Test status
Simulation time 289179211 ps
CPU time 5.48 seconds
Started Oct 12 05:55:11 AM UTC 24
Finished Oct 12 05:55:17 AM UTC 24
Peak memory 273148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3887588322 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_perf_precise.3887588322
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/2.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/2.i2c_host_smoke.3355568820
Short name T269
Test name
Test status
Simulation time 1508163623 ps
CPU time 30.44 seconds
Started Oct 12 05:55:05 AM UTC 24
Finished Oct 12 05:55:37 AM UTC 24
Peak memory 396092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3355568820 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.i2c_host_smoke.3355568820
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/2.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/2.i2c_host_stretch_timeout.3068403488
Short name T147
Test name
Test status
Simulation time 552836124 ps
CPU time 13.09 seconds
Started Oct 12 05:55:11 AM UTC 24
Finished Oct 12 05:55:25 AM UTC 24
Peak memory 232248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3068403488 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_stretch_timeout.3068403488
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/2.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/2.i2c_sec_cm.421261605
Short name T186
Test name
Test status
Simulation time 64065340 ps
CPU time 1.56 seconds
Started Oct 12 05:55:43 AM UTC 24
Finished Oct 12 05:55:46 AM UTC 24
Peak memory 244936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=421261605 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_sec_cm.421261605
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/2.i2c_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/2.i2c_target_bad_addr.3987092245
Short name T67
Test name
Test status
Simulation time 1950816027 ps
CPU time 6.41 seconds
Started Oct 12 05:55:32 AM UTC 24
Finished Oct 12 05:55:39 AM UTC 24
Peak memory 225768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=3987092245 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_bad_addr.3987092245
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/2.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/2.i2c_target_fifo_reset_acq.966860299
Short name T148
Test name
Test status
Simulation time 349835046 ps
CPU time 2.31 seconds
Started Oct 12 05:55:27 AM UTC 24
Finished Oct 12 05:55:30 AM UTC 24
Peak memory 215396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9668602
99 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_fifo_reset_acq.966860299
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/2.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/2.i2c_target_fifo_reset_tx.1730372022
Short name T150
Test name
Test status
Simulation time 217657706 ps
CPU time 1.22 seconds
Started Oct 12 05:55:29 AM UTC 24
Finished Oct 12 05:55:31 AM UTC 24
Peak memory 225492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1730372
022 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_fifo_reset_tx.1730372022
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/2.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/2.i2c_target_fifo_watermarks_acq.4211250040
Short name T276
Test name
Test status
Simulation time 1213529560 ps
CPU time 3.88 seconds
Started Oct 12 05:55:38 AM UTC 24
Finished Oct 12 05:55:43 AM UTC 24
Peak memory 215772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4211250
040 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_fifo_watermark
s_acq.4211250040
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/2.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/2.i2c_target_fifo_watermarks_tx.293189549
Short name T305
Test name
Test status
Simulation time 311798701 ps
CPU time 2.4 seconds
Started Oct 12 05:55:39 AM UTC 24
Finished Oct 12 05:55:42 AM UTC 24
Peak memory 215256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2931895
49 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_fifo_watermarks_tx.293189549
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/2.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/2.i2c_target_intr_smoke.894757786
Short name T300
Test name
Test status
Simulation time 1057369473 ps
CPU time 8.8 seconds
Started Oct 12 05:55:21 AM UTC 24
Finished Oct 12 05:55:31 AM UTC 24
Peak memory 225696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=894757
786 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_intr_smoke.894757786
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/2.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/2.i2c_target_intr_stress_wr.3158341184
Short name T52
Test name
Test status
Simulation time 9566937918 ps
CPU time 41.56 seconds
Started Oct 12 05:55:22 AM UTC 24
Finished Oct 12 05:56:05 AM UTC 24
Peak memory 676808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3158341184 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_intr_stress
_wr.3158341184
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/2.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/2.i2c_target_nack_acqfull.3141109218
Short name T155
Test name
Test status
Simulation time 2384393535 ps
CPU time 4.02 seconds
Started Oct 12 05:55:40 AM UTC 24
Finished Oct 12 05:55:45 AM UTC 24
Peak memory 226024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3141109
218 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_nack_acqfull.3141109218
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/2.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/2.i2c_target_nack_acqfull_addr.513608052
Short name T68
Test name
Test status
Simulation time 1726738224 ps
CPU time 4.16 seconds
Started Oct 12 05:55:40 AM UTC 24
Finished Oct 12 05:55:45 AM UTC 24
Peak memory 215488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5136080
52 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_nack_acqfull_addr.513608052
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/2.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/2.i2c_target_nack_txstretch.177602835
Short name T61
Test name
Test status
Simulation time 937172056 ps
CPU time 2.82 seconds
Started Oct 12 05:55:41 AM UTC 24
Finished Oct 12 05:55:45 AM UTC 24
Peak memory 232684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1776028
35 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_nack_txstretch.177602835
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/2.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/2.i2c_target_perf.1045934039
Short name T303
Test name
Test status
Simulation time 2084443565 ps
CPU time 4.06 seconds
Started Oct 12 05:55:31 AM UTC 24
Finished Oct 12 05:55:36 AM UTC 24
Peak memory 225964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1045934
039 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_perf.1045934039
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/2.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/2.i2c_target_smbus_maxlen.4211509893
Short name T43
Test name
Test status
Simulation time 1075045310 ps
CPU time 3.98 seconds
Started Oct 12 05:55:39 AM UTC 24
Finished Oct 12 05:55:44 AM UTC 24
Peak memory 215172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4211509
893 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_smbus_maxlen.4211509893
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/2.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/2.i2c_target_smoke.3784219418
Short name T149
Test name
Test status
Simulation time 997516237 ps
CPU time 17.15 seconds
Started Oct 12 05:55:12 AM UTC 24
Finished Oct 12 05:55:30 AM UTC 24
Peak memory 232596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3784219418 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_smoke.3784219418
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/2.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/2.i2c_target_stress_all.2006722039
Short name T59
Test name
Test status
Simulation time 52733597208 ps
CPU time 195.42 seconds
Started Oct 12 05:55:31 AM UTC 24
Finished Oct 12 05:58:49 AM UTC 24
Peak memory 1436540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=200672
2039 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_stress_all.2006722039
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/2.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/2.i2c_target_stress_rd.2923832038
Short name T265
Test name
Test status
Simulation time 1309799781 ps
CPU time 59 seconds
Started Oct 12 05:55:17 AM UTC 24
Finished Oct 12 05:56:18 AM UTC 24
Peak memory 225684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2923832038 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_stress_rd.2923832038
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/2.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/2.i2c_target_stress_wr.3677065908
Short name T1020
Test name
Test status
Simulation time 59792145382 ps
CPU time 1187.17 seconds
Started Oct 12 05:55:12 AM UTC 24
Finished Oct 12 06:15:10 AM UTC 24
Peak memory 10017988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3677065908 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_stress_wr.3677065908
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/2.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/2.i2c_target_timeout.3091601973
Short name T302
Test name
Test status
Simulation time 3842829904 ps
CPU time 7.65 seconds
Started Oct 12 05:55:24 AM UTC 24
Finished Oct 12 05:55:33 AM UTC 24
Peak memory 232780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3091601
973 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_timeout.3091601973
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/2.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/2.i2c_target_tx_stretch_ctrl.287426204
Short name T289
Test name
Test status
Simulation time 816712490 ps
CPU time 18.6 seconds
Started Oct 12 05:55:39 AM UTC 24
Finished Oct 12 05:55:59 AM UTC 24
Peak memory 215396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2874262
04 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_target_tx_stretch_ctrl.287426204
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/2.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/20.i2c_alert_test.3845784187
Short name T771
Test name
Test status
Simulation time 87932253 ps
CPU time 0.88 seconds
Started Oct 12 06:09:29 AM UTC 24
Finished Oct 12 06:09:31 AM UTC 24
Peak memory 215628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3845784187 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_alert_test.3845784187
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/20.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/20.i2c_host_error_intr.1501742944
Short name T749
Test name
Test status
Simulation time 83107131 ps
CPU time 2.18 seconds
Started Oct 12 06:08:50 AM UTC 24
Finished Oct 12 06:08:53 AM UTC 24
Peak memory 226112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1501742944 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 20.i2c_host_error_intr.1501742944
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/20.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/20.i2c_host_fifo_fmt_empty.53748101
Short name T750
Test name
Test status
Simulation time 1541673344 ps
CPU time 10.93 seconds
Started Oct 12 06:08:47 AM UTC 24
Finished Oct 12 06:08:59 AM UTC 24
Peak memory 306152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=53748101 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_fmt_empty.53748101
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/20.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/20.i2c_host_fifo_full.3776204489
Short name T790
Test name
Test status
Simulation time 1946233204 ps
CPU time 65.62 seconds
Started Oct 12 06:08:48 AM UTC 24
Finished Oct 12 06:09:55 AM UTC 24
Peak memory 517076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3776204489 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_full.3776204489
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/20.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/20.i2c_host_fifo_overflow.1577350201
Short name T784
Test name
Test status
Simulation time 1687763525 ps
CPU time 58.55 seconds
Started Oct 12 06:08:47 AM UTC 24
Finished Oct 12 06:09:47 AM UTC 24
Peak memory 564176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1577350201 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_overflow.1577350201
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/20.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/20.i2c_host_fifo_reset_fmt.188697382
Short name T746
Test name
Test status
Simulation time 476012696 ps
CPU time 1.72 seconds
Started Oct 12 06:08:47 AM UTC 24
Finished Oct 12 06:08:49 AM UTC 24
Peak memory 213332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=188697382 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_fmt.188697382
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/20.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/20.i2c_host_fifo_reset_rx.1741762192
Short name T748
Test name
Test status
Simulation time 925332437 ps
CPU time 5.41 seconds
Started Oct 12 06:08:47 AM UTC 24
Finished Oct 12 06:08:53 AM UTC 24
Peak memory 215548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1741762192 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_rx.1741762192
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/20.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/20.i2c_host_fifo_watermark.217698231
Short name T118
Test name
Test status
Simulation time 5516034574 ps
CPU time 67.74 seconds
Started Oct 12 06:08:46 AM UTC 24
Finished Oct 12 06:09:55 AM UTC 24
Peak memory 891776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=217698231 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_watermark.217698231
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/20.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/20.i2c_host_may_nack.2908715765
Short name T257
Test name
Test status
Simulation time 1918250010 ps
CPU time 24.59 seconds
Started Oct 12 06:09:22 AM UTC 24
Finished Oct 12 06:09:48 AM UTC 24
Peak memory 215444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2908715765 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.i2c_host_may_nack.2908715765
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/20.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/20.i2c_host_mode_toggle.2312765919
Short name T765
Test name
Test status
Simulation time 156705813 ps
CPU time 3.25 seconds
Started Oct 12 06:09:21 AM UTC 24
Finished Oct 12 06:09:26 AM UTC 24
Peak memory 229736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2312765919 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_mode_toggle.2312765919
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/20.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/20.i2c_host_override.4093035479
Short name T745
Test name
Test status
Simulation time 29054940 ps
CPU time 1.02 seconds
Started Oct 12 06:08:45 AM UTC 24
Finished Oct 12 06:08:47 AM UTC 24
Peak memory 213212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4093035479 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.i2c_host_override.4093035479
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/20.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/20.i2c_host_perf.2772475810
Short name T753
Test name
Test status
Simulation time 712350798 ps
CPU time 19.82 seconds
Started Oct 12 06:08:48 AM UTC 24
Finished Oct 12 06:09:09 AM UTC 24
Peak memory 215388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2772475810 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 20.i2c_host_perf.2772475810
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/20.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/20.i2c_host_perf_precise.2149409799
Short name T747
Test name
Test status
Simulation time 93482308 ps
CPU time 1.71 seconds
Started Oct 12 06:08:48 AM UTC 24
Finished Oct 12 06:08:51 AM UTC 24
Peak memory 235596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2149409799 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_perf_precise.2149409799
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/20.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/20.i2c_host_smoke.60599029
Short name T757
Test name
Test status
Simulation time 22536309522 ps
CPU time 26.2 seconds
Started Oct 12 06:08:45 AM UTC 24
Finished Oct 12 06:09:13 AM UTC 24
Peak memory 373952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=60599029 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ho
st_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 20.i2c_host_smoke.60599029
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/20.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/20.i2c_host_stress_all.1736599662
Short name T1410
Test name
Test status
Simulation time 51451963038 ps
CPU time 817.14 seconds
Started Oct 12 06:08:51 AM UTC 24
Finished Oct 12 06:22:38 AM UTC 24
Peak memory 1967064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1736599662 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 20.i2c_host_stress_all.1736599662
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/20.i2c_host_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/20.i2c_host_stretch_timeout.758882082
Short name T751
Test name
Test status
Simulation time 495882005 ps
CPU time 13.81 seconds
Started Oct 12 06:08:48 AM UTC 24
Finished Oct 12 06:09:03 AM UTC 24
Peak memory 226148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=758882082 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_stretch_timeout.758882082
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/20.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/20.i2c_target_bad_addr.3514230455
Short name T770
Test name
Test status
Simulation time 4587243761 ps
CPU time 10.75 seconds
Started Oct 12 06:09:16 AM UTC 24
Finished Oct 12 06:09:28 AM UTC 24
Peak memory 225768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=3514230455 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_bad_ad
dr.3514230455
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/20.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/20.i2c_target_fifo_reset_acq.2125313764
Short name T759
Test name
Test status
Simulation time 201652723 ps
CPU time 1.67 seconds
Started Oct 12 06:09:12 AM UTC 24
Finished Oct 12 06:09:15 AM UTC 24
Peak memory 215636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2125313
764 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_fifo_reset_acq.2125313764
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/20.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/20.i2c_target_fifo_reset_tx.2250438633
Short name T760
Test name
Test status
Simulation time 201053486 ps
CPU time 1.94 seconds
Started Oct 12 06:09:14 AM UTC 24
Finished Oct 12 06:09:17 AM UTC 24
Peak memory 215596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2250438
633 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_fifo_reset_tx.2250438633
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/20.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/20.i2c_target_fifo_watermarks_acq.3477598157
Short name T769
Test name
Test status
Simulation time 1412469854 ps
CPU time 3.42 seconds
Started Oct 12 06:09:23 AM UTC 24
Finished Oct 12 06:09:28 AM UTC 24
Peak memory 215168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3477598
157 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_fifo_watermar
ks_acq.3477598157
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/20.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/20.i2c_target_fifo_watermarks_tx.1691280247
Short name T768
Test name
Test status
Simulation time 224631529 ps
CPU time 1.42 seconds
Started Oct 12 06:09:24 AM UTC 24
Finished Oct 12 06:09:27 AM UTC 24
Peak memory 213628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1691280
247 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_fifo_watermark
s_tx.1691280247
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/20.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/20.i2c_target_hrst.735878630
Short name T763
Test name
Test status
Simulation time 3786502456 ps
CPU time 3.2 seconds
Started Oct 12 06:09:18 AM UTC 24
Finished Oct 12 06:09:22 AM UTC 24
Peak memory 215540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7358786
30 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_hrst.735878630
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/20.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/20.i2c_target_intr_smoke.2573696565
Short name T755
Test name
Test status
Simulation time 625193287 ps
CPU time 6.83 seconds
Started Oct 12 06:09:04 AM UTC 24
Finished Oct 12 06:09:12 AM UTC 24
Peak memory 225768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=257369
6565 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_intr_smoke.2573696565
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/20.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/20.i2c_target_intr_stress_wr.1201670369
Short name T780
Test name
Test status
Simulation time 10537063417 ps
CPU time 27.02 seconds
Started Oct 12 06:09:09 AM UTC 24
Finished Oct 12 06:09:37 AM UTC 24
Peak memory 857032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1201670369 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_intr_stres
s_wr.1201670369
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/20.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/20.i2c_target_nack_acqfull.2341587052
Short name T774
Test name
Test status
Simulation time 1616921716 ps
CPU time 3.26 seconds
Started Oct 12 06:09:28 AM UTC 24
Finished Oct 12 06:09:32 AM UTC 24
Peak memory 225664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2341587
052 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_nack_acqfull.2341587052
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/20.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/20.i2c_target_nack_acqfull_addr.2772684793
Short name T776
Test name
Test status
Simulation time 1555070862 ps
CPU time 3.68 seconds
Started Oct 12 06:09:28 AM UTC 24
Finished Oct 12 06:09:32 AM UTC 24
Peak memory 215604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2772684
793 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_nack_acqfull_ad
dr.2772684793
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/20.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/20.i2c_target_perf.2906372396
Short name T767
Test name
Test status
Simulation time 957167592 ps
CPU time 11.28 seconds
Started Oct 12 06:09:14 AM UTC 24
Finished Oct 12 06:09:26 AM UTC 24
Peak memory 225960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2906372
396 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_perf.2906372396
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/20.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/20.i2c_target_smbus_maxlen.1650976715
Short name T772
Test name
Test status
Simulation time 2323571101 ps
CPU time 4.06 seconds
Started Oct 12 06:09:26 AM UTC 24
Finished Oct 12 06:09:32 AM UTC 24
Peak memory 215312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1650976
715 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_smbus_maxlen.1650976715
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/20.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/20.i2c_target_smoke.590481089
Short name T762
Test name
Test status
Simulation time 1589759304 ps
CPU time 25.27 seconds
Started Oct 12 06:08:55 AM UTC 24
Finished Oct 12 06:09:21 AM UTC 24
Peak memory 225972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=590481089 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_smoke.590481089
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/20.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/20.i2c_target_stress_all.4232179565
Short name T788
Test name
Test status
Simulation time 10199868463 ps
CPU time 34.05 seconds
Started Oct 12 06:09:16 AM UTC 24
Finished Oct 12 06:09:52 AM UTC 24
Peak memory 281476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=423217
9565 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_stress_all.4232179565
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/20.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/20.i2c_target_stress_rd.3691277521
Short name T782
Test name
Test status
Simulation time 919159075 ps
CPU time 45.42 seconds
Started Oct 12 06:08:56 AM UTC 24
Finished Oct 12 06:09:43 AM UTC 24
Peak memory 225744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3691277521 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_stress_rd.3691277521
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/20.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/20.i2c_target_stress_wr.981353365
Short name T1091
Test name
Test status
Simulation time 42147325820 ps
CPU time 448.7 seconds
Started Oct 12 06:08:55 AM UTC 24
Finished Oct 12 06:16:28 AM UTC 24
Peak memory 5868420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=981353365 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_stress_wr.981353365
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/20.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/20.i2c_target_stretch.2589734493
Short name T761
Test name
Test status
Simulation time 3474247633 ps
CPU time 18.18 seconds
Started Oct 12 06:09:00 AM UTC 24
Finished Oct 12 06:09:20 AM UTC 24
Peak memory 345348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2589734493 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_stretch.2589734493
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/20.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/20.i2c_target_timeout.3732824109
Short name T764
Test name
Test status
Simulation time 5942500141 ps
CPU time 12.56 seconds
Started Oct 12 06:09:10 AM UTC 24
Finished Oct 12 06:09:24 AM UTC 24
Peak memory 232164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3732824
109 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_timeout.3732824109
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/20.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/20.i2c_target_tx_stretch_ctrl.3364666066
Short name T777
Test name
Test status
Simulation time 297938955 ps
CPU time 6.84 seconds
Started Oct 12 06:09:26 AM UTC 24
Finished Oct 12 06:09:34 AM UTC 24
Peak memory 225684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3364666
066 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_target_tx_stretch_ctrl.3364666066
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/20.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/21.i2c_alert_test.3599716899
Short name T809
Test name
Test status
Simulation time 18367359 ps
CPU time 1.04 seconds
Started Oct 12 06:10:05 AM UTC 24
Finished Oct 12 06:10:07 AM UTC 24
Peak memory 215628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3599716899 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_alert_test.3599716899
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/21.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/21.i2c_host_error_intr.2777529454
Short name T786
Test name
Test status
Simulation time 196886727 ps
CPU time 4.29 seconds
Started Oct 12 06:09:44 AM UTC 24
Finished Oct 12 06:09:49 AM UTC 24
Peak memory 225796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2777529454 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 21.i2c_host_error_intr.2777529454
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/21.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/21.i2c_host_fifo_fmt_empty.1329456879
Short name T791
Test name
Test status
Simulation time 336845130 ps
CPU time 20.8 seconds
Started Oct 12 06:09:33 AM UTC 24
Finished Oct 12 06:09:56 AM UTC 24
Peak memory 267464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1329456879 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_fmt_empty.1329456879
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/21.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/21.i2c_host_fifo_full.1326359415
Short name T832
Test name
Test status
Simulation time 3028263810 ps
CPU time 69.07 seconds
Started Oct 12 06:09:37 AM UTC 24
Finished Oct 12 06:10:48 AM UTC 24
Peak memory 445372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1326359415 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_full.1326359415
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/21.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/21.i2c_host_fifo_overflow.2469250519
Short name T816
Test name
Test status
Simulation time 1518273973 ps
CPU time 49.89 seconds
Started Oct 12 06:09:33 AM UTC 24
Finished Oct 12 06:10:25 AM UTC 24
Peak memory 594752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2469250519 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_overflow.2469250519
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/21.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/21.i2c_host_fifo_reset_fmt.3786992343
Short name T779
Test name
Test status
Simulation time 517164188 ps
CPU time 1.73 seconds
Started Oct 12 06:09:33 AM UTC 24
Finished Oct 12 06:09:36 AM UTC 24
Peak memory 215716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3786992343 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_fmt.3786992343
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/21.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/21.i2c_host_fifo_reset_rx.978094480
Short name T787
Test name
Test status
Simulation time 416933312 ps
CPU time 13.83 seconds
Started Oct 12 06:09:35 AM UTC 24
Finished Oct 12 06:09:51 AM UTC 24
Peak memory 259020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=978094480 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_rx.978094480
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/21.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/21.i2c_host_fifo_watermark.2836313449
Short name T986
Test name
Test status
Simulation time 21518642183 ps
CPU time 305.73 seconds
Started Oct 12 06:09:33 AM UTC 24
Finished Oct 12 06:14:43 AM UTC 24
Peak memory 1510664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2836313449 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_watermark.2836313449
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/21.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/21.i2c_host_may_nack.3451536377
Short name T811
Test name
Test status
Simulation time 1642134802 ps
CPU time 7.83 seconds
Started Oct 12 06:10:00 AM UTC 24
Finished Oct 12 06:10:09 AM UTC 24
Peak memory 215456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3451536377 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.i2c_host_may_nack.3451536377
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/21.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/21.i2c_host_override.999170687
Short name T778
Test name
Test status
Simulation time 41759216 ps
CPU time 1.05 seconds
Started Oct 12 06:09:33 AM UTC 24
Finished Oct 12 06:09:36 AM UTC 24
Peak memory 213212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=999170687 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 21.i2c_host_override.999170687
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/21.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/21.i2c_host_perf.4246380422
Short name T851
Test name
Test status
Simulation time 6682214881 ps
CPU time 86.08 seconds
Started Oct 12 06:09:38 AM UTC 24
Finished Oct 12 06:11:06 AM UTC 24
Peak memory 361540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4246380422 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 21.i2c_host_perf.4246380422
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/21.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/21.i2c_host_perf_precise.3172071923
Short name T796
Test name
Test status
Simulation time 856707674 ps
CPU time 37.43 seconds
Started Oct 12 06:09:39 AM UTC 24
Finished Oct 12 06:10:18 AM UTC 24
Peak memory 334984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3172071923 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_perf_precise.3172071923
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/21.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/21.i2c_host_smoke.1029876917
Short name T805
Test name
Test status
Simulation time 3122652909 ps
CPU time 31.21 seconds
Started Oct 12 06:09:32 AM UTC 24
Finished Oct 12 06:10:05 AM UTC 24
Peak memory 316492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1029876917 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 21.i2c_host_smoke.1029876917
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/21.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/21.i2c_host_stretch_timeout.1870609012
Short name T795
Test name
Test status
Simulation time 1747245606 ps
CPU time 17.87 seconds
Started Oct 12 06:09:39 AM UTC 24
Finished Oct 12 06:09:58 AM UTC 24
Peak memory 232224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1870609012 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_stretch_timeout.1870609012
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/21.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/21.i2c_target_bad_addr.140584290
Short name T807
Test name
Test status
Simulation time 1330535748 ps
CPU time 6.17 seconds
Started Oct 12 06:09:58 AM UTC 24
Finished Oct 12 06:10:06 AM UTC 24
Peak memory 229800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=140584290 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_bad_addr.140584290
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/21.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/21.i2c_target_fifo_reset_acq.293256660
Short name T798
Test name
Test status
Simulation time 185703157 ps
CPU time 2.04 seconds
Started Oct 12 06:09:56 AM UTC 24
Finished Oct 12 06:09:59 AM UTC 24
Peak memory 215216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2932566
60 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_fifo_reset_acq.293256660
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/21.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/21.i2c_target_fifo_reset_tx.2618741024
Short name T797
Test name
Test status
Simulation time 1164263151 ps
CPU time 2.03 seconds
Started Oct 12 06:09:56 AM UTC 24
Finished Oct 12 06:09:59 AM UTC 24
Peak memory 215512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2618741
024 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_fifo_reset_tx.2618741024
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/21.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/21.i2c_target_fifo_watermarks_acq.964836068
Short name T802
Test name
Test status
Simulation time 675343021 ps
CPU time 3.57 seconds
Started Oct 12 06:10:00 AM UTC 24
Finished Oct 12 06:10:04 AM UTC 24
Peak memory 215448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9648360
68 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_fifo_watermark
s_acq.964836068
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/21.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/21.i2c_target_fifo_watermarks_tx.1089268529
Short name T800
Test name
Test status
Simulation time 554828553 ps
CPU time 2.27 seconds
Started Oct 12 06:10:00 AM UTC 24
Finished Oct 12 06:10:03 AM UTC 24
Peak memory 215252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1089268
529 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_fifo_watermark
s_tx.1089268529
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/21.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/21.i2c_target_intr_smoke.2237277923
Short name T799
Test name
Test status
Simulation time 1812233222 ps
CPU time 9.57 seconds
Started Oct 12 06:09:51 AM UTC 24
Finished Oct 12 06:10:02 AM UTC 24
Peak memory 229864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=223727
7923 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_intr_smoke.2237277923
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/21.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/21.i2c_target_intr_stress_wr.1705230192
Short name T830
Test name
Test status
Simulation time 21532305037 ps
CPU time 52.08 seconds
Started Oct 12 06:09:53 AM UTC 24
Finished Oct 12 06:10:47 AM UTC 24
Peak memory 1080192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1705230192 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_intr_stres
s_wr.1705230192
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/21.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/21.i2c_target_nack_acqfull.2433928532
Short name T803
Test name
Test status
Simulation time 2589225129 ps
CPU time 4.42 seconds
Started Oct 12 06:10:04 AM UTC 24
Finished Oct 12 06:10:10 AM UTC 24
Peak memory 225776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2433928
532 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_nack_acqfull.2433928532
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/21.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/21.i2c_target_nack_acqfull_addr.429776892
Short name T775
Test name
Test status
Simulation time 499994917 ps
CPU time 4.27 seconds
Started Oct 12 06:10:05 AM UTC 24
Finished Oct 12 06:10:11 AM UTC 24
Peak memory 215412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4297768
92 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_nack_acqfull_addr.429776892
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/21.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/21.i2c_target_nack_txstretch.2892526096
Short name T812
Test name
Test status
Simulation time 736895264 ps
CPU time 2.37 seconds
Started Oct 12 06:10:05 AM UTC 24
Finished Oct 12 06:10:09 AM UTC 24
Peak memory 232392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2892526
096 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_nack_txstretch.2892526096
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/21.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/21.i2c_target_perf.1937197610
Short name T806
Test name
Test status
Simulation time 3203276839 ps
CPU time 8.22 seconds
Started Oct 12 06:09:56 AM UTC 24
Finished Oct 12 06:10:06 AM UTC 24
Peak memory 226012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1937197
610 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_perf.1937197610
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/21.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/21.i2c_target_smbus_maxlen.2647620789
Short name T810
Test name
Test status
Simulation time 1671921165 ps
CPU time 3.15 seconds
Started Oct 12 06:10:04 AM UTC 24
Finished Oct 12 06:10:08 AM UTC 24
Peak memory 215172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2647620
789 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_smbus_maxlen.2647620789
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/21.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/21.i2c_target_smoke.1780759368
Short name T817
Test name
Test status
Simulation time 5016095952 ps
CPU time 37.69 seconds
Started Oct 12 06:09:48 AM UTC 24
Finished Oct 12 06:10:27 AM UTC 24
Peak memory 232460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1780759368 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_smoke.1780759368
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/21.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/21.i2c_target_stress_all.2994681269
Short name T1089
Test name
Test status
Simulation time 68065257950 ps
CPU time 381.62 seconds
Started Oct 12 06:09:58 AM UTC 24
Finished Oct 12 06:16:24 AM UTC 24
Peak memory 3077204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=299468
1269 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_stress_all.2994681269
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/21.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/21.i2c_target_stress_rd.2634967633
Short name T792
Test name
Test status
Simulation time 348014673 ps
CPU time 6.61 seconds
Started Oct 12 06:09:49 AM UTC 24
Finished Oct 12 06:09:57 AM UTC 24
Peak memory 215388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2634967633 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_stress_rd.2634967633
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/21.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/21.i2c_target_stress_wr.3585927719
Short name T793
Test name
Test status
Simulation time 15110683784 ps
CPU time 7.89 seconds
Started Oct 12 06:09:48 AM UTC 24
Finished Oct 12 06:09:57 AM UTC 24
Peak memory 215968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3585927719 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_stress_wr.3585927719
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/21.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/21.i2c_target_stretch.3369045009
Short name T818
Test name
Test status
Simulation time 1796115440 ps
CPU time 37.86 seconds
Started Oct 12 06:09:50 AM UTC 24
Finished Oct 12 06:10:30 AM UTC 24
Peak memory 611272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3369045009 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_stretch.3369045009
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/21.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/21.i2c_target_timeout.1244744777
Short name T801
Test name
Test status
Simulation time 1441202869 ps
CPU time 9.61 seconds
Started Oct 12 06:09:53 AM UTC 24
Finished Oct 12 06:10:03 AM UTC 24
Peak memory 232592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1244744
777 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_timeout.1244744777
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/21.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/21.i2c_target_tx_stretch_ctrl.2501487897
Short name T808
Test name
Test status
Simulation time 51756421 ps
CPU time 1.74 seconds
Started Oct 12 06:10:03 AM UTC 24
Finished Oct 12 06:10:06 AM UTC 24
Peak memory 215532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2501487
897 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_target_tx_stretch_ctrl.2501487897
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/21.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/22.i2c_alert_test.3365738032
Short name T837
Test name
Test status
Simulation time 18246470 ps
CPU time 0.91 seconds
Started Oct 12 06:10:49 AM UTC 24
Finished Oct 12 06:10:51 AM UTC 24
Peak memory 215628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3365738032 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_alert_test.3365738032
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/22.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/22.i2c_host_error_intr.279197969
Short name T804
Test name
Test status
Simulation time 163456668 ps
CPU time 6.04 seconds
Started Oct 12 06:10:11 AM UTC 24
Finished Oct 12 06:10:19 AM UTC 24
Peak memory 229944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=279197969 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 22.i2c_host_error_intr.279197969
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/22.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/22.i2c_host_fifo_fmt_empty.3481268555
Short name T814
Test name
Test status
Simulation time 899684498 ps
CPU time 10.74 seconds
Started Oct 12 06:10:09 AM UTC 24
Finished Oct 12 06:10:21 AM UTC 24
Peak memory 246672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3481268555 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_fmt_empty.3481268555
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/22.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/22.i2c_host_fifo_full.3505767091
Short name T891
Test name
Test status
Simulation time 3187995142 ps
CPU time 122.24 seconds
Started Oct 12 06:10:10 AM UTC 24
Finished Oct 12 06:12:15 AM UTC 24
Peak memory 564224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3505767091 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_full.3505767091
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/22.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/22.i2c_host_fifo_overflow.4234997299
Short name T852
Test name
Test status
Simulation time 4375077310 ps
CPU time 59.38 seconds
Started Oct 12 06:10:08 AM UTC 24
Finished Oct 12 06:11:09 AM UTC 24
Peak memory 775124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4234997299 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_overflow.4234997299
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/22.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/22.i2c_host_fifo_reset_fmt.1147624203
Short name T813
Test name
Test status
Simulation time 222207866 ps
CPU time 1.51 seconds
Started Oct 12 06:10:08 AM UTC 24
Finished Oct 12 06:10:10 AM UTC 24
Peak memory 213332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1147624203 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_fmt.1147624203
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/22.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/22.i2c_host_fifo_reset_rx.2475211842
Short name T758
Test name
Test status
Simulation time 304725287 ps
CPU time 5.25 seconds
Started Oct 12 06:10:10 AM UTC 24
Finished Oct 12 06:10:16 AM UTC 24
Peak memory 238532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2475211842 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_rx.2475211842
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/22.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/22.i2c_host_fifo_watermark.3461969285
Short name T875
Test name
Test status
Simulation time 4325044886 ps
CPU time 94.3 seconds
Started Oct 12 06:10:07 AM UTC 24
Finished Oct 12 06:11:43 AM UTC 24
Peak memory 1240452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3461969285 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_watermark.3461969285
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/22.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/22.i2c_host_may_nack.1890341395
Short name T836
Test name
Test status
Simulation time 1717078162 ps
CPU time 5.6 seconds
Started Oct 12 06:10:43 AM UTC 24
Finished Oct 12 06:10:50 AM UTC 24
Peak memory 215704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1890341395 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.i2c_host_may_nack.1890341395
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/22.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/22.i2c_host_mode_toggle.629809960
Short name T828
Test name
Test status
Simulation time 107525237 ps
CPU time 2.83 seconds
Started Oct 12 06:10:42 AM UTC 24
Finished Oct 12 06:10:46 AM UTC 24
Peak memory 229812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=629809960 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 22.i2c_host_mode_toggle.629809960
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/22.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/22.i2c_host_override.3093500076
Short name T141
Test name
Test status
Simulation time 27888524 ps
CPU time 1.11 seconds
Started Oct 12 06:10:07 AM UTC 24
Finished Oct 12 06:10:09 AM UTC 24
Peak memory 213208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3093500076 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.i2c_host_override.3093500076
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/22.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/22.i2c_host_perf.2587362171
Short name T1013
Test name
Test status
Simulation time 13276869772 ps
CPU time 287.23 seconds
Started Oct 12 06:10:10 AM UTC 24
Finished Oct 12 06:15:01 AM UTC 24
Peak memory 215760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2587362171 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 22.i2c_host_perf.2587362171
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/22.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/22.i2c_host_perf_precise.1020400787
Short name T756
Test name
Test status
Simulation time 307703805 ps
CPU time 1.78 seconds
Started Oct 12 06:10:10 AM UTC 24
Finished Oct 12 06:10:13 AM UTC 24
Peak memory 225576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1020400787 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_perf_precise.1020400787
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/22.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/22.i2c_host_smoke.2569228135
Short name T824
Test name
Test status
Simulation time 5957462368 ps
CPU time 32.9 seconds
Started Oct 12 06:10:07 AM UTC 24
Finished Oct 12 06:10:41 AM UTC 24
Peak memory 314256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2569228135 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.i2c_host_smoke.2569228135
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/22.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/22.i2c_host_stretch_timeout.395268297
Short name T845
Test name
Test status
Simulation time 2979287951 ps
CPU time 42.28 seconds
Started Oct 12 06:10:11 AM UTC 24
Finished Oct 12 06:10:55 AM UTC 24
Peak memory 225760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=395268297 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_stretch_timeout.395268297
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/22.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/22.i2c_target_bad_addr.954815951
Short name T834
Test name
Test status
Simulation time 1121617871 ps
CPU time 7.8 seconds
Started Oct 12 06:10:39 AM UTC 24
Finished Oct 12 06:10:48 AM UTC 24
Peak memory 225776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=954815951 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_bad_addr.954815951
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/22.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/22.i2c_target_fifo_reset_acq.3381022678
Short name T820
Test name
Test status
Simulation time 306210166 ps
CPU time 3.23 seconds
Started Oct 12 06:10:31 AM UTC 24
Finished Oct 12 06:10:36 AM UTC 24
Peak memory 215400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3381022
678 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_fifo_reset_acq.3381022678
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/22.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/22.i2c_target_fifo_reset_tx.1417572209
Short name T822
Test name
Test status
Simulation time 1386538858 ps
CPU time 2.47 seconds
Started Oct 12 06:10:34 AM UTC 24
Finished Oct 12 06:10:38 AM UTC 24
Peak memory 219632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1417572
209 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_fifo_reset_tx.1417572209
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/22.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/22.i2c_target_fifo_watermarks_acq.201934912
Short name T833
Test name
Test status
Simulation time 1756137956 ps
CPU time 3.54 seconds
Started Oct 12 06:10:43 AM UTC 24
Finished Oct 12 06:10:48 AM UTC 24
Peak memory 215464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2019349
12 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_fifo_watermark
s_acq.201934912
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/22.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/22.i2c_target_fifo_watermarks_tx.311805
Short name T835
Test name
Test status
Simulation time 109054357 ps
CPU time 1.62 seconds
Started Oct 12 06:10:45 AM UTC 24
Finished Oct 12 06:10:48 AM UTC 24
Peak memory 215512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=311805
-assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_fifo_watermarks_tx.311805
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/22.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/22.i2c_target_hrst.2265930508
Short name T826
Test name
Test status
Simulation time 690049790 ps
CPU time 2.89 seconds
Started Oct 12 06:10:39 AM UTC 24
Finished Oct 12 06:10:43 AM UTC 24
Peak memory 217772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2265930
508 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_hrst.2265930508
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/22.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/22.i2c_target_intr_smoke.502176622
Short name T821
Test name
Test status
Simulation time 2247573192 ps
CPU time 8.97 seconds
Started Oct 12 06:10:26 AM UTC 24
Finished Oct 12 06:10:36 AM UTC 24
Peak memory 232712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=502176
622 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_intr_smoke.502176622
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/22.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/22.i2c_target_intr_stress_wr.3565383168
Short name T829
Test name
Test status
Simulation time 6679666536 ps
CPU time 18.98 seconds
Started Oct 12 06:10:26 AM UTC 24
Finished Oct 12 06:10:46 AM UTC 24
Peak memory 537460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3565383168 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_intr_stres
s_wr.3565383168
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/22.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/22.i2c_target_nack_acqfull.1412137692
Short name T841
Test name
Test status
Simulation time 2247792178 ps
CPU time 3.25 seconds
Started Oct 12 06:10:49 AM UTC 24
Finished Oct 12 06:10:53 AM UTC 24
Peak memory 225772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1412137
692 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_nack_acqfull.1412137692
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/22.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/22.i2c_target_nack_acqfull_addr.1316617728
Short name T843
Test name
Test status
Simulation time 2268798647 ps
CPU time 5.22 seconds
Started Oct 12 06:10:49 AM UTC 24
Finished Oct 12 06:10:55 AM UTC 24
Peak memory 215476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1316617
728 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_nack_acqfull_ad
dr.1316617728
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/22.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/22.i2c_target_nack_txstretch.3871050602
Short name T839
Test name
Test status
Simulation time 143700275 ps
CPU time 2.54 seconds
Started Oct 12 06:10:49 AM UTC 24
Finished Oct 12 06:10:52 AM UTC 24
Peak memory 232580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3871050
602 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_nack_txstretch.3871050602
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/22.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/22.i2c_target_perf.934908267
Short name T827
Test name
Test status
Simulation time 3377287227 ps
CPU time 6.84 seconds
Started Oct 12 06:10:37 AM UTC 24
Finished Oct 12 06:10:45 AM UTC 24
Peak memory 231920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9349082
67 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_perf.934908267
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/22.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/22.i2c_target_smbus_maxlen.661723525
Short name T840
Test name
Test status
Simulation time 3415530289 ps
CPU time 4.11 seconds
Started Oct 12 06:10:47 AM UTC 24
Finished Oct 12 06:10:53 AM UTC 24
Peak memory 215308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6617235
25 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_smbus_maxlen.661723525
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/22.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/22.i2c_target_smoke.3038770274
Short name T831
Test name
Test status
Simulation time 1352081038 ps
CPU time 28.63 seconds
Started Oct 12 06:10:18 AM UTC 24
Finished Oct 12 06:10:48 AM UTC 24
Peak memory 225824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3038770274 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_smoke.3038770274
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/22.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/22.i2c_target_stress_all.638728117
Short name T883
Test name
Test status
Simulation time 35582947939 ps
CPU time 83.03 seconds
Started Oct 12 06:10:37 AM UTC 24
Finished Oct 12 06:12:01 AM UTC 24
Peak memory 883924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=638728
117 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_stress_all.638728117
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/22.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/22.i2c_target_stress_rd.724470486
Short name T850
Test name
Test status
Simulation time 2368155290 ps
CPU time 44.36 seconds
Started Oct 12 06:10:20 AM UTC 24
Finished Oct 12 06:11:06 AM UTC 24
Peak memory 225772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=724470486 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_stress_rd.724470486
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/22.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/22.i2c_target_stress_wr.99776055
Short name T916
Test name
Test status
Simulation time 71476201782 ps
CPU time 149.72 seconds
Started Oct 12 06:10:19 AM UTC 24
Finished Oct 12 06:12:51 AM UTC 24
Peak memory 1795096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=99776055 -assert nopostpro
c +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_stress_wr.99776055
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/22.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/22.i2c_target_stretch.1877348015
Short name T819
Test name
Test status
Simulation time 3397467427 ps
CPU time 8.06 seconds
Started Oct 12 06:10:22 AM UTC 24
Finished Oct 12 06:10:31 AM UTC 24
Peak memory 297984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1877348015 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_stretch.1877348015
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/22.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/22.i2c_target_timeout.3371264935
Short name T823
Test name
Test status
Simulation time 3131941621 ps
CPU time 8.52 seconds
Started Oct 12 06:10:28 AM UTC 24
Finished Oct 12 06:10:38 AM UTC 24
Peak memory 232360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3371264
935 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_timeout.3371264935
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/22.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/22.i2c_target_tx_stretch_ctrl.1942009506
Short name T849
Test name
Test status
Simulation time 747634095 ps
CPU time 16.87 seconds
Started Oct 12 06:10:46 AM UTC 24
Finished Oct 12 06:11:04 AM UTC 24
Peak memory 215464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1942009
506 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_target_tx_stretch_ctrl.1942009506
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/22.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/23.i2c_alert_test.1947528557
Short name T869
Test name
Test status
Simulation time 18751977 ps
CPU time 0.99 seconds
Started Oct 12 06:11:32 AM UTC 24
Finished Oct 12 06:11:34 AM UTC 24
Peak memory 215628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1947528557 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_alert_test.1947528557
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/23.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/23.i2c_host_error_intr.3621645837
Short name T846
Test name
Test status
Simulation time 739105126 ps
CPU time 1.92 seconds
Started Oct 12 06:10:56 AM UTC 24
Finished Oct 12 06:10:59 AM UTC 24
Peak memory 225392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3621645837 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 23.i2c_host_error_intr.3621645837
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/23.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/23.i2c_host_fifo_fmt_empty.1975543328
Short name T853
Test name
Test status
Simulation time 1245253968 ps
CPU time 16.03 seconds
Started Oct 12 06:10:53 AM UTC 24
Finished Oct 12 06:11:11 AM UTC 24
Peak memory 279412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1975543328 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_fmt_empty.1975543328
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/23.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/23.i2c_host_fifo_full.4007769405
Short name T884
Test name
Test status
Simulation time 9258710098 ps
CPU time 69.1 seconds
Started Oct 12 06:10:53 AM UTC 24
Finished Oct 12 06:12:04 AM UTC 24
Peak memory 680964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4007769405 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_full.4007769405
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/23.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/23.i2c_host_fifo_overflow.1494765153
Short name T927
Test name
Test status
Simulation time 4160047776 ps
CPU time 132 seconds
Started Oct 12 06:10:52 AM UTC 24
Finished Oct 12 06:13:07 AM UTC 24
Peak memory 699600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1494765153 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_overflow.1494765153
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/23.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/23.i2c_host_fifo_reset_fmt.4164484337
Short name T844
Test name
Test status
Simulation time 536689542 ps
CPU time 1.68 seconds
Started Oct 12 06:10:52 AM UTC 24
Finished Oct 12 06:10:55 AM UTC 24
Peak memory 213332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4164484337 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_fmt.4164484337
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/23.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/23.i2c_host_fifo_reset_rx.3501294676
Short name T847
Test name
Test status
Simulation time 512122087 ps
CPU time 4.89 seconds
Started Oct 12 06:10:53 AM UTC 24
Finished Oct 12 06:11:00 AM UTC 24
Peak memory 215592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3501294676 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_rx.3501294676
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/23.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/23.i2c_host_fifo_watermark.1559563185
Short name T926
Test name
Test status
Simulation time 26350091670 ps
CPU time 132.93 seconds
Started Oct 12 06:10:51 AM UTC 24
Finished Oct 12 06:13:06 AM UTC 24
Peak memory 1385324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1559563185 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_watermark.1559563185
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/23.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/23.i2c_host_may_nack.573976292
Short name T260
Test name
Test status
Simulation time 522187906 ps
CPU time 8.55 seconds
Started Oct 12 06:11:23 AM UTC 24
Finished Oct 12 06:11:33 AM UTC 24
Peak memory 215840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=573976292 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 23.i2c_host_may_nack.573976292
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/23.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/23.i2c_host_override.1334134315
Short name T838
Test name
Test status
Simulation time 26094814 ps
CPU time 1.02 seconds
Started Oct 12 06:10:49 AM UTC 24
Finished Oct 12 06:10:51 AM UTC 24
Peak memory 213208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1334134315 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.i2c_host_override.1334134315
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/23.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/23.i2c_host_perf.3400402664
Short name T906
Test name
Test status
Simulation time 18532934587 ps
CPU time 88.8 seconds
Started Oct 12 06:10:55 AM UTC 24
Finished Oct 12 06:12:25 AM UTC 24
Peak memory 215528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3400402664 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 23.i2c_host_perf.3400402664
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/23.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/23.i2c_host_perf_precise.4072220055
Short name T848
Test name
Test status
Simulation time 664641170 ps
CPU time 4.78 seconds
Started Oct 12 06:10:56 AM UTC 24
Finished Oct 12 06:11:02 AM UTC 24
Peak memory 238332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4072220055 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_perf_precise.4072220055
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/23.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/23.i2c_host_smoke.2494231157
Short name T858
Test name
Test status
Simulation time 1131091981 ps
CPU time 28.88 seconds
Started Oct 12 06:10:49 AM UTC 24
Finished Oct 12 06:11:19 AM UTC 24
Peak memory 377664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2494231157 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 23.i2c_host_smoke.2494231157
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/23.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/23.i2c_host_stretch_timeout.2946055379
Short name T877
Test name
Test status
Simulation time 3858737260 ps
CPU time 48.02 seconds
Started Oct 12 06:10:56 AM UTC 24
Finished Oct 12 06:11:45 AM UTC 24
Peak memory 225812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2946055379 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_stretch_timeout.2946055379
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/23.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/23.i2c_target_bad_addr.2032722551
Short name T866
Test name
Test status
Simulation time 2334046388 ps
CPU time 9.83 seconds
Started Oct 12 06:11:20 AM UTC 24
Finished Oct 12 06:11:31 AM UTC 24
Peak memory 225772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=2032722551 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_bad_ad
dr.2032722551
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/23.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/23.i2c_target_fifo_reset_acq.2449749208
Short name T859
Test name
Test status
Simulation time 348220377 ps
CPU time 2.58 seconds
Started Oct 12 06:11:17 AM UTC 24
Finished Oct 12 06:11:20 AM UTC 24
Peak memory 215400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2449749
208 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_fifo_reset_acq.2449749208
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/23.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/23.i2c_target_fifo_reset_tx.371518293
Short name T860
Test name
Test status
Simulation time 236940588 ps
CPU time 1.92 seconds
Started Oct 12 06:11:18 AM UTC 24
Finished Oct 12 06:11:21 AM UTC 24
Peak memory 213276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3715182
93 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_fifo_reset_tx.371518293
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/23.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/23.i2c_target_fifo_watermarks_acq.1952745801
Short name T867
Test name
Test status
Simulation time 665203354 ps
CPU time 5.89 seconds
Started Oct 12 06:11:25 AM UTC 24
Finished Oct 12 06:11:31 AM UTC 24
Peak memory 215720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1952745
801 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_fifo_watermar
ks_acq.1952745801
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/23.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/23.i2c_target_fifo_watermarks_tx.2013209808
Short name T864
Test name
Test status
Simulation time 316807516 ps
CPU time 2.68 seconds
Started Oct 12 06:11:27 AM UTC 24
Finished Oct 12 06:11:30 AM UTC 24
Peak memory 215248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2013209
808 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_fifo_watermark
s_tx.2013209808
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/23.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/23.i2c_target_intr_smoke.3773921446
Short name T857
Test name
Test status
Simulation time 1351154803 ps
CPU time 11.27 seconds
Started Oct 12 06:11:06 AM UTC 24
Finished Oct 12 06:11:19 AM UTC 24
Peak memory 232588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=377392
1446 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_intr_smoke.3773921446
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/23.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/23.i2c_target_intr_stress_wr.1630655110
Short name T856
Test name
Test status
Simulation time 3688034588 ps
CPU time 5.97 seconds
Started Oct 12 06:11:09 AM UTC 24
Finished Oct 12 06:11:16 AM UTC 24
Peak memory 215780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1630655110 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_intr_stres
s_wr.1630655110
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/23.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/23.i2c_target_nack_acqfull.1484171830
Short name T872
Test name
Test status
Simulation time 2390345346 ps
CPU time 5.03 seconds
Started Oct 12 06:11:31 AM UTC 24
Finished Oct 12 06:11:37 AM UTC 24
Peak memory 225760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1484171
830 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_nack_acqfull.1484171830
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/23.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/23.i2c_target_nack_acqfull_addr.1340403419
Short name T873
Test name
Test status
Simulation time 4486015269 ps
CPU time 4.56 seconds
Started Oct 12 06:11:32 AM UTC 24
Finished Oct 12 06:11:38 AM UTC 24
Peak memory 215640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1340403
419 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_nack_acqfull_ad
dr.1340403419
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/23.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/23.i2c_target_nack_txstretch.387292965
Short name T870
Test name
Test status
Simulation time 586276764 ps
CPU time 2.73 seconds
Started Oct 12 06:11:32 AM UTC 24
Finished Oct 12 06:11:36 AM UTC 24
Peak memory 232328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3872929
65 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_nack_txstretch.387292965
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/23.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/23.i2c_target_perf.988378855
Short name T863
Test name
Test status
Simulation time 8342595398 ps
CPU time 7.35 seconds
Started Oct 12 06:11:18 AM UTC 24
Finished Oct 12 06:11:26 AM UTC 24
Peak memory 232304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9883788
55 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_perf.988378855
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/23.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/23.i2c_target_smbus_maxlen.2022889620
Short name T868
Test name
Test status
Simulation time 2275788179 ps
CPU time 3.72 seconds
Started Oct 12 06:11:28 AM UTC 24
Finished Oct 12 06:11:33 AM UTC 24
Peak memory 215240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2022889
620 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_smbus_maxlen.2022889620
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/23.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/23.i2c_target_smoke.1432190965
Short name T86
Test name
Test status
Simulation time 5949964433 ps
CPU time 20.5 seconds
Started Oct 12 06:11:01 AM UTC 24
Finished Oct 12 06:11:23 AM UTC 24
Peak memory 225700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1432190965 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_smoke.1432190965
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/23.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/23.i2c_target_stress_rd.3528402576
Short name T862
Test name
Test status
Simulation time 1876097041 ps
CPU time 19.39 seconds
Started Oct 12 06:11:05 AM UTC 24
Finished Oct 12 06:11:26 AM UTC 24
Peak memory 230184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3528402576 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_stress_rd.3528402576
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/23.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/23.i2c_target_stress_wr.243478088
Short name T855
Test name
Test status
Simulation time 13007101206 ps
CPU time 12.24 seconds
Started Oct 12 06:11:02 AM UTC 24
Finished Oct 12 06:11:16 AM UTC 24
Peak memory 215788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=243478088 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_stress_wr.243478088
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/23.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/23.i2c_target_stretch.157941519
Short name T854
Test name
Test status
Simulation time 2251365469 ps
CPU time 3.99 seconds
Started Oct 12 06:11:06 AM UTC 24
Finished Oct 12 06:11:11 AM UTC 24
Peak memory 229792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=157941519 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_stretch.157941519
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/23.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/23.i2c_target_timeout.3237060560
Short name T861
Test name
Test status
Simulation time 1257287777 ps
CPU time 11.14 seconds
Started Oct 12 06:11:12 AM UTC 24
Finished Oct 12 06:11:24 AM UTC 24
Peak memory 225704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3237060
560 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_timeout.3237060560
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/23.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/23.i2c_target_tx_stretch_ctrl.3543480016
Short name T871
Test name
Test status
Simulation time 385664640 ps
CPU time 8.09 seconds
Started Oct 12 06:11:27 AM UTC 24
Finished Oct 12 06:11:36 AM UTC 24
Peak memory 215788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3543480
016 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_target_tx_stretch_ctrl.3543480016
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/23.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/24.i2c_alert_test.2279285669
Short name T902
Test name
Test status
Simulation time 18490271 ps
CPU time 0.94 seconds
Started Oct 12 06:12:22 AM UTC 24
Finished Oct 12 06:12:24 AM UTC 24
Peak memory 215628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2279285669 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_alert_test.2279285669
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/24.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/24.i2c_host_error_intr.3610248760
Short name T881
Test name
Test status
Simulation time 727671903 ps
CPU time 11.76 seconds
Started Oct 12 06:11:46 AM UTC 24
Finished Oct 12 06:11:59 AM UTC 24
Peak memory 259016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3610248760 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 24.i2c_host_error_intr.3610248760
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/24.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/24.i2c_host_fifo_fmt_empty.3381205531
Short name T880
Test name
Test status
Simulation time 283796840 ps
CPU time 15.46 seconds
Started Oct 12 06:11:38 AM UTC 24
Finished Oct 12 06:11:54 AM UTC 24
Peak memory 261040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3381205531 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_fmt_empty.3381205531
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/24.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/24.i2c_host_fifo_full.512093241
Short name T1004
Test name
Test status
Simulation time 28404469170 ps
CPU time 193.2 seconds
Started Oct 12 06:11:39 AM UTC 24
Finished Oct 12 06:14:55 AM UTC 24
Peak memory 666544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=512093241 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_full.512093241
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/24.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/24.i2c_host_fifo_overflow.1373864637
Short name T947
Test name
Test status
Simulation time 1821659006 ps
CPU time 116.39 seconds
Started Oct 12 06:11:37 AM UTC 24
Finished Oct 12 06:13:35 AM UTC 24
Peak memory 609176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1373864637 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_overflow.1373864637
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/24.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/24.i2c_host_fifo_reset_fmt.1321500542
Short name T874
Test name
Test status
Simulation time 421078049 ps
CPU time 1.95 seconds
Started Oct 12 06:11:37 AM UTC 24
Finished Oct 12 06:11:40 AM UTC 24
Peak memory 213272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1321500542 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_fmt.1321500542
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/24.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/24.i2c_host_fifo_reset_rx.4225863225
Short name T879
Test name
Test status
Simulation time 144267456 ps
CPU time 10.09 seconds
Started Oct 12 06:11:38 AM UTC 24
Finished Oct 12 06:11:49 AM UTC 24
Peak memory 215400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4225863225 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_rx.4225863225
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/24.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/24.i2c_host_fifo_watermark.3705001677
Short name T1003
Test name
Test status
Simulation time 15682172188 ps
CPU time 195.65 seconds
Started Oct 12 06:11:35 AM UTC 24
Finished Oct 12 06:14:54 AM UTC 24
Peak memory 1137996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3705001677 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_watermark.3705001677
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/24.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/24.i2c_host_may_nack.3545407571
Short name T897
Test name
Test status
Simulation time 1248686386 ps
CPU time 5.57 seconds
Started Oct 12 06:12:15 AM UTC 24
Finished Oct 12 06:12:21 AM UTC 24
Peak memory 215832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3545407571 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.i2c_host_may_nack.3545407571
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/24.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/24.i2c_host_override.1731663649
Short name T142
Test name
Test status
Simulation time 26884519 ps
CPU time 0.97 seconds
Started Oct 12 06:11:34 AM UTC 24
Finished Oct 12 06:11:36 AM UTC 24
Peak memory 213212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1731663649 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.i2c_host_override.1731663649
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/24.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/24.i2c_host_perf.1547975775
Short name T939
Test name
Test status
Simulation time 7236465255 ps
CPU time 93.03 seconds
Started Oct 12 06:11:40 AM UTC 24
Finished Oct 12 06:13:15 AM UTC 24
Peak memory 463800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1547975775 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 24.i2c_host_perf.1547975775
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/24.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/24.i2c_host_perf_precise.752197430
Short name T878
Test name
Test status
Simulation time 743932078 ps
CPU time 1.93 seconds
Started Oct 12 06:11:44 AM UTC 24
Finished Oct 12 06:11:47 AM UTC 24
Peak memory 225576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=752197430 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_perf_precise.752197430
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/24.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/24.i2c_host_smoke.1344320668
Short name T890
Test name
Test status
Simulation time 3125183925 ps
CPU time 38.49 seconds
Started Oct 12 06:11:33 AM UTC 24
Finished Oct 12 06:12:13 AM UTC 24
Peak memory 416772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1344320668 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.i2c_host_smoke.1344320668
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/24.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/24.i2c_host_stress_all.103981814
Short name T280
Test name
Test status
Simulation time 60008531067 ps
CPU time 1351.55 seconds
Started Oct 12 06:11:48 AM UTC 24
Finished Oct 12 06:34:35 AM UTC 24
Peak memory 2919560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=103981814 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 24.i2c_host_stress_all.103981814
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/24.i2c_host_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/24.i2c_host_stretch_timeout.1112209545
Short name T893
Test name
Test status
Simulation time 581232204 ps
CPU time 30.03 seconds
Started Oct 12 06:11:45 AM UTC 24
Finished Oct 12 06:12:17 AM UTC 24
Peak memory 226016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1112209545 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_stretch_timeout.1112209545
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/24.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/24.i2c_target_bad_addr.1348010121
Short name T899
Test name
Test status
Simulation time 4329313134 ps
CPU time 9.17 seconds
Started Oct 12 06:12:13 AM UTC 24
Finished Oct 12 06:12:23 AM UTC 24
Peak memory 232768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=1348010121 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_bad_ad
dr.1348010121
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/24.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/24.i2c_target_fifo_reset_acq.3207281298
Short name T888
Test name
Test status
Simulation time 429432279 ps
CPU time 1.26 seconds
Started Oct 12 06:12:08 AM UTC 24
Finished Oct 12 06:12:10 AM UTC 24
Peak memory 215636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3207281
298 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_fifo_reset_acq.3207281298
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/24.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/24.i2c_target_fifo_reset_tx.1432772097
Short name T889
Test name
Test status
Simulation time 166046089 ps
CPU time 1.84 seconds
Started Oct 12 06:12:09 AM UTC 24
Finished Oct 12 06:12:12 AM UTC 24
Peak memory 215576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1432772
097 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_fifo_reset_tx.1432772097
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/24.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/24.i2c_target_fifo_watermarks_acq.1728036675
Short name T896
Test name
Test status
Simulation time 1969369853 ps
CPU time 2.79 seconds
Started Oct 12 06:12:16 AM UTC 24
Finished Oct 12 06:12:20 AM UTC 24
Peak memory 215704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1728036
675 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_fifo_watermar
ks_acq.1728036675
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/24.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/24.i2c_target_fifo_watermarks_tx.2418416116
Short name T895
Test name
Test status
Simulation time 72847117 ps
CPU time 1.4 seconds
Started Oct 12 06:12:17 AM UTC 24
Finished Oct 12 06:12:19 AM UTC 24
Peak memory 215568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2418416
116 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_fifo_watermark
s_tx.2418416116
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/24.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/24.i2c_target_intr_smoke.2687321519
Short name T887
Test name
Test status
Simulation time 598972735 ps
CPU time 5.92 seconds
Started Oct 12 06:12:02 AM UTC 24
Finished Oct 12 06:12:09 AM UTC 24
Peak memory 225708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=268732
1519 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_intr_smoke.2687321519
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/24.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/24.i2c_target_intr_stress_wr.1050163615
Short name T951
Test name
Test status
Simulation time 17602772854 ps
CPU time 101.17 seconds
Started Oct 12 06:12:02 AM UTC 24
Finished Oct 12 06:13:45 AM UTC 24
Peak memory 1481600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1050163615 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_intr_stres
s_wr.1050163615
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/24.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/24.i2c_target_nack_acqfull.2318818010
Short name T904
Test name
Test status
Simulation time 445822480 ps
CPU time 3.64 seconds
Started Oct 12 06:12:19 AM UTC 24
Finished Oct 12 06:12:24 AM UTC 24
Peak memory 226148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2318818
010 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_nack_acqfull.2318818010
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/24.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/24.i2c_target_nack_acqfull_addr.3918718774
Short name T905
Test name
Test status
Simulation time 530027882 ps
CPU time 3.2 seconds
Started Oct 12 06:12:20 AM UTC 24
Finished Oct 12 06:12:25 AM UTC 24
Peak memory 215808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3918718
774 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_nack_acqfull_ad
dr.3918718774
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/24.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/24.i2c_target_perf.4017896198
Short name T894
Test name
Test status
Simulation time 1769194583 ps
CPU time 5.81 seconds
Started Oct 12 06:12:11 AM UTC 24
Finished Oct 12 06:12:18 AM UTC 24
Peak memory 229844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4017896
198 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_perf.4017896198
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/24.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/24.i2c_target_smbus_maxlen.2521135976
Short name T901
Test name
Test status
Simulation time 455605957 ps
CPU time 4.09 seconds
Started Oct 12 06:12:18 AM UTC 24
Finished Oct 12 06:12:23 AM UTC 24
Peak memory 215244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2521135
976 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_smbus_maxlen.2521135976
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/24.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/24.i2c_target_smoke.3061108459
Short name T885
Test name
Test status
Simulation time 2539256726 ps
CPU time 15.56 seconds
Started Oct 12 06:11:49 AM UTC 24
Finished Oct 12 06:12:06 AM UTC 24
Peak memory 225704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3061108459 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_smoke.3061108459
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/24.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/24.i2c_target_stress_all.947405981
Short name T946
Test name
Test status
Simulation time 64985367627 ps
CPU time 78.72 seconds
Started Oct 12 06:12:12 AM UTC 24
Finished Oct 12 06:13:32 AM UTC 24
Peak memory 810196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=947405
981 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_stress_all.947405981
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/24.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/24.i2c_target_stress_rd.252547501
Short name T940
Test name
Test status
Simulation time 3369329808 ps
CPU time 77.55 seconds
Started Oct 12 06:11:56 AM UTC 24
Finished Oct 12 06:13:15 AM UTC 24
Peak memory 231972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=252547501 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_stress_rd.252547501
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/24.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/24.i2c_target_stress_wr.2393919640
Short name T898
Test name
Test status
Simulation time 24863642217 ps
CPU time 25.98 seconds
Started Oct 12 06:11:56 AM UTC 24
Finished Oct 12 06:12:23 AM UTC 24
Peak memory 457788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2393919640 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_stress_wr.2393919640
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/24.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/24.i2c_target_stretch.795123114
Short name T886
Test name
Test status
Simulation time 1933687188 ps
CPU time 6.78 seconds
Started Oct 12 06:12:00 AM UTC 24
Finished Oct 12 06:12:08 AM UTC 24
Peak memory 252800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=795123114 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_stretch.795123114
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/24.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/24.i2c_target_timeout.3136135888
Short name T892
Test name
Test status
Simulation time 13890723170 ps
CPU time 10.51 seconds
Started Oct 12 06:12:05 AM UTC 24
Finished Oct 12 06:12:17 AM UTC 24
Peak memory 242636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3136135
888 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_timeout.3136135888
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/24.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/24.i2c_target_tx_stretch_ctrl.4146158822
Short name T900
Test name
Test status
Simulation time 153961798 ps
CPU time 5.24 seconds
Started Oct 12 06:12:17 AM UTC 24
Finished Oct 12 06:12:23 AM UTC 24
Peak memory 215456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4146158
822 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_target_tx_stretch_ctrl.4146158822
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/24.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/25.i2c_alert_test.3192386916
Short name T937
Test name
Test status
Simulation time 47325608 ps
CPU time 1.01 seconds
Started Oct 12 06:13:12 AM UTC 24
Finished Oct 12 06:13:14 AM UTC 24
Peak memory 215628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3192386916 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_alert_test.3192386916
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/25.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/25.i2c_host_error_intr.4087600672
Short name T911
Test name
Test status
Simulation time 90932853 ps
CPU time 3.36 seconds
Started Oct 12 06:12:27 AM UTC 24
Finished Oct 12 06:12:31 AM UTC 24
Peak memory 225852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4087600672 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 25.i2c_host_error_intr.4087600672
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/25.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/25.i2c_host_fifo_fmt_empty.907102006
Short name T915
Test name
Test status
Simulation time 399160151 ps
CPU time 18.21 seconds
Started Oct 12 06:12:24 AM UTC 24
Finished Oct 12 06:12:43 AM UTC 24
Peak memory 299912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=907102006 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_fmt_empty.907102006
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/25.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/25.i2c_host_fifo_full.917831918
Short name T976
Test name
Test status
Simulation time 10226569785 ps
CPU time 116.43 seconds
Started Oct 12 06:12:25 AM UTC 24
Finished Oct 12 06:14:24 AM UTC 24
Peak memory 721804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=917831918 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_full.917831918
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/25.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/25.i2c_host_fifo_overflow.3793599553
Short name T1044
Test name
Test status
Simulation time 9509263369 ps
CPU time 189.86 seconds
Started Oct 12 06:12:24 AM UTC 24
Finished Oct 12 06:15:37 AM UTC 24
Peak memory 795912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3793599553 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_overflow.3793599553
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/25.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/25.i2c_host_fifo_reset_fmt.1103337763
Short name T908
Test name
Test status
Simulation time 83464973 ps
CPU time 1.12 seconds
Started Oct 12 06:12:24 AM UTC 24
Finished Oct 12 06:12:26 AM UTC 24
Peak memory 213332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1103337763 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_fmt.1103337763
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/25.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/25.i2c_host_fifo_reset_rx.2138267029
Short name T912
Test name
Test status
Simulation time 1086427063 ps
CPU time 4.82 seconds
Started Oct 12 06:12:25 AM UTC 24
Finished Oct 12 06:12:31 AM UTC 24
Peak memory 236352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2138267029 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_rx.2138267029
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/25.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/25.i2c_host_fifo_watermark.1658353762
Short name T1048
Test name
Test status
Simulation time 3296237999 ps
CPU time 193 seconds
Started Oct 12 06:12:24 AM UTC 24
Finished Oct 12 06:15:40 AM UTC 24
Peak memory 1057736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1658353762 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_watermark.1658353762
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/25.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/25.i2c_host_may_nack.3009343954
Short name T251
Test name
Test status
Simulation time 1890020073 ps
CPU time 7.82 seconds
Started Oct 12 06:13:03 AM UTC 24
Finished Oct 12 06:13:11 AM UTC 24
Peak memory 215576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3009343954 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.i2c_host_may_nack.3009343954
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/25.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/25.i2c_host_override.3832493327
Short name T907
Test name
Test status
Simulation time 211782722 ps
CPU time 1.03 seconds
Started Oct 12 06:12:24 AM UTC 24
Finished Oct 12 06:12:26 AM UTC 24
Peak memory 213212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3832493327 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.i2c_host_override.3832493327
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/25.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/25.i2c_host_perf.1939942030
Short name T971
Test name
Test status
Simulation time 5069753517 ps
CPU time 107.24 seconds
Started Oct 12 06:12:25 AM UTC 24
Finished Oct 12 06:14:15 AM UTC 24
Peak memory 494792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1939942030 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 25.i2c_host_perf.1939942030
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/25.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/25.i2c_host_perf_precise.307303926
Short name T910
Test name
Test status
Simulation time 223719062 ps
CPU time 2.44 seconds
Started Oct 12 06:12:25 AM UTC 24
Finished Oct 12 06:12:29 AM UTC 24
Peak memory 231848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=307303926 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_perf_precise.307303926
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/25.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/25.i2c_host_smoke.656253114
Short name T935
Test name
Test status
Simulation time 4993137727 ps
CPU time 49.05 seconds
Started Oct 12 06:12:23 AM UTC 24
Finished Oct 12 06:13:13 AM UTC 24
Peak memory 400644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=656253114 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 25.i2c_host_smoke.656253114
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/25.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/25.i2c_host_stretch_timeout.3424966624
Short name T921
Test name
Test status
Simulation time 604379588 ps
CPU time 28.92 seconds
Started Oct 12 06:12:27 AM UTC 24
Finished Oct 12 06:12:57 AM UTC 24
Peak memory 225688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3424966624 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_stretch_timeout.3424966624
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/25.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/25.i2c_target_bad_addr.2299305784
Short name T925
Test name
Test status
Simulation time 1498375014 ps
CPU time 6.7 seconds
Started Oct 12 06:12:57 AM UTC 24
Finished Oct 12 06:13:05 AM UTC 24
Peak memory 227752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=2299305784 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_bad_ad
dr.2299305784
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/25.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/25.i2c_target_fifo_reset_acq.3404970402
Short name T918
Test name
Test status
Simulation time 176104266 ps
CPU time 1.03 seconds
Started Oct 12 06:12:52 AM UTC 24
Finished Oct 12 06:12:54 AM UTC 24
Peak memory 215576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3404970
402 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_fifo_reset_acq.3404970402
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/25.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/25.i2c_target_fifo_reset_tx.3029023369
Short name T920
Test name
Test status
Simulation time 437939111 ps
CPU time 2.38 seconds
Started Oct 12 06:12:53 AM UTC 24
Finished Oct 12 06:12:57 AM UTC 24
Peak memory 215400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3029023
369 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_fifo_reset_tx.3029023369
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/25.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/25.i2c_target_fifo_watermarks_acq.3369092360
Short name T928
Test name
Test status
Simulation time 1686724978 ps
CPU time 3.87 seconds
Started Oct 12 06:13:03 AM UTC 24
Finished Oct 12 06:13:07 AM UTC 24
Peak memory 215460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3369092
360 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_fifo_watermar
ks_acq.3369092360
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/25.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/25.i2c_target_fifo_watermarks_tx.2632676143
Short name T929
Test name
Test status
Simulation time 170288627 ps
CPU time 1.75 seconds
Started Oct 12 06:13:06 AM UTC 24
Finished Oct 12 06:13:08 AM UTC 24
Peak memory 215572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2632676
143 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_fifo_watermark
s_tx.2632676143
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/25.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/25.i2c_target_hrst.2073750135
Short name T922
Test name
Test status
Simulation time 638558997 ps
CPU time 3.03 seconds
Started Oct 12 06:12:57 AM UTC 24
Finished Oct 12 06:13:02 AM UTC 24
Peak memory 227872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2073750
135 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_hrst.2073750135
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/25.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/25.i2c_target_intr_smoke.2129101336
Short name T917
Test name
Test status
Simulation time 4840229073 ps
CPU time 12.36 seconds
Started Oct 12 06:12:37 AM UTC 24
Finished Oct 12 06:12:51 AM UTC 24
Peak memory 231960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=212910
1336 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_intr_smoke.2129101336
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/25.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/25.i2c_target_intr_stress_wr.2287693971
Short name T942
Test name
Test status
Simulation time 15493748095 ps
CPU time 36.28 seconds
Started Oct 12 06:12:39 AM UTC 24
Finished Oct 12 06:13:17 AM UTC 24
Peak memory 615292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2287693971 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_intr_stres
s_wr.2287693971
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/25.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/25.i2c_target_nack_acqfull.993036634
Short name T934
Test name
Test status
Simulation time 901860118 ps
CPU time 3.89 seconds
Started Oct 12 06:13:08 AM UTC 24
Finished Oct 12 06:13:13 AM UTC 24
Peak memory 226064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9930366
34 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_nack_acqfull.993036634
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/25.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/25.i2c_target_nack_acqfull_addr.2181471658
Short name T933
Test name
Test status
Simulation time 478339551 ps
CPU time 3.66 seconds
Started Oct 12 06:13:08 AM UTC 24
Finished Oct 12 06:13:13 AM UTC 24
Peak memory 215488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2181471
658 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_nack_acqfull_ad
dr.2181471658
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/25.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/25.i2c_target_nack_txstretch.3289714996
Short name T932
Test name
Test status
Simulation time 154205256 ps
CPU time 2.59 seconds
Started Oct 12 06:13:09 AM UTC 24
Finished Oct 12 06:13:13 AM UTC 24
Peak memory 232256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3289714
996 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_nack_txstretch.3289714996
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/25.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/25.i2c_target_perf.4031535083
Short name T923
Test name
Test status
Simulation time 509065109 ps
CPU time 5.53 seconds
Started Oct 12 06:12:55 AM UTC 24
Finished Oct 12 06:13:02 AM UTC 24
Peak memory 226024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4031535
083 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_perf.4031535083
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/25.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/25.i2c_target_smbus_maxlen.1849459192
Short name T931
Test name
Test status
Simulation time 838394338 ps
CPU time 3.64 seconds
Started Oct 12 06:13:07 AM UTC 24
Finished Oct 12 06:13:11 AM UTC 24
Peak memory 215436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1849459
192 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_smbus_maxlen.1849459192
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/25.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/25.i2c_target_smoke.146279067
Short name T930
Test name
Test status
Simulation time 8468677469 ps
CPU time 40.74 seconds
Started Oct 12 06:12:29 AM UTC 24
Finished Oct 12 06:13:11 AM UTC 24
Peak memory 226100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=146279067 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_smoke.146279067
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/25.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/25.i2c_target_stress_all.3525682267
Short name T1739
Test name
Test status
Simulation time 66534504399 ps
CPU time 1815.05 seconds
Started Oct 12 06:12:56 AM UTC 24
Finished Oct 12 06:43:31 AM UTC 24
Peak memory 12905460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=352568
2267 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_stress_all.3525682267
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/25.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/25.i2c_target_stress_rd.3744688718
Short name T914
Test name
Test status
Simulation time 273464929 ps
CPU time 5.36 seconds
Started Oct 12 06:12:32 AM UTC 24
Finished Oct 12 06:12:39 AM UTC 24
Peak memory 215404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3744688718 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_stress_rd.3744688718
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/25.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/25.i2c_target_stress_wr.822681239
Short name T993
Test name
Test status
Simulation time 48095021053 ps
CPU time 136.48 seconds
Started Oct 12 06:12:30 AM UTC 24
Finished Oct 12 06:14:49 AM UTC 24
Peak memory 1821956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=822681239 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_stress_wr.822681239
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/25.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/25.i2c_target_stretch.1440562505
Short name T913
Test name
Test status
Simulation time 211297139 ps
CPU time 2.86 seconds
Started Oct 12 06:12:32 AM UTC 24
Finished Oct 12 06:12:36 AM UTC 24
Peak memory 215708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1440562505 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_stretch.1440562505
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/25.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/25.i2c_target_timeout.1719925359
Short name T919
Test name
Test status
Simulation time 18339237021 ps
CPU time 10.77 seconds
Started Oct 12 06:12:44 AM UTC 24
Finished Oct 12 06:12:56 AM UTC 24
Peak memory 232396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1719925
359 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_timeout.1719925359
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/25.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/25.i2c_target_tx_stretch_ctrl.2710430028
Short name T936
Test name
Test status
Simulation time 218792616 ps
CPU time 5.69 seconds
Started Oct 12 06:13:07 AM UTC 24
Finished Oct 12 06:13:13 AM UTC 24
Peak memory 215468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2710430
028 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_target_tx_stretch_ctrl.2710430028
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/25.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/26.i2c_alert_test.2536260774
Short name T924
Test name
Test status
Simulation time 28682460 ps
CPU time 0.94 seconds
Started Oct 12 06:14:04 AM UTC 24
Finished Oct 12 06:14:06 AM UTC 24
Peak memory 215628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2536260774 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_alert_test.2536260774
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/26.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/26.i2c_host_error_intr.3432840415
Short name T944
Test name
Test status
Simulation time 122593570 ps
CPU time 2.26 seconds
Started Oct 12 06:13:17 AM UTC 24
Finished Oct 12 06:13:20 AM UTC 24
Peak memory 225988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3432840415 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 26.i2c_host_error_intr.3432840415
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/26.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/26.i2c_host_fifo_fmt_empty.3587775582
Short name T948
Test name
Test status
Simulation time 2945421967 ps
CPU time 26.44 seconds
Started Oct 12 06:13:15 AM UTC 24
Finished Oct 12 06:13:42 AM UTC 24
Peak memory 304328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3587775582 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_fmt_empty.3587775582
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/26.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/26.i2c_host_fifo_full.1899837110
Short name T1046
Test name
Test status
Simulation time 4912498377 ps
CPU time 140.73 seconds
Started Oct 12 06:13:15 AM UTC 24
Finished Oct 12 06:15:38 AM UTC 24
Peak memory 541540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1899837110 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_full.1899837110
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/26.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/26.i2c_host_fifo_overflow.1425818794
Short name T972
Test name
Test status
Simulation time 4810943257 ps
CPU time 62.36 seconds
Started Oct 12 06:13:14 AM UTC 24
Finished Oct 12 06:14:17 AM UTC 24
Peak memory 842696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1425818794 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_overflow.1425818794
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/26.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/26.i2c_host_fifo_reset_fmt.2210056623
Short name T941
Test name
Test status
Simulation time 349810166 ps
CPU time 1.21 seconds
Started Oct 12 06:13:14 AM UTC 24
Finished Oct 12 06:13:16 AM UTC 24
Peak memory 213272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2210056623 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_fmt.2210056623
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/26.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/26.i2c_host_fifo_reset_rx.2572507954
Short name T945
Test name
Test status
Simulation time 504267919 ps
CPU time 5.26 seconds
Started Oct 12 06:13:15 AM UTC 24
Finished Oct 12 06:13:21 AM UTC 24
Peak memory 234384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2572507954 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_rx.2572507954
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/26.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/26.i2c_host_fifo_watermark.1599363124
Short name T1105
Test name
Test status
Simulation time 50271404196 ps
CPU time 198.65 seconds
Started Oct 12 06:13:13 AM UTC 24
Finished Oct 12 06:16:35 AM UTC 24
Peak memory 1062148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1599363124 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_watermark.1599363124
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/26.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/26.i2c_host_may_nack.1058698098
Short name T261
Test name
Test status
Simulation time 486881928 ps
CPU time 8.05 seconds
Started Oct 12 06:13:56 AM UTC 24
Finished Oct 12 06:14:05 AM UTC 24
Peak memory 215712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1058698098 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.i2c_host_may_nack.1058698098
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/26.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/26.i2c_host_override.4194524142
Short name T938
Test name
Test status
Simulation time 27098930 ps
CPU time 0.98 seconds
Started Oct 12 06:13:12 AM UTC 24
Finished Oct 12 06:13:14 AM UTC 24
Peak memory 213212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4194524142 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.i2c_host_override.4194524142
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/26.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/26.i2c_host_perf.2360024371
Short name T979
Test name
Test status
Simulation time 18802137045 ps
CPU time 74.15 seconds
Started Oct 12 06:13:16 AM UTC 24
Finished Oct 12 06:14:32 AM UTC 24
Peak memory 555900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2360024371 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 26.i2c_host_perf.2360024371
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/26.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/26.i2c_host_perf_precise.3213634454
Short name T943
Test name
Test status
Simulation time 148926122 ps
CPU time 2.15 seconds
Started Oct 12 06:13:16 AM UTC 24
Finished Oct 12 06:13:19 AM UTC 24
Peak memory 215656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3213634454 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_perf_precise.3213634454
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/26.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/26.i2c_host_smoke.2543441301
Short name T950
Test name
Test status
Simulation time 1540639837 ps
CPU time 30.43 seconds
Started Oct 12 06:13:12 AM UTC 24
Finished Oct 12 06:13:44 AM UTC 24
Peak memory 373960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2543441301 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 26.i2c_host_smoke.2543441301
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/26.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/26.i2c_host_stretch_timeout.1464319720
Short name T954
Test name
Test status
Simulation time 924315776 ps
CPU time 34.94 seconds
Started Oct 12 06:13:16 AM UTC 24
Finished Oct 12 06:13:52 AM UTC 24
Peak memory 225760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1464319720 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_stretch_timeout.1464319720
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/26.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/26.i2c_target_bad_addr.2237109599
Short name T960
Test name
Test status
Simulation time 844816772 ps
CPU time 7.34 seconds
Started Oct 12 06:13:50 AM UTC 24
Finished Oct 12 06:13:58 AM UTC 24
Peak memory 229764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=2237109599 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_bad_ad
dr.2237109599
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/26.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/26.i2c_target_fifo_reset_acq.2445296918
Short name T952
Test name
Test status
Simulation time 189928077 ps
CPU time 1.94 seconds
Started Oct 12 06:13:45 AM UTC 24
Finished Oct 12 06:13:48 AM UTC 24
Peak memory 215536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2445296
918 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_fifo_reset_acq.2445296918
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/26.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/26.i2c_target_fifo_reset_tx.3961470442
Short name T953
Test name
Test status
Simulation time 461011319 ps
CPU time 1.67 seconds
Started Oct 12 06:13:46 AM UTC 24
Finished Oct 12 06:13:49 AM UTC 24
Peak memory 215576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3961470
442 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_fifo_reset_tx.3961470442
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/26.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/26.i2c_target_fifo_watermarks_acq.3751991593
Short name T962
Test name
Test status
Simulation time 455901052 ps
CPU time 3.94 seconds
Started Oct 12 06:13:57 AM UTC 24
Finished Oct 12 06:14:02 AM UTC 24
Peak memory 215456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3751991
593 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_fifo_watermar
ks_acq.3751991593
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/26.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/26.i2c_target_fifo_watermarks_tx.3912100478
Short name T961
Test name
Test status
Simulation time 433785510 ps
CPU time 2.07 seconds
Started Oct 12 06:13:58 AM UTC 24
Finished Oct 12 06:14:01 AM UTC 24
Peak memory 215252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3912100
478 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_fifo_watermark
s_tx.3912100478
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/26.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/26.i2c_target_intr_smoke.558770145
Short name T949
Test name
Test status
Simulation time 1810861650 ps
CPU time 8.57 seconds
Started Oct 12 06:13:33 AM UTC 24
Finished Oct 12 06:13:43 AM UTC 24
Peak memory 232256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=558770
145 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_intr_smoke.558770145
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/26.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/26.i2c_target_intr_stress_wr.3116085425
Short name T958
Test name
Test status
Simulation time 5119189806 ps
CPU time 20.02 seconds
Started Oct 12 06:13:36 AM UTC 24
Finished Oct 12 06:13:57 AM UTC 24
Peak memory 215836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3116085425 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_intr_stres
s_wr.3116085425
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/26.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/26.i2c_target_nack_acqfull.3765653669
Short name T964
Test name
Test status
Simulation time 541380709 ps
CPU time 4.47 seconds
Started Oct 12 06:14:00 AM UTC 24
Finished Oct 12 06:14:06 AM UTC 24
Peak memory 225828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3765653
669 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_nack_acqfull.3765653669
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/26.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/26.i2c_target_nack_acqfull_addr.2281477249
Short name T967
Test name
Test status
Simulation time 1165680995 ps
CPU time 4.61 seconds
Started Oct 12 06:14:02 AM UTC 24
Finished Oct 12 06:14:08 AM UTC 24
Peak memory 215348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2281477
249 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_nack_acqfull_ad
dr.2281477249
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/26.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/26.i2c_target_nack_txstretch.1813077247
Short name T965
Test name
Test status
Simulation time 1939147246 ps
CPU time 2.53 seconds
Started Oct 12 06:14:03 AM UTC 24
Finished Oct 12 06:14:06 AM UTC 24
Peak memory 232256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1813077
247 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_nack_txstretch.1813077247
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/26.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/26.i2c_target_perf.3972430347
Short name T956
Test name
Test status
Simulation time 6272636666 ps
CPU time 6.81 seconds
Started Oct 12 06:13:47 AM UTC 24
Finished Oct 12 06:13:55 AM UTC 24
Peak memory 232412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3972430
347 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_perf.3972430347
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/26.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/26.i2c_target_smbus_maxlen.4054329469
Short name T903
Test name
Test status
Simulation time 1639076168 ps
CPU time 3.46 seconds
Started Oct 12 06:13:59 AM UTC 24
Finished Oct 12 06:14:04 AM UTC 24
Peak memory 215504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4054329
469 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_smbus_maxlen.4054329469
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/26.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/26.i2c_target_smoke.1022957582
Short name T957
Test name
Test status
Simulation time 882842929 ps
CPU time 33.99 seconds
Started Oct 12 06:13:20 AM UTC 24
Finished Oct 12 06:13:56 AM UTC 24
Peak memory 225616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1022957582 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_smoke.1022957582
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/26.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/26.i2c_target_stress_all.796810982
Short name T272
Test name
Test status
Simulation time 27883658593 ps
CPU time 282.16 seconds
Started Oct 12 06:13:49 AM UTC 24
Finished Oct 12 06:18:35 AM UTC 24
Peak memory 2683920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=796810
982 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_stress_all.796810982
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/26.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/26.i2c_target_stress_rd.2621187490
Short name T975
Test name
Test status
Simulation time 5880087359 ps
CPU time 58.75 seconds
Started Oct 12 06:13:22 AM UTC 24
Finished Oct 12 06:14:22 AM UTC 24
Peak memory 227740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2621187490 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_stress_rd.2621187490
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/26.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/26.i2c_target_stress_wr.2724398669
Short name T959
Test name
Test status
Simulation time 22939771204 ps
CPU time 34.67 seconds
Started Oct 12 06:13:21 AM UTC 24
Finished Oct 12 06:13:57 AM UTC 24
Peak memory 429248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2724398669 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_stress_wr.2724398669
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/26.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/26.i2c_target_stretch.725967014
Short name T1037
Test name
Test status
Simulation time 5412631941 ps
CPU time 110.42 seconds
Started Oct 12 06:13:32 AM UTC 24
Finished Oct 12 06:15:24 AM UTC 24
Peak memory 1135808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=725967014 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_stretch.725967014
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/26.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/26.i2c_target_timeout.3527855636
Short name T955
Test name
Test status
Simulation time 15184036644 ps
CPU time 10.77 seconds
Started Oct 12 06:13:43 AM UTC 24
Finished Oct 12 06:13:55 AM UTC 24
Peak memory 242528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3527855
636 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_timeout.3527855636
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/26.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/26.i2c_target_tx_stretch_ctrl.3129780627
Short name T963
Test name
Test status
Simulation time 153700678 ps
CPU time 4.57 seconds
Started Oct 12 06:13:58 AM UTC 24
Finished Oct 12 06:14:04 AM UTC 24
Peak memory 215468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3129780
627 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_target_tx_stretch_ctrl.3129780627
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/26.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/27.i2c_alert_test.4007108286
Short name T997
Test name
Test status
Simulation time 22781371 ps
CPU time 1.03 seconds
Started Oct 12 06:14:50 AM UTC 24
Finished Oct 12 06:14:52 AM UTC 24
Peak memory 215628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4007108286 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_alert_test.4007108286
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/27.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/27.i2c_host_error_intr.4003195753
Short name T973
Test name
Test status
Simulation time 89331571 ps
CPU time 2.9 seconds
Started Oct 12 06:14:16 AM UTC 24
Finished Oct 12 06:14:20 AM UTC 24
Peak memory 226108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4003195753 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 27.i2c_host_error_intr.4003195753
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/27.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/27.i2c_host_fifo_fmt_empty.1189612512
Short name T969
Test name
Test status
Simulation time 174455105 ps
CPU time 5.22 seconds
Started Oct 12 06:14:07 AM UTC 24
Finished Oct 12 06:14:13 AM UTC 24
Peak memory 238396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1189612512 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_fmt_empty.1189612512
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/27.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/27.i2c_host_fifo_full.2053777995
Short name T1154
Test name
Test status
Simulation time 7036285564 ps
CPU time 221.17 seconds
Started Oct 12 06:14:09 AM UTC 24
Finished Oct 12 06:17:54 AM UTC 24
Peak memory 750596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2053777995 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_full.2053777995
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/27.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/27.i2c_host_fifo_overflow.2773253254
Short name T988
Test name
Test status
Simulation time 13525356763 ps
CPU time 36.27 seconds
Started Oct 12 06:14:07 AM UTC 24
Finished Oct 12 06:14:45 AM UTC 24
Peak memory 558348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2773253254 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_overflow.2773253254
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/27.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/27.i2c_host_fifo_reset_fmt.3144418772
Short name T968
Test name
Test status
Simulation time 92228666 ps
CPU time 1.49 seconds
Started Oct 12 06:14:07 AM UTC 24
Finished Oct 12 06:14:10 AM UTC 24
Peak memory 213332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3144418772 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_fmt.3144418772
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/27.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/27.i2c_host_fifo_reset_rx.3544315043
Short name T970
Test name
Test status
Simulation time 375988876 ps
CPU time 4.77 seconds
Started Oct 12 06:14:08 AM UTC 24
Finished Oct 12 06:14:14 AM UTC 24
Peak memory 215844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3544315043 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_rx.3544315043
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/27.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/27.i2c_host_fifo_watermark.3519950828
Short name T1132
Test name
Test status
Simulation time 13858116177 ps
CPU time 191.63 seconds
Started Oct 12 06:14:06 AM UTC 24
Finished Oct 12 06:17:21 AM UTC 24
Peak memory 1064324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3519950828 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_watermark.3519950828
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/27.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/27.i2c_host_may_nack.4209099807
Short name T994
Test name
Test status
Simulation time 941911958 ps
CPU time 3.9 seconds
Started Oct 12 06:14:44 AM UTC 24
Finished Oct 12 06:14:49 AM UTC 24
Peak memory 215384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4209099807 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.i2c_host_may_nack.4209099807
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/27.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/27.i2c_host_override.1435501108
Short name T966
Test name
Test status
Simulation time 45393706 ps
CPU time 1.06 seconds
Started Oct 12 06:14:05 AM UTC 24
Finished Oct 12 06:14:07 AM UTC 24
Peak memory 213212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1435501108 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.i2c_host_override.1435501108
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/27.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/27.i2c_host_perf.2046586934
Short name T977
Test name
Test status
Simulation time 3335512254 ps
CPU time 14.74 seconds
Started Oct 12 06:14:10 AM UTC 24
Finished Oct 12 06:14:26 AM UTC 24
Peak memory 302152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2046586934 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 27.i2c_host_perf.2046586934
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/27.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/27.i2c_host_perf_precise.252241458
Short name T974
Test name
Test status
Simulation time 589452845 ps
CPU time 4 seconds
Started Oct 12 06:14:15 AM UTC 24
Finished Oct 12 06:14:20 AM UTC 24
Peak memory 246648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=252241458 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_perf_precise.252241458
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/27.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/27.i2c_host_smoke.3558055773
Short name T989
Test name
Test status
Simulation time 27845056011 ps
CPU time 39.92 seconds
Started Oct 12 06:14:05 AM UTC 24
Finished Oct 12 06:14:46 AM UTC 24
Peak memory 351176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3558055773 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 27.i2c_host_smoke.3558055773
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/27.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/27.i2c_host_stress_all.519682185
Short name T233
Test name
Test status
Simulation time 4656263094 ps
CPU time 134.55 seconds
Started Oct 12 06:14:18 AM UTC 24
Finished Oct 12 06:16:35 AM UTC 24
Peak memory 670868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=519682185 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 27.i2c_host_stress_all.519682185
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/27.i2c_host_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/27.i2c_host_stretch_timeout.3499574181
Short name T1008
Test name
Test status
Simulation time 3283956026 ps
CPU time 42.17 seconds
Started Oct 12 06:14:15 AM UTC 24
Finished Oct 12 06:14:58 AM UTC 24
Peak memory 225752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3499574181 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_stretch_timeout.3499574181
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/27.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/27.i2c_target_bad_addr.1637061245
Short name T990
Test name
Test status
Simulation time 4530597193 ps
CPU time 7.13 seconds
Started Oct 12 06:14:39 AM UTC 24
Finished Oct 12 06:14:47 AM UTC 24
Peak memory 232396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=1637061245 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_bad_ad
dr.1637061245
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/27.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/27.i2c_target_fifo_reset_acq.2742538452
Short name T982
Test name
Test status
Simulation time 531351123 ps
CPU time 1.51 seconds
Started Oct 12 06:14:35 AM UTC 24
Finished Oct 12 06:14:38 AM UTC 24
Peak memory 215576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2742538
452 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_fifo_reset_acq.2742538452
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/27.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/27.i2c_target_fifo_reset_tx.1092969372
Short name T983
Test name
Test status
Simulation time 432558942 ps
CPU time 2.03 seconds
Started Oct 12 06:14:35 AM UTC 24
Finished Oct 12 06:14:39 AM UTC 24
Peak memory 225968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1092969
372 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_fifo_reset_tx.1092969372
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/27.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/27.i2c_target_fifo_watermarks_acq.693122740
Short name T995
Test name
Test status
Simulation time 2353101164 ps
CPU time 5.42 seconds
Started Oct 12 06:14:44 AM UTC 24
Finished Oct 12 06:14:50 AM UTC 24
Peak memory 215788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6931227
40 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_fifo_watermark
s_acq.693122740
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/27.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/27.i2c_target_fifo_watermarks_tx.3587013378
Short name T991
Test name
Test status
Simulation time 179727871 ps
CPU time 1.53 seconds
Started Oct 12 06:14:45 AM UTC 24
Finished Oct 12 06:14:48 AM UTC 24
Peak memory 215572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3587013
378 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_fifo_watermark
s_tx.3587013378
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/27.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/27.i2c_target_hrst.2285761053
Short name T987
Test name
Test status
Simulation time 3095946873 ps
CPU time 3.28 seconds
Started Oct 12 06:14:40 AM UTC 24
Finished Oct 12 06:14:44 AM UTC 24
Peak memory 225756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2285761
053 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_hrst.2285761053
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/27.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/27.i2c_target_intr_smoke.286981908
Short name T980
Test name
Test status
Simulation time 737454340 ps
CPU time 5.64 seconds
Started Oct 12 06:14:27 AM UTC 24
Finished Oct 12 06:14:34 AM UTC 24
Peak memory 225764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=286981
908 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_intr_smoke.286981908
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/27.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/27.i2c_target_intr_stress_wr.3345292135
Short name T1017
Test name
Test status
Simulation time 16558907290 ps
CPU time 37.63 seconds
Started Oct 12 06:14:30 AM UTC 24
Finished Oct 12 06:15:09 AM UTC 24
Peak memory 979912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3345292135 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_intr_stres
s_wr.3345292135
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/27.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/27.i2c_target_nack_acqfull_addr.1584622675
Short name T1001
Test name
Test status
Simulation time 10529777974 ps
CPU time 3.92 seconds
Started Oct 12 06:14:48 AM UTC 24
Finished Oct 12 06:14:53 AM UTC 24
Peak memory 215936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1584622
675 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_nack_acqfull_ad
dr.1584622675
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/27.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/27.i2c_target_nack_txstretch.816252259
Short name T998
Test name
Test status
Simulation time 499546440 ps
CPU time 2.25 seconds
Started Oct 12 06:14:49 AM UTC 24
Finished Oct 12 06:14:52 AM UTC 24
Peak memory 232324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8162522
59 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_nack_txstretch.816252259
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/27.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/27.i2c_target_perf.1032502030
Short name T992
Test name
Test status
Simulation time 3611177738 ps
CPU time 10.01 seconds
Started Oct 12 06:14:36 AM UTC 24
Finished Oct 12 06:14:48 AM UTC 24
Peak memory 232028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1032502
030 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_perf.1032502030
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/27.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/27.i2c_target_smbus_maxlen.1033161376
Short name T996
Test name
Test status
Simulation time 536144073 ps
CPU time 3.19 seconds
Started Oct 12 06:14:47 AM UTC 24
Finished Oct 12 06:14:51 AM UTC 24
Peak memory 215504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1033161
376 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_smbus_maxlen.1033161376
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/27.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/27.i2c_target_smoke.1995748766
Short name T981
Test name
Test status
Simulation time 1882819647 ps
CPU time 14.69 seconds
Started Oct 12 06:14:21 AM UTC 24
Finished Oct 12 06:14:37 AM UTC 24
Peak memory 225820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1995748766 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_smoke.1995748766
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/27.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/27.i2c_target_stress_all.149622848
Short name T1545
Test name
Test status
Simulation time 41684265030 ps
CPU time 615.54 seconds
Started Oct 12 06:14:38 AM UTC 24
Finished Oct 12 06:25:00 AM UTC 24
Peak memory 6972356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=149622
848 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_stress_all.149622848
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/27.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/27.i2c_target_stress_rd.3371554656
Short name T1012
Test name
Test status
Simulation time 8372464133 ps
CPU time 35.67 seconds
Started Oct 12 06:14:23 AM UTC 24
Finished Oct 12 06:15:01 AM UTC 24
Peak memory 225692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3371554656 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_stress_rd.3371554656
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/27.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/27.i2c_target_stress_wr.437740678
Short name T1002
Test name
Test status
Simulation time 11997371258 ps
CPU time 31.34 seconds
Started Oct 12 06:14:21 AM UTC 24
Finished Oct 12 06:14:54 AM UTC 24
Peak memory 215576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=437740678 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_stress_wr.437740678
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/27.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/27.i2c_target_stretch.2516238012
Short name T978
Test name
Test status
Simulation time 249169491 ps
CPU time 2.18 seconds
Started Oct 12 06:14:25 AM UTC 24
Finished Oct 12 06:14:29 AM UTC 24
Peak memory 215540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2516238012 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_stretch.2516238012
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/27.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/27.i2c_target_timeout.1497985291
Short name T984
Test name
Test status
Simulation time 1136796799 ps
CPU time 7.94 seconds
Started Oct 12 06:14:30 AM UTC 24
Finished Oct 12 06:14:39 AM UTC 24
Peak memory 226080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1497985
291 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_timeout.1497985291
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/27.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/27.i2c_target_tx_stretch_ctrl.3549081019
Short name T1010
Test name
Test status
Simulation time 722464344 ps
CPU time 13.77 seconds
Started Oct 12 06:14:45 AM UTC 24
Finished Oct 12 06:15:00 AM UTC 24
Peak memory 232464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3549081
019 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_target_tx_stretch_ctrl.3549081019
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/27.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/28.i2c_alert_test.3625575756
Short name T1033
Test name
Test status
Simulation time 37983837 ps
CPU time 0.99 seconds
Started Oct 12 06:15:19 AM UTC 24
Finished Oct 12 06:15:21 AM UTC 24
Peak memory 215628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3625575756 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_alert_test.3625575756
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/28.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/28.i2c_host_error_intr.2837395346
Short name T1041
Test name
Test status
Simulation time 3075778333 ps
CPU time 26.21 seconds
Started Oct 12 06:14:56 AM UTC 24
Finished Oct 12 06:15:23 AM UTC 24
Peak memory 288016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2837395346 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 28.i2c_host_error_intr.2837395346
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/28.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/28.i2c_host_fifo_fmt_empty.745769052
Short name T1014
Test name
Test status
Simulation time 745756891 ps
CPU time 10.47 seconds
Started Oct 12 06:14:53 AM UTC 24
Finished Oct 12 06:15:05 AM UTC 24
Peak memory 250804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=745769052 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_fmt_empty.745769052
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/28.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/28.i2c_host_fifo_full.2443351103
Short name T1141
Test name
Test status
Simulation time 2827299066 ps
CPU time 161.46 seconds
Started Oct 12 06:14:54 AM UTC 24
Finished Oct 12 06:17:38 AM UTC 24
Peak memory 463876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2443351103 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_full.2443351103
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/28.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/28.i2c_host_fifo_overflow.3324323073
Short name T1075
Test name
Test status
Simulation time 3281812039 ps
CPU time 72.14 seconds
Started Oct 12 06:14:52 AM UTC 24
Finished Oct 12 06:16:06 AM UTC 24
Peak memory 764936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3324323073 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_overflow.3324323073
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/28.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/28.i2c_host_fifo_reset_fmt.3300956171
Short name T1006
Test name
Test status
Simulation time 138534745 ps
CPU time 2.12 seconds
Started Oct 12 06:14:53 AM UTC 24
Finished Oct 12 06:14:57 AM UTC 24
Peak memory 215452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3300956171 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_fmt.3300956171
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/28.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/28.i2c_host_fifo_reset_rx.2441970864
Short name T1009
Test name
Test status
Simulation time 580784426 ps
CPU time 4.32 seconds
Started Oct 12 06:14:54 AM UTC 24
Finished Oct 12 06:14:59 AM UTC 24
Peak memory 215784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2441970864 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_rx.2441970864
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/28.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/28.i2c_host_fifo_watermark.2661626759
Short name T1228
Test name
Test status
Simulation time 4868360621 ps
CPU time 265.99 seconds
Started Oct 12 06:14:52 AM UTC 24
Finished Oct 12 06:19:22 AM UTC 24
Peak memory 1371348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2661626759 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_watermark.2661626759
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/28.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/28.i2c_host_may_nack.299343824
Short name T1031
Test name
Test status
Simulation time 299784161 ps
CPU time 4.85 seconds
Started Oct 12 06:15:13 AM UTC 24
Finished Oct 12 06:15:19 AM UTC 24
Peak memory 215464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=299343824 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 28.i2c_host_may_nack.299343824
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/28.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/28.i2c_host_mode_toggle.4253977382
Short name T1026
Test name
Test status
Simulation time 276455836 ps
CPU time 2.85 seconds
Started Oct 12 06:15:12 AM UTC 24
Finished Oct 12 06:15:16 AM UTC 24
Peak memory 215368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4253977382 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_mode_toggle.4253977382
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/28.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/28.i2c_host_override.4257638440
Short name T1000
Test name
Test status
Simulation time 27979443 ps
CPU time 1.05 seconds
Started Oct 12 06:14:51 AM UTC 24
Finished Oct 12 06:14:53 AM UTC 24
Peak memory 213212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4257638440 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.i2c_host_override.4257638440
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/28.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/28.i2c_host_perf.3142990382
Short name T1237
Test name
Test status
Simulation time 6638714542 ps
CPU time 281.76 seconds
Started Oct 12 06:14:55 AM UTC 24
Finished Oct 12 06:19:40 AM UTC 24
Peak memory 783236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3142990382 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 28.i2c_host_perf.3142990382
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/28.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/28.i2c_host_perf_precise.3663200511
Short name T1007
Test name
Test status
Simulation time 142584509 ps
CPU time 1.63 seconds
Started Oct 12 06:14:55 AM UTC 24
Finished Oct 12 06:14:57 AM UTC 24
Peak memory 213212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3663200511 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_perf_precise.3663200511
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/28.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/28.i2c_host_smoke.3256290212
Short name T1072
Test name
Test status
Simulation time 6248587891 ps
CPU time 71.82 seconds
Started Oct 12 06:14:50 AM UTC 24
Finished Oct 12 06:16:03 AM UTC 24
Peak memory 340944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3256290212 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 28.i2c_host_smoke.3256290212
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/28.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/28.i2c_host_stretch_timeout.2713639991
Short name T1029
Test name
Test status
Simulation time 4396946720 ps
CPU time 21.87 seconds
Started Oct 12 06:14:55 AM UTC 24
Finished Oct 12 06:15:18 AM UTC 24
Peak memory 231956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2713639991 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_stretch_timeout.2713639991
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/28.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/28.i2c_target_fifo_reset_acq.3300686318
Short name T1019
Test name
Test status
Simulation time 196633221 ps
CPU time 1.98 seconds
Started Oct 12 06:15:07 AM UTC 24
Finished Oct 12 06:15:10 AM UTC 24
Peak memory 215536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3300686
318 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_fifo_reset_acq.3300686318
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/28.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/28.i2c_target_fifo_reset_tx.1971560383
Short name T1022
Test name
Test status
Simulation time 221847126 ps
CPU time 2.47 seconds
Started Oct 12 06:15:09 AM UTC 24
Finished Oct 12 06:15:12 AM UTC 24
Peak memory 215528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1971560
383 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_fifo_reset_tx.1971560383
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/28.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/28.i2c_target_fifo_watermarks_acq.3055293005
Short name T1028
Test name
Test status
Simulation time 479017343 ps
CPU time 2.6 seconds
Started Oct 12 06:15:14 AM UTC 24
Finished Oct 12 06:15:17 AM UTC 24
Peak memory 215500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3055293
005 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_fifo_watermar
ks_acq.3055293005
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/28.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/28.i2c_target_fifo_watermarks_tx.3048015916
Short name T1030
Test name
Test status
Simulation time 177498635 ps
CPU time 2.65 seconds
Started Oct 12 06:15:15 AM UTC 24
Finished Oct 12 06:15:18 AM UTC 24
Peak memory 215180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3048015
916 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_fifo_watermark
s_tx.3048015916
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/28.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/28.i2c_target_intr_smoke.4079489238
Short name T1025
Test name
Test status
Simulation time 2880218724 ps
CPU time 11.94 seconds
Started Oct 12 06:15:02 AM UTC 24
Finished Oct 12 06:15:15 AM UTC 24
Peak memory 232340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=407948
9238 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_intr_smoke.4079489238
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/28.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/28.i2c_target_intr_stress_wr.3544198636
Short name T1049
Test name
Test status
Simulation time 4194888112 ps
CPU time 37.31 seconds
Started Oct 12 06:15:02 AM UTC 24
Finished Oct 12 06:15:40 AM UTC 24
Peak memory 1178820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3544198636 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_intr_stres
s_wr.3544198636
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/28.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/28.i2c_target_nack_acqfull.1764963173
Short name T1036
Test name
Test status
Simulation time 2004864384 ps
CPU time 3.03 seconds
Started Oct 12 06:15:18 AM UTC 24
Finished Oct 12 06:15:22 AM UTC 24
Peak memory 225712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1764963
173 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_nack_acqfull.1764963173
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/28.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/28.i2c_target_nack_acqfull_addr.3944535321
Short name T1038
Test name
Test status
Simulation time 1104264314 ps
CPU time 3.34 seconds
Started Oct 12 06:15:18 AM UTC 24
Finished Oct 12 06:15:22 AM UTC 24
Peak memory 215488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3944535
321 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_nack_acqfull_ad
dr.3944535321
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/28.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/28.i2c_target_perf.3892764346
Short name T1027
Test name
Test status
Simulation time 2926545553 ps
CPU time 5.93 seconds
Started Oct 12 06:15:10 AM UTC 24
Finished Oct 12 06:15:17 AM UTC 24
Peak memory 232300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3892764
346 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_perf.3892764346
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/28.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/28.i2c_target_smbus_maxlen.4149569395
Short name T1035
Test name
Test status
Simulation time 996703751 ps
CPU time 3.89 seconds
Started Oct 12 06:15:17 AM UTC 24
Finished Oct 12 06:15:22 AM UTC 24
Peak memory 215172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4149569
395 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_smbus_maxlen.4149569395
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/28.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/28.i2c_target_smoke.2352429502
Short name T1021
Test name
Test status
Simulation time 719478606 ps
CPU time 11.87 seconds
Started Oct 12 06:14:58 AM UTC 24
Finished Oct 12 06:15:11 AM UTC 24
Peak memory 225764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2352429502 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_smoke.2352429502
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/28.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/28.i2c_target_stress_all.3898059151
Short name T1134
Test name
Test status
Simulation time 108059927828 ps
CPU time 133.22 seconds
Started Oct 12 06:15:10 AM UTC 24
Finished Oct 12 06:17:26 AM UTC 24
Peak memory 1066232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=389805
9151 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_stress_all.3898059151
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/28.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/28.i2c_target_stress_rd.2570985290
Short name T1015
Test name
Test status
Simulation time 1983776027 ps
CPU time 5.61 seconds
Started Oct 12 06:14:59 AM UTC 24
Finished Oct 12 06:15:06 AM UTC 24
Peak memory 215516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2570985290 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_stress_rd.2570985290
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/28.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/28.i2c_target_stress_wr.2354557051
Short name T1034
Test name
Test status
Simulation time 24804537863 ps
CPU time 20.85 seconds
Started Oct 12 06:14:59 AM UTC 24
Finished Oct 12 06:15:21 AM UTC 24
Peak memory 379972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2354557051 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_stress_wr.2354557051
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/28.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/28.i2c_target_timeout.2967277247
Short name T1023
Test name
Test status
Simulation time 2763562058 ps
CPU time 8.97 seconds
Started Oct 12 06:15:03 AM UTC 24
Finished Oct 12 06:15:13 AM UTC 24
Peak memory 232344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2967277
247 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_timeout.2967277247
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/28.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/28.i2c_target_tx_stretch_ctrl.2173531315
Short name T1032
Test name
Test status
Simulation time 116425032 ps
CPU time 3.94 seconds
Started Oct 12 06:15:16 AM UTC 24
Finished Oct 12 06:15:21 AM UTC 24
Peak memory 215724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2173531
315 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_target_tx_stretch_ctrl.2173531315
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/28.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/29.i2c_alert_test.1081263689
Short name T1061
Test name
Test status
Simulation time 50226315 ps
CPU time 1.04 seconds
Started Oct 12 06:15:51 AM UTC 24
Finished Oct 12 06:15:53 AM UTC 24
Peak memory 215628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1081263689 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_alert_test.1081263689
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/29.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/29.i2c_host_error_intr.4025909175
Short name T1045
Test name
Test status
Simulation time 269267251 ps
CPU time 11.53 seconds
Started Oct 12 06:15:24 AM UTC 24
Finished Oct 12 06:15:37 AM UTC 24
Peak memory 244936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4025909175 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 29.i2c_host_error_intr.4025909175
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/29.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/29.i2c_host_fifo_fmt_empty.523937273
Short name T1016
Test name
Test status
Simulation time 519143503 ps
CPU time 7.46 seconds
Started Oct 12 06:15:23 AM UTC 24
Finished Oct 12 06:15:32 AM UTC 24
Peak memory 271320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=523937273 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_fmt_empty.523937273
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/29.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/29.i2c_host_fifo_full.2764469565
Short name T1102
Test name
Test status
Simulation time 9831396502 ps
CPU time 69.26 seconds
Started Oct 12 06:15:23 AM UTC 24
Finished Oct 12 06:16:34 AM UTC 24
Peak memory 574716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2764469565 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_full.2764469565
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/29.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/29.i2c_host_fifo_overflow.2552578429
Short name T1162
Test name
Test status
Simulation time 2304944565 ps
CPU time 156.96 seconds
Started Oct 12 06:15:22 AM UTC 24
Finished Oct 12 06:18:01 AM UTC 24
Peak memory 723924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2552578429 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_overflow.2552578429
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/29.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/29.i2c_host_fifo_reset_fmt.2993525900
Short name T1042
Test name
Test status
Simulation time 373857235 ps
CPU time 1.47 seconds
Started Oct 12 06:15:22 AM UTC 24
Finished Oct 12 06:15:24 AM UTC 24
Peak memory 213332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2993525900 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_fmt.2993525900
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/29.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/29.i2c_host_fifo_reset_rx.3913294206
Short name T985
Test name
Test status
Simulation time 185076880 ps
CPU time 5.16 seconds
Started Oct 12 06:15:23 AM UTC 24
Finished Oct 12 06:15:29 AM UTC 24
Peak memory 215432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3913294206 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_rx.3913294206
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/29.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/29.i2c_host_fifo_watermark.131283949
Short name T1161
Test name
Test status
Simulation time 2845477998 ps
CPU time 156.71 seconds
Started Oct 12 06:15:22 AM UTC 24
Finished Oct 12 06:18:01 AM UTC 24
Peak memory 836668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=131283949 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_watermark.131283949
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/29.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/29.i2c_host_may_nack.1299707639
Short name T1080
Test name
Test status
Simulation time 4303477305 ps
CPU time 29.37 seconds
Started Oct 12 06:15:44 AM UTC 24
Finished Oct 12 06:16:15 AM UTC 24
Peak memory 215504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1299707639 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.i2c_host_may_nack.1299707639
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/29.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/29.i2c_host_override.1526576485
Short name T1039
Test name
Test status
Simulation time 35561012 ps
CPU time 1.02 seconds
Started Oct 12 06:15:21 AM UTC 24
Finished Oct 12 06:15:22 AM UTC 24
Peak memory 213208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1526576485 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.i2c_host_override.1526576485
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/29.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/29.i2c_host_perf.396968761
Short name T1005
Test name
Test status
Simulation time 430308279 ps
CPU time 6.19 seconds
Started Oct 12 06:15:23 AM UTC 24
Finished Oct 12 06:15:30 AM UTC 24
Peak memory 248712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=396968761 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 29.i2c_host_perf.396968761
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/29.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/29.i2c_host_perf_precise.3884647971
Short name T1057
Test name
Test status
Simulation time 6222412861 ps
CPU time 24.97 seconds
Started Oct 12 06:15:23 AM UTC 24
Finished Oct 12 06:15:50 AM UTC 24
Peak memory 215900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3884647971 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_perf_precise.3884647971
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/29.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/29.i2c_host_smoke.1308212043
Short name T1076
Test name
Test status
Simulation time 914748047 ps
CPU time 44.58 seconds
Started Oct 12 06:15:21 AM UTC 24
Finished Oct 12 06:16:07 AM UTC 24
Peak memory 275648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1308212043 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.i2c_host_smoke.1308212043
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/29.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/29.i2c_host_stress_all.1340543111
Short name T128
Test name
Test status
Simulation time 13345307905 ps
CPU time 471.89 seconds
Started Oct 12 06:15:26 AM UTC 24
Finished Oct 12 06:23:23 AM UTC 24
Peak memory 1969180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1340543111 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 29.i2c_host_stress_all.1340543111
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/29.i2c_host_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/29.i2c_host_stretch_timeout.1713930511
Short name T1043
Test name
Test status
Simulation time 1190464227 ps
CPU time 6.97 seconds
Started Oct 12 06:15:24 AM UTC 24
Finished Oct 12 06:15:32 AM UTC 24
Peak memory 225696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1713930511 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_stretch_timeout.1713930511
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/29.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/29.i2c_target_bad_addr.3999263618
Short name T1054
Test name
Test status
Simulation time 1012095479 ps
CPU time 5.81 seconds
Started Oct 12 06:15:42 AM UTC 24
Finished Oct 12 06:15:48 AM UTC 24
Peak memory 231852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=3999263618 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_bad_ad
dr.3999263618
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/29.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/29.i2c_target_fifo_reset_acq.3775188902
Short name T1052
Test name
Test status
Simulation time 263382086 ps
CPU time 3.03 seconds
Started Oct 12 06:15:39 AM UTC 24
Finished Oct 12 06:15:43 AM UTC 24
Peak memory 215468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3775188
902 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_fifo_reset_acq.3775188902
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/29.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/29.i2c_target_fifo_reset_tx.3992407032
Short name T1051
Test name
Test status
Simulation time 465493875 ps
CPU time 1.91 seconds
Started Oct 12 06:15:39 AM UTC 24
Finished Oct 12 06:15:42 AM UTC 24
Peak memory 215636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3992407
032 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_fifo_reset_tx.3992407032
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/29.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/29.i2c_target_fifo_watermarks_acq.1119380402
Short name T1059
Test name
Test status
Simulation time 1428763755 ps
CPU time 3.66 seconds
Started Oct 12 06:15:45 AM UTC 24
Finished Oct 12 06:15:50 AM UTC 24
Peak memory 215524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1119380
402 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_fifo_watermar
ks_acq.1119380402
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/29.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/29.i2c_target_fifo_watermarks_tx.4168310390
Short name T1058
Test name
Test status
Simulation time 84071824 ps
CPU time 1.49 seconds
Started Oct 12 06:15:47 AM UTC 24
Finished Oct 12 06:15:50 AM UTC 24
Peak memory 213508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4168310
390 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_fifo_watermark
s_tx.4168310390
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/29.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/29.i2c_target_intr_smoke.3924712873
Short name T1050
Test name
Test status
Simulation time 2378241713 ps
CPU time 8.07 seconds
Started Oct 12 06:15:32 AM UTC 24
Finished Oct 12 06:15:41 AM UTC 24
Peak memory 230052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=392471
2873 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_intr_smoke.3924712873
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/29.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/29.i2c_target_intr_stress_wr.482164994
Short name T1111
Test name
Test status
Simulation time 23712206255 ps
CPU time 70.8 seconds
Started Oct 12 06:15:33 AM UTC 24
Finished Oct 12 06:16:46 AM UTC 24
Peak memory 1440644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=482164994 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_intr_stress
_wr.482164994
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/29.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/29.i2c_target_nack_acqfull.2928942559
Short name T1068
Test name
Test status
Simulation time 2171726299 ps
CPU time 4.71 seconds
Started Oct 12 06:15:50 AM UTC 24
Finished Oct 12 06:15:56 AM UTC 24
Peak memory 225700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2928942
559 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_nack_acqfull.2928942559
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/29.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/29.i2c_target_nack_acqfull_addr.7215575
Short name T1066
Test name
Test status
Simulation time 897363453 ps
CPU time 4.15 seconds
Started Oct 12 06:15:50 AM UTC 24
Finished Oct 12 06:15:56 AM UTC 24
Peak memory 215396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7215575
-assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_nack_acqfull_addr.7215575
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/29.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/29.i2c_target_perf.734786589
Short name T1056
Test name
Test status
Simulation time 5259709564 ps
CPU time 7.79 seconds
Started Oct 12 06:15:41 AM UTC 24
Finished Oct 12 06:15:49 AM UTC 24
Peak memory 232332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7347865
89 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_perf.734786589
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/29.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/29.i2c_target_smbus_maxlen.3544282552
Short name T1064
Test name
Test status
Simulation time 938105914 ps
CPU time 3.17 seconds
Started Oct 12 06:15:49 AM UTC 24
Finished Oct 12 06:15:53 AM UTC 24
Peak memory 215632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3544282
552 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_smbus_maxlen.3544282552
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/29.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/29.i2c_target_smoke.4159462683
Short name T1047
Test name
Test status
Simulation time 2588396081 ps
CPU time 11.96 seconds
Started Oct 12 06:15:26 AM UTC 24
Finished Oct 12 06:15:39 AM UTC 24
Peak memory 226028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4159462683 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_smoke.4159462683
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/29.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/29.i2c_target_stress_all.2250673992
Short name T1245
Test name
Test status
Simulation time 47476355496 ps
CPU time 245.27 seconds
Started Oct 12 06:15:41 AM UTC 24
Finished Oct 12 06:19:49 AM UTC 24
Peak memory 2847732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=225067
3992 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_stress_all.2250673992
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/29.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/29.i2c_target_stress_rd.1917854473
Short name T1063
Test name
Test status
Simulation time 3452689731 ps
CPU time 21.95 seconds
Started Oct 12 06:15:30 AM UTC 24
Finished Oct 12 06:15:53 AM UTC 24
Peak memory 232816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1917854473 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_stress_rd.1917854473
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/29.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/29.i2c_target_stress_wr.4224292749
Short name T1062
Test name
Test status
Simulation time 41019100718 ps
CPU time 24.98 seconds
Started Oct 12 06:15:27 AM UTC 24
Finished Oct 12 06:15:53 AM UTC 24
Peak memory 539584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4224292749 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_stress_wr.4224292749
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/29.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/29.i2c_target_stretch.3359449901
Short name T1053
Test name
Test status
Simulation time 614389515 ps
CPU time 11.56 seconds
Started Oct 12 06:15:31 AM UTC 24
Finished Oct 12 06:15:44 AM UTC 24
Peak memory 318252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3359449901 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_stretch.3359449901
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/29.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/29.i2c_target_timeout.976103881
Short name T1055
Test name
Test status
Simulation time 2430429621 ps
CPU time 9.38 seconds
Started Oct 12 06:15:38 AM UTC 24
Finished Oct 12 06:15:49 AM UTC 24
Peak memory 232464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9761038
81 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_timeout.976103881
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/29.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/29.i2c_target_tx_stretch_ctrl.3198064498
Short name T1060
Test name
Test status
Simulation time 43557913 ps
CPU time 2.09 seconds
Started Oct 12 06:15:49 AM UTC 24
Finished Oct 12 06:15:52 AM UTC 24
Peak memory 215724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3198064
498 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_target_tx_stretch_ctrl.3198064498
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/29.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/3.i2c_alert_test.4255538606
Short name T322
Test name
Test status
Simulation time 49765890 ps
CPU time 0.99 seconds
Started Oct 12 05:56:31 AM UTC 24
Finished Oct 12 05:56:33 AM UTC 24
Peak memory 213392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4255538606 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_alert_test.4255538606
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/3.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/3.i2c_host_error_intr.3464450360
Short name T21
Test name
Test status
Simulation time 249740357 ps
CPU time 2.56 seconds
Started Oct 12 05:55:54 AM UTC 24
Finished Oct 12 05:55:58 AM UTC 24
Peak memory 225760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3464450360 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 3.i2c_host_error_intr.3464450360
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/3.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/3.i2c_host_fifo_fmt_empty.304703185
Short name T306
Test name
Test status
Simulation time 679684971 ps
CPU time 9.6 seconds
Started Oct 12 05:55:47 AM UTC 24
Finished Oct 12 05:55:58 AM UTC 24
Peak memory 285560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=304703185 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_fmt_empty.304703185
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/3.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/3.i2c_host_fifo_full.148412175
Short name T158
Test name
Test status
Simulation time 1975277623 ps
CPU time 48.51 seconds
Started Oct 12 05:55:47 AM UTC 24
Finished Oct 12 05:56:37 AM UTC 24
Peak memory 300224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=148412175 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_full.148412175
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/3.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/3.i2c_host_fifo_overflow.1747528890
Short name T174
Test name
Test status
Simulation time 1703609986 ps
CPU time 138.38 seconds
Started Oct 12 05:55:46 AM UTC 24
Finished Oct 12 05:58:07 AM UTC 24
Peak memory 650440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1747528890 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_overflow.1747528890
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/3.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/3.i2c_host_fifo_reset_fmt.1333553850
Short name T239
Test name
Test status
Simulation time 259467676 ps
CPU time 1.37 seconds
Started Oct 12 05:55:46 AM UTC 24
Finished Oct 12 05:55:48 AM UTC 24
Peak memory 213332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1333553850 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_fmt.1333553850
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/3.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/3.i2c_host_fifo_reset_rx.4088190585
Short name T171
Test name
Test status
Simulation time 337227872 ps
CPU time 11.92 seconds
Started Oct 12 05:55:47 AM UTC 24
Finished Oct 12 05:56:00 AM UTC 24
Peak memory 242792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4088190585 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_rx.4088190585
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/3.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/3.i2c_host_fifo_watermark.2244754586
Short name T175
Test name
Test status
Simulation time 6737639924 ps
CPU time 144.54 seconds
Started Oct 12 05:55:45 AM UTC 24
Finished Oct 12 05:58:12 AM UTC 24
Peak memory 1520592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2244754586 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_watermark.2244754586
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/3.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/3.i2c_host_may_nack.3142057651
Short name T37
Test name
Test status
Simulation time 3099217947 ps
CPU time 23.44 seconds
Started Oct 12 05:56:22 AM UTC 24
Finished Oct 12 05:56:47 AM UTC 24
Peak memory 215820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3142057651 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.i2c_host_may_nack.3142057651
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/3.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/3.i2c_host_override.3540586721
Short name T288
Test name
Test status
Simulation time 22306367 ps
CPU time 0.91 seconds
Started Oct 12 05:55:45 AM UTC 24
Finished Oct 12 05:55:46 AM UTC 24
Peak memory 213208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3540586721 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.i2c_host_override.3540586721
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/3.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/3.i2c_host_perf.758848873
Short name T235
Test name
Test status
Simulation time 6111376768 ps
CPU time 342.39 seconds
Started Oct 12 05:55:47 AM UTC 24
Finished Oct 12 06:01:34 AM UTC 24
Peak memory 1152064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=758848873 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 3.i2c_host_perf.758848873
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/3.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/3.i2c_host_perf_precise.3679425290
Short name T234
Test name
Test status
Simulation time 253281104 ps
CPU time 3.05 seconds
Started Oct 12 05:55:49 AM UTC 24
Finished Oct 12 05:55:53 AM UTC 24
Peak memory 215384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3679425290 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_perf_precise.3679425290
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/3.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/3.i2c_host_smoke.566372569
Short name T336
Test name
Test status
Simulation time 8546770343 ps
CPU time 97.8 seconds
Started Oct 12 05:55:43 AM UTC 24
Finished Oct 12 05:57:23 AM UTC 24
Peak memory 464128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=566372569 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 3.i2c_host_smoke.566372569
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/3.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/3.i2c_host_stretch_timeout.3165405162
Short name T284
Test name
Test status
Simulation time 1371842978 ps
CPU time 38.93 seconds
Started Oct 12 05:55:52 AM UTC 24
Finished Oct 12 05:56:33 AM UTC 24
Peak memory 226092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3165405162 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_stretch_timeout.3165405162
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/3.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/3.i2c_sec_cm.4013187625
Short name T191
Test name
Test status
Simulation time 851285191 ps
CPU time 1.52 seconds
Started Oct 12 05:56:30 AM UTC 24
Finished Oct 12 05:56:32 AM UTC 24
Peak memory 244936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4013187625 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_sec_cm.4013187625
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/3.i2c_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/3.i2c_target_bad_addr.2924764431
Short name T315
Test name
Test status
Simulation time 3906421754 ps
CPU time 5.12 seconds
Started Oct 12 05:56:17 AM UTC 24
Finished Oct 12 05:56:24 AM UTC 24
Peak memory 225700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=2924764431 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_bad_addr.2924764431
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/3.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/3.i2c_target_fifo_reset_acq.1349938676
Short name T309
Test name
Test status
Simulation time 341529732 ps
CPU time 1.56 seconds
Started Oct 12 05:56:13 AM UTC 24
Finished Oct 12 05:56:16 AM UTC 24
Peak memory 213508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1349938
676 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_fifo_reset_acq.1349938676
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/3.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/3.i2c_target_fifo_reset_tx.89032077
Short name T310
Test name
Test status
Simulation time 132420923 ps
CPU time 1.55 seconds
Started Oct 12 05:56:14 AM UTC 24
Finished Oct 12 05:56:17 AM UTC 24
Peak memory 215452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8903207
7 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_fifo_reset_tx.89032077
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/3.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/3.i2c_target_fifo_watermarks_acq.2530097891
Short name T318
Test name
Test status
Simulation time 2818053152 ps
CPU time 4.71 seconds
Started Oct 12 05:56:23 AM UTC 24
Finished Oct 12 05:56:29 AM UTC 24
Peak memory 215572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2530097
891 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_fifo_watermark
s_acq.2530097891
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/3.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/3.i2c_target_fifo_watermarks_tx.1375859275
Short name T316
Test name
Test status
Simulation time 163113002 ps
CPU time 2.52 seconds
Started Oct 12 05:56:24 AM UTC 24
Finished Oct 12 05:56:28 AM UTC 24
Peak memory 215180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1375859
275 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_fifo_watermarks
_tx.1375859275
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/3.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/3.i2c_target_hrst.1188754382
Short name T180
Test name
Test status
Simulation time 677754312 ps
CPU time 3.22 seconds
Started Oct 12 05:56:17 AM UTC 24
Finished Oct 12 05:56:22 AM UTC 24
Peak memory 225712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1188754
382 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_hrst.1188754382
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/3.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/3.i2c_target_intr_smoke.4108471659
Short name T308
Test name
Test status
Simulation time 4606423269 ps
CPU time 10.42 seconds
Started Oct 12 05:56:01 AM UTC 24
Finished Oct 12 05:56:12 AM UTC 24
Peak memory 242632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=410847
1659 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_intr_smoke.4108471659
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/3.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/3.i2c_target_intr_stress_wr.3220391907
Short name T320
Test name
Test status
Simulation time 5592552513 ps
CPU time 22.54 seconds
Started Oct 12 05:56:06 AM UTC 24
Finished Oct 12 05:56:30 AM UTC 24
Peak memory 215448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3220391907 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_intr_stress
_wr.3220391907
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/3.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/3.i2c_target_nack_acqfull.2728984438
Short name T156
Test name
Test status
Simulation time 3085940316 ps
CPU time 4.43 seconds
Started Oct 12 05:56:28 AM UTC 24
Finished Oct 12 05:56:34 AM UTC 24
Peak memory 226084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2728984
438 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_nack_acqfull.2728984438
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/3.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/3.i2c_target_nack_acqfull_addr.950746788
Short name T157
Test name
Test status
Simulation time 1995550146 ps
CPU time 4.04 seconds
Started Oct 12 05:56:29 AM UTC 24
Finished Oct 12 05:56:34 AM UTC 24
Peak memory 215612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9507467
88 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_nack_acqfull_addr.950746788
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/3.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/3.i2c_target_perf.193613769
Short name T313
Test name
Test status
Simulation time 476800029 ps
CPU time 4.1 seconds
Started Oct 12 05:56:16 AM UTC 24
Finished Oct 12 05:56:21 AM UTC 24
Peak memory 225708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1936137
69 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_perf.193613769
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/3.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/3.i2c_target_smbus_maxlen.2587591715
Short name T319
Test name
Test status
Simulation time 863222748 ps
CPU time 3.14 seconds
Started Oct 12 05:56:25 AM UTC 24
Finished Oct 12 05:56:29 AM UTC 24
Peak memory 215168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2587591
715 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_smbus_maxlen.2587591715
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/3.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/3.i2c_target_smoke.2345822271
Short name T307
Test name
Test status
Simulation time 618375934 ps
CPU time 13.52 seconds
Started Oct 12 05:55:56 AM UTC 24
Finished Oct 12 05:56:11 AM UTC 24
Peak memory 225752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2345822271 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_smoke.2345822271
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/3.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/3.i2c_target_stress_all.893885091
Short name T57
Test name
Test status
Simulation time 30557794358 ps
CPU time 63.11 seconds
Started Oct 12 05:56:16 AM UTC 24
Finished Oct 12 05:57:21 AM UTC 24
Peak memory 461688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=893885
091 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_stress_all.893885091
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/3.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/3.i2c_target_stress_rd.2285025446
Short name T266
Test name
Test status
Simulation time 5970042751 ps
CPU time 29.22 seconds
Started Oct 12 05:55:59 AM UTC 24
Finished Oct 12 05:56:29 AM UTC 24
Peak memory 242900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2285025446 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_stress_rd.2285025446
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/3.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/3.i2c_target_stress_wr.3844158185
Short name T58
Test name
Test status
Simulation time 57185868879 ps
CPU time 167.51 seconds
Started Oct 12 05:55:59 AM UTC 24
Finished Oct 12 05:58:48 AM UTC 24
Peak memory 2413824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3844158185 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_stress_wr.3844158185
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/3.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/3.i2c_target_timeout.3055562636
Short name T312
Test name
Test status
Simulation time 2300474521 ps
CPU time 10.69 seconds
Started Oct 12 05:56:09 AM UTC 24
Finished Oct 12 05:56:21 AM UTC 24
Peak memory 226028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3055562
636 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_timeout.3055562636
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/3.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/3.i2c_target_tx_stretch_ctrl.3242548038
Short name T317
Test name
Test status
Simulation time 69760097 ps
CPU time 2.92 seconds
Started Oct 12 05:56:24 AM UTC 24
Finished Oct 12 05:56:28 AM UTC 24
Peak memory 215400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3242548
038 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_target_tx_stretch_ctrl.3242548038
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/3.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/30.i2c_alert_test.601181634
Short name T1096
Test name
Test status
Simulation time 21794485 ps
CPU time 0.87 seconds
Started Oct 12 06:16:29 AM UTC 24
Finished Oct 12 06:16:31 AM UTC 24
Peak memory 215628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=601181634 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_alert_test.601181634
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/30.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/30.i2c_host_error_intr.3480366519
Short name T1074
Test name
Test status
Simulation time 552804923 ps
CPU time 2.07 seconds
Started Oct 12 06:16:03 AM UTC 24
Finished Oct 12 06:16:06 AM UTC 24
Peak memory 229892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3480366519 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 30.i2c_host_error_intr.3480366519
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/30.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/30.i2c_host_fifo_fmt_empty.1648039696
Short name T1077
Test name
Test status
Simulation time 406999649 ps
CPU time 11.82 seconds
Started Oct 12 06:15:55 AM UTC 24
Finished Oct 12 06:16:08 AM UTC 24
Peak memory 304120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1648039696 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_fmt_empty.1648039696
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/30.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/30.i2c_host_fifo_full.4134144040
Short name T1170
Test name
Test status
Simulation time 2331171087 ps
CPU time 132.04 seconds
Started Oct 12 06:15:56 AM UTC 24
Finished Oct 12 06:18:11 AM UTC 24
Peak memory 715784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4134144040 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_full.4134144040
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/30.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/30.i2c_host_fifo_overflow.1375413225
Short name T1128
Test name
Test status
Simulation time 22537088562 ps
CPU time 71.5 seconds
Started Oct 12 06:15:54 AM UTC 24
Finished Oct 12 06:17:07 AM UTC 24
Peak memory 820104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1375413225 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_overflow.1375413225
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/30.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/30.i2c_host_fifo_reset_fmt.1148487863
Short name T1069
Test name
Test status
Simulation time 474932095 ps
CPU time 1.51 seconds
Started Oct 12 06:15:54 AM UTC 24
Finished Oct 12 06:15:57 AM UTC 24
Peak memory 213332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1148487863 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_fmt.1148487863
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/30.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/30.i2c_host_fifo_reset_rx.2227846449
Short name T1073
Test name
Test status
Simulation time 224541742 ps
CPU time 8.08 seconds
Started Oct 12 06:15:56 AM UTC 24
Finished Oct 12 06:16:05 AM UTC 24
Peak memory 215844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2227846449 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_rx.2227846449
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/30.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/30.i2c_host_fifo_watermark.2246773609
Short name T1173
Test name
Test status
Simulation time 19463891416 ps
CPU time 138.04 seconds
Started Oct 12 06:15:54 AM UTC 24
Finished Oct 12 06:18:14 AM UTC 24
Peak memory 1555636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2246773609 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_watermark.2246773609
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/30.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/30.i2c_host_may_nack.3975062332
Short name T1108
Test name
Test status
Simulation time 558252836 ps
CPU time 20.13 seconds
Started Oct 12 06:16:20 AM UTC 24
Finished Oct 12 06:16:41 AM UTC 24
Peak memory 215456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3975062332 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.i2c_host_may_nack.3975062332
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/30.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/30.i2c_host_override.4196302068
Short name T1067
Test name
Test status
Simulation time 154844985 ps
CPU time 1.07 seconds
Started Oct 12 06:15:54 AM UTC 24
Finished Oct 12 06:15:56 AM UTC 24
Peak memory 213212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4196302068 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.i2c_host_override.4196302068
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/30.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/30.i2c_host_perf.1947616305
Short name T1409
Test name
Test status
Simulation time 28878501587 ps
CPU time 389.39 seconds
Started Oct 12 06:15:57 AM UTC 24
Finished Oct 12 06:22:32 AM UTC 24
Peak memory 287308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1947616305 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 30.i2c_host_perf.1947616305
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/30.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/30.i2c_host_perf_precise.771349350
Short name T1113
Test name
Test status
Simulation time 5766323141 ps
CPU time 49 seconds
Started Oct 12 06:15:57 AM UTC 24
Finished Oct 12 06:16:48 AM UTC 24
Peak memory 225340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=771349350 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_perf_precise.771349350
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/30.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/30.i2c_host_smoke.667371119
Short name T1104
Test name
Test status
Simulation time 1618566180 ps
CPU time 40.24 seconds
Started Oct 12 06:15:53 AM UTC 24
Finished Oct 12 06:16:34 AM UTC 24
Peak memory 382036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=667371119 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 30.i2c_host_smoke.667371119
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/30.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/30.i2c_host_stress_all.3089739929
Short name T122
Test name
Test status
Simulation time 53376887925 ps
CPU time 337.51 seconds
Started Oct 12 06:16:04 AM UTC 24
Finished Oct 12 06:21:46 AM UTC 24
Peak memory 2112588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3089739929 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 30.i2c_host_stress_all.3089739929
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/30.i2c_host_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/30.i2c_host_stretch_timeout.1330686549
Short name T1095
Test name
Test status
Simulation time 2855584443 ps
CPU time 31.75 seconds
Started Oct 12 06:15:58 AM UTC 24
Finished Oct 12 06:16:31 AM UTC 24
Peak memory 225760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1330686549 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_stretch_timeout.1330686549
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/30.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/30.i2c_target_bad_addr.1041244371
Short name T1092
Test name
Test status
Simulation time 1001435420 ps
CPU time 9.01 seconds
Started Oct 12 06:16:18 AM UTC 24
Finished Oct 12 06:16:28 AM UTC 24
Peak memory 229920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=1041244371 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_bad_ad
dr.1041244371
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/30.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/30.i2c_target_fifo_reset_acq.2207734228
Short name T1084
Test name
Test status
Simulation time 3329890137 ps
CPU time 2.33 seconds
Started Oct 12 06:16:16 AM UTC 24
Finished Oct 12 06:16:19 AM UTC 24
Peak memory 215464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2207734
228 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_fifo_reset_acq.2207734228
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/30.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/30.i2c_target_fifo_reset_tx.3193136903
Short name T1085
Test name
Test status
Simulation time 257011487 ps
CPU time 2.36 seconds
Started Oct 12 06:16:16 AM UTC 24
Finished Oct 12 06:16:19 AM UTC 24
Peak memory 215468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3193136
903 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_fifo_reset_tx.3193136903
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/30.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/30.i2c_target_fifo_watermarks_acq.646983180
Short name T1094
Test name
Test status
Simulation time 652673698 ps
CPU time 5.39 seconds
Started Oct 12 06:16:22 AM UTC 24
Finished Oct 12 06:16:29 AM UTC 24
Peak memory 215728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6469831
80 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_fifo_watermark
s_acq.646983180
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/30.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/30.i2c_target_fifo_watermarks_tx.3097166660
Short name T1093
Test name
Test status
Simulation time 1825270798 ps
CPU time 2.36 seconds
Started Oct 12 06:16:24 AM UTC 24
Finished Oct 12 06:16:28 AM UTC 24
Peak memory 215504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3097166
660 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_fifo_watermark
s_tx.3097166660
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/30.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/30.i2c_target_hrst.4164708233
Short name T1086
Test name
Test status
Simulation time 172321856 ps
CPU time 2.54 seconds
Started Oct 12 06:16:18 AM UTC 24
Finished Oct 12 06:16:21 AM UTC 24
Peak memory 215524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4164708
233 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_hrst.4164708233
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/30.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/30.i2c_target_intr_smoke.1141836468
Short name T1081
Test name
Test status
Simulation time 1314625854 ps
CPU time 6.18 seconds
Started Oct 12 06:16:08 AM UTC 24
Finished Oct 12 06:16:16 AM UTC 24
Peak memory 225752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=114183
6468 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_intr_smoke.1141836468
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/30.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/30.i2c_target_intr_stress_wr.1186737333
Short name T1078
Test name
Test status
Simulation time 272197432 ps
CPU time 3.02 seconds
Started Oct 12 06:16:09 AM UTC 24
Finished Oct 12 06:16:14 AM UTC 24
Peak memory 215576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1186737333 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_intr_stres
s_wr.1186737333
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/30.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/30.i2c_target_nack_acqfull.2011615322
Short name T1101
Test name
Test status
Simulation time 2049784446 ps
CPU time 4.54 seconds
Started Oct 12 06:16:28 AM UTC 24
Finished Oct 12 06:16:34 AM UTC 24
Peak memory 225768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2011615
322 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_nack_acqfull.2011615322
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/30.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/30.i2c_target_nack_acqfull_addr.1826713141
Short name T1098
Test name
Test status
Simulation time 1670394203 ps
CPU time 2.64 seconds
Started Oct 12 06:16:29 AM UTC 24
Finished Oct 12 06:16:33 AM UTC 24
Peak memory 215676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1826713
141 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_nack_acqfull_ad
dr.1826713141
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/30.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/30.i2c_target_perf.2027327445
Short name T1090
Test name
Test status
Simulation time 3713556218 ps
CPU time 8.8 seconds
Started Oct 12 06:16:17 AM UTC 24
Finished Oct 12 06:16:27 AM UTC 24
Peak memory 232300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2027327
445 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_perf.2027327445
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/30.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/30.i2c_target_smbus_maxlen.1679675727
Short name T1097
Test name
Test status
Simulation time 2127585373 ps
CPU time 4.35 seconds
Started Oct 12 06:16:25 AM UTC 24
Finished Oct 12 06:16:32 AM UTC 24
Peak memory 215248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1679675
727 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_smbus_maxlen.1679675727
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/30.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/30.i2c_target_smoke.2193169860
Short name T87
Test name
Test status
Simulation time 1017074805 ps
CPU time 10.4 seconds
Started Oct 12 06:16:04 AM UTC 24
Finished Oct 12 06:16:15 AM UTC 24
Peak memory 225968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2193169860 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_smoke.2193169860
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/30.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/30.i2c_target_stress_all.2105600191
Short name T1120
Test name
Test status
Simulation time 26440579011 ps
CPU time 43.25 seconds
Started Oct 12 06:16:17 AM UTC 24
Finished Oct 12 06:17:01 AM UTC 24
Peak memory 297936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=210560
0191 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_stress_all.2105600191
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/30.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/30.i2c_target_stress_rd.1354081421
Short name T1100
Test name
Test status
Simulation time 3025166940 ps
CPU time 48.06 seconds
Started Oct 12 06:16:07 AM UTC 24
Finished Oct 12 06:16:57 AM UTC 24
Peak memory 225768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1354081421 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_stress_rd.1354081421
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/30.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/30.i2c_target_stress_wr.2844220382
Short name T1149
Test name
Test status
Simulation time 47438341620 ps
CPU time 99.91 seconds
Started Oct 12 06:16:06 AM UTC 24
Finished Oct 12 06:17:48 AM UTC 24
Peak memory 1856768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2844220382 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_stress_wr.2844220382
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/30.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/30.i2c_target_stretch.4119581556
Short name T1200
Test name
Test status
Simulation time 3811228127 ps
CPU time 164.33 seconds
Started Oct 12 06:16:07 AM UTC 24
Finished Oct 12 06:18:54 AM UTC 24
Peak memory 1094980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4119581556 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_stretch.4119581556
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/30.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/30.i2c_target_timeout.244342236
Short name T1087
Test name
Test status
Simulation time 7305280337 ps
CPU time 9.99 seconds
Started Oct 12 06:16:11 AM UTC 24
Finished Oct 12 06:16:23 AM UTC 24
Peak memory 226028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2443422
36 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_timeout.244342236
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/30.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/30.i2c_target_tx_stretch_ctrl.3253474171
Short name T1099
Test name
Test status
Simulation time 188305912 ps
CPU time 6.15 seconds
Started Oct 12 06:16:25 AM UTC 24
Finished Oct 12 06:16:33 AM UTC 24
Peak memory 215724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3253474
171 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_target_tx_stretch_ctrl.3253474171
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/30.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/31.i2c_alert_test.1733479247
Short name T1124
Test name
Test status
Simulation time 27927679 ps
CPU time 0.95 seconds
Started Oct 12 06:17:04 AM UTC 24
Finished Oct 12 06:17:06 AM UTC 24
Peak memory 215628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1733479247 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_alert_test.1733479247
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/31.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/31.i2c_host_error_intr.3423544904
Short name T1107
Test name
Test status
Simulation time 244863818 ps
CPU time 3.36 seconds
Started Oct 12 06:16:36 AM UTC 24
Finished Oct 12 06:16:40 AM UTC 24
Peak memory 228088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3423544904 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 31.i2c_host_error_intr.3423544904
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/31.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/31.i2c_host_fifo_fmt_empty.3536174870
Short name T1110
Test name
Test status
Simulation time 347812678 ps
CPU time 9.51 seconds
Started Oct 12 06:16:34 AM UTC 24
Finished Oct 12 06:16:45 AM UTC 24
Peak memory 287628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3536174870 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_fmt_empty.3536174870
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/31.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/31.i2c_host_fifo_full.3619844647
Short name T1244
Test name
Test status
Simulation time 6132388472 ps
CPU time 191.63 seconds
Started Oct 12 06:16:35 AM UTC 24
Finished Oct 12 06:19:49 AM UTC 24
Peak memory 424828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3619844647 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_full.3619844647
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/31.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/31.i2c_host_fifo_overflow.1138367702
Short name T1169
Test name
Test status
Simulation time 1540625920 ps
CPU time 96.22 seconds
Started Oct 12 06:16:32 AM UTC 24
Finished Oct 12 06:18:10 AM UTC 24
Peak memory 590872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1138367702 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_overflow.1138367702
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/31.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/31.i2c_host_fifo_reset_fmt.2055534885
Short name T1106
Test name
Test status
Simulation time 309801267 ps
CPU time 1.28 seconds
Started Oct 12 06:16:34 AM UTC 24
Finished Oct 12 06:16:37 AM UTC 24
Peak memory 213272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2055534885 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_fmt.2055534885
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/31.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/31.i2c_host_fifo_reset_rx.4271888191
Short name T1114
Test name
Test status
Simulation time 2364017190 ps
CPU time 12.9 seconds
Started Oct 12 06:16:34 AM UTC 24
Finished Oct 12 06:16:48 AM UTC 24
Peak memory 215768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4271888191 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_rx.4271888191
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/31.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/31.i2c_host_fifo_watermark.4038789722
Short name T1206
Test name
Test status
Simulation time 11046773558 ps
CPU time 144.75 seconds
Started Oct 12 06:16:32 AM UTC 24
Finished Oct 12 06:18:59 AM UTC 24
Peak memory 1540976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4038789722 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_watermark.4038789722
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/31.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/31.i2c_host_may_nack.3127895714
Short name T1133
Test name
Test status
Simulation time 559375018 ps
CPU time 21.52 seconds
Started Oct 12 06:16:58 AM UTC 24
Finished Oct 12 06:17:21 AM UTC 24
Peak memory 215692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3127895714 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.i2c_host_may_nack.3127895714
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/31.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/31.i2c_host_override.2407040637
Short name T1103
Test name
Test status
Simulation time 27351334 ps
CPU time 1.06 seconds
Started Oct 12 06:16:32 AM UTC 24
Finished Oct 12 06:16:34 AM UTC 24
Peak memory 213212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2407040637 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.i2c_host_override.2407040637
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/31.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/31.i2c_host_perf.486875623
Short name T1135
Test name
Test status
Simulation time 13244756364 ps
CPU time 49.36 seconds
Started Oct 12 06:16:36 AM UTC 24
Finished Oct 12 06:17:27 AM UTC 24
Peak memory 215528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=486875623 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 31.i2c_host_perf.486875623
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/31.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/31.i2c_host_perf_precise.1104800579
Short name T1109
Test name
Test status
Simulation time 1317218409 ps
CPU time 6.94 seconds
Started Oct 12 06:16:36 AM UTC 24
Finished Oct 12 06:16:44 AM UTC 24
Peak memory 215376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1104800579 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_perf_precise.1104800579
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/31.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/31.i2c_host_smoke.424968726
Short name T1065
Test name
Test status
Simulation time 4974404339 ps
CPU time 27.92 seconds
Started Oct 12 06:16:30 AM UTC 24
Finished Oct 12 06:17:00 AM UTC 24
Peak memory 300036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=424968726 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 31.i2c_host_smoke.424968726
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/31.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/31.i2c_host_stress_all.4007464833
Short name T120
Test name
Test status
Simulation time 30528763646 ps
CPU time 202.45 seconds
Started Oct 12 06:16:36 AM UTC 24
Finished Oct 12 06:20:01 AM UTC 24
Peak memory 1842196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4007464833 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 31.i2c_host_stress_all.4007464833
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/31.i2c_host_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/31.i2c_host_stretch_timeout.1675675471
Short name T1112
Test name
Test status
Simulation time 2208939601 ps
CPU time 8.88 seconds
Started Oct 12 06:16:36 AM UTC 24
Finished Oct 12 06:16:46 AM UTC 24
Peak memory 228008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1675675471 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_stretch_timeout.1675675471
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/31.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/31.i2c_target_bad_addr.480808867
Short name T1040
Test name
Test status
Simulation time 883371939 ps
CPU time 7.23 seconds
Started Oct 12 06:16:55 AM UTC 24
Finished Oct 12 06:17:03 AM UTC 24
Peak memory 229864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=480808867 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_bad_addr.480808867
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/31.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/31.i2c_target_fifo_reset_acq.585847057
Short name T1115
Test name
Test status
Simulation time 849702307 ps
CPU time 1.95 seconds
Started Oct 12 06:16:50 AM UTC 24
Finished Oct 12 06:16:53 AM UTC 24
Peak memory 215576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5858470
57 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_fifo_reset_acq.585847057
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/31.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/31.i2c_target_fifo_reset_tx.3489962460
Short name T1117
Test name
Test status
Simulation time 175261068 ps
CPU time 1.66 seconds
Started Oct 12 06:16:52 AM UTC 24
Finished Oct 12 06:16:54 AM UTC 24
Peak memory 215512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3489962
460 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_fifo_reset_tx.3489962460
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/31.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/31.i2c_target_fifo_watermarks_acq.3552292433
Short name T1122
Test name
Test status
Simulation time 3310371934 ps
CPU time 3.66 seconds
Started Oct 12 06:17:01 AM UTC 24
Finished Oct 12 06:17:05 AM UTC 24
Peak memory 225812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3552292
433 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_fifo_watermar
ks_acq.3552292433
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/31.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/31.i2c_target_fifo_watermarks_tx.3102896760
Short name T1121
Test name
Test status
Simulation time 783770416 ps
CPU time 2.09 seconds
Started Oct 12 06:17:01 AM UTC 24
Finished Oct 12 06:17:04 AM UTC 24
Peak memory 215376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3102896
760 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_fifo_watermark
s_tx.3102896760
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/31.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/31.i2c_target_intr_smoke.4202523687
Short name T1116
Test name
Test status
Simulation time 1812287436 ps
CPU time 7.93 seconds
Started Oct 12 06:16:45 AM UTC 24
Finished Oct 12 06:16:54 AM UTC 24
Peak memory 225692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=420252
3687 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_intr_smoke.4202523687
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/31.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/31.i2c_target_intr_stress_wr.3762526526
Short name T1185
Test name
Test status
Simulation time 9671345326 ps
CPU time 99.36 seconds
Started Oct 12 06:16:46 AM UTC 24
Finished Oct 12 06:18:28 AM UTC 24
Peak memory 2477252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3762526526 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_intr_stres
s_wr.3762526526
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/31.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/31.i2c_target_nack_acqfull.1661336554
Short name T1129
Test name
Test status
Simulation time 486133861 ps
CPU time 4.33 seconds
Started Oct 12 06:17:02 AM UTC 24
Finished Oct 12 06:17:07 AM UTC 24
Peak memory 225828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1661336
554 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_nack_acqfull.1661336554
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/31.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/31.i2c_target_nack_acqfull_addr.2802701660
Short name T1127
Test name
Test status
Simulation time 1625384169 ps
CPU time 4.04 seconds
Started Oct 12 06:17:02 AM UTC 24
Finished Oct 12 06:17:07 AM UTC 24
Peak memory 215604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2802701
660 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_nack_acqfull_ad
dr.2802701660
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/31.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/31.i2c_target_nack_txstretch.4020836213
Short name T1125
Test name
Test status
Simulation time 572506489 ps
CPU time 2.13 seconds
Started Oct 12 06:17:03 AM UTC 24
Finished Oct 12 06:17:06 AM UTC 24
Peak memory 232248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4020836
213 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_nack_txstretch.4020836213
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/31.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/31.i2c_target_perf.1047673703
Short name T1119
Test name
Test status
Simulation time 6634970845 ps
CPU time 4.38 seconds
Started Oct 12 06:16:54 AM UTC 24
Finished Oct 12 06:16:59 AM UTC 24
Peak memory 232712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1047673
703 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_perf.1047673703
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/31.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/31.i2c_target_smbus_maxlen.3152953144
Short name T1123
Test name
Test status
Simulation time 432808992 ps
CPU time 3.6 seconds
Started Oct 12 06:17:01 AM UTC 24
Finished Oct 12 06:17:05 AM UTC 24
Peak memory 215504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3152953
144 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_smbus_maxlen.3152953144
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/31.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/31.i2c_target_smoke.3682980492
Short name T1071
Test name
Test status
Simulation time 773758664 ps
CPU time 23.61 seconds
Started Oct 12 06:16:37 AM UTC 24
Finished Oct 12 06:17:02 AM UTC 24
Peak memory 225764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3682980492 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_smoke.3682980492
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/31.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/31.i2c_target_stress_all.1736464479
Short name T1549
Test name
Test status
Simulation time 61531577132 ps
CPU time 487.49 seconds
Started Oct 12 06:16:55 AM UTC 24
Finished Oct 12 06:25:08 AM UTC 24
Peak memory 4631756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=173646
4479 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_stress_all.1736464479
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/31.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/31.i2c_target_stress_rd.2854881849
Short name T1088
Test name
Test status
Simulation time 860904955 ps
CPU time 16.81 seconds
Started Oct 12 06:16:42 AM UTC 24
Finished Oct 12 06:17:00 AM UTC 24
Peak memory 232376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2854881849 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_stress_rd.2854881849
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/31.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/31.i2c_target_stress_wr.2815757960
Short name T1239
Test name
Test status
Simulation time 48603978963 ps
CPU time 178.46 seconds
Started Oct 12 06:16:41 AM UTC 24
Finished Oct 12 06:19:42 AM UTC 24
Peak memory 2532208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2815757960 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_stress_wr.2815757960
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/31.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/31.i2c_target_stretch.172922277
Short name T1118
Test name
Test status
Simulation time 2263489176 ps
CPU time 11.73 seconds
Started Oct 12 06:16:44 AM UTC 24
Finished Oct 12 06:16:57 AM UTC 24
Peak memory 304256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=172922277 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_stretch.172922277
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/31.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/31.i2c_target_timeout.2109040931
Short name T1082
Test name
Test status
Simulation time 4989411917 ps
CPU time 12.69 seconds
Started Oct 12 06:16:47 AM UTC 24
Finished Oct 12 06:17:00 AM UTC 24
Peak memory 242628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2109040
931 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_timeout.2109040931
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/31.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/31.i2c_target_tx_stretch_ctrl.670529115
Short name T1126
Test name
Test status
Simulation time 204236029 ps
CPU time 5.02 seconds
Started Oct 12 06:17:01 AM UTC 24
Finished Oct 12 06:17:07 AM UTC 24
Peak memory 215472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6705291
15 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_target_tx_stretch_ctrl.670529115
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/31.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/32.i2c_alert_test.2697984933
Short name T1157
Test name
Test status
Simulation time 22474409 ps
CPU time 0.96 seconds
Started Oct 12 06:17:55 AM UTC 24
Finished Oct 12 06:17:57 AM UTC 24
Peak memory 213264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2697984933 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_alert_test.2697984933
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/32.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/32.i2c_host_error_intr.2070584836
Short name T1131
Test name
Test status
Simulation time 132981724 ps
CPU time 3.33 seconds
Started Oct 12 06:17:11 AM UTC 24
Finished Oct 12 06:17:16 AM UTC 24
Peak memory 227776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2070584836 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 32.i2c_host_error_intr.2070584836
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/32.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/32.i2c_host_fifo_fmt_empty.3830447470
Short name T1136
Test name
Test status
Simulation time 404521534 ps
CPU time 20.2 seconds
Started Oct 12 06:17:08 AM UTC 24
Finished Oct 12 06:17:29 AM UTC 24
Peak memory 299840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3830447470 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_fmt_empty.3830447470
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/32.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/32.i2c_host_fifo_full.1380650069
Short name T1300
Test name
Test status
Simulation time 6314832701 ps
CPU time 198.81 seconds
Started Oct 12 06:17:08 AM UTC 24
Finished Oct 12 06:20:30 AM UTC 24
Peak memory 488396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1380650069 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_full.1380650069
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/32.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/32.i2c_host_fifo_overflow.1050788161
Short name T1178
Test name
Test status
Simulation time 9862722872 ps
CPU time 74.09 seconds
Started Oct 12 06:17:07 AM UTC 24
Finished Oct 12 06:18:23 AM UTC 24
Peak memory 809992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1050788161 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_overflow.1050788161
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/32.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/32.i2c_host_fifo_reset_fmt.4097150723
Short name T244
Test name
Test status
Simulation time 69433139 ps
CPU time 1.55 seconds
Started Oct 12 06:17:08 AM UTC 24
Finished Oct 12 06:17:10 AM UTC 24
Peak memory 213272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4097150723 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_fmt.4097150723
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/32.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/32.i2c_host_fifo_reset_rx.202447510
Short name T1130
Test name
Test status
Simulation time 415551515 ps
CPU time 6.27 seconds
Started Oct 12 06:17:08 AM UTC 24
Finished Oct 12 06:17:15 AM UTC 24
Peak memory 215528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=202447510 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_rx.202447510
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/32.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/32.i2c_host_fifo_watermark.4237364238
Short name T119
Test name
Test status
Simulation time 3637898537 ps
CPU time 78.31 seconds
Started Oct 12 06:17:06 AM UTC 24
Finished Oct 12 06:18:27 AM UTC 24
Peak memory 961488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4237364238 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_watermark.4237364238
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/32.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/32.i2c_host_may_nack.1425997525
Short name T1168
Test name
Test status
Simulation time 579969770 ps
CPU time 21.24 seconds
Started Oct 12 06:17:46 AM UTC 24
Finished Oct 12 06:18:08 AM UTC 24
Peak memory 215456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1425997525 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.i2c_host_may_nack.1425997525
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/32.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/32.i2c_host_override.3119536860
Short name T143
Test name
Test status
Simulation time 55105404 ps
CPU time 0.98 seconds
Started Oct 12 06:17:04 AM UTC 24
Finished Oct 12 06:17:06 AM UTC 24
Peak memory 213212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3119536860 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.i2c_host_override.3119536860
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/32.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/32.i2c_host_perf.562304047
Short name T1190
Test name
Test status
Simulation time 10662118277 ps
CPU time 79.71 seconds
Started Oct 12 06:17:08 AM UTC 24
Finished Oct 12 06:18:30 AM UTC 24
Peak memory 875468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=562304047 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 32.i2c_host_perf.562304047
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/32.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/32.i2c_host_perf_precise.3970594567
Short name T1199
Test name
Test status
Simulation time 5848248316 ps
CPU time 99.87 seconds
Started Oct 12 06:17:08 AM UTC 24
Finished Oct 12 06:18:50 AM UTC 24
Peak memory 215452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3970594567 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_perf_precise.3970594567
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/32.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/32.i2c_host_smoke.2494038449
Short name T1140
Test name
Test status
Simulation time 1762278993 ps
CPU time 31.68 seconds
Started Oct 12 06:17:04 AM UTC 24
Finished Oct 12 06:17:37 AM UTC 24
Peak memory 298240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2494038449 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.i2c_host_smoke.2494038449
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/32.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/32.i2c_host_stretch_timeout.2483006372
Short name T1137
Test name
Test status
Simulation time 1203545582 ps
CPU time 20.98 seconds
Started Oct 12 06:17:08 AM UTC 24
Finished Oct 12 06:17:30 AM UTC 24
Peak memory 232224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2483006372 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_stretch_timeout.2483006372
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/32.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/32.i2c_target_bad_addr.220527727
Short name T1152
Test name
Test status
Simulation time 2304759396 ps
CPU time 10.77 seconds
Started Oct 12 06:17:41 AM UTC 24
Finished Oct 12 06:17:53 AM UTC 24
Peak memory 219940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=220527727 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_bad_addr.220527727
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/32.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/32.i2c_target_fifo_reset_acq.3835771421
Short name T1142
Test name
Test status
Simulation time 265655798 ps
CPU time 1.8 seconds
Started Oct 12 06:17:37 AM UTC 24
Finished Oct 12 06:17:40 AM UTC 24
Peak memory 215576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3835771
421 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_fifo_reset_acq.3835771421
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/32.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/32.i2c_target_fifo_reset_tx.3717141987
Short name T1144
Test name
Test status
Simulation time 258946950 ps
CPU time 2.71 seconds
Started Oct 12 06:17:38 AM UTC 24
Finished Oct 12 06:17:42 AM UTC 24
Peak memory 219568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3717141
987 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_fifo_reset_tx.3717141987
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/32.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/32.i2c_target_fifo_watermarks_acq.3624393795
Short name T1151
Test name
Test status
Simulation time 1467459299 ps
CPU time 4.09 seconds
Started Oct 12 06:17:47 AM UTC 24
Finished Oct 12 06:17:52 AM UTC 24
Peak memory 215832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3624393
795 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_fifo_watermar
ks_acq.3624393795
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/32.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/32.i2c_target_fifo_watermarks_tx.4200804461
Short name T1150
Test name
Test status
Simulation time 626496746 ps
CPU time 2.11 seconds
Started Oct 12 06:17:48 AM UTC 24
Finished Oct 12 06:17:52 AM UTC 24
Peak memory 215508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4200804
461 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_fifo_watermark
s_tx.4200804461
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/32.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/32.i2c_target_hrst.973365613
Short name T1148
Test name
Test status
Simulation time 1221597935 ps
CPU time 3.8 seconds
Started Oct 12 06:17:43 AM UTC 24
Finished Oct 12 06:17:48 AM UTC 24
Peak memory 225832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9733656
13 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_hrst.973365613
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/32.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/32.i2c_target_intr_smoke.4128799717
Short name T1138
Test name
Test status
Simulation time 525999353 ps
CPU time 5.68 seconds
Started Oct 12 06:17:28 AM UTC 24
Finished Oct 12 06:17:35 AM UTC 24
Peak memory 232596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=412879
9717 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_intr_smoke.4128799717
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/32.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/32.i2c_target_intr_stress_wr.549961028
Short name T1261
Test name
Test status
Simulation time 13681363554 ps
CPU time 144.59 seconds
Started Oct 12 06:17:30 AM UTC 24
Finished Oct 12 06:19:57 AM UTC 24
Peak memory 3535828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=549961028 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_intr_stress
_wr.549961028
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/32.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/32.i2c_target_nack_acqfull.515751584
Short name T1159
Test name
Test status
Simulation time 496443150 ps
CPU time 4.85 seconds
Started Oct 12 06:17:53 AM UTC 24
Finished Oct 12 06:17:59 AM UTC 24
Peak memory 225964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5157515
84 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_nack_acqfull.515751584
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/32.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/32.i2c_target_nack_acqfull_addr.3435097332
Short name T49
Test name
Test status
Simulation time 4025473852 ps
CPU time 3.29 seconds
Started Oct 12 06:17:54 AM UTC 24
Finished Oct 12 06:17:58 AM UTC 24
Peak memory 215808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3435097
332 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_nack_acqfull_ad
dr.3435097332
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/32.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/32.i2c_target_nack_txstretch.409372696
Short name T1158
Test name
Test status
Simulation time 136029610 ps
CPU time 2.51 seconds
Started Oct 12 06:17:54 AM UTC 24
Finished Oct 12 06:17:58 AM UTC 24
Peak memory 232248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4093726
96 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_nack_txstretch.409372696
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/32.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/32.i2c_target_perf.1587359304
Short name T1146
Test name
Test status
Simulation time 4455620232 ps
CPU time 6.61 seconds
Started Oct 12 06:17:39 AM UTC 24
Finished Oct 12 06:17:46 AM UTC 24
Peak memory 232312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1587359
304 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_perf.1587359304
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/32.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/32.i2c_target_smbus_maxlen.2748077941
Short name T1155
Test name
Test status
Simulation time 461459874 ps
CPU time 3.88 seconds
Started Oct 12 06:17:49 AM UTC 24
Finished Oct 12 06:17:54 AM UTC 24
Peak memory 215172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2748077
941 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_smbus_maxlen.2748077941
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/32.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/32.i2c_target_smoke.3954796715
Short name T1145
Test name
Test status
Simulation time 973605032 ps
CPU time 27.91 seconds
Started Oct 12 06:17:16 AM UTC 24
Finished Oct 12 06:17:46 AM UTC 24
Peak memory 232268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3954796715 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_smoke.3954796715
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/32.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/32.i2c_target_stress_all.1580039963
Short name T1171
Test name
Test status
Simulation time 95908575828 ps
CPU time 29.71 seconds
Started Oct 12 06:17:41 AM UTC 24
Finished Oct 12 06:18:12 AM UTC 24
Peak memory 248836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=158003
9963 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_stress_all.1580039963
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/32.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/32.i2c_target_stress_rd.3708947452
Short name T1163
Test name
Test status
Simulation time 1627788217 ps
CPU time 40.96 seconds
Started Oct 12 06:17:22 AM UTC 24
Finished Oct 12 06:18:04 AM UTC 24
Peak memory 225956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3708947452 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_stress_rd.3708947452
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/32.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/32.i2c_target_stress_wr.3202098390
Short name T1139
Test name
Test status
Simulation time 16367773739 ps
CPU time 13.39 seconds
Started Oct 12 06:17:22 AM UTC 24
Finished Oct 12 06:17:36 AM UTC 24
Peak memory 215784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3202098390 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_stress_wr.3202098390
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/32.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/32.i2c_target_stretch.3603574617
Short name T1226
Test name
Test status
Simulation time 2646053928 ps
CPU time 108.39 seconds
Started Oct 12 06:17:27 AM UTC 24
Finished Oct 12 06:19:17 AM UTC 24
Peak memory 805900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3603574617 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_stretch.3603574617
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/32.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/32.i2c_target_timeout.1142920965
Short name T1143
Test name
Test status
Simulation time 5836926429 ps
CPU time 9.58 seconds
Started Oct 12 06:17:31 AM UTC 24
Finished Oct 12 06:17:42 AM UTC 24
Peak memory 225696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1142920
965 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_timeout.1142920965
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/32.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/32.i2c_target_tx_stretch_ctrl.3394523192
Short name T1156
Test name
Test status
Simulation time 227640559 ps
CPU time 7.33 seconds
Started Oct 12 06:17:48 AM UTC 24
Finished Oct 12 06:17:57 AM UTC 24
Peak memory 228012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3394523
192 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_target_tx_stretch_ctrl.3394523192
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/32.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/33.i2c_alert_test.422309459
Short name T1191
Test name
Test status
Simulation time 23081502 ps
CPU time 1.03 seconds
Started Oct 12 06:18:28 AM UTC 24
Finished Oct 12 06:18:30 AM UTC 24
Peak memory 215628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=422309459 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_alert_test.422309459
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/33.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/33.i2c_host_error_intr.680789144
Short name T1165
Test name
Test status
Simulation time 465088486 ps
CPU time 2.48 seconds
Started Oct 12 06:18:02 AM UTC 24
Finished Oct 12 06:18:06 AM UTC 24
Peak memory 225840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=680789144 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 33.i2c_host_error_intr.680789144
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/33.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/33.i2c_host_fifo_fmt_empty.2535483861
Short name T1166
Test name
Test status
Simulation time 331787489 ps
CPU time 7.57 seconds
Started Oct 12 06:17:58 AM UTC 24
Finished Oct 12 06:18:07 AM UTC 24
Peak memory 285880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2535483861 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_fmt_empty.2535483861
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/33.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/33.i2c_host_fifo_full.2916207816
Short name T1351
Test name
Test status
Simulation time 3333077558 ps
CPU time 190.87 seconds
Started Oct 12 06:18:00 AM UTC 24
Finished Oct 12 06:21:13 AM UTC 24
Peak memory 765252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2916207816 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_full.2916207816
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/33.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/33.i2c_host_fifo_overflow.2725302681
Short name T1263
Test name
Test status
Simulation time 2718940033 ps
CPU time 118.73 seconds
Started Oct 12 06:17:58 AM UTC 24
Finished Oct 12 06:19:59 AM UTC 24
Peak memory 609288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2725302681 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_overflow.2725302681
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/33.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/33.i2c_host_fifo_reset_fmt.2677271483
Short name T1160
Test name
Test status
Simulation time 286834340 ps
CPU time 1.55 seconds
Started Oct 12 06:17:58 AM UTC 24
Finished Oct 12 06:18:01 AM UTC 24
Peak memory 213332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2677271483 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_fmt.2677271483
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/33.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/33.i2c_host_fifo_reset_rx.632829836
Short name T1167
Test name
Test status
Simulation time 332251095 ps
CPU time 6.96 seconds
Started Oct 12 06:18:00 AM UTC 24
Finished Oct 12 06:18:08 AM UTC 24
Peak memory 242692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=632829836 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_rx.632829836
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/33.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/33.i2c_host_fifo_watermark.2434897186
Short name T1209
Test name
Test status
Simulation time 6143142814 ps
CPU time 63.29 seconds
Started Oct 12 06:17:57 AM UTC 24
Finished Oct 12 06:19:02 AM UTC 24
Peak memory 914384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2434897186 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_watermark.2434897186
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/33.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/33.i2c_host_may_nack.169100484
Short name T1186
Test name
Test status
Simulation time 288352872 ps
CPU time 5.01 seconds
Started Oct 12 06:18:22 AM UTC 24
Finished Oct 12 06:18:28 AM UTC 24
Peak memory 215524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=169100484 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 33.i2c_host_may_nack.169100484
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/33.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/33.i2c_host_perf.3927569939
Short name T1198
Test name
Test status
Simulation time 2783352694 ps
CPU time 45.87 seconds
Started Oct 12 06:18:00 AM UTC 24
Finished Oct 12 06:18:47 AM UTC 24
Peak memory 225836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3927569939 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 33.i2c_host_perf.3927569939
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/33.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/33.i2c_host_perf_precise.3588261881
Short name T1164
Test name
Test status
Simulation time 41318953 ps
CPU time 2.6 seconds
Started Oct 12 06:18:02 AM UTC 24
Finished Oct 12 06:18:06 AM UTC 24
Peak memory 239968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3588261881 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_perf_precise.3588261881
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/33.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/33.i2c_host_smoke.2169764369
Short name T1195
Test name
Test status
Simulation time 2365974942 ps
CPU time 42.99 seconds
Started Oct 12 06:17:55 AM UTC 24
Finished Oct 12 06:18:40 AM UTC 24
Peak memory 461776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2169764369 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.i2c_host_smoke.2169764369
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/33.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/33.i2c_host_stretch_timeout.3282179889
Short name T1172
Test name
Test status
Simulation time 461591412 ps
CPU time 9.52 seconds
Started Oct 12 06:18:02 AM UTC 24
Finished Oct 12 06:18:13 AM UTC 24
Peak memory 225764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3282179889 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_stretch_timeout.3282179889
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/33.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/33.i2c_target_bad_addr.814966884
Short name T1182
Test name
Test status
Simulation time 456838040 ps
CPU time 4.15 seconds
Started Oct 12 06:18:19 AM UTC 24
Finished Oct 12 06:18:24 AM UTC 24
Peak memory 228080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=814966884 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_bad_addr.814966884
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/33.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/33.i2c_target_fifo_reset_acq.2452065031
Short name T1174
Test name
Test status
Simulation time 278486160 ps
CPU time 2.54 seconds
Started Oct 12 06:18:13 AM UTC 24
Finished Oct 12 06:18:17 AM UTC 24
Peak memory 215472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2452065
031 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_fifo_reset_acq.2452065031
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/33.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/33.i2c_target_fifo_reset_tx.944135537
Short name T1176
Test name
Test status
Simulation time 619569917 ps
CPU time 2.11 seconds
Started Oct 12 06:18:15 AM UTC 24
Finished Oct 12 06:18:18 AM UTC 24
Peak memory 217516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9441355
37 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_fifo_reset_tx.944135537
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/33.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/33.i2c_target_fifo_watermarks_acq.2892090765
Short name T1187
Test name
Test status
Simulation time 2039967030 ps
CPU time 3.94 seconds
Started Oct 12 06:18:23 AM UTC 24
Finished Oct 12 06:18:28 AM UTC 24
Peak memory 215444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2892090
765 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_fifo_watermar
ks_acq.2892090765
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/33.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/33.i2c_target_fifo_watermarks_tx.3609983111
Short name T1183
Test name
Test status
Simulation time 181897920 ps
CPU time 1.52 seconds
Started Oct 12 06:18:23 AM UTC 24
Finished Oct 12 06:18:26 AM UTC 24
Peak memory 213508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3609983
111 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_fifo_watermark
s_tx.3609983111
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/33.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/33.i2c_target_hrst.2631175399
Short name T1180
Test name
Test status
Simulation time 1311461425 ps
CPU time 3.93 seconds
Started Oct 12 06:18:19 AM UTC 24
Finished Oct 12 06:18:24 AM UTC 24
Peak memory 225764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2631175
399 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_hrst.2631175399
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/33.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/33.i2c_target_intr_smoke.1361013100
Short name T1175
Test name
Test status
Simulation time 1978954700 ps
CPU time 6.21 seconds
Started Oct 12 06:18:10 AM UTC 24
Finished Oct 12 06:18:17 AM UTC 24
Peak memory 225632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=136101
3100 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_intr_smoke.1361013100
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/33.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/33.i2c_target_intr_stress_wr.1480004065
Short name T1531
Test name
Test status
Simulation time 26086543430 ps
CPU time 393.43 seconds
Started Oct 12 06:18:12 AM UTC 24
Finished Oct 12 06:24:50 AM UTC 24
Peak memory 6079684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1480004065 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_intr_stres
s_wr.1480004065
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/33.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/33.i2c_target_nack_acqfull.469870286
Short name T1193
Test name
Test status
Simulation time 2873795247 ps
CPU time 4.55 seconds
Started Oct 12 06:18:25 AM UTC 24
Finished Oct 12 06:18:30 AM UTC 24
Peak memory 225888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4698702
86 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_nack_acqfull.469870286
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/33.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/33.i2c_target_nack_acqfull_addr.2775806596
Short name T1189
Test name
Test status
Simulation time 1431812525 ps
CPU time 3.66 seconds
Started Oct 12 06:18:25 AM UTC 24
Finished Oct 12 06:18:29 AM UTC 24
Peak memory 215488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2775806
596 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_nack_acqfull_ad
dr.2775806596
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/33.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/33.i2c_target_nack_txstretch.3374607331
Short name T1192
Test name
Test status
Simulation time 128178003 ps
CPU time 2.19 seconds
Started Oct 12 06:18:27 AM UTC 24
Finished Oct 12 06:18:30 AM UTC 24
Peak memory 232256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3374607
331 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_nack_txstretch.3374607331
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/33.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/33.i2c_target_perf.4263659261
Short name T1179
Test name
Test status
Simulation time 1533707453 ps
CPU time 6.28 seconds
Started Oct 12 06:18:16 AM UTC 24
Finished Oct 12 06:18:24 AM UTC 24
Peak memory 232232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4263659
261 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_perf.4263659261
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/33.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/33.i2c_target_smbus_maxlen.3335674121
Short name T1188
Test name
Test status
Simulation time 474028788 ps
CPU time 3.56 seconds
Started Oct 12 06:18:25 AM UTC 24
Finished Oct 12 06:18:29 AM UTC 24
Peak memory 215168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3335674
121 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_smbus_maxlen.3335674121
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/33.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/33.i2c_target_smoke.2005862971
Short name T1177
Test name
Test status
Simulation time 696962684 ps
CPU time 13.53 seconds
Started Oct 12 06:18:06 AM UTC 24
Finished Oct 12 06:18:21 AM UTC 24
Peak memory 225768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2005862971 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_smoke.2005862971
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/33.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/33.i2c_target_stress_all.4203154019
Short name T1423
Test name
Test status
Simulation time 74929339599 ps
CPU time 270.41 seconds
Started Oct 12 06:18:17 AM UTC 24
Finished Oct 12 06:22:51 AM UTC 24
Peak memory 2378608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=420315
4019 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_stress_all.4203154019
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/33.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/33.i2c_target_stress_rd.3728057561
Short name T1147
Test name
Test status
Simulation time 4747847017 ps
CPU time 21.78 seconds
Started Oct 12 06:18:08 AM UTC 24
Finished Oct 12 06:18:32 AM UTC 24
Peak memory 232764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3728057561 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_stress_rd.3728057561
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/33.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/33.i2c_target_stress_wr.15725017
Short name T1386
Test name
Test status
Simulation time 65490223901 ps
CPU time 232.59 seconds
Started Oct 12 06:18:06 AM UTC 24
Finished Oct 12 06:22:02 AM UTC 24
Peak memory 2980828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=15725017 -assert nopostpro
c +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_stress_wr.15725017
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/33.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/33.i2c_target_stretch.93425213
Short name T1224
Test name
Test status
Simulation time 3336994477 ps
CPU time 63.74 seconds
Started Oct 12 06:18:08 AM UTC 24
Finished Oct 12 06:19:14 AM UTC 24
Peak memory 559996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=93425213 -assert nopostpro
c +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_stretch.93425213
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/33.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/33.i2c_target_timeout.1438640150
Short name T1181
Test name
Test status
Simulation time 2871588654 ps
CPU time 10.83 seconds
Started Oct 12 06:18:12 AM UTC 24
Finished Oct 12 06:18:24 AM UTC 24
Peak memory 225756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1438640
150 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_timeout.1438640150
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/33.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/33.i2c_target_tx_stretch_ctrl.2486012188
Short name T1184
Test name
Test status
Simulation time 61538594 ps
CPU time 2.35 seconds
Started Oct 12 06:18:24 AM UTC 24
Finished Oct 12 06:18:28 AM UTC 24
Peak memory 215656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2486012
188 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_target_tx_stretch_ctrl.2486012188
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/33.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/34.i2c_alert_test.1652944691
Short name T1221
Test name
Test status
Simulation time 27190807 ps
CPU time 1.03 seconds
Started Oct 12 06:19:11 AM UTC 24
Finished Oct 12 06:19:13 AM UTC 24
Peak memory 215628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1652944691 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_alert_test.1652944691
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/34.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/34.i2c_host_error_intr.2398607982
Short name T1205
Test name
Test status
Simulation time 443968234 ps
CPU time 23.06 seconds
Started Oct 12 06:18:33 AM UTC 24
Finished Oct 12 06:18:57 AM UTC 24
Peak memory 302300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2398607982 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 34.i2c_host_error_intr.2398607982
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/34.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/34.i2c_host_fifo_fmt_empty.1036303252
Short name T1196
Test name
Test status
Simulation time 307817211 ps
CPU time 8.66 seconds
Started Oct 12 06:18:30 AM UTC 24
Finished Oct 12 06:18:40 AM UTC 24
Peak memory 279360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1036303252 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_fmt_empty.1036303252
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/34.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/34.i2c_host_fifo_full.3983949787
Short name T1391
Test name
Test status
Simulation time 15649366979 ps
CPU time 213.98 seconds
Started Oct 12 06:18:31 AM UTC 24
Finished Oct 12 06:22:08 AM UTC 24
Peak memory 703812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3983949787 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_full.3983949787
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/34.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/34.i2c_host_fifo_overflow.2131877434
Short name T1231
Test name
Test status
Simulation time 9692175528 ps
CPU time 60.8 seconds
Started Oct 12 06:18:29 AM UTC 24
Finished Oct 12 06:19:32 AM UTC 24
Peak memory 576660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2131877434 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_overflow.2131877434
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/34.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/34.i2c_host_fifo_reset_fmt.1788893509
Short name T1194
Test name
Test status
Simulation time 593797051 ps
CPU time 1.49 seconds
Started Oct 12 06:18:30 AM UTC 24
Finished Oct 12 06:18:33 AM UTC 24
Peak memory 213332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1788893509 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_fmt.1788893509
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/34.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/34.i2c_host_fifo_reset_rx.1302782460
Short name T1197
Test name
Test status
Simulation time 637499534 ps
CPU time 11.45 seconds
Started Oct 12 06:18:31 AM UTC 24
Finished Oct 12 06:18:43 AM UTC 24
Peak memory 215468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1302782460 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_rx.1302782460
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/34.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/34.i2c_host_fifo_watermark.432251827
Short name T1248
Test name
Test status
Simulation time 2983509846 ps
CPU time 79.89 seconds
Started Oct 12 06:18:29 AM UTC 24
Finished Oct 12 06:19:51 AM UTC 24
Peak memory 959696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=432251827 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_watermark.432251827
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/34.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/34.i2c_host_may_nack.2348976107
Short name T252
Test name
Test status
Simulation time 2126195842 ps
CPU time 26.19 seconds
Started Oct 12 06:19:02 AM UTC 24
Finished Oct 12 06:19:29 AM UTC 24
Peak memory 215512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2348976107 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.i2c_host_may_nack.2348976107
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/34.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/34.i2c_host_override.3100505479
Short name T144
Test name
Test status
Simulation time 31889939 ps
CPU time 1.1 seconds
Started Oct 12 06:18:29 AM UTC 24
Finished Oct 12 06:18:31 AM UTC 24
Peak memory 213144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3100505479 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.i2c_host_override.3100505479
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/34.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/34.i2c_host_perf.1692632833
Short name T1541
Test name
Test status
Simulation time 27520836504 ps
CPU time 382.25 seconds
Started Oct 12 06:18:31 AM UTC 24
Finished Oct 12 06:24:58 AM UTC 24
Peak memory 1000452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1692632833 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 34.i2c_host_perf.1692632833
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/34.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/34.i2c_host_perf_precise.1726165105
Short name T1483
Test name
Test status
Simulation time 5849553487 ps
CPU time 310.33 seconds
Started Oct 12 06:18:32 AM UTC 24
Finished Oct 12 06:23:46 AM UTC 24
Peak memory 1231716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1726165105 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_perf_precise.1726165105
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/34.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/34.i2c_host_smoke.64779662
Short name T1210
Test name
Test status
Simulation time 3160129199 ps
CPU time 33.07 seconds
Started Oct 12 06:18:29 AM UTC 24
Finished Oct 12 06:19:03 AM UTC 24
Peak memory 428996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=64779662 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ho
st_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 34.i2c_host_smoke.64779662
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/34.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/34.i2c_host_stretch_timeout.3869893971
Short name T1202
Test name
Test status
Simulation time 1707045925 ps
CPU time 23.04 seconds
Started Oct 12 06:18:32 AM UTC 24
Finished Oct 12 06:18:56 AM UTC 24
Peak memory 225732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3869893971 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_stretch_timeout.3869893971
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/34.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/34.i2c_target_bad_addr.287738356
Short name T1215
Test name
Test status
Simulation time 2777149765 ps
CPU time 9.72 seconds
Started Oct 12 06:18:58 AM UTC 24
Finished Oct 12 06:19:09 AM UTC 24
Peak memory 231844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=287738356 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_bad_addr.287738356
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/34.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/34.i2c_target_fifo_reset_acq.975848651
Short name T1208
Test name
Test status
Simulation time 249670317 ps
CPU time 2.98 seconds
Started Oct 12 06:18:57 AM UTC 24
Finished Oct 12 06:19:01 AM UTC 24
Peak memory 215396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9758486
51 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_fifo_reset_acq.975848651
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/34.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/34.i2c_target_fifo_reset_tx.3880435104
Short name T1207
Test name
Test status
Simulation time 250680611 ps
CPU time 1.62 seconds
Started Oct 12 06:18:57 AM UTC 24
Finished Oct 12 06:19:00 AM UTC 24
Peak memory 215576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3880435
104 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_fifo_reset_tx.3880435104
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/34.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/34.i2c_target_fifo_watermarks_acq.3000620004
Short name T1214
Test name
Test status
Simulation time 1025196236 ps
CPU time 4.59 seconds
Started Oct 12 06:19:03 AM UTC 24
Finished Oct 12 06:19:09 AM UTC 24
Peak memory 215840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3000620
004 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_fifo_watermar
ks_acq.3000620004
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/34.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/34.i2c_target_fifo_watermarks_tx.2755681552
Short name T1212
Test name
Test status
Simulation time 140209044 ps
CPU time 1.48 seconds
Started Oct 12 06:19:04 AM UTC 24
Finished Oct 12 06:19:06 AM UTC 24
Peak memory 215572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2755681
552 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_fifo_watermark
s_tx.2755681552
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/34.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/34.i2c_target_intr_smoke.4123532114
Short name T1201
Test name
Test status
Simulation time 6546418921 ps
CPU time 7.15 seconds
Started Oct 12 06:18:48 AM UTC 24
Finished Oct 12 06:18:56 AM UTC 24
Peak memory 232636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=412353
2114 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_intr_smoke.4123532114
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/34.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/34.i2c_target_intr_stress_wr.3678006802
Short name T1247
Test name
Test status
Simulation time 18516858803 ps
CPU time 58.07 seconds
Started Oct 12 06:18:51 AM UTC 24
Finished Oct 12 06:19:50 AM UTC 24
Peak memory 1147772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3678006802 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_intr_stres
s_wr.3678006802
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/34.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/34.i2c_target_nack_acqfull.1426369736
Short name T1218
Test name
Test status
Simulation time 1621359437 ps
CPU time 3.63 seconds
Started Oct 12 06:19:07 AM UTC 24
Finished Oct 12 06:19:12 AM UTC 24
Peak memory 225704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1426369
736 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_nack_acqfull.1426369736
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/34.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/34.i2c_target_nack_acqfull_addr.728343361
Short name T1220
Test name
Test status
Simulation time 1789239166 ps
CPU time 3.28 seconds
Started Oct 12 06:19:08 AM UTC 24
Finished Oct 12 06:19:13 AM UTC 24
Peak memory 215488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7283433
61 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_nack_acqfull_addr.728343361
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/34.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/34.i2c_target_nack_txstretch.3784475170
Short name T1219
Test name
Test status
Simulation time 139125754 ps
CPU time 2.05 seconds
Started Oct 12 06:19:09 AM UTC 24
Finished Oct 12 06:19:13 AM UTC 24
Peak memory 232652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3784475
170 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_nack_txstretch.3784475170
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/34.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/34.i2c_target_perf.2073382972
Short name T1213
Test name
Test status
Simulation time 2857147072 ps
CPU time 8.5 seconds
Started Oct 12 06:18:57 AM UTC 24
Finished Oct 12 06:19:07 AM UTC 24
Peak memory 227744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2073382
972 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_perf.2073382972
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/34.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/34.i2c_target_smbus_maxlen.3661008047
Short name T1222
Test name
Test status
Simulation time 589068553 ps
CPU time 4.86 seconds
Started Oct 12 06:19:07 AM UTC 24
Finished Oct 12 06:19:13 AM UTC 24
Peak memory 215176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3661008
047 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_smbus_maxlen.3661008047
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/34.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/34.i2c_target_smoke.476366525
Short name T1203
Test name
Test status
Simulation time 2355426597 ps
CPU time 19.04 seconds
Started Oct 12 06:18:36 AM UTC 24
Finished Oct 12 06:18:57 AM UTC 24
Peak memory 226152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=476366525 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_smoke.476366525
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/34.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/34.i2c_target_stress_all.555798176
Short name T1290
Test name
Test status
Simulation time 44171854091 ps
CPU time 79.66 seconds
Started Oct 12 06:18:58 AM UTC 24
Finished Oct 12 06:20:20 AM UTC 24
Peak memory 949188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=555798
176 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_stress_all.555798176
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/34.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/34.i2c_target_stress_rd.3487493270
Short name T1217
Test name
Test status
Simulation time 1068505838 ps
CPU time 28.11 seconds
Started Oct 12 06:18:41 AM UTC 24
Finished Oct 12 06:19:11 AM UTC 24
Peak memory 226016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3487493270 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_stress_rd.3487493270
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/34.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/34.i2c_target_stress_wr.2831838410
Short name T1649
Test name
Test status
Simulation time 44638922510 ps
CPU time 568.88 seconds
Started Oct 12 06:18:40 AM UTC 24
Finished Oct 12 06:28:15 AM UTC 24
Peak memory 6595776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2831838410 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_stress_wr.2831838410
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/34.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/34.i2c_target_timeout.2838413294
Short name T1211
Test name
Test status
Simulation time 4333440252 ps
CPU time 11.51 seconds
Started Oct 12 06:18:52 AM UTC 24
Finished Oct 12 06:19:04 AM UTC 24
Peak memory 232400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2838413
294 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_timeout.2838413294
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/34.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/34.i2c_target_tx_stretch_ctrl.3770687593
Short name T1216
Test name
Test status
Simulation time 176655684 ps
CPU time 4.53 seconds
Started Oct 12 06:19:05 AM UTC 24
Finished Oct 12 06:19:11 AM UTC 24
Peak memory 215396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3770687
593 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_target_tx_stretch_ctrl.3770687593
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/34.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/35.i2c_alert_test.1400686628
Short name T1251
Test name
Test status
Simulation time 17324954 ps
CPU time 0.84 seconds
Started Oct 12 06:19:51 AM UTC 24
Finished Oct 12 06:19:52 AM UTC 24
Peak memory 215628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1400686628 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_alert_test.1400686628
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/35.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/35.i2c_host_error_intr.335085122
Short name T1236
Test name
Test status
Simulation time 504409556 ps
CPU time 18.67 seconds
Started Oct 12 06:19:19 AM UTC 24
Finished Oct 12 06:19:39 AM UTC 24
Peak memory 246856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=335085122 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 35.i2c_host_error_intr.335085122
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/35.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/35.i2c_host_fifo_fmt_empty.1340938787
Short name T1230
Test name
Test status
Simulation time 711010735 ps
CPU time 9.04 seconds
Started Oct 12 06:19:14 AM UTC 24
Finished Oct 12 06:19:24 AM UTC 24
Peak memory 295796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1340938787 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_fmt_empty.1340938787
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/35.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/35.i2c_host_fifo_full.2061546087
Short name T1298
Test name
Test status
Simulation time 2331638055 ps
CPU time 73.16 seconds
Started Oct 12 06:19:14 AM UTC 24
Finished Oct 12 06:20:29 AM UTC 24
Peak memory 609284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2061546087 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_full.2061546087
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/35.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/35.i2c_host_fifo_overflow.2817785784
Short name T1266
Test name
Test status
Simulation time 3066773140 ps
CPU time 47.21 seconds
Started Oct 12 06:19:14 AM UTC 24
Finished Oct 12 06:20:03 AM UTC 24
Peak memory 605188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2817785784 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_overflow.2817785784
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/35.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/35.i2c_host_fifo_reset_fmt.3836584716
Short name T1225
Test name
Test status
Simulation time 256955279 ps
CPU time 1.74 seconds
Started Oct 12 06:19:14 AM UTC 24
Finished Oct 12 06:19:17 AM UTC 24
Peak memory 213332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3836584716 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_fmt.3836584716
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/35.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/35.i2c_host_fifo_reset_rx.1775953909
Short name T1229
Test name
Test status
Simulation time 823772891 ps
CPU time 7.01 seconds
Started Oct 12 06:19:14 AM UTC 24
Finished Oct 12 06:19:22 AM UTC 24
Peak memory 215452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1775953909 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_rx.1775953909
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/35.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/35.i2c_host_fifo_watermark.3135792685
Short name T121
Test name
Test status
Simulation time 9906918245 ps
CPU time 96.26 seconds
Started Oct 12 06:19:13 AM UTC 24
Finished Oct 12 06:20:51 AM UTC 24
Peak memory 1446920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3135792685 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_watermark.3135792685
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/35.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/35.i2c_host_may_nack.1499128996
Short name T1257
Test name
Test status
Simulation time 2074964042 ps
CPU time 10.07 seconds
Started Oct 12 06:19:44 AM UTC 24
Finished Oct 12 06:19:56 AM UTC 24
Peak memory 215772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1499128996 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.i2c_host_may_nack.1499128996
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/35.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/35.i2c_host_override.2183542623
Short name T1223
Test name
Test status
Simulation time 90944768 ps
CPU time 0.95 seconds
Started Oct 12 06:19:12 AM UTC 24
Finished Oct 12 06:19:14 AM UTC 24
Peak memory 213212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2183542623 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.i2c_host_override.2183542623
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/35.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/35.i2c_host_perf.4092151676
Short name T1234
Test name
Test status
Simulation time 31834080084 ps
CPU time 21.1 seconds
Started Oct 12 06:19:15 AM UTC 24
Finished Oct 12 06:19:38 AM UTC 24
Peak memory 215588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4092151676 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 35.i2c_host_perf.4092151676
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/35.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/35.i2c_host_perf_precise.2927829434
Short name T1227
Test name
Test status
Simulation time 98738698 ps
CPU time 1.54 seconds
Started Oct 12 06:19:15 AM UTC 24
Finished Oct 12 06:19:18 AM UTC 24
Peak memory 213212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2927829434 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_perf_precise.2927829434
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/35.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/35.i2c_host_smoke.2042459221
Short name T1242
Test name
Test status
Simulation time 1806908492 ps
CPU time 32.34 seconds
Started Oct 12 06:19:12 AM UTC 24
Finished Oct 12 06:19:45 AM UTC 24
Peak memory 443524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2042459221 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.i2c_host_smoke.2042459221
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/35.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/35.i2c_host_stretch_timeout.1354987249
Short name T1232
Test name
Test status
Simulation time 1148821662 ps
CPU time 14.06 seconds
Started Oct 12 06:19:18 AM UTC 24
Finished Oct 12 06:19:33 AM UTC 24
Peak memory 225684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1354987249 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_stretch_timeout.1354987249
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/35.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/35.i2c_target_bad_addr.949780897
Short name T1250
Test name
Test status
Simulation time 2025879454 ps
CPU time 8.41 seconds
Started Oct 12 06:19:43 AM UTC 24
Finished Oct 12 06:19:52 AM UTC 24
Peak memory 230052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=949780897 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_bad_addr.949780897
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/35.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/35.i2c_target_fifo_reset_acq.3195719155
Short name T1238
Test name
Test status
Simulation time 158425218 ps
CPU time 2.03 seconds
Started Oct 12 06:19:38 AM UTC 24
Finished Oct 12 06:19:41 AM UTC 24
Peak memory 215512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3195719
155 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_fifo_reset_acq.3195719155
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/35.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/35.i2c_target_fifo_reset_tx.1840757895
Short name T1240
Test name
Test status
Simulation time 251785462 ps
CPU time 1.39 seconds
Started Oct 12 06:19:40 AM UTC 24
Finished Oct 12 06:19:43 AM UTC 24
Peak memory 215576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1840757
895 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_fifo_reset_tx.1840757895
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/35.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/35.i2c_target_fifo_watermarks_acq.222547889
Short name T1253
Test name
Test status
Simulation time 544518525 ps
CPU time 5.59 seconds
Started Oct 12 06:19:46 AM UTC 24
Finished Oct 12 06:19:53 AM UTC 24
Peak memory 215396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2225478
89 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_fifo_watermark
s_acq.222547889
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/35.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/35.i2c_target_fifo_watermarks_tx.2837160623
Short name T1246
Test name
Test status
Simulation time 161747541 ps
CPU time 2.12 seconds
Started Oct 12 06:19:46 AM UTC 24
Finished Oct 12 06:19:49 AM UTC 24
Peak memory 215244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2837160
623 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_fifo_watermark
s_tx.2837160623
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/35.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/35.i2c_target_intr_smoke.4057977325
Short name T1235
Test name
Test status
Simulation time 1105675538 ps
CPU time 7.17 seconds
Started Oct 12 06:19:30 AM UTC 24
Finished Oct 12 06:19:38 AM UTC 24
Peak memory 225640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=405797
7325 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_intr_smoke.4057977325
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/35.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/35.i2c_target_intr_stress_wr.1594022035
Short name T1243
Test name
Test status
Simulation time 13255405481 ps
CPU time 11.74 seconds
Started Oct 12 06:19:34 AM UTC 24
Finished Oct 12 06:19:47 AM UTC 24
Peak memory 215504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1594022035 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_intr_stres
s_wr.1594022035
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/35.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/35.i2c_target_nack_acqfull.2366259574
Short name T1260
Test name
Test status
Simulation time 1114172489 ps
CPU time 5.09 seconds
Started Oct 12 06:19:51 AM UTC 24
Finished Oct 12 06:19:57 AM UTC 24
Peak memory 225636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2366259
574 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_nack_acqfull.2366259574
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/35.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/35.i2c_target_nack_acqfull_addr.2154304970
Short name T1259
Test name
Test status
Simulation time 2135256008 ps
CPU time 4.76 seconds
Started Oct 12 06:19:51 AM UTC 24
Finished Oct 12 06:19:56 AM UTC 24
Peak memory 215412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2154304
970 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_nack_acqfull_ad
dr.2154304970
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/35.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/35.i2c_target_perf.2943881530
Short name T1249
Test name
Test status
Simulation time 849000822 ps
CPU time 10.19 seconds
Started Oct 12 06:19:40 AM UTC 24
Finished Oct 12 06:19:52 AM UTC 24
Peak memory 232424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2943881
530 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_perf.2943881530
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/35.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/35.i2c_target_smbus_maxlen.861148004
Short name T1254
Test name
Test status
Simulation time 481219711 ps
CPU time 2.91 seconds
Started Oct 12 06:19:49 AM UTC 24
Finished Oct 12 06:19:53 AM UTC 24
Peak memory 215244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8611480
04 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_smbus_maxlen.861148004
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/35.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/35.i2c_target_smoke.2621503005
Short name T1270
Test name
Test status
Simulation time 6508185059 ps
CPU time 42.37 seconds
Started Oct 12 06:19:24 AM UTC 24
Finished Oct 12 06:20:09 AM UTC 24
Peak memory 226088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2621503005 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_smoke.2621503005
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/35.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/35.i2c_target_stress_all.4267104003
Short name T1287
Test name
Test status
Simulation time 25363455699 ps
CPU time 36.11 seconds
Started Oct 12 06:19:41 AM UTC 24
Finished Oct 12 06:20:18 AM UTC 24
Peak memory 281536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=426710
4003 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_stress_all.4267104003
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/35.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/35.i2c_target_stress_rd.2806673155
Short name T1325
Test name
Test status
Simulation time 1579279044 ps
CPU time 78.81 seconds
Started Oct 12 06:19:26 AM UTC 24
Finished Oct 12 06:20:47 AM UTC 24
Peak memory 229732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2806673155 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_stress_rd.2806673155
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/35.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/35.i2c_target_stress_wr.4090835452
Short name T1233
Test name
Test status
Simulation time 9246733393 ps
CPU time 9.15 seconds
Started Oct 12 06:19:25 AM UTC 24
Finished Oct 12 06:19:35 AM UTC 24
Peak memory 215528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4090835452 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_stress_wr.4090835452
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/35.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/35.i2c_target_stretch.974201374
Short name T1295
Test name
Test status
Simulation time 3540026692 ps
CPU time 58.67 seconds
Started Oct 12 06:19:26 AM UTC 24
Finished Oct 12 06:20:27 AM UTC 24
Peak memory 545772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=974201374 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_stretch.974201374
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/35.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/35.i2c_target_timeout.1857803112
Short name T1241
Test name
Test status
Simulation time 18491646836 ps
CPU time 10.08 seconds
Started Oct 12 06:19:34 AM UTC 24
Finished Oct 12 06:19:45 AM UTC 24
Peak memory 232264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1857803
112 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_timeout.1857803112
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/35.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/35.i2c_target_tx_stretch_ctrl.1918496983
Short name T1252
Test name
Test status
Simulation time 78765523 ps
CPU time 3.48 seconds
Started Oct 12 06:19:48 AM UTC 24
Finished Oct 12 06:19:53 AM UTC 24
Peak memory 215788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1918496
983 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_target_tx_stretch_ctrl.1918496983
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/35.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/36.i2c_alert_test.3656990577
Short name T1279
Test name
Test status
Simulation time 95816960 ps
CPU time 0.98 seconds
Started Oct 12 06:20:11 AM UTC 24
Finished Oct 12 06:20:13 AM UTC 24
Peak memory 215628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3656990577 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_alert_test.3656990577
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/36.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/36.i2c_host_error_intr.3641076144
Short name T1265
Test name
Test status
Simulation time 421016053 ps
CPU time 2.39 seconds
Started Oct 12 06:19:57 AM UTC 24
Finished Oct 12 06:20:00 AM UTC 24
Peak memory 227820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3641076144 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 36.i2c_host_error_intr.3641076144
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/36.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/36.i2c_host_fifo_fmt_empty.2168343407
Short name T1255
Test name
Test status
Simulation time 1310114305 ps
CPU time 10.12 seconds
Started Oct 12 06:19:54 AM UTC 24
Finished Oct 12 06:20:06 AM UTC 24
Peak memory 301960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2168343407 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_fmt_empty.2168343407
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/36.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/36.i2c_host_fifo_full.1040358942
Short name T1345
Test name
Test status
Simulation time 11316319171 ps
CPU time 74.3 seconds
Started Oct 12 06:19:55 AM UTC 24
Finished Oct 12 06:21:11 AM UTC 24
Peak memory 531388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1040358942 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_full.1040358942
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/36.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/36.i2c_host_fifo_overflow.1907479129
Short name T1335
Test name
Test status
Simulation time 2188788218 ps
CPU time 67.02 seconds
Started Oct 12 06:19:53 AM UTC 24
Finished Oct 12 06:21:02 AM UTC 24
Peak memory 734416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1907479129 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_overflow.1907479129
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/36.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/36.i2c_host_fifo_reset_fmt.844434880
Short name T1258
Test name
Test status
Simulation time 992879790 ps
CPU time 1.6 seconds
Started Oct 12 06:19:53 AM UTC 24
Finished Oct 12 06:19:56 AM UTC 24
Peak memory 213212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=844434880 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_fmt.844434880
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/36.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/36.i2c_host_fifo_reset_rx.3411349806
Short name T1264
Test name
Test status
Simulation time 519706475 ps
CPU time 4.45 seconds
Started Oct 12 06:19:54 AM UTC 24
Finished Oct 12 06:20:00 AM UTC 24
Peak memory 238476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3411349806 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_rx.3411349806
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/36.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/36.i2c_host_fifo_watermark.4097836511
Short name T1475
Test name
Test status
Simulation time 21841078244 ps
CPU time 227.11 seconds
Started Oct 12 06:19:53 AM UTC 24
Finished Oct 12 06:23:43 AM UTC 24
Peak memory 1223684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4097836511 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_watermark.4097836511
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/36.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/36.i2c_host_may_nack.2198874018
Short name T1278
Test name
Test status
Simulation time 351112638 ps
CPU time 3.64 seconds
Started Oct 12 06:20:07 AM UTC 24
Finished Oct 12 06:20:12 AM UTC 24
Peak memory 215440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2198874018 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.i2c_host_may_nack.2198874018
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/36.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/36.i2c_host_mode_toggle.524169039
Short name T1272
Test name
Test status
Simulation time 128464511 ps
CPU time 1.76 seconds
Started Oct 12 06:20:07 AM UTC 24
Finished Oct 12 06:20:10 AM UTC 24
Peak memory 225572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=524169039 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 36.i2c_host_mode_toggle.524169039
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/36.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/36.i2c_host_override.490817783
Short name T1256
Test name
Test status
Simulation time 26904156 ps
CPU time 1.04 seconds
Started Oct 12 06:19:52 AM UTC 24
Finished Oct 12 06:19:54 AM UTC 24
Peak memory 213212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=490817783 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 36.i2c_host_override.490817783
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/36.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/36.i2c_host_perf.4269146696
Short name T1506
Test name
Test status
Simulation time 4905845463 ps
CPU time 259.77 seconds
Started Oct 12 06:19:55 AM UTC 24
Finished Oct 12 06:24:18 AM UTC 24
Peak memory 740544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4269146696 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 36.i2c_host_perf.4269146696
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/36.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/36.i2c_host_perf_precise.1838967545
Short name T1262
Test name
Test status
Simulation time 229666523 ps
CPU time 2.22 seconds
Started Oct 12 06:19:55 AM UTC 24
Finished Oct 12 06:19:58 AM UTC 24
Peak memory 215516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1838967545 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_perf_precise.1838967545
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/36.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/36.i2c_host_smoke.4020075458
Short name T1289
Test name
Test status
Simulation time 1483476293 ps
CPU time 25.1 seconds
Started Oct 12 06:19:52 AM UTC 24
Finished Oct 12 06:20:18 AM UTC 24
Peak memory 342940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4020075458 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 36.i2c_host_smoke.4020075458
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/36.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/36.i2c_host_stretch_timeout.537513230
Short name T1271
Test name
Test status
Simulation time 3675337468 ps
CPU time 11.5 seconds
Started Oct 12 06:19:57 AM UTC 24
Finished Oct 12 06:20:09 AM UTC 24
Peak memory 227712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=537513230 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_stretch_timeout.537513230
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/36.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/36.i2c_target_bad_addr.1301164524
Short name T1284
Test name
Test status
Simulation time 1949552122 ps
CPU time 8.1 seconds
Started Oct 12 06:20:06 AM UTC 24
Finished Oct 12 06:20:15 AM UTC 24
Peak memory 225704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=1301164524 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_bad_ad
dr.1301164524
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/36.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/36.i2c_target_fifo_reset_acq.4155031406
Short name T292
Test name
Test status
Simulation time 1752630196 ps
CPU time 2.62 seconds
Started Oct 12 06:20:02 AM UTC 24
Finished Oct 12 06:20:06 AM UTC 24
Peak memory 225640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4155031
406 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_fifo_reset_acq.4155031406
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/36.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/36.i2c_target_fifo_reset_tx.437325380
Short name T1268
Test name
Test status
Simulation time 377840225 ps
CPU time 1.84 seconds
Started Oct 12 06:20:03 AM UTC 24
Finished Oct 12 06:20:06 AM UTC 24
Peak memory 215636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4373253
80 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_fifo_reset_tx.437325380
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/36.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/36.i2c_target_fifo_watermarks_acq.3485632663
Short name T1274
Test name
Test status
Simulation time 957877795 ps
CPU time 2.47 seconds
Started Oct 12 06:20:07 AM UTC 24
Finished Oct 12 06:20:11 AM UTC 24
Peak memory 215836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3485632
663 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_fifo_watermar
ks_acq.3485632663
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/36.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/36.i2c_target_fifo_watermarks_tx.1190863046
Short name T1277
Test name
Test status
Simulation time 334303831 ps
CPU time 2.02 seconds
Started Oct 12 06:20:08 AM UTC 24
Finished Oct 12 06:20:11 AM UTC 24
Peak memory 215248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1190863
046 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_fifo_watermark
s_tx.1190863046
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/36.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/36.i2c_target_intr_smoke.1219891929
Short name T1269
Test name
Test status
Simulation time 1039017342 ps
CPU time 6.17 seconds
Started Oct 12 06:20:01 AM UTC 24
Finished Oct 12 06:20:08 AM UTC 24
Peak memory 225636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=121989
1929 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_intr_smoke.1219891929
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/36.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/36.i2c_target_intr_stress_wr.399172384
Short name T1291
Test name
Test status
Simulation time 13042030140 ps
CPU time 19.56 seconds
Started Oct 12 06:20:01 AM UTC 24
Finished Oct 12 06:20:22 AM UTC 24
Peak memory 431116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=399172384 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_intr_stress
_wr.399172384
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/36.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/36.i2c_target_nack_acqfull.198785887
Short name T1282
Test name
Test status
Simulation time 555354342 ps
CPU time 3.41 seconds
Started Oct 12 06:20:09 AM UTC 24
Finished Oct 12 06:20:14 AM UTC 24
Peak memory 226020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1987858
87 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_nack_acqfull.198785887
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/36.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/36.i2c_target_nack_acqfull_addr.4235856232
Short name T1286
Test name
Test status
Simulation time 2303598222 ps
CPU time 4.47 seconds
Started Oct 12 06:20:11 AM UTC 24
Finished Oct 12 06:20:16 AM UTC 24
Peak memory 215680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4235856
232 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_nack_acqfull_ad
dr.4235856232
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/36.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/36.i2c_target_nack_txstretch.2649379118
Short name T1283
Test name
Test status
Simulation time 534475305 ps
CPU time 2.52 seconds
Started Oct 12 06:20:11 AM UTC 24
Finished Oct 12 06:20:14 AM UTC 24
Peak memory 232332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2649379
118 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_nack_txstretch.2649379118
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/36.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/36.i2c_target_perf.2401064814
Short name T1276
Test name
Test status
Simulation time 2868759413 ps
CPU time 5.71 seconds
Started Oct 12 06:20:04 AM UTC 24
Finished Oct 12 06:20:11 AM UTC 24
Peak memory 226024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2401064
814 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_perf.2401064814
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/36.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/36.i2c_target_smbus_maxlen.2559388032
Short name T1281
Test name
Test status
Simulation time 438502000 ps
CPU time 2.77 seconds
Started Oct 12 06:20:09 AM UTC 24
Finished Oct 12 06:20:13 AM UTC 24
Peak memory 215504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2559388
032 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_smbus_maxlen.2559388032
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/36.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/36.i2c_target_smoke.2511764038
Short name T1280
Test name
Test status
Simulation time 908112322 ps
CPU time 13.81 seconds
Started Oct 12 06:19:58 AM UTC 24
Finished Oct 12 06:20:13 AM UTC 24
Peak memory 225664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2511764038 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_smoke.2511764038
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/36.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/36.i2c_target_stress_all.3326042263
Short name T1740
Test name
Test status
Simulation time 75995865508 ps
CPU time 1410.41 seconds
Started Oct 12 06:20:06 AM UTC 24
Finished Oct 12 06:43:48 AM UTC 24
Peak memory 10919104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=332604
2263 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_stress_all.3326042263
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/36.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/36.i2c_target_stress_rd.2867902360
Short name T1320
Test name
Test status
Simulation time 3682326816 ps
CPU time 39.8 seconds
Started Oct 12 06:19:59 AM UTC 24
Finished Oct 12 06:20:40 AM UTC 24
Peak memory 225884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2867902360 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_stress_rd.2867902360
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/36.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/36.i2c_target_stress_wr.1771719424
Short name T1267
Test name
Test status
Simulation time 15522462554 ps
CPU time 6.82 seconds
Started Oct 12 06:19:58 AM UTC 24
Finished Oct 12 06:20:06 AM UTC 24
Peak memory 215456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1771719424 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_stress_wr.1771719424
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/36.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/36.i2c_target_stretch.405040700
Short name T1204
Test name
Test status
Simulation time 293384616 ps
CPU time 2.4 seconds
Started Oct 12 06:20:01 AM UTC 24
Finished Oct 12 06:20:04 AM UTC 24
Peak memory 215584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=405040700 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_stretch.405040700
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/36.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/36.i2c_target_timeout.1918168040
Short name T1273
Test name
Test status
Simulation time 2236035651 ps
CPU time 7.81 seconds
Started Oct 12 06:20:01 AM UTC 24
Finished Oct 12 06:20:10 AM UTC 24
Peak memory 232448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1918168
040 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_timeout.1918168040
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/36.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/36.i2c_target_tx_stretch_ctrl.1383539238
Short name T1275
Test name
Test status
Simulation time 64962614 ps
CPU time 1.92 seconds
Started Oct 12 06:20:08 AM UTC 24
Finished Oct 12 06:20:11 AM UTC 24
Peak memory 215532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1383539
238 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_target_tx_stretch_ctrl.1383539238
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/36.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/37.i2c_alert_test.389383801
Short name T1311
Test name
Test status
Simulation time 78902445 ps
CPU time 0.92 seconds
Started Oct 12 06:20:35 AM UTC 24
Finished Oct 12 06:20:37 AM UTC 24
Peak memory 215628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=389383801 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_alert_test.389383801
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/37.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/37.i2c_host_error_intr.2424969632
Short name T1288
Test name
Test status
Simulation time 143363382 ps
CPU time 2.25 seconds
Started Oct 12 06:20:15 AM UTC 24
Finished Oct 12 06:20:18 AM UTC 24
Peak memory 232476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2424969632 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 37.i2c_host_error_intr.2424969632
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/37.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/37.i2c_host_fifo_fmt_empty.2565833169
Short name T1294
Test name
Test status
Simulation time 1379605326 ps
CPU time 8.12 seconds
Started Oct 12 06:20:13 AM UTC 24
Finished Oct 12 06:20:22 AM UTC 24
Peak memory 271500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2565833169 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_fmt_empty.2565833169
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/37.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/37.i2c_host_fifo_full.831256595
Short name T1480
Test name
Test status
Simulation time 8011065485 ps
CPU time 207.8 seconds
Started Oct 12 06:20:15 AM UTC 24
Finished Oct 12 06:23:45 AM UTC 24
Peak memory 883904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=831256595 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_full.831256595
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/37.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/37.i2c_host_fifo_overflow.3161538793
Short name T1343
Test name
Test status
Simulation time 4269454940 ps
CPU time 56.31 seconds
Started Oct 12 06:20:12 AM UTC 24
Finished Oct 12 06:21:10 AM UTC 24
Peak memory 746448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3161538793 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_overflow.3161538793
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/37.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/37.i2c_host_fifo_reset_fmt.1181541693
Short name T1285
Test name
Test status
Simulation time 93441214 ps
CPU time 1.17 seconds
Started Oct 12 06:20:13 AM UTC 24
Finished Oct 12 06:20:15 AM UTC 24
Peak memory 213332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1181541693 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_fmt.1181541693
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/37.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/37.i2c_host_fifo_reset_rx.4137983263
Short name T1293
Test name
Test status
Simulation time 144208020 ps
CPU time 7.77 seconds
Started Oct 12 06:20:13 AM UTC 24
Finished Oct 12 06:20:22 AM UTC 24
Peak memory 240836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4137983263 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_rx.4137983263
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/37.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/37.i2c_host_fifo_watermark.3432750825
Short name T1412
Test name
Test status
Simulation time 4613534994 ps
CPU time 140.29 seconds
Started Oct 12 06:20:12 AM UTC 24
Finished Oct 12 06:22:35 AM UTC 24
Peak memory 1393536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3432750825 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_watermark.3432750825
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/37.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/37.i2c_host_may_nack.1526527936
Short name T1324
Test name
Test status
Simulation time 578517548 ps
CPU time 13.99 seconds
Started Oct 12 06:20:31 AM UTC 24
Finished Oct 12 06:20:46 AM UTC 24
Peak memory 215384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1526527936 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.i2c_host_may_nack.1526527936
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/37.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/37.i2c_host_mode_toggle.3262802275
Short name T1306
Test name
Test status
Simulation time 147104673 ps
CPU time 2.5 seconds
Started Oct 12 06:20:30 AM UTC 24
Finished Oct 12 06:20:34 AM UTC 24
Peak memory 229740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3262802275 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_mode_toggle.3262802275
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/37.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/37.i2c_host_override.2940450745
Short name T263
Test name
Test status
Simulation time 49340921 ps
CPU time 1.02 seconds
Started Oct 12 06:20:12 AM UTC 24
Finished Oct 12 06:20:14 AM UTC 24
Peak memory 213212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2940450745 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.i2c_host_override.2940450745
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/37.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/37.i2c_host_perf.1088898803
Short name T1738
Test name
Test status
Simulation time 50150982110 ps
CPU time 1285.32 seconds
Started Oct 12 06:20:15 AM UTC 24
Finished Oct 12 06:41:53 AM UTC 24
Peak memory 3458248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1088898803 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 37.i2c_host_perf.1088898803
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/37.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/37.i2c_host_perf_precise.3603736155
Short name T1319
Test name
Test status
Simulation time 427245264 ps
CPU time 24.29 seconds
Started Oct 12 06:20:15 AM UTC 24
Finished Oct 12 06:20:40 AM UTC 24
Peak memory 289996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3603736155 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_perf_precise.3603736155
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/37.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/37.i2c_host_smoke.3736231824
Short name T1329
Test name
Test status
Simulation time 1821793386 ps
CPU time 40.15 seconds
Started Oct 12 06:20:12 AM UTC 24
Finished Oct 12 06:20:53 AM UTC 24
Peak memory 478208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3736231824 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 37.i2c_host_smoke.3736231824
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/37.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/37.i2c_host_stretch_timeout.1591293667
Short name T1310
Test name
Test status
Simulation time 950234887 ps
CPU time 19.88 seconds
Started Oct 12 06:20:15 AM UTC 24
Finished Oct 12 06:20:36 AM UTC 24
Peak memory 232648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1591293667 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_stretch_timeout.1591293667
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/37.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/37.i2c_target_bad_addr.1722265844
Short name T1315
Test name
Test status
Simulation time 971605929 ps
CPU time 8.15 seconds
Started Oct 12 06:20:29 AM UTC 24
Finished Oct 12 06:20:39 AM UTC 24
Peak memory 232384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=1722265844 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_bad_ad
dr.1722265844
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/37.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/37.i2c_target_fifo_reset_acq.3049020342
Short name T88
Test name
Test status
Simulation time 174334149 ps
CPU time 1.93 seconds
Started Oct 12 06:20:24 AM UTC 24
Finished Oct 12 06:20:27 AM UTC 24
Peak memory 215576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3049020
342 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_fifo_reset_acq.3049020342
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/37.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/37.i2c_target_fifo_reset_tx.236033970
Short name T1299
Test name
Test status
Simulation time 612666487 ps
CPU time 2.34 seconds
Started Oct 12 06:20:26 AM UTC 24
Finished Oct 12 06:20:29 AM UTC 24
Peak memory 215536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2360339
70 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_fifo_reset_tx.236033970
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/37.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/37.i2c_target_fifo_watermarks_acq.2708774450
Short name T1309
Test name
Test status
Simulation time 293366995 ps
CPU time 3.66 seconds
Started Oct 12 06:20:31 AM UTC 24
Finished Oct 12 06:20:35 AM UTC 24
Peak memory 215164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2708774
450 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_fifo_watermar
ks_acq.2708774450
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/37.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/37.i2c_target_fifo_watermarks_tx.2413448119
Short name T1307
Test name
Test status
Simulation time 301359477 ps
CPU time 1.45 seconds
Started Oct 12 06:20:32 AM UTC 24
Finished Oct 12 06:20:34 AM UTC 24
Peak memory 212940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2413448
119 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_fifo_watermark
s_tx.2413448119
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/37.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/37.i2c_target_hrst.2791675360
Short name T1304
Test name
Test status
Simulation time 350699881 ps
CPU time 2.3 seconds
Started Oct 12 06:20:29 AM UTC 24
Finished Oct 12 06:20:33 AM UTC 24
Peak memory 225772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2791675
360 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_hrst.2791675360
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/37.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/37.i2c_target_intr_smoke.1900406148
Short name T1301
Test name
Test status
Simulation time 2952983054 ps
CPU time 9.81 seconds
Started Oct 12 06:20:19 AM UTC 24
Finished Oct 12 06:20:30 AM UTC 24
Peak memory 242904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=190040
6148 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_intr_smoke.1900406148
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/37.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/37.i2c_target_intr_stress_wr.110583257
Short name T1303
Test name
Test status
Simulation time 10019797955 ps
CPU time 10.2 seconds
Started Oct 12 06:20:21 AM UTC 24
Finished Oct 12 06:20:32 AM UTC 24
Peak memory 215908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=110583257 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_intr_stress
_wr.110583257
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/37.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/37.i2c_target_nack_acqfull.3349664412
Short name T1317
Test name
Test status
Simulation time 511742710 ps
CPU time 4.02 seconds
Started Oct 12 06:20:34 AM UTC 24
Finished Oct 12 06:20:39 AM UTC 24
Peak memory 226024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3349664
412 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_nack_acqfull.3349664412
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/37.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/37.i2c_target_nack_acqfull_addr.2381896392
Short name T1318
Test name
Test status
Simulation time 675913793 ps
CPU time 4.81 seconds
Started Oct 12 06:20:34 AM UTC 24
Finished Oct 12 06:20:40 AM UTC 24
Peak memory 215348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2381896
392 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_nack_acqfull_ad
dr.2381896392
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/37.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/37.i2c_target_nack_txstretch.4091937463
Short name T1313
Test name
Test status
Simulation time 253091954 ps
CPU time 2.12 seconds
Started Oct 12 06:20:35 AM UTC 24
Finished Oct 12 06:20:38 AM UTC 24
Peak memory 232392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4091937
463 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_nack_txstretch.4091937463
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/37.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/37.i2c_target_perf.3959901819
Short name T1308
Test name
Test status
Simulation time 3133137343 ps
CPU time 6.45 seconds
Started Oct 12 06:20:27 AM UTC 24
Finished Oct 12 06:20:35 AM UTC 24
Peak memory 232168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3959901
819 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_perf.3959901819
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/37.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/37.i2c_target_smbus_maxlen.3853371117
Short name T1312
Test name
Test status
Simulation time 958072134 ps
CPU time 3.61 seconds
Started Oct 12 06:20:33 AM UTC 24
Finished Oct 12 06:20:38 AM UTC 24
Peak memory 215244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3853371
117 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_smbus_maxlen.3853371117
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/37.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/37.i2c_target_smoke.2575854704
Short name T1297
Test name
Test status
Simulation time 1601895213 ps
CPU time 11.68 seconds
Started Oct 12 06:20:16 AM UTC 24
Finished Oct 12 06:20:29 AM UTC 24
Peak memory 226024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2575854704 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_smoke.2575854704
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/37.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/37.i2c_target_stress_all.706213613
Short name T1431
Test name
Test status
Simulation time 34778986100 ps
CPU time 147.52 seconds
Started Oct 12 06:20:28 AM UTC 24
Finished Oct 12 06:22:58 AM UTC 24
Peak memory 1328140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=706213
613 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_stress_all.706213613
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/37.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/37.i2c_target_stress_rd.3166612873
Short name T1296
Test name
Test status
Simulation time 338574659 ps
CPU time 7.97 seconds
Started Oct 12 06:20:19 AM UTC 24
Finished Oct 12 06:20:28 AM UTC 24
Peak memory 215516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3166612873 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_stress_rd.3166612873
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/37.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/37.i2c_target_stress_wr.879237492
Short name T1447
Test name
Test status
Simulation time 45839460200 ps
CPU time 169.42 seconds
Started Oct 12 06:20:17 AM UTC 24
Finished Oct 12 06:23:09 AM UTC 24
Peak memory 2628476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=879237492 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_stress_wr.879237492
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/37.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/37.i2c_target_stretch.3610095844
Short name T1302
Test name
Test status
Simulation time 2750223069 ps
CPU time 10.52 seconds
Started Oct 12 06:20:19 AM UTC 24
Finished Oct 12 06:20:31 AM UTC 24
Peak memory 351224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3610095844 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_stretch.3610095844
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/37.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/37.i2c_target_timeout.574147386
Short name T1305
Test name
Test status
Simulation time 4482290077 ps
CPU time 9.49 seconds
Started Oct 12 06:20:23 AM UTC 24
Finished Oct 12 06:20:33 AM UTC 24
Peak memory 225892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5741473
86 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_timeout.574147386
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/37.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/37.i2c_target_tx_stretch_ctrl.707237127
Short name T1316
Test name
Test status
Simulation time 245277254 ps
CPU time 5.83 seconds
Started Oct 12 06:20:32 AM UTC 24
Finished Oct 12 06:20:39 AM UTC 24
Peak memory 215092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7072371
27 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_target_tx_stretch_ctrl.707237127
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/37.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/38.i2c_alert_test.3324102296
Short name T1349
Test name
Test status
Simulation time 18389156 ps
CPU time 0.97 seconds
Started Oct 12 06:21:10 AM UTC 24
Finished Oct 12 06:21:12 AM UTC 24
Peak memory 215628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3324102296 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_alert_test.3324102296
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/38.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/38.i2c_host_error_intr.2945798649
Short name T1326
Test name
Test status
Simulation time 451186403 ps
CPU time 6.09 seconds
Started Oct 12 06:20:41 AM UTC 24
Finished Oct 12 06:20:49 AM UTC 24
Peak memory 261096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2945798649 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 38.i2c_host_error_intr.2945798649
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/38.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/38.i2c_host_fifo_fmt_empty.3405620466
Short name T1328
Test name
Test status
Simulation time 506982584 ps
CPU time 13.52 seconds
Started Oct 12 06:20:39 AM UTC 24
Finished Oct 12 06:20:53 AM UTC 24
Peak memory 296008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3405620466 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_fmt_empty.3405620466
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/38.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/38.i2c_host_fifo_full.4074491574
Short name T1375
Test name
Test status
Simulation time 10375442356 ps
CPU time 75.19 seconds
Started Oct 12 06:20:40 AM UTC 24
Finished Oct 12 06:21:57 AM UTC 24
Peak memory 633796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4074491574 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_full.4074491574
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/38.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/38.i2c_host_fifo_overflow.1772559017
Short name T1366
Test name
Test status
Simulation time 10423615430 ps
CPU time 64.65 seconds
Started Oct 12 06:20:38 AM UTC 24
Finished Oct 12 06:21:44 AM UTC 24
Peak memory 746508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1772559017 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_overflow.1772559017
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/38.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/38.i2c_host_fifo_reset_fmt.626956739
Short name T1321
Test name
Test status
Simulation time 127339815 ps
CPU time 1.59 seconds
Started Oct 12 06:20:39 AM UTC 24
Finished Oct 12 06:20:41 AM UTC 24
Peak memory 213332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=626956739 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_fmt.626956739
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/38.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/38.i2c_host_fifo_reset_rx.1259868146
Short name T1323
Test name
Test status
Simulation time 144659951 ps
CPU time 4.11 seconds
Started Oct 12 06:20:40 AM UTC 24
Finished Oct 12 06:20:45 AM UTC 24
Peak memory 215452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1259868146 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_rx.1259868146
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/38.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/38.i2c_host_fifo_watermark.765474578
Short name T1426
Test name
Test status
Simulation time 3480633941 ps
CPU time 194.93 seconds
Started Oct 12 06:20:37 AM UTC 24
Finished Oct 12 06:23:54 AM UTC 24
Peak memory 1045712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=765474578 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_watermark.765474578
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/38.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/38.i2c_host_may_nack.2164350099
Short name T1356
Test name
Test status
Simulation time 4035608749 ps
CPU time 12.34 seconds
Started Oct 12 06:21:02 AM UTC 24
Finished Oct 12 06:21:16 AM UTC 24
Peak memory 215520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2164350099 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.i2c_host_may_nack.2164350099
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/38.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/38.i2c_host_override.60949931
Short name T1314
Test name
Test status
Simulation time 102407914 ps
CPU time 0.96 seconds
Started Oct 12 06:20:36 AM UTC 24
Finished Oct 12 06:20:38 AM UTC 24
Peak memory 213328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=60949931 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ho
st_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 38.i2c_host_override.60949931
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/38.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/38.i2c_host_perf.808234291
Short name T1414
Test name
Test status
Simulation time 8099367802 ps
CPU time 113.71 seconds
Started Oct 12 06:20:40 AM UTC 24
Finished Oct 12 06:22:36 AM UTC 24
Peak memory 1014724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=808234291 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 38.i2c_host_perf.808234291
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/38.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/38.i2c_host_perf_precise.4227827194
Short name T1322
Test name
Test status
Simulation time 74037774 ps
CPU time 2.21 seconds
Started Oct 12 06:20:40 AM UTC 24
Finished Oct 12 06:20:43 AM UTC 24
Peak memory 225584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4227827194 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_perf_precise.4227827194
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/38.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/38.i2c_host_smoke.2454046004
Short name T1370
Test name
Test status
Simulation time 6412296500 ps
CPU time 73.27 seconds
Started Oct 12 06:20:35 AM UTC 24
Finished Oct 12 06:21:50 AM UTC 24
Peak memory 447548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2454046004 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 38.i2c_host_smoke.2454046004
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/38.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/38.i2c_host_stress_all.3543107282
Short name T283
Test name
Test status
Simulation time 103718848732 ps
CPU time 988.04 seconds
Started Oct 12 06:20:42 AM UTC 24
Finished Oct 12 06:37:20 AM UTC 24
Peak memory 3073404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3543107282 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 38.i2c_host_stress_all.3543107282
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/38.i2c_host_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/38.i2c_host_stretch_timeout.3516884263
Short name T1330
Test name
Test status
Simulation time 2172301709 ps
CPU time 12.61 seconds
Started Oct 12 06:20:41 AM UTC 24
Finished Oct 12 06:20:55 AM UTC 24
Peak memory 225824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3516884263 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_stretch_timeout.3516884263
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/38.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/38.i2c_target_bad_addr.4287388374
Short name T1338
Test name
Test status
Simulation time 4729017052 ps
CPU time 6.36 seconds
Started Oct 12 06:20:59 AM UTC 24
Finished Oct 12 06:21:06 AM UTC 24
Peak memory 226028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=4287388374 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_bad_ad
dr.4287388374
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/38.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/38.i2c_target_fifo_reset_acq.2255806492
Short name T1333
Test name
Test status
Simulation time 279418913 ps
CPU time 3.05 seconds
Started Oct 12 06:20:54 AM UTC 24
Finished Oct 12 06:20:59 AM UTC 24
Peak memory 215448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2255806
492 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_fifo_reset_acq.2255806492
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/38.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/38.i2c_target_fifo_reset_tx.1392237630
Short name T1332
Test name
Test status
Simulation time 644150316 ps
CPU time 2.23 seconds
Started Oct 12 06:20:55 AM UTC 24
Finished Oct 12 06:20:58 AM UTC 24
Peak memory 217516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1392237
630 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_fifo_reset_tx.1392237630
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/38.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/38.i2c_target_fifo_watermarks_acq.1820716947
Short name T1339
Test name
Test status
Simulation time 3023883561 ps
CPU time 4.32 seconds
Started Oct 12 06:21:03 AM UTC 24
Finished Oct 12 06:21:09 AM UTC 24
Peak memory 225756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1820716
947 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_fifo_watermar
ks_acq.1820716947
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/38.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/38.i2c_target_fifo_watermarks_tx.3576108041
Short name T1292
Test name
Test status
Simulation time 160764074 ps
CPU time 2.14 seconds
Started Oct 12 06:21:03 AM UTC 24
Finished Oct 12 06:21:07 AM UTC 24
Peak memory 215628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3576108
041 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_fifo_watermark
s_tx.3576108041
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/38.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/38.i2c_target_hrst.2663848057
Short name T1336
Test name
Test status
Simulation time 382749310 ps
CPU time 4.43 seconds
Started Oct 12 06:20:59 AM UTC 24
Finished Oct 12 06:21:04 AM UTC 24
Peak memory 215840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2663848
057 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_hrst.2663848057
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/38.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/38.i2c_target_intr_smoke.969849539
Short name T1331
Test name
Test status
Simulation time 834170778 ps
CPU time 7.37 seconds
Started Oct 12 06:20:48 AM UTC 24
Finished Oct 12 06:20:57 AM UTC 24
Peak memory 225704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=969849
539 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_intr_smoke.969849539
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/38.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/38.i2c_target_intr_stress_wr.327480233
Short name T1341
Test name
Test status
Simulation time 13951176870 ps
CPU time 19.67 seconds
Started Oct 12 06:20:49 AM UTC 24
Finished Oct 12 06:21:10 AM UTC 24
Peak memory 506936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=327480233 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_intr_stress
_wr.327480233
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/38.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/38.i2c_target_nack_acqfull.1145072709
Short name T1346
Test name
Test status
Simulation time 563280926 ps
CPU time 4.13 seconds
Started Oct 12 06:21:07 AM UTC 24
Finished Oct 12 06:21:12 AM UTC 24
Peak memory 225968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1145072
709 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_nack_acqfull.1145072709
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/38.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/38.i2c_target_nack_acqfull_addr.494857579
Short name T1353
Test name
Test status
Simulation time 1068403572 ps
CPU time 5.17 seconds
Started Oct 12 06:21:08 AM UTC 24
Finished Oct 12 06:21:14 AM UTC 24
Peak memory 215808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4948575
79 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_nack_acqfull_addr.494857579
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/38.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/38.i2c_target_nack_txstretch.2063193176
Short name T1350
Test name
Test status
Simulation time 1806786477 ps
CPU time 1.65 seconds
Started Oct 12 06:21:10 AM UTC 24
Finished Oct 12 06:21:13 AM UTC 24
Peak memory 231192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2063193
176 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_nack_txstretch.2063193176
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/38.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/38.i2c_target_perf.3603173260
Short name T1334
Test name
Test status
Simulation time 2728453198 ps
CPU time 4.15 seconds
Started Oct 12 06:20:56 AM UTC 24
Finished Oct 12 06:21:01 AM UTC 24
Peak memory 226080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3603173
260 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_perf.3603173260
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/38.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/38.i2c_target_smbus_maxlen.4235506657
Short name T1342
Test name
Test status
Simulation time 2389920709 ps
CPU time 3.36 seconds
Started Oct 12 06:21:05 AM UTC 24
Finished Oct 12 06:21:10 AM UTC 24
Peak memory 215568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4235506
657 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_smbus_maxlen.4235506657
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/38.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/38.i2c_target_smoke.3754536831
Short name T1348
Test name
Test status
Simulation time 3732454120 ps
CPU time 28.35 seconds
Started Oct 12 06:20:43 AM UTC 24
Finished Oct 12 06:21:12 AM UTC 24
Peak memory 227888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3754536831 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_smoke.3754536831
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/38.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/38.i2c_target_stress_all.2340674379
Short name T1392
Test name
Test status
Simulation time 34139242242 ps
CPU time 68.58 seconds
Started Oct 12 06:20:58 AM UTC 24
Finished Oct 12 06:22:08 AM UTC 24
Peak memory 248780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=234067
4379 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_stress_all.2340674379
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/38.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/38.i2c_target_stress_rd.2450703925
Short name T1327
Test name
Test status
Simulation time 363731136 ps
CPU time 5.5 seconds
Started Oct 12 06:20:46 AM UTC 24
Finished Oct 12 06:20:52 AM UTC 24
Peak memory 215896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2450703925 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_stress_rd.2450703925
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/38.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/38.i2c_target_stress_wr.833761059
Short name T1340
Test name
Test status
Simulation time 32817616524 ps
CPU time 24.36 seconds
Started Oct 12 06:20:44 AM UTC 24
Finished Oct 12 06:21:09 AM UTC 24
Peak memory 420808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=833761059 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_stress_wr.833761059
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/38.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/38.i2c_target_timeout.1538241236
Short name T1337
Test name
Test status
Simulation time 4876766038 ps
CPU time 11.65 seconds
Started Oct 12 06:20:52 AM UTC 24
Finished Oct 12 06:21:05 AM UTC 24
Peak memory 242628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1538241
236 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_timeout.1538241236
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/38.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/38.i2c_target_tx_stretch_ctrl.484730602
Short name T1347
Test name
Test status
Simulation time 227458466 ps
CPU time 5.42 seconds
Started Oct 12 06:21:05 AM UTC 24
Finished Oct 12 06:21:12 AM UTC 24
Peak memory 215400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4847306
02 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_target_tx_stretch_ctrl.484730602
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/38.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/39.i2c_alert_test.2277972442
Short name T1380
Test name
Test status
Simulation time 35816344 ps
CPU time 0.99 seconds
Started Oct 12 06:21:57 AM UTC 24
Finished Oct 12 06:21:59 AM UTC 24
Peak memory 215628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2277972442 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_alert_test.2277972442
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/39.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/39.i2c_host_error_intr.3469982871
Short name T1358
Test name
Test status
Simulation time 944723707 ps
CPU time 3.65 seconds
Started Oct 12 06:21:15 AM UTC 24
Finished Oct 12 06:21:20 AM UTC 24
Peak memory 225720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3469982871 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 39.i2c_host_error_intr.3469982871
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/39.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/39.i2c_host_fifo_fmt_empty.636835969
Short name T1361
Test name
Test status
Simulation time 460224084 ps
CPU time 12.2 seconds
Started Oct 12 06:21:14 AM UTC 24
Finished Oct 12 06:21:27 AM UTC 24
Peak memory 277692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=636835969 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_fmt_empty.636835969
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/39.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/39.i2c_host_fifo_full.2911795899
Short name T1402
Test name
Test status
Simulation time 10426673616 ps
CPU time 67.98 seconds
Started Oct 12 06:21:14 AM UTC 24
Finished Oct 12 06:22:24 AM UTC 24
Peak memory 265224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2911795899 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_full.2911795899
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/39.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/39.i2c_host_fifo_overflow.1020724044
Short name T1394
Test name
Test status
Simulation time 1628397375 ps
CPU time 55.38 seconds
Started Oct 12 06:21:12 AM UTC 24
Finished Oct 12 06:22:09 AM UTC 24
Peak memory 621180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1020724044 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_overflow.1020724044
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/39.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/39.i2c_host_fifo_reset_fmt.3359328013
Short name T1354
Test name
Test status
Simulation time 150139445 ps
CPU time 2.07 seconds
Started Oct 12 06:21:12 AM UTC 24
Finished Oct 12 06:21:15 AM UTC 24
Peak memory 215140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3359328013 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_fmt.3359328013
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/39.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/39.i2c_host_fifo_reset_rx.2346998079
Short name T1359
Test name
Test status
Simulation time 130125287 ps
CPU time 5.22 seconds
Started Oct 12 06:21:14 AM UTC 24
Finished Oct 12 06:21:20 AM UTC 24
Peak memory 215528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2346998079 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_rx.2346998079
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/39.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/39.i2c_host_fifo_watermark.3185848921
Short name T1419
Test name
Test status
Simulation time 82300835066 ps
CPU time 91.89 seconds
Started Oct 12 06:21:11 AM UTC 24
Finished Oct 12 06:22:45 AM UTC 24
Peak memory 1168336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3185848921 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_watermark.3185848921
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/39.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/39.i2c_host_may_nack.24235266
Short name T1378
Test name
Test status
Simulation time 464479746 ps
CPU time 10.04 seconds
Started Oct 12 06:21:47 AM UTC 24
Finished Oct 12 06:21:58 AM UTC 24
Peak memory 215452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=24235266 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ho
st_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 39.i2c_host_may_nack.24235266
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/39.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/39.i2c_host_override.2573606507
Short name T1352
Test name
Test status
Simulation time 16816287 ps
CPU time 0.96 seconds
Started Oct 12 06:21:11 AM UTC 24
Finished Oct 12 06:21:13 AM UTC 24
Peak memory 213212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2573606507 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.i2c_host_override.2573606507
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/39.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/39.i2c_host_perf.1447847177
Short name T1401
Test name
Test status
Simulation time 26120777273 ps
CPU time 65.68 seconds
Started Oct 12 06:21:14 AM UTC 24
Finished Oct 12 06:22:21 AM UTC 24
Peak memory 258940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1447847177 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 39.i2c_host_perf.1447847177
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/39.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/39.i2c_host_perf_precise.797881637
Short name T1357
Test name
Test status
Simulation time 399725123 ps
CPU time 2.56 seconds
Started Oct 12 06:21:14 AM UTC 24
Finished Oct 12 06:21:18 AM UTC 24
Peak memory 215400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=797881637 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_perf_precise.797881637
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/39.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/39.i2c_host_smoke.87997696
Short name T1369
Test name
Test status
Simulation time 3379153894 ps
CPU time 35.54 seconds
Started Oct 12 06:21:11 AM UTC 24
Finished Oct 12 06:21:48 AM UTC 24
Peak memory 363520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=87997696 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ho
st_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 39.i2c_host_smoke.87997696
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/39.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/39.i2c_host_stress_all.4119429663
Short name T245
Test name
Test status
Simulation time 209910216596 ps
CPU time 329.29 seconds
Started Oct 12 06:21:15 AM UTC 24
Finished Oct 12 06:26:49 AM UTC 24
Peak memory 2643340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4119429663 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 39.i2c_host_stress_all.4119429663
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/39.i2c_host_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/39.i2c_host_stretch_timeout.1647721159
Short name T1381
Test name
Test status
Simulation time 4091935877 ps
CPU time 43.91 seconds
Started Oct 12 06:21:15 AM UTC 24
Finished Oct 12 06:22:01 AM UTC 24
Peak memory 225696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1647721159 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_stretch_timeout.1647721159
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/39.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/39.i2c_target_bad_addr.56832968
Short name T1372
Test name
Test status
Simulation time 926559059 ps
CPU time 7.33 seconds
Started Oct 12 06:21:44 AM UTC 24
Finished Oct 12 06:21:52 AM UTC 24
Peak memory 225900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=56832968 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_bad_addr.56832968
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/39.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/39.i2c_target_fifo_reset_acq.952634566
Short name T152
Test name
Test status
Simulation time 522468058 ps
CPU time 1.88 seconds
Started Oct 12 06:21:38 AM UTC 24
Finished Oct 12 06:21:41 AM UTC 24
Peak memory 213512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9526345
66 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_fifo_reset_acq.952634566
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/39.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/39.i2c_target_fifo_reset_tx.2112568685
Short name T1365
Test name
Test status
Simulation time 736123483 ps
CPU time 2.69 seconds
Started Oct 12 06:21:39 AM UTC 24
Finished Oct 12 06:21:43 AM UTC 24
Peak memory 217520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2112568
685 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_fifo_reset_tx.2112568685
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/39.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/39.i2c_target_fifo_watermarks_acq.2664110154
Short name T1373
Test name
Test status
Simulation time 826460571 ps
CPU time 3.83 seconds
Started Oct 12 06:21:49 AM UTC 24
Finished Oct 12 06:21:54 AM UTC 24
Peak memory 215388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2664110
154 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_fifo_watermar
ks_acq.2664110154
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/39.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/39.i2c_target_fifo_watermarks_tx.929211711
Short name T1371
Test name
Test status
Simulation time 113901299 ps
CPU time 1.6 seconds
Started Oct 12 06:21:49 AM UTC 24
Finished Oct 12 06:21:52 AM UTC 24
Peak memory 213512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9292117
11 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_fifo_watermarks
_tx.929211711
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/39.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/39.i2c_target_intr_smoke.2748750995
Short name T1362
Test name
Test status
Simulation time 3822730540 ps
CPU time 9.53 seconds
Started Oct 12 06:21:22 AM UTC 24
Finished Oct 12 06:21:32 AM UTC 24
Peak memory 225776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=274875
0995 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_intr_smoke.2748750995
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/39.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/39.i2c_target_intr_stress_wr.1788513184
Short name T1428
Test name
Test status
Simulation time 27554156806 ps
CPU time 86.55 seconds
Started Oct 12 06:21:28 AM UTC 24
Finished Oct 12 06:22:56 AM UTC 24
Peak memory 1619208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1788513184 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_intr_stres
s_wr.1788513184
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/39.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/39.i2c_target_nack_acqfull.1655728254
Short name T1379
Test name
Test status
Simulation time 570661289 ps
CPU time 4.75 seconds
Started Oct 12 06:21:52 AM UTC 24
Finished Oct 12 06:21:58 AM UTC 24
Peak memory 225640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1655728
254 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_nack_acqfull.1655728254
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/39.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/39.i2c_target_nack_acqfull_addr.289151427
Short name T1377
Test name
Test status
Simulation time 1688087410 ps
CPU time 4.42 seconds
Started Oct 12 06:21:52 AM UTC 24
Finished Oct 12 06:21:58 AM UTC 24
Peak memory 215412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2891514
27 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_nack_acqfull_addr.289151427
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/39.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/39.i2c_target_nack_txstretch.2110240738
Short name T1376
Test name
Test status
Simulation time 180089305 ps
CPU time 2.12 seconds
Started Oct 12 06:21:55 AM UTC 24
Finished Oct 12 06:21:58 AM UTC 24
Peak memory 232328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2110240
738 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_nack_txstretch.2110240738
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/39.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/39.i2c_target_perf.38123740
Short name T1367
Test name
Test status
Simulation time 706451149 ps
CPU time 6.45 seconds
Started Oct 12 06:21:40 AM UTC 24
Finished Oct 12 06:21:48 AM UTC 24
Peak memory 232328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3812374
0 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_perf.38123740
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/39.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/39.i2c_target_smbus_maxlen.631664012
Short name T1374
Test name
Test status
Simulation time 1870738114 ps
CPU time 3.82 seconds
Started Oct 12 06:21:51 AM UTC 24
Finished Oct 12 06:21:56 AM UTC 24
Peak memory 215500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6316640
12 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_smbus_maxlen.631664012
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/39.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/39.i2c_target_smoke.2225507630
Short name T1360
Test name
Test status
Simulation time 718093628 ps
CPU time 9.1 seconds
Started Oct 12 06:21:16 AM UTC 24
Finished Oct 12 06:21:26 AM UTC 24
Peak memory 226024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2225507630 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_smoke.2225507630
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/39.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/39.i2c_target_stress_all.1831831195
Short name T1726
Test name
Test status
Simulation time 26469506034 ps
CPU time 445.82 seconds
Started Oct 12 06:21:42 AM UTC 24
Finished Oct 12 06:29:14 AM UTC 24
Peak memory 5594028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=183183
1195 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_stress_all.1831831195
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/39.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/39.i2c_target_stress_rd.1732915604
Short name T1385
Test name
Test status
Simulation time 4587620828 ps
CPU time 41.53 seconds
Started Oct 12 06:21:18 AM UTC 24
Finished Oct 12 06:22:01 AM UTC 24
Peak memory 228192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1732915604 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_stress_rd.1732915604
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/39.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/39.i2c_target_stress_wr.3778610580
Short name T1393
Test name
Test status
Simulation time 21383948614 ps
CPU time 50.83 seconds
Started Oct 12 06:21:16 AM UTC 24
Finished Oct 12 06:22:08 AM UTC 24
Peak memory 449728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3778610580 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_stress_wr.3778610580
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/39.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/39.i2c_target_stretch.2737326097
Short name T1363
Test name
Test status
Simulation time 1797202974 ps
CPU time 16.41 seconds
Started Oct 12 06:21:20 AM UTC 24
Finished Oct 12 06:21:38 AM UTC 24
Peak memory 535756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2737326097 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_stretch.2737326097
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/39.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/39.i2c_target_timeout.510421173
Short name T1364
Test name
Test status
Simulation time 2512286079 ps
CPU time 9.86 seconds
Started Oct 12 06:21:28 AM UTC 24
Finished Oct 12 06:21:39 AM UTC 24
Peak memory 232656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5104211
73 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_timeout.510421173
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/39.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/39.i2c_target_tx_stretch_ctrl.2365035621
Short name T1383
Test name
Test status
Simulation time 515976036 ps
CPU time 10.82 seconds
Started Oct 12 06:21:49 AM UTC 24
Finished Oct 12 06:22:01 AM UTC 24
Peak memory 226088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2365035
621 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_target_tx_stretch_ctrl.2365035621
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/39.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/4.i2c_alert_test.2089965668
Short name T338
Test name
Test status
Simulation time 150954172 ps
CPU time 0.93 seconds
Started Oct 12 05:57:24 AM UTC 24
Finished Oct 12 05:57:26 AM UTC 24
Peak memory 213392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2089965668 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_alert_test.2089965668
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/4.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/4.i2c_host_error_intr.4154489278
Short name T26
Test name
Test status
Simulation time 90069493 ps
CPU time 2.16 seconds
Started Oct 12 05:56:38 AM UTC 24
Finished Oct 12 05:56:41 AM UTC 24
Peak memory 226040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4154489278 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 4.i2c_host_error_intr.4154489278
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/4.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/4.i2c_host_fifo_fmt_empty.1354099825
Short name T325
Test name
Test status
Simulation time 5364787546 ps
CPU time 11.31 seconds
Started Oct 12 05:56:34 AM UTC 24
Finished Oct 12 05:56:47 AM UTC 24
Peak memory 310152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1354099825 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_fmt_empty.1354099825
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/4.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/4.i2c_host_fifo_full.3698149407
Short name T351
Test name
Test status
Simulation time 4136961570 ps
CPU time 114.95 seconds
Started Oct 12 05:56:34 AM UTC 24
Finished Oct 12 05:58:32 AM UTC 24
Peak memory 310536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3698149407 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_full.3698149407
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/4.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/4.i2c_host_fifo_overflow.2463054272
Short name T373
Test name
Test status
Simulation time 2445973659 ps
CPU time 170.95 seconds
Started Oct 12 05:56:33 AM UTC 24
Finished Oct 12 05:59:27 AM UTC 24
Peak memory 675136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2463054272 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_overflow.2463054272
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/4.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/4.i2c_host_fifo_reset_fmt.255348628
Short name T240
Test name
Test status
Simulation time 291055170 ps
CPU time 1.79 seconds
Started Oct 12 05:56:34 AM UTC 24
Finished Oct 12 05:56:37 AM UTC 24
Peak memory 213264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=255348628 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_fmt.255348628
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/4.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/4.i2c_host_fifo_reset_rx.3992099322
Short name T173
Test name
Test status
Simulation time 653143245 ps
CPU time 7.75 seconds
Started Oct 12 05:56:34 AM UTC 24
Finished Oct 12 05:56:43 AM UTC 24
Peak memory 246732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3992099322 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_rx.3992099322
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/4.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/4.i2c_host_fifo_watermark.222832816
Short name T176
Test name
Test status
Simulation time 2535750452 ps
CPU time 156.51 seconds
Started Oct 12 05:56:31 AM UTC 24
Finished Oct 12 05:59:10 AM UTC 24
Peak memory 822332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=222832816 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_watermark.222832816
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/4.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/4.i2c_host_may_nack.3317655828
Short name T258
Test name
Test status
Simulation time 815115560 ps
CPU time 7.62 seconds
Started Oct 12 05:57:13 AM UTC 24
Finished Oct 12 05:57:22 AM UTC 24
Peak memory 215384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3317655828 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.i2c_host_may_nack.3317655828
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/4.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/4.i2c_host_override.2698522284
Short name T321
Test name
Test status
Simulation time 15726908 ps
CPU time 0.93 seconds
Started Oct 12 05:56:31 AM UTC 24
Finished Oct 12 05:56:33 AM UTC 24
Peak memory 213208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2698522284 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.i2c_host_override.2698522284
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/4.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/4.i2c_host_perf.699142359
Short name T33
Test name
Test status
Simulation time 12645801613 ps
CPU time 352.94 seconds
Started Oct 12 05:56:35 AM UTC 24
Finished Oct 12 06:02:33 AM UTC 24
Peak memory 1028988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=699142359 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 4.i2c_host_perf.699142359
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/4.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/4.i2c_host_perf_precise.4272857067
Short name T324
Test name
Test status
Simulation time 475629532 ps
CPU time 9.05 seconds
Started Oct 12 05:56:35 AM UTC 24
Finished Oct 12 05:56:46 AM UTC 24
Peak memory 215336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4272857067 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_perf_precise.4272857067
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/4.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/4.i2c_host_smoke.2633694031
Short name T30
Test name
Test status
Simulation time 1628550425 ps
CPU time 74.36 seconds
Started Oct 12 05:56:31 AM UTC 24
Finished Oct 12 05:57:47 AM UTC 24
Peak memory 355520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2633694031 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.i2c_host_smoke.2633694031
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/4.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/4.i2c_host_stretch_timeout.2486897299
Short name T333
Test name
Test status
Simulation time 3386019994 ps
CPU time 38 seconds
Started Oct 12 05:56:35 AM UTC 24
Finished Oct 12 05:57:15 AM UTC 24
Peak memory 226092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2486897299 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_stretch_timeout.2486897299
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/4.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/4.i2c_sec_cm.2232858526
Short name T192
Test name
Test status
Simulation time 720932934 ps
CPU time 1.35 seconds
Started Oct 12 05:57:23 AM UTC 24
Finished Oct 12 05:57:25 AM UTC 24
Peak memory 244936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2232858526 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_sec_cm.2232858526
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/4.i2c_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/4.i2c_target_bad_addr.568970372
Short name T332
Test name
Test status
Simulation time 1139226921 ps
CPU time 9.7 seconds
Started Oct 12 05:57:02 AM UTC 24
Finished Oct 12 05:57:13 AM UTC 24
Peak memory 225632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=568970372 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_bad_addr.568970372
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/4.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/4.i2c_target_fifo_reset_acq.3228922347
Short name T177
Test name
Test status
Simulation time 791928705 ps
CPU time 1.89 seconds
Started Oct 12 05:56:57 AM UTC 24
Finished Oct 12 05:57:00 AM UTC 24
Peak memory 225572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3228922
347 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_fifo_reset_acq.3228922347
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/4.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/4.i2c_target_fifo_watermarks_acq.2926963042
Short name T335
Test name
Test status
Simulation time 570068325 ps
CPU time 5.01 seconds
Started Oct 12 05:57:14 AM UTC 24
Finished Oct 12 05:57:20 AM UTC 24
Peak memory 215780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2926963
042 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_fifo_watermark
s_acq.2926963042
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/4.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/4.i2c_target_fifo_watermarks_tx.1016751191
Short name T334
Test name
Test status
Simulation time 132234571 ps
CPU time 1.92 seconds
Started Oct 12 05:57:15 AM UTC 24
Finished Oct 12 05:57:18 AM UTC 24
Peak memory 215516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1016751
191 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_fifo_watermarks
_tx.1016751191
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/4.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/4.i2c_target_intr_smoke.3710858892
Short name T327
Test name
Test status
Simulation time 2052823681 ps
CPU time 8.67 seconds
Started Oct 12 05:56:47 AM UTC 24
Finished Oct 12 05:56:57 AM UTC 24
Peak memory 229728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=371085
8892 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_intr_smoke.3710858892
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/4.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/4.i2c_target_intr_stress_wr.1407785858
Short name T344
Test name
Test status
Simulation time 15362827157 ps
CPU time 68.69 seconds
Started Oct 12 05:56:49 AM UTC 24
Finished Oct 12 05:57:59 AM UTC 24
Peak memory 1889220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1407785858 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_intr_stress
_wr.1407785858
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/4.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/4.i2c_target_nack_acqfull.2898965147
Short name T341
Test name
Test status
Simulation time 9393470489 ps
CPU time 4.38 seconds
Started Oct 12 05:57:22 AM UTC 24
Finished Oct 12 05:57:27 AM UTC 24
Peak memory 225888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2898965
147 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_nack_acqfull.2898965147
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/4.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/4.i2c_target_nack_acqfull_addr.86061134
Short name T340
Test name
Test status
Simulation time 2025700541 ps
CPU time 4.1 seconds
Started Oct 12 05:57:22 AM UTC 24
Finished Oct 12 05:57:27 AM UTC 24
Peak memory 215476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8606113
4 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_nack_acqfull_addr.86061134
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/4.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/4.i2c_target_nack_txstretch.1697931820
Short name T62
Test name
Test status
Simulation time 595294401 ps
CPU time 2.09 seconds
Started Oct 12 05:57:22 AM UTC 24
Finished Oct 12 05:57:25 AM UTC 24
Peak memory 232332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1697931
820 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_nack_txstretch.1697931820
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/4.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/4.i2c_target_perf.3899025294
Short name T270
Test name
Test status
Simulation time 16095610137 ps
CPU time 9.24 seconds
Started Oct 12 05:56:59 AM UTC 24
Finished Oct 12 05:57:09 AM UTC 24
Peak memory 229868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3899025
294 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_perf.3899025294
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/4.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/4.i2c_target_smbus_maxlen.244239290
Short name T337
Test name
Test status
Simulation time 525479161 ps
CPU time 3.64 seconds
Started Oct 12 05:57:21 AM UTC 24
Finished Oct 12 05:57:26 AM UTC 24
Peak memory 215568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2442392
90 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_smbus_maxlen.244239290
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/4.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/4.i2c_target_smoke.2262765399
Short name T326
Test name
Test status
Simulation time 4664315151 ps
CPU time 8.39 seconds
Started Oct 12 05:56:42 AM UTC 24
Finished Oct 12 05:56:51 AM UTC 24
Peak memory 225888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2262765399 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_smoke.2262765399
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/4.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/4.i2c_target_stress_all.3759375015
Short name T456
Test name
Test status
Simulation time 33509801321 ps
CPU time 314.88 seconds
Started Oct 12 05:57:01 AM UTC 24
Finished Oct 12 06:02:20 AM UTC 24
Peak memory 2825428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=375937
5015 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_stress_all.3759375015
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/4.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/4.i2c_target_stress_rd.2564728459
Short name T328
Test name
Test status
Simulation time 1899373019 ps
CPU time 9.93 seconds
Started Oct 12 05:56:46 AM UTC 24
Finished Oct 12 05:56:57 AM UTC 24
Peak memory 215524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2564728459 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_stress_rd.2564728459
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/4.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/4.i2c_target_stress_wr.3609348375
Short name T323
Test name
Test status
Simulation time 14223754612 ps
CPU time 53.25 seconds
Started Oct 12 05:56:44 AM UTC 24
Finished Oct 12 05:57:39 AM UTC 24
Peak memory 215904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3609348375 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_stress_wr.3609348375
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/4.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/4.i2c_target_stretch.1431397465
Short name T329
Test name
Test status
Simulation time 3199796421 ps
CPU time 9.86 seconds
Started Oct 12 05:56:47 AM UTC 24
Finished Oct 12 05:56:58 AM UTC 24
Peak memory 335116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1431397465 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_stretch.1431397465
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/4.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/4.i2c_target_timeout.3142489493
Short name T331
Test name
Test status
Simulation time 5294136297 ps
CPU time 9.23 seconds
Started Oct 12 05:56:52 AM UTC 24
Finished Oct 12 05:57:03 AM UTC 24
Peak memory 246736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3142489
493 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_timeout.3142489493
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/4.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/4.i2c_target_tx_stretch_ctrl.2108506730
Short name T339
Test name
Test status
Simulation time 220852383 ps
CPU time 5.88 seconds
Started Oct 12 05:57:20 AM UTC 24
Finished Oct 12 05:57:27 AM UTC 24
Peak memory 215660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2108506
730 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_target_tx_stretch_ctrl.2108506730
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/4.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/40.i2c_alert_test.1093233140
Short name T1368
Test name
Test status
Simulation time 132377196 ps
CPU time 0.97 seconds
Started Oct 12 06:22:36 AM UTC 24
Finished Oct 12 06:22:37 AM UTC 24
Peak memory 213392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1093233140 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_alert_test.1093233140
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/40.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/40.i2c_host_error_intr.3421640844
Short name T1389
Test name
Test status
Simulation time 62017496 ps
CPU time 2.27 seconds
Started Oct 12 06:22:03 AM UTC 24
Finished Oct 12 06:22:06 AM UTC 24
Peak memory 225772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3421640844 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 40.i2c_host_error_intr.3421640844
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/40.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/40.i2c_host_fifo_fmt_empty.4130299048
Short name T1390
Test name
Test status
Simulation time 246208848 ps
CPU time 6.82 seconds
Started Oct 12 06:21:59 AM UTC 24
Finished Oct 12 06:22:07 AM UTC 24
Peak memory 260936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4130299048 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_fmt_empty.4130299048
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/40.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/40.i2c_host_fifo_full.2807865345
Short name T1556
Test name
Test status
Simulation time 13942866662 ps
CPU time 192.67 seconds
Started Oct 12 06:22:01 AM UTC 24
Finished Oct 12 06:25:17 AM UTC 24
Peak memory 701436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2807865345 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_full.2807865345
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/40.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/40.i2c_host_fifo_overflow.1524971664
Short name T1424
Test name
Test status
Simulation time 1621027529 ps
CPU time 50.86 seconds
Started Oct 12 06:21:59 AM UTC 24
Finished Oct 12 06:22:51 AM UTC 24
Peak memory 578500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1524971664 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_overflow.1524971664
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/40.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/40.i2c_host_fifo_reset_fmt.1270076585
Short name T1387
Test name
Test status
Simulation time 288139116 ps
CPU time 1.9 seconds
Started Oct 12 06:21:59 AM UTC 24
Finished Oct 12 06:22:02 AM UTC 24
Peak memory 215656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1270076585 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_fmt.1270076585
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/40.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/40.i2c_host_fifo_reset_rx.3179848967
Short name T1395
Test name
Test status
Simulation time 493891344 ps
CPU time 9.65 seconds
Started Oct 12 06:22:00 AM UTC 24
Finished Oct 12 06:22:11 AM UTC 24
Peak memory 215456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3179848967 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_rx.3179848967
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/40.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/40.i2c_host_fifo_watermark.4166783240
Short name T1486
Test name
Test status
Simulation time 4629128835 ps
CPU time 114.83 seconds
Started Oct 12 06:21:59 AM UTC 24
Finished Oct 12 06:23:56 AM UTC 24
Peak memory 1190764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4166783240 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_watermark.4166783240
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/40.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/40.i2c_host_may_nack.2888875718
Short name T1416
Test name
Test status
Simulation time 301786524 ps
CPU time 13.12 seconds
Started Oct 12 06:22:25 AM UTC 24
Finished Oct 12 06:22:39 AM UTC 24
Peak memory 215712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2888875718 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.i2c_host_may_nack.2888875718
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/40.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/40.i2c_host_mode_toggle.537746161
Short name T1403
Test name
Test status
Simulation time 185413741 ps
CPU time 2.78 seconds
Started Oct 12 06:22:23 AM UTC 24
Finished Oct 12 06:22:26 AM UTC 24
Peak memory 215844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=537746161 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 40.i2c_host_mode_toggle.537746161
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/40.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/40.i2c_host_override.1257869490
Short name T1384
Test name
Test status
Simulation time 40371759 ps
CPU time 1.04 seconds
Started Oct 12 06:21:59 AM UTC 24
Finished Oct 12 06:22:01 AM UTC 24
Peak memory 213212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1257869490 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.i2c_host_override.1257869490
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/40.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/40.i2c_host_perf.3983163035
Short name T1684
Test name
Test status
Simulation time 7200933029 ps
CPU time 302.31 seconds
Started Oct 12 06:22:02 AM UTC 24
Finished Oct 12 06:27:08 AM UTC 24
Peak memory 494848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3983163035 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 40.i2c_host_perf.3983163035
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/40.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/40.i2c_host_perf_precise.3226146027
Short name T1388
Test name
Test status
Simulation time 107621088 ps
CPU time 1.67 seconds
Started Oct 12 06:22:02 AM UTC 24
Finished Oct 12 06:22:04 AM UTC 24
Peak memory 213212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3226146027 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_perf_precise.3226146027
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/40.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/40.i2c_host_smoke.1692217342
Short name T1355
Test name
Test status
Simulation time 3251309981 ps
CPU time 38.09 seconds
Started Oct 12 06:21:58 AM UTC 24
Finished Oct 12 06:22:37 AM UTC 24
Peak memory 424980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1692217342 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 40.i2c_host_smoke.1692217342
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/40.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/40.i2c_host_stress_all.2305220082
Short name T277
Test name
Test status
Simulation time 5570068438 ps
CPU time 215.59 seconds
Started Oct 12 06:22:03 AM UTC 24
Finished Oct 12 06:25:42 AM UTC 24
Peak memory 908312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2305220082 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 40.i2c_host_stress_all.2305220082
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/40.i2c_host_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/40.i2c_host_stretch_timeout.3848763923
Short name T1404
Test name
Test status
Simulation time 2115373389 ps
CPU time 22.62 seconds
Started Oct 12 06:22:03 AM UTC 24
Finished Oct 12 06:22:27 AM UTC 24
Peak memory 225708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3848763923 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_stretch_timeout.3848763923
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/40.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/40.i2c_target_bad_addr.1542108420
Short name T1407
Test name
Test status
Simulation time 1211965384 ps
CPU time 9.35 seconds
Started Oct 12 06:22:20 AM UTC 24
Finished Oct 12 06:22:31 AM UTC 24
Peak memory 231908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=1542108420 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_bad_ad
dr.1542108420
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/40.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/40.i2c_target_fifo_reset_acq.1179270391
Short name T1397
Test name
Test status
Simulation time 175244992 ps
CPU time 1.33 seconds
Started Oct 12 06:22:16 AM UTC 24
Finished Oct 12 06:22:18 AM UTC 24
Peak memory 213632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1179270
391 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_fifo_reset_acq.1179270391
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/40.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/40.i2c_target_fifo_reset_tx.4110625944
Short name T1400
Test name
Test status
Simulation time 328089963 ps
CPU time 1.64 seconds
Started Oct 12 06:22:18 AM UTC 24
Finished Oct 12 06:22:21 AM UTC 24
Peak memory 215636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4110625
944 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_fifo_reset_tx.4110625944
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/40.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/40.i2c_target_fifo_watermarks_acq.107787013
Short name T1408
Test name
Test status
Simulation time 496601524 ps
CPU time 3.96 seconds
Started Oct 12 06:22:27 AM UTC 24
Finished Oct 12 06:22:32 AM UTC 24
Peak memory 215592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1077870
13 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_fifo_watermark
s_acq.107787013
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/40.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/40.i2c_target_fifo_watermarks_tx.1382018006
Short name T1406
Test name
Test status
Simulation time 116603266 ps
CPU time 1.47 seconds
Started Oct 12 06:22:28 AM UTC 24
Finished Oct 12 06:22:30 AM UTC 24
Peak memory 213508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1382018
006 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_fifo_watermark
s_tx.1382018006
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/40.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/40.i2c_target_intr_smoke.2242985489
Short name T1398
Test name
Test status
Simulation time 1616400703 ps
CPU time 8.21 seconds
Started Oct 12 06:22:10 AM UTC 24
Finished Oct 12 06:22:19 AM UTC 24
Peak memory 225768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=224298
5489 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_intr_smoke.2242985489
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/40.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/40.i2c_target_intr_stress_wr.3240791388
Short name T1421
Test name
Test status
Simulation time 17191085416 ps
CPU time 39.34 seconds
Started Oct 12 06:22:10 AM UTC 24
Finished Oct 12 06:22:50 AM UTC 24
Peak memory 763076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3240791388 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_intr_stres
s_wr.3240791388
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/40.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/40.i2c_target_nack_acqfull.175064714
Short name T1344
Test name
Test status
Simulation time 647396402 ps
CPU time 2.84 seconds
Started Oct 12 06:22:32 AM UTC 24
Finished Oct 12 06:22:36 AM UTC 24
Peak memory 225956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1750647
14 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_nack_acqfull.175064714
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/40.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/40.i2c_target_nack_acqfull_addr.4205639839
Short name T1415
Test name
Test status
Simulation time 1090537909 ps
CPU time 3.37 seconds
Started Oct 12 06:22:33 AM UTC 24
Finished Oct 12 06:22:38 AM UTC 24
Peak memory 215740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4205639
839 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_nack_acqfull_ad
dr.4205639839
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/40.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/40.i2c_target_nack_txstretch.1417113118
Short name T1382
Test name
Test status
Simulation time 512805679 ps
CPU time 1.63 seconds
Started Oct 12 06:22:33 AM UTC 24
Finished Oct 12 06:22:36 AM UTC 24
Peak memory 232768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1417113
118 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_nack_txstretch.1417113118
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/40.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/40.i2c_target_perf.684047350
Short name T1405
Test name
Test status
Simulation time 618359546 ps
CPU time 8.74 seconds
Started Oct 12 06:22:19 AM UTC 24
Finished Oct 12 06:22:29 AM UTC 24
Peak memory 227816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6840473
50 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_perf.684047350
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/40.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/40.i2c_target_smbus_maxlen.21061417
Short name T1413
Test name
Test status
Simulation time 1728427813 ps
CPU time 3.37 seconds
Started Oct 12 06:22:31 AM UTC 24
Finished Oct 12 06:22:36 AM UTC 24
Peak memory 215180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2106141
7 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_smbus_maxlen.21061417
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/40.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/40.i2c_target_smoke.203162055
Short name T89
Test name
Test status
Simulation time 3026868036 ps
CPU time 30.99 seconds
Started Oct 12 06:22:05 AM UTC 24
Finished Oct 12 06:22:37 AM UTC 24
Peak memory 225832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=203162055 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_smoke.203162055
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/40.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/40.i2c_target_stress_all.3614013242
Short name T1459
Test name
Test status
Simulation time 9371216205 ps
CPU time 64.66 seconds
Started Oct 12 06:22:20 AM UTC 24
Finished Oct 12 06:23:27 AM UTC 24
Peak memory 328708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=361401
3242 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_stress_all.3614013242
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/40.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/40.i2c_target_stress_rd.2326198466
Short name T1396
Test name
Test status
Simulation time 288821103 ps
CPU time 7.93 seconds
Started Oct 12 06:22:08 AM UTC 24
Finished Oct 12 06:22:17 AM UTC 24
Peak memory 215464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2326198466 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_stress_rd.2326198466
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/40.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/40.i2c_target_stress_wr.1970474233
Short name T1430
Test name
Test status
Simulation time 19714024879 ps
CPU time 49.13 seconds
Started Oct 12 06:22:07 AM UTC 24
Finished Oct 12 06:22:58 AM UTC 24
Peak memory 215512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1970474233 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_stress_wr.1970474233
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/40.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/40.i2c_target_timeout.475589161
Short name T1399
Test name
Test status
Simulation time 5975624364 ps
CPU time 7.6 seconds
Started Oct 12 06:22:11 AM UTC 24
Finished Oct 12 06:22:19 AM UTC 24
Peak memory 226148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4755891
61 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_timeout.475589161
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/40.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/40.i2c_target_tx_stretch_ctrl.3189403122
Short name T1411
Test name
Test status
Simulation time 154594006 ps
CPU time 3.44 seconds
Started Oct 12 06:22:30 AM UTC 24
Finished Oct 12 06:22:35 AM UTC 24
Peak memory 215720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3189403
122 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_target_tx_stretch_ctrl.3189403122
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/40.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/41.i2c_alert_test.3556095279
Short name T1444
Test name
Test status
Simulation time 15485160 ps
CPU time 0.98 seconds
Started Oct 12 06:23:06 AM UTC 24
Finished Oct 12 06:23:08 AM UTC 24
Peak memory 215628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3556095279 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_alert_test.3556095279
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/41.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/41.i2c_host_error_intr.2261006142
Short name T1418
Test name
Test status
Simulation time 416876410 ps
CPU time 3.84 seconds
Started Oct 12 06:22:40 AM UTC 24
Finished Oct 12 06:22:45 AM UTC 24
Peak memory 229892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2261006142 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 41.i2c_host_error_intr.2261006142
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/41.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/41.i2c_host_fifo_fmt_empty.2905755658
Short name T1425
Test name
Test status
Simulation time 607724453 ps
CPU time 14.7 seconds
Started Oct 12 06:22:37 AM UTC 24
Finished Oct 12 06:22:53 AM UTC 24
Peak memory 271620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2905755658 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_fmt_empty.2905755658
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/41.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/41.i2c_host_fifo_full.3098928005
Short name T1490
Test name
Test status
Simulation time 5531660104 ps
CPU time 81.92 seconds
Started Oct 12 06:22:38 AM UTC 24
Finished Oct 12 06:24:02 AM UTC 24
Peak memory 433080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3098928005 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_full.3098928005
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/41.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/41.i2c_host_fifo_overflow.3252417912
Short name T1516
Test name
Test status
Simulation time 3796289848 ps
CPU time 107.96 seconds
Started Oct 12 06:22:37 AM UTC 24
Finished Oct 12 06:24:27 AM UTC 24
Peak memory 678792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3252417912 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_overflow.3252417912
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/41.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/41.i2c_host_fifo_reset_fmt.2698458246
Short name T1417
Test name
Test status
Simulation time 165394346 ps
CPU time 1.26 seconds
Started Oct 12 06:22:37 AM UTC 24
Finished Oct 12 06:22:39 AM UTC 24
Peak memory 212988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2698458246 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_fmt.2698458246
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/41.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/41.i2c_host_fifo_reset_rx.2874647451
Short name T1420
Test name
Test status
Simulation time 228090923 ps
CPU time 8.8 seconds
Started Oct 12 06:22:38 AM UTC 24
Finished Oct 12 06:22:48 AM UTC 24
Peak memory 215308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2874647451 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_rx.2874647451
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/41.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/41.i2c_host_fifo_watermark.1722055633
Short name T1601
Test name
Test status
Simulation time 71720747037 ps
CPU time 195.74 seconds
Started Oct 12 06:22:37 AM UTC 24
Finished Oct 12 06:25:56 AM UTC 24
Peak memory 1055672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1722055633 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_watermark.1722055633
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/41.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/41.i2c_host_may_nack.767412227
Short name T1446
Test name
Test status
Simulation time 1096529566 ps
CPU time 8.43 seconds
Started Oct 12 06:22:59 AM UTC 24
Finished Oct 12 06:23:09 AM UTC 24
Peak memory 215508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=767412227 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 41.i2c_host_may_nack.767412227
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/41.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/41.i2c_host_override.3611029641
Short name T145
Test name
Test status
Simulation time 29357846 ps
CPU time 0.95 seconds
Started Oct 12 06:22:36 AM UTC 24
Finished Oct 12 06:22:38 AM UTC 24
Peak memory 213212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3611029641 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.i2c_host_override.3611029641
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/41.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/41.i2c_host_perf.523618748
Short name T1615
Test name
Test status
Simulation time 52530735327 ps
CPU time 206.51 seconds
Started Oct 12 06:22:38 AM UTC 24
Finished Oct 12 06:26:08 AM UTC 24
Peak memory 248704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=523618748 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 41.i2c_host_perf.523618748
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/41.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/41.i2c_host_perf_precise.1175766000
Short name T1422
Test name
Test status
Simulation time 3084027382 ps
CPU time 10.86 seconds
Started Oct 12 06:22:39 AM UTC 24
Finished Oct 12 06:22:50 AM UTC 24
Peak memory 215444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1175766000 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_perf_precise.1175766000
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/41.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/41.i2c_host_smoke.1672966700
Short name T1441
Test name
Test status
Simulation time 6992286094 ps
CPU time 29.33 seconds
Started Oct 12 06:22:36 AM UTC 24
Finished Oct 12 06:23:06 AM UTC 24
Peak memory 357636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1672966700 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.i2c_host_smoke.1672966700
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/41.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/41.i2c_host_stress_all.2079189863
Short name T278
Test name
Test status
Simulation time 40262089562 ps
CPU time 915.1 seconds
Started Oct 12 06:22:40 AM UTC 24
Finished Oct 12 06:38:05 AM UTC 24
Peak memory 2755660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2079189863 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 41.i2c_host_stress_all.2079189863
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/41.i2c_host_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/41.i2c_host_stretch_timeout.26303021
Short name T1433
Test name
Test status
Simulation time 4768758020 ps
CPU time 19.07 seconds
Started Oct 12 06:22:40 AM UTC 24
Finished Oct 12 06:23:00 AM UTC 24
Peak memory 242684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=26303021 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ho
st_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_stretch_timeout.26303021
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/41.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/41.i2c_target_bad_addr.3603198507
Short name T1440
Test name
Test status
Simulation time 2022378553 ps
CPU time 5.68 seconds
Started Oct 12 06:22:58 AM UTC 24
Finished Oct 12 06:23:05 AM UTC 24
Peak memory 225636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=3603198507 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_bad_ad
dr.3603198507
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/41.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/41.i2c_target_fifo_reset_acq.405648362
Short name T1429
Test name
Test status
Simulation time 389918400 ps
CPU time 1.91 seconds
Started Oct 12 06:22:54 AM UTC 24
Finished Oct 12 06:22:57 AM UTC 24
Peak memory 215536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4056483
62 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_fifo_reset_acq.405648362
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/41.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/41.i2c_target_fifo_reset_tx.1387883521
Short name T1432
Test name
Test status
Simulation time 537898878 ps
CPU time 1.92 seconds
Started Oct 12 06:22:55 AM UTC 24
Finished Oct 12 06:22:58 AM UTC 24
Peak memory 215536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1387883
521 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_fifo_reset_tx.1387883521
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/41.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/41.i2c_target_fifo_watermarks_acq.350278730
Short name T1436
Test name
Test status
Simulation time 222728430 ps
CPU time 1.52 seconds
Started Oct 12 06:23:00 AM UTC 24
Finished Oct 12 06:23:03 AM UTC 24
Peak memory 215568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3502787
30 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_fifo_watermark
s_acq.350278730
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/41.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/41.i2c_target_hrst.1850107265
Short name T1435
Test name
Test status
Simulation time 407655458 ps
CPU time 2.68 seconds
Started Oct 12 06:22:59 AM UTC 24
Finished Oct 12 06:23:03 AM UTC 24
Peak memory 226080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1850107
265 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_hrst.1850107265
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/41.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/41.i2c_target_intr_smoke.356648203
Short name T1434
Test name
Test status
Simulation time 4938861912 ps
CPU time 8.41 seconds
Started Oct 12 06:22:51 AM UTC 24
Finished Oct 12 06:23:01 AM UTC 24
Peak memory 232764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=356648
203 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_intr_smoke.356648203
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/41.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/41.i2c_target_intr_stress_wr.770891797
Short name T1457
Test name
Test status
Simulation time 12698088020 ps
CPU time 29.92 seconds
Started Oct 12 06:22:51 AM UTC 24
Finished Oct 12 06:23:23 AM UTC 24
Peak memory 807892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=770891797 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_intr_stress
_wr.770891797
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/41.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/41.i2c_target_nack_acqfull.3067100593
Short name T1450
Test name
Test status
Simulation time 491243376 ps
CPU time 4.95 seconds
Started Oct 12 06:23:05 AM UTC 24
Finished Oct 12 06:23:11 AM UTC 24
Peak memory 225752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3067100
593 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_nack_acqfull.3067100593
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/41.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/41.i2c_target_nack_acqfull_addr.829435186
Short name T1449
Test name
Test status
Simulation time 2321865168 ps
CPU time 3.83 seconds
Started Oct 12 06:23:05 AM UTC 24
Finished Oct 12 06:23:10 AM UTC 24
Peak memory 215804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8294351
86 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_nack_acqfull_addr.829435186
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/41.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/41.i2c_target_nack_txstretch.1922050903
Short name T1445
Test name
Test status
Simulation time 351736633 ps
CPU time 2.43 seconds
Started Oct 12 06:23:05 AM UTC 24
Finished Oct 12 06:23:09 AM UTC 24
Peak memory 232520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1922050
903 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_nack_txstretch.1922050903
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/41.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/41.i2c_target_perf.3717066430
Short name T1438
Test name
Test status
Simulation time 3800284936 ps
CPU time 4.53 seconds
Started Oct 12 06:22:58 AM UTC 24
Finished Oct 12 06:23:04 AM UTC 24
Peak memory 231912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3717066
430 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_perf.3717066430
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/41.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/41.i2c_target_smbus_maxlen.3519530541
Short name T1442
Test name
Test status
Simulation time 433678269 ps
CPU time 2.67 seconds
Started Oct 12 06:23:04 AM UTC 24
Finished Oct 12 06:23:08 AM UTC 24
Peak memory 215248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3519530
541 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_smbus_maxlen.3519530541
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/41.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/41.i2c_target_smoke.1079548750
Short name T1458
Test name
Test status
Simulation time 1260641567 ps
CPU time 41.71 seconds
Started Oct 12 06:22:40 AM UTC 24
Finished Oct 12 06:23:23 AM UTC 24
Peak memory 226024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1079548750 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_smoke.1079548750
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/41.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/41.i2c_target_stress_all.1107859956
Short name T1557
Test name
Test status
Simulation time 13327143702 ps
CPU time 138 seconds
Started Oct 12 06:22:58 AM UTC 24
Finished Oct 12 06:25:19 AM UTC 24
Peak memory 2427912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=110785
9956 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_stress_all.1107859956
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/41.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/41.i2c_target_stress_rd.2573294805
Short name T1451
Test name
Test status
Simulation time 2215902423 ps
CPU time 24.08 seconds
Started Oct 12 06:22:46 AM UTC 24
Finished Oct 12 06:23:11 AM UTC 24
Peak memory 225692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2573294805 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_stress_rd.2573294805
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/41.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/41.i2c_target_stress_wr.4170757248
Short name T1619
Test name
Test status
Simulation time 44788307895 ps
CPU time 203.65 seconds
Started Oct 12 06:22:45 AM UTC 24
Finished Oct 12 06:26:11 AM UTC 24
Peak memory 3251196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4170757248 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_stress_wr.4170757248
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/41.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/41.i2c_target_stretch.1626185135
Short name T1427
Test name
Test status
Simulation time 1830135019 ps
CPU time 3.15 seconds
Started Oct 12 06:22:49 AM UTC 24
Finished Oct 12 06:22:53 AM UTC 24
Peak memory 215516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1626185135 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_stretch.1626185135
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/41.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/41.i2c_target_timeout.2178858084
Short name T1439
Test name
Test status
Simulation time 5926154672 ps
CPU time 11.53 seconds
Started Oct 12 06:22:53 AM UTC 24
Finished Oct 12 06:23:05 AM UTC 24
Peak memory 225692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2178858
084 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_timeout.2178858084
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/41.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/41.i2c_target_tx_stretch_ctrl.3856281212
Short name T1443
Test name
Test status
Simulation time 74946299 ps
CPU time 3.1 seconds
Started Oct 12 06:23:04 AM UTC 24
Finished Oct 12 06:23:08 AM UTC 24
Peak memory 215724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3856281
212 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_target_tx_stretch_ctrl.3856281212
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/41.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/42.i2c_alert_test.4205160473
Short name T1474
Test name
Test status
Simulation time 16357815 ps
CPU time 0.96 seconds
Started Oct 12 06:23:41 AM UTC 24
Finished Oct 12 06:23:43 AM UTC 24
Peak memory 215588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4205160473 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_alert_test.4205160473
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/42.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/42.i2c_host_error_intr.1035551110
Short name T1455
Test name
Test status
Simulation time 1045570811 ps
CPU time 5.88 seconds
Started Oct 12 06:23:12 AM UTC 24
Finished Oct 12 06:23:20 AM UTC 24
Peak memory 246748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1035551110 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 42.i2c_host_error_intr.1035551110
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/42.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/42.i2c_host_fifo_fmt_empty.1281293439
Short name T1456
Test name
Test status
Simulation time 1038891036 ps
CPU time 10.81 seconds
Started Oct 12 06:23:10 AM UTC 24
Finished Oct 12 06:23:22 AM UTC 24
Peak memory 242680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1281293439 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_fmt_empty.1281293439
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/42.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/42.i2c_host_fifo_full.718071414
Short name T1513
Test name
Test status
Simulation time 10208109072 ps
CPU time 72.54 seconds
Started Oct 12 06:23:10 AM UTC 24
Finished Oct 12 06:24:24 AM UTC 24
Peak memory 500660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=718071414 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_full.718071414
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/42.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/42.i2c_host_fifo_overflow.2045148223
Short name T1600
Test name
Test status
Simulation time 16405855816 ps
CPU time 164.09 seconds
Started Oct 12 06:23:09 AM UTC 24
Finished Oct 12 06:25:55 AM UTC 24
Peak memory 843080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2045148223 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_overflow.2045148223
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/42.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/42.i2c_host_fifo_reset_fmt.3109689178
Short name T1452
Test name
Test status
Simulation time 439147824 ps
CPU time 1.98 seconds
Started Oct 12 06:23:10 AM UTC 24
Finished Oct 12 06:23:13 AM UTC 24
Peak memory 215164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3109689178 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_fmt.3109689178
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/42.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/42.i2c_host_fifo_reset_rx.1972903911
Short name T1454
Test name
Test status
Simulation time 236857780 ps
CPU time 5.75 seconds
Started Oct 12 06:23:10 AM UTC 24
Finished Oct 12 06:23:17 AM UTC 24
Peak memory 215372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1972903911 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_rx.1972903911
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/42.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/42.i2c_host_fifo_watermark.3002748494
Short name T1515
Test name
Test status
Simulation time 3308801457 ps
CPU time 76.17 seconds
Started Oct 12 06:23:09 AM UTC 24
Finished Oct 12 06:24:27 AM UTC 24
Peak memory 1061764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3002748494 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_watermark.3002748494
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/42.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/42.i2c_host_may_nack.2262611716
Short name T1476
Test name
Test status
Simulation time 419616639 ps
CPU time 7.55 seconds
Started Oct 12 06:23:35 AM UTC 24
Finished Oct 12 06:23:44 AM UTC 24
Peak memory 215440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2262611716 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.i2c_host_may_nack.2262611716
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/42.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/42.i2c_host_mode_toggle.3132325427
Short name T1468
Test name
Test status
Simulation time 107316700 ps
CPU time 3.22 seconds
Started Oct 12 06:23:34 AM UTC 24
Finished Oct 12 06:23:38 AM UTC 24
Peak memory 232380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3132325427 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_mode_toggle.3132325427
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/42.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/42.i2c_host_override.830833915
Short name T1448
Test name
Test status
Simulation time 52560365 ps
CPU time 1.05 seconds
Started Oct 12 06:23:07 AM UTC 24
Finished Oct 12 06:23:09 AM UTC 24
Peak memory 213212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=830833915 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 42.i2c_host_override.830833915
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/42.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/42.i2c_host_perf.2556383877
Short name T1712
Test name
Test status
Simulation time 25632586566 ps
CPU time 267.44 seconds
Started Oct 12 06:23:10 AM UTC 24
Finished Oct 12 06:27:42 AM UTC 24
Peak memory 215760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2556383877 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 42.i2c_host_perf.2556383877
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/42.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/42.i2c_host_perf_precise.4185394654
Short name T1453
Test name
Test status
Simulation time 53849522 ps
CPU time 2.03 seconds
Started Oct 12 06:23:11 AM UTC 24
Finished Oct 12 06:23:14 AM UTC 24
Peak memory 225904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4185394654 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_perf_precise.4185394654
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/42.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/42.i2c_host_smoke.3066269029
Short name T1464
Test name
Test status
Simulation time 7382576721 ps
CPU time 26.32 seconds
Started Oct 12 06:23:06 AM UTC 24
Finished Oct 12 06:23:34 AM UTC 24
Peak memory 330960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3066269029 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 42.i2c_host_smoke.3066269029
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/42.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/42.i2c_host_stretch_timeout.2698803314
Short name T1473
Test name
Test status
Simulation time 576391707 ps
CPU time 27.75 seconds
Started Oct 12 06:23:12 AM UTC 24
Finished Oct 12 06:23:42 AM UTC 24
Peak memory 225708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2698803314 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_stretch_timeout.2698803314
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/42.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/42.i2c_target_bad_addr.620234710
Short name T1469
Test name
Test status
Simulation time 1966484577 ps
CPU time 6.91 seconds
Started Oct 12 06:23:31 AM UTC 24
Finished Oct 12 06:23:39 AM UTC 24
Peak memory 225712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=620234710 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_bad_addr.620234710
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/42.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/42.i2c_target_fifo_reset_acq.1261031396
Short name T1460
Test name
Test status
Simulation time 556889200 ps
CPU time 1.71 seconds
Started Oct 12 06:23:24 AM UTC 24
Finished Oct 12 06:23:27 AM UTC 24
Peak memory 213272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1261031
396 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_fifo_reset_acq.1261031396
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/42.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/42.i2c_target_fifo_reset_tx.3819597579
Short name T1462
Test name
Test status
Simulation time 686563675 ps
CPU time 1.7 seconds
Started Oct 12 06:23:28 AM UTC 24
Finished Oct 12 06:23:30 AM UTC 24
Peak memory 227560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3819597
579 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_fifo_reset_tx.3819597579
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/42.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/42.i2c_target_fifo_watermarks_acq.507558226
Short name T1472
Test name
Test status
Simulation time 763374974 ps
CPU time 2.89 seconds
Started Oct 12 06:23:36 AM UTC 24
Finished Oct 12 06:23:40 AM UTC 24
Peak memory 215776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5075582
26 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_fifo_watermark
s_acq.507558226
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/42.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/42.i2c_target_fifo_watermarks_tx.4001413501
Short name T1470
Test name
Test status
Simulation time 227476283 ps
CPU time 1.83 seconds
Started Oct 12 06:23:36 AM UTC 24
Finished Oct 12 06:23:39 AM UTC 24
Peak memory 215572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4001413
501 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_fifo_watermark
s_tx.4001413501
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/42.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/42.i2c_target_hrst.2279359427
Short name T1467
Test name
Test status
Simulation time 280704257 ps
CPU time 3.48 seconds
Started Oct 12 06:23:31 AM UTC 24
Finished Oct 12 06:23:35 AM UTC 24
Peak memory 225692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2279359
427 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_hrst.2279359427
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/42.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/42.i2c_target_intr_smoke.4047236100
Short name T1465
Test name
Test status
Simulation time 5458422723 ps
CPU time 9.9 seconds
Started Oct 12 06:23:24 AM UTC 24
Finished Oct 12 06:23:35 AM UTC 24
Peak memory 228080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=404723
6100 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_intr_smoke.4047236100
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/42.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/42.i2c_target_intr_stress_wr.932591825
Short name T1484
Test name
Test status
Simulation time 14899043139 ps
CPU time 21.24 seconds
Started Oct 12 06:23:24 AM UTC 24
Finished Oct 12 06:23:47 AM UTC 24
Peak memory 525248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=932591825 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_intr_stress
_wr.932591825
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/42.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/42.i2c_target_nack_acqfull.1143936762
Short name T1481
Test name
Test status
Simulation time 1433632709 ps
CPU time 5.07 seconds
Started Oct 12 06:23:40 AM UTC 24
Finished Oct 12 06:23:46 AM UTC 24
Peak memory 226092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1143936
762 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_nack_acqfull.1143936762
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/42.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/42.i2c_target_nack_acqfull_addr.4101614261
Short name T50
Test name
Test status
Simulation time 536632524 ps
CPU time 5.58 seconds
Started Oct 12 06:23:40 AM UTC 24
Finished Oct 12 06:23:46 AM UTC 24
Peak memory 215744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4101614
261 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_nack_acqfull_ad
dr.4101614261
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/42.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/42.i2c_target_nack_txstretch.1719019962
Short name T1477
Test name
Test status
Simulation time 309766735 ps
CPU time 2.78 seconds
Started Oct 12 06:23:41 AM UTC 24
Finished Oct 12 06:23:45 AM UTC 24
Peak memory 232280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1719019
962 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_nack_txstretch.1719019962
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/42.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/42.i2c_target_perf.1919053565
Short name T1463
Test name
Test status
Simulation time 3720431775 ps
CPU time 4.57 seconds
Started Oct 12 06:23:28 AM UTC 24
Finished Oct 12 06:23:33 AM UTC 24
Peak memory 232456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1919053
565 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_perf.1919053565
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/42.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/42.i2c_target_smbus_maxlen.2207576337
Short name T1478
Test name
Test status
Simulation time 2227773980 ps
CPU time 4.15 seconds
Started Oct 12 06:23:39 AM UTC 24
Finished Oct 12 06:23:45 AM UTC 24
Peak memory 215248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2207576
337 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_smbus_maxlen.2207576337
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/42.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/42.i2c_target_smoke.1968063235
Short name T1461
Test name
Test status
Simulation time 743322235 ps
CPU time 13.37 seconds
Started Oct 12 06:23:16 AM UTC 24
Finished Oct 12 06:23:30 AM UTC 24
Peak memory 226032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1968063235 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_smoke.1968063235
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/42.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/42.i2c_target_stress_all.672482182
Short name T1542
Test name
Test status
Simulation time 208122332486 ps
CPU time 88.34 seconds
Started Oct 12 06:23:28 AM UTC 24
Finished Oct 12 06:24:58 AM UTC 24
Peak memory 621892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=672482
182 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_stress_all.672482182
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/42.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/42.i2c_target_stress_rd.731812872
Short name T1479
Test name
Test status
Simulation time 6296820235 ps
CPU time 22.84 seconds
Started Oct 12 06:23:21 AM UTC 24
Finished Oct 12 06:23:45 AM UTC 24
Peak memory 248756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=731812872 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_stress_rd.731812872
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/42.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/42.i2c_target_stress_wr.2976471710
Short name T1611
Test name
Test status
Simulation time 28986988783 ps
CPU time 160.23 seconds
Started Oct 12 06:23:18 AM UTC 24
Finished Oct 12 06:26:01 AM UTC 24
Peak memory 2329796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2976471710 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_stress_wr.2976471710
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/42.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/42.i2c_target_stretch.3944337546
Short name T1500
Test name
Test status
Simulation time 3626847822 ps
CPU time 50.86 seconds
Started Oct 12 06:23:23 AM UTC 24
Finished Oct 12 06:24:15 AM UTC 24
Peak memory 1049548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3944337546 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_stretch.3944337546
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/42.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/42.i2c_target_timeout.1758861053
Short name T1466
Test name
Test status
Simulation time 1100442065 ps
CPU time 9.81 seconds
Started Oct 12 06:23:24 AM UTC 24
Finished Oct 12 06:23:35 AM UTC 24
Peak memory 225824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1758861
053 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_timeout.1758861053
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/42.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/42.i2c_target_tx_stretch_ctrl.2235457285
Short name T1471
Test name
Test status
Simulation time 68171252 ps
CPU time 2.71 seconds
Started Oct 12 06:23:36 AM UTC 24
Finished Oct 12 06:23:40 AM UTC 24
Peak memory 215464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2235457
285 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_target_tx_stretch_ctrl.2235457285
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/42.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/43.i2c_alert_test.3695836666
Short name T1508
Test name
Test status
Simulation time 17214012 ps
CPU time 0.9 seconds
Started Oct 12 06:24:19 AM UTC 24
Finished Oct 12 06:24:20 AM UTC 24
Peak memory 215628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3695836666 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_alert_test.3695836666
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/43.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/43.i2c_host_error_intr.1261875888
Short name T1487
Test name
Test status
Simulation time 327885614 ps
CPU time 8.25 seconds
Started Oct 12 06:23:47 AM UTC 24
Finished Oct 12 06:23:56 AM UTC 24
Peak memory 232392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1261875888 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 43.i2c_host_error_intr.1261875888
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/43.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/43.i2c_host_fifo_fmt_empty.4278161534
Short name T1489
Test name
Test status
Simulation time 598127076 ps
CPU time 14.34 seconds
Started Oct 12 06:23:45 AM UTC 24
Finished Oct 12 06:24:01 AM UTC 24
Peak memory 351232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4278161534 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_fmt_empty.4278161534
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/43.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/43.i2c_host_fifo_full.445592136
Short name T1573
Test name
Test status
Simulation time 3828172473 ps
CPU time 102.75 seconds
Started Oct 12 06:23:47 AM UTC 24
Finished Oct 12 06:25:31 AM UTC 24
Peak memory 681228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=445592136 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_full.445592136
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/43.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/43.i2c_host_fifo_overflow.4114449983
Short name T1523
Test name
Test status
Simulation time 4114474479 ps
CPU time 57.02 seconds
Started Oct 12 06:23:44 AM UTC 24
Finished Oct 12 06:24:43 AM UTC 24
Peak memory 752532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4114449983 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_overflow.4114449983
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/43.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/43.i2c_host_fifo_reset_fmt.2784024610
Short name T1437
Test name
Test status
Simulation time 616527813 ps
CPU time 2.22 seconds
Started Oct 12 06:23:45 AM UTC 24
Finished Oct 12 06:23:49 AM UTC 24
Peak memory 215440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2784024610 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_fmt.2784024610
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/43.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/43.i2c_host_fifo_reset_rx.3884458703
Short name T1485
Test name
Test status
Simulation time 444310501 ps
CPU time 3.76 seconds
Started Oct 12 06:23:45 AM UTC 24
Finished Oct 12 06:23:50 AM UTC 24
Peak memory 215444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3884458703 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_rx.3884458703
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/43.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/43.i2c_host_fifo_watermark.3910269117
Short name T123
Test name
Test status
Simulation time 9962274735 ps
CPU time 109.77 seconds
Started Oct 12 06:23:44 AM UTC 24
Finished Oct 12 06:25:36 AM UTC 24
Peak memory 1389836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3910269117 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_watermark.3910269117
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/43.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/43.i2c_host_may_nack.419909532
Short name T1527
Test name
Test status
Simulation time 2723830182 ps
CPU time 30.61 seconds
Started Oct 12 06:24:13 AM UTC 24
Finished Oct 12 06:24:45 AM UTC 24
Peak memory 215572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=419909532 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 43.i2c_host_may_nack.419909532
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/43.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/43.i2c_host_mode_toggle.2179473455
Short name T1503
Test name
Test status
Simulation time 600392658 ps
CPU time 7.3 seconds
Started Oct 12 06:24:09 AM UTC 24
Finished Oct 12 06:24:17 AM UTC 24
Peak memory 226096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2179473455 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_mode_toggle.2179473455
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/43.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/43.i2c_host_override.3431278004
Short name T1482
Test name
Test status
Simulation time 89215688 ps
CPU time 1.05 seconds
Started Oct 12 06:23:44 AM UTC 24
Finished Oct 12 06:23:46 AM UTC 24
Peak memory 213212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3431278004 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.i2c_host_override.3431278004
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/43.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/43.i2c_host_perf.2508035205
Short name T1553
Test name
Test status
Simulation time 7773381414 ps
CPU time 82.48 seconds
Started Oct 12 06:23:47 AM UTC 24
Finished Oct 12 06:25:11 AM UTC 24
Peak memory 859456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2508035205 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 43.i2c_host_perf.2508035205
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/43.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/43.i2c_host_perf_precise.3783248718
Short name T1504
Test name
Test status
Simulation time 6076257713 ps
CPU time 29.34 seconds
Started Oct 12 06:23:47 AM UTC 24
Finished Oct 12 06:24:17 AM UTC 24
Peak memory 215516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3783248718 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_perf_precise.3783248718
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/43.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/43.i2c_host_smoke.1850525423
Short name T1566
Test name
Test status
Simulation time 24055054118 ps
CPU time 102.49 seconds
Started Oct 12 06:23:43 AM UTC 24
Finished Oct 12 06:25:27 AM UTC 24
Peak memory 398356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1850525423 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.i2c_host_smoke.1850525423
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/43.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/43.i2c_host_stretch_timeout.2429884227
Short name T1488
Test name
Test status
Simulation time 619461034 ps
CPU time 11.99 seconds
Started Oct 12 06:23:47 AM UTC 24
Finished Oct 12 06:24:00 AM UTC 24
Peak memory 227932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2429884227 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_stretch_timeout.2429884227
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/43.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/43.i2c_target_bad_addr.3134042892
Short name T1501
Test name
Test status
Simulation time 2299350741 ps
CPU time 7.27 seconds
Started Oct 12 06:24:07 AM UTC 24
Finished Oct 12 06:24:16 AM UTC 24
Peak memory 232404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=3134042892 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_bad_ad
dr.3134042892
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/43.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/43.i2c_target_fifo_reset_acq.4276735914
Short name T153
Test name
Test status
Simulation time 222698636 ps
CPU time 2.23 seconds
Started Oct 12 06:24:03 AM UTC 24
Finished Oct 12 06:24:06 AM UTC 24
Peak memory 215728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4276735
914 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_fifo_reset_acq.4276735914
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/43.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/43.i2c_target_fifo_reset_tx.3252456621
Short name T1494
Test name
Test status
Simulation time 217588112 ps
CPU time 2.56 seconds
Started Oct 12 06:24:04 AM UTC 24
Finished Oct 12 06:24:08 AM UTC 24
Peak memory 215396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3252456
621 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_fifo_reset_tx.3252456621
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/43.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/43.i2c_target_fifo_watermarks_acq.573080555
Short name T1505
Test name
Test status
Simulation time 557783584 ps
CPU time 3.76 seconds
Started Oct 12 06:24:13 AM UTC 24
Finished Oct 12 06:24:18 AM UTC 24
Peak memory 225572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5730805
55 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_fifo_watermark
s_acq.573080555
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/43.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/43.i2c_target_fifo_watermarks_tx.3515481229
Short name T1502
Test name
Test status
Simulation time 115437186 ps
CPU time 1.92 seconds
Started Oct 12 06:24:14 AM UTC 24
Finished Oct 12 06:24:17 AM UTC 24
Peak memory 215632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3515481
229 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_fifo_watermark
s_tx.3515481229
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/43.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/43.i2c_target_hrst.1011643442
Short name T1498
Test name
Test status
Simulation time 4096799484 ps
CPU time 2.96 seconds
Started Oct 12 06:24:09 AM UTC 24
Finished Oct 12 06:24:12 AM UTC 24
Peak memory 225756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1011643
442 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_hrst.1011643442
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/43.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/43.i2c_target_intr_smoke.3892269066
Short name T1493
Test name
Test status
Simulation time 10680069086 ps
CPU time 7.08 seconds
Started Oct 12 06:23:57 AM UTC 24
Finished Oct 12 06:24:05 AM UTC 24
Peak memory 232112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=389226
9066 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_intr_smoke.3892269066
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/43.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/43.i2c_target_intr_stress_wr.1554314977
Short name T1641
Test name
Test status
Simulation time 13288724664 ps
CPU time 160.67 seconds
Started Oct 12 06:23:57 AM UTC 24
Finished Oct 12 06:26:40 AM UTC 24
Peak memory 3409088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1554314977 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_intr_stres
s_wr.1554314977
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/43.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/43.i2c_target_nack_acqfull.964085400
Short name T1511
Test name
Test status
Simulation time 2640468218 ps
CPU time 5.69 seconds
Started Oct 12 06:24:16 AM UTC 24
Finished Oct 12 06:24:23 AM UTC 24
Peak memory 225964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9640854
00 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_nack_acqfull.964085400
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/43.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/43.i2c_target_nack_acqfull_addr.957853858
Short name T1512
Test name
Test status
Simulation time 1025221195 ps
CPU time 4.71 seconds
Started Oct 12 06:24:17 AM UTC 24
Finished Oct 12 06:24:23 AM UTC 24
Peak memory 215484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9578538
58 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_nack_acqfull_addr.957853858
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/43.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/43.i2c_target_perf.39438152
Short name T1496
Test name
Test status
Simulation time 1917065981 ps
CPU time 5.91 seconds
Started Oct 12 06:24:05 AM UTC 24
Finished Oct 12 06:24:12 AM UTC 24
Peak memory 229756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3943815
2 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_perf.39438152
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/43.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/43.i2c_target_smbus_maxlen.3238974331
Short name T1510
Test name
Test status
Simulation time 591347778 ps
CPU time 5.28 seconds
Started Oct 12 06:24:16 AM UTC 24
Finished Oct 12 06:24:22 AM UTC 24
Peak memory 215120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3238974
331 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_smbus_maxlen.3238974331
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/43.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/43.i2c_target_smoke.719918828
Short name T1495
Test name
Test status
Simulation time 7741240814 ps
CPU time 18.78 seconds
Started Oct 12 06:23:48 AM UTC 24
Finished Oct 12 06:24:08 AM UTC 24
Peak memory 225836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=719918828 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_smoke.719918828
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/43.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/43.i2c_target_stress_all.1370823285
Short name T1728
Test name
Test status
Simulation time 23636843043 ps
CPU time 323.52 seconds
Started Oct 12 06:24:05 AM UTC 24
Finished Oct 12 06:29:33 AM UTC 24
Peak memory 3814248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=137082
3285 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_stress_all.1370823285
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/43.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/43.i2c_target_stress_rd.2602363861
Short name T1563
Test name
Test status
Simulation time 9918178959 ps
CPU time 88.99 seconds
Started Oct 12 06:23:51 AM UTC 24
Finished Oct 12 06:25:23 AM UTC 24
Peak memory 231968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2602363861 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_stress_rd.2602363861
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/43.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/43.i2c_target_stress_wr.3949170968
Short name T1547
Test name
Test status
Simulation time 22223904615 ps
CPU time 74.16 seconds
Started Oct 12 06:23:49 AM UTC 24
Finished Oct 12 06:25:05 AM UTC 24
Peak memory 717688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3949170968 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_stress_wr.3949170968
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/43.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/43.i2c_target_stretch.2897483193
Short name T1491
Test name
Test status
Simulation time 3642621601 ps
CPU time 7.2 seconds
Started Oct 12 06:23:55 AM UTC 24
Finished Oct 12 06:24:04 AM UTC 24
Peak memory 232176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2897483193 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_stretch.2897483193
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/43.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/43.i2c_target_timeout.1807317638
Short name T1499
Test name
Test status
Simulation time 7395096121 ps
CPU time 12.16 seconds
Started Oct 12 06:24:01 AM UTC 24
Finished Oct 12 06:24:14 AM UTC 24
Peak memory 232700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1807317
638 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_timeout.1807317638
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/43.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/43.i2c_target_tx_stretch_ctrl.2689566951
Short name T1507
Test name
Test status
Simulation time 70371021 ps
CPU time 3.05 seconds
Started Oct 12 06:24:15 AM UTC 24
Finished Oct 12 06:24:19 AM UTC 24
Peak memory 215468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2689566
951 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_target_tx_stretch_ctrl.2689566951
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/43.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/44.i2c_alert_test.3576244930
Short name T1539
Test name
Test status
Simulation time 17384360 ps
CPU time 0.98 seconds
Started Oct 12 06:24:55 AM UTC 24
Finished Oct 12 06:24:57 AM UTC 24
Peak memory 215628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3576244930 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_alert_test.3576244930
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/44.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/44.i2c_host_error_intr.1726499386
Short name T1519
Test name
Test status
Simulation time 217256105 ps
CPU time 3.6 seconds
Started Oct 12 06:24:27 AM UTC 24
Finished Oct 12 06:24:32 AM UTC 24
Peak memory 225720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1726499386 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 44.i2c_host_error_intr.1726499386
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/44.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/44.i2c_host_fifo_fmt_empty.3452546338
Short name T1520
Test name
Test status
Simulation time 2091974692 ps
CPU time 13.07 seconds
Started Oct 12 06:24:23 AM UTC 24
Finished Oct 12 06:24:37 AM UTC 24
Peak memory 299968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3452546338 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_fmt_empty.3452546338
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/44.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/44.i2c_host_fifo_full.2473454438
Short name T1584
Test name
Test status
Simulation time 2951955978 ps
CPU time 77.03 seconds
Started Oct 12 06:24:24 AM UTC 24
Finished Oct 12 06:25:43 AM UTC 24
Peak memory 531460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2473454438 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_full.2473454438
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/44.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/44.i2c_host_fifo_overflow.1927730481
Short name T1572
Test name
Test status
Simulation time 4296779168 ps
CPU time 68.5 seconds
Started Oct 12 06:24:21 AM UTC 24
Finished Oct 12 06:25:31 AM UTC 24
Peak memory 918484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1927730481 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_overflow.1927730481
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/44.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/44.i2c_host_fifo_reset_fmt.1992869839
Short name T1514
Test name
Test status
Simulation time 1139666064 ps
CPU time 1.47 seconds
Started Oct 12 06:24:22 AM UTC 24
Finished Oct 12 06:24:24 AM UTC 24
Peak memory 213332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1992869839 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_fmt.1992869839
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/44.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/44.i2c_host_fifo_reset_rx.3695987354
Short name T1518
Test name
Test status
Simulation time 185311895 ps
CPU time 7.68 seconds
Started Oct 12 06:24:23 AM UTC 24
Finished Oct 12 06:24:32 AM UTC 24
Peak memory 248704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3695987354 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_rx.3695987354
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/44.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/44.i2c_host_fifo_watermark.2694535433
Short name T1720
Test name
Test status
Simulation time 24296619963 ps
CPU time 250.53 seconds
Started Oct 12 06:24:20 AM UTC 24
Finished Oct 12 06:28:34 AM UTC 24
Peak memory 1242112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2694535433 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_watermark.2694535433
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/44.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/44.i2c_host_may_nack.2045897194
Short name T1555
Test name
Test status
Simulation time 2756013712 ps
CPU time 26.43 seconds
Started Oct 12 06:24:47 AM UTC 24
Finished Oct 12 06:25:15 AM UTC 24
Peak memory 215504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2045897194 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.i2c_host_may_nack.2045897194
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/44.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/44.i2c_host_override.4127648439
Short name T1509
Test name
Test status
Simulation time 28771755 ps
CPU time 1.12 seconds
Started Oct 12 06:24:20 AM UTC 24
Finished Oct 12 06:24:22 AM UTC 24
Peak memory 213212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4127648439 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.i2c_host_override.4127648439
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/44.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/44.i2c_host_perf.1787992750
Short name T1733
Test name
Test status
Simulation time 6970232188 ps
CPU time 359.49 seconds
Started Oct 12 06:24:24 AM UTC 24
Finished Oct 12 06:30:29 AM UTC 24
Peak memory 1328056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1787992750 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 44.i2c_host_perf.1787992750
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/44.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/44.i2c_host_perf_precise.3738849189
Short name T1517
Test name
Test status
Simulation time 229089399 ps
CPU time 3.48 seconds
Started Oct 12 06:24:25 AM UTC 24
Finished Oct 12 06:24:30 AM UTC 24
Peak memory 215516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3738849189 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_perf_precise.3738849189
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/44.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/44.i2c_host_smoke.3738417323
Short name T1552
Test name
Test status
Simulation time 998226299 ps
CPU time 49.62 seconds
Started Oct 12 06:24:19 AM UTC 24
Finished Oct 12 06:25:10 AM UTC 24
Peak memory 298116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3738417323 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.i2c_host_smoke.3738417323
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/44.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/44.i2c_host_stretch_timeout.3088294631
Short name T1521
Test name
Test status
Simulation time 467941326 ps
CPU time 10.76 seconds
Started Oct 12 06:24:26 AM UTC 24
Finished Oct 12 06:24:37 AM UTC 24
Peak memory 232144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3088294631 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_stretch_timeout.3088294631
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/44.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/44.i2c_target_bad_addr.3639593934
Short name T1535
Test name
Test status
Simulation time 4316103755 ps
CPU time 6.94 seconds
Started Oct 12 06:24:46 AM UTC 24
Finished Oct 12 06:24:54 AM UTC 24
Peak memory 227804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=3639593934 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_bad_ad
dr.3639593934
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/44.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/44.i2c_target_fifo_reset_acq.3473215012
Short name T1526
Test name
Test status
Simulation time 1539414115 ps
CPU time 2.57 seconds
Started Oct 12 06:24:40 AM UTC 24
Finished Oct 12 06:24:45 AM UTC 24
Peak memory 215596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3473215
012 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_fifo_reset_acq.3473215012
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/44.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/44.i2c_target_fifo_reset_tx.219229237
Short name T1528
Test name
Test status
Simulation time 326166581 ps
CPU time 2.14 seconds
Started Oct 12 06:24:42 AM UTC 24
Finished Oct 12 06:24:46 AM UTC 24
Peak memory 225632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2192292
37 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_fifo_reset_tx.219229237
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/44.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/44.i2c_target_fifo_watermarks_acq.85180253
Short name T1534
Test name
Test status
Simulation time 364767217 ps
CPU time 4.16 seconds
Started Oct 12 06:24:47 AM UTC 24
Finished Oct 12 06:24:52 AM UTC 24
Peak memory 215584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8518025
3 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_fifo_watermarks
_acq.85180253
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/44.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/44.i2c_target_fifo_watermarks_tx.2651519123
Short name T1533
Test name
Test status
Simulation time 220125108 ps
CPU time 1.13 seconds
Started Oct 12 06:24:50 AM UTC 24
Finished Oct 12 06:24:52 AM UTC 24
Peak memory 213268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2651519
123 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_fifo_watermark
s_tx.2651519123
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/44.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/44.i2c_target_intr_smoke.2138869520
Short name T1524
Test name
Test status
Simulation time 3946529682 ps
CPU time 9.51 seconds
Started Oct 12 06:24:33 AM UTC 24
Finished Oct 12 06:24:44 AM UTC 24
Peak memory 232720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=213886
9520 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_intr_smoke.2138869520
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/44.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/44.i2c_target_intr_stress_wr.769067772
Short name T1529
Test name
Test status
Simulation time 3586361246 ps
CPU time 8.75 seconds
Started Oct 12 06:24:36 AM UTC 24
Finished Oct 12 06:24:46 AM UTC 24
Peak memory 215592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=769067772 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_intr_stress
_wr.769067772
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/44.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/44.i2c_target_nack_acqfull.3491544338
Short name T1543
Test name
Test status
Simulation time 543753857 ps
CPU time 5.46 seconds
Started Oct 12 06:24:52 AM UTC 24
Finished Oct 12 06:24:58 AM UTC 24
Peak memory 225688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3491544
338 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_nack_acqfull.3491544338
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/44.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/44.i2c_target_nack_acqfull_addr.3555980661
Short name T1540
Test name
Test status
Simulation time 2585562464 ps
CPU time 2.81 seconds
Started Oct 12 06:24:54 AM UTC 24
Finished Oct 12 06:24:58 AM UTC 24
Peak memory 215804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3555980
661 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_nack_acqfull_ad
dr.3555980661
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/44.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/44.i2c_target_nack_txstretch.2845852310
Short name T1538
Test name
Test status
Simulation time 138857433 ps
CPU time 2.14 seconds
Started Oct 12 06:24:54 AM UTC 24
Finished Oct 12 06:24:57 AM UTC 24
Peak memory 232584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2845852
310 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_nack_txstretch.2845852310
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/44.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/44.i2c_target_perf.897185068
Short name T1532
Test name
Test status
Simulation time 518576436 ps
CPU time 5.8 seconds
Started Oct 12 06:24:44 AM UTC 24
Finished Oct 12 06:24:51 AM UTC 24
Peak memory 225712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8971850
68 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_perf.897185068
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/44.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/44.i2c_target_smbus_maxlen.797181182
Short name T1537
Test name
Test status
Simulation time 986379557 ps
CPU time 2.83 seconds
Started Oct 12 06:24:51 AM UTC 24
Finished Oct 12 06:24:55 AM UTC 24
Peak memory 215504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7971811
82 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_smbus_maxlen.797181182
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/44.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/44.i2c_target_smoke.3894964417
Short name T1525
Test name
Test status
Simulation time 1560960373 ps
CPU time 14.66 seconds
Started Oct 12 06:24:28 AM UTC 24
Finished Oct 12 06:24:44 AM UTC 24
Peak memory 229724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3894964417 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_smoke.3894964417
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/44.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/44.i2c_target_stress_all.1319494781
Short name T1665
Test name
Test status
Simulation time 46335790368 ps
CPU time 133.08 seconds
Started Oct 12 06:24:45 AM UTC 24
Finished Oct 12 06:27:00 AM UTC 24
Peak memory 1373052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=131949
4781 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_stress_all.1319494781
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/44.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/44.i2c_target_stress_rd.308358611
Short name T1492
Test name
Test status
Simulation time 4672996229 ps
CPU time 49.24 seconds
Started Oct 12 06:24:32 AM UTC 24
Finished Oct 12 06:25:23 AM UTC 24
Peak memory 227820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=308358611 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_stress_rd.308358611
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/44.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/44.i2c_target_stress_wr.6029436
Short name T1737
Test name
Test status
Simulation time 52361310755 ps
CPU time 787.74 seconds
Started Oct 12 06:24:31 AM UTC 24
Finished Oct 12 06:37:46 AM UTC 24
Peak memory 8312012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6029436 -assert nopostproc
+UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_stress_wr.6029436
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/44.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/44.i2c_target_stretch.1734460061
Short name T1522
Test name
Test status
Simulation time 1482696389 ps
CPU time 5.5 seconds
Started Oct 12 06:24:33 AM UTC 24
Finished Oct 12 06:24:40 AM UTC 24
Peak memory 225592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1734460061 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_stretch.1734460061
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/44.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/44.i2c_target_timeout.1623169998
Short name T1530
Test name
Test status
Simulation time 4840721017 ps
CPU time 8.79 seconds
Started Oct 12 06:24:39 AM UTC 24
Finished Oct 12 06:24:49 AM UTC 24
Peak memory 226084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1623169
998 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_timeout.1623169998
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/44.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/44.i2c_target_tx_stretch_ctrl.3168968814
Short name T1536
Test name
Test status
Simulation time 81967490 ps
CPU time 2.8 seconds
Started Oct 12 06:24:51 AM UTC 24
Finished Oct 12 06:24:55 AM UTC 24
Peak memory 215396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3168968
814 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_target_tx_stretch_ctrl.3168968814
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/44.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/45.i2c_alert_test.469300640
Short name T1575
Test name
Test status
Simulation time 18259481 ps
CPU time 0.98 seconds
Started Oct 12 06:25:29 AM UTC 24
Finished Oct 12 06:25:31 AM UTC 24
Peak memory 215628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=469300640 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_alert_test.469300640
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/45.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/45.i2c_host_error_intr.1401436542
Short name T1550
Test name
Test status
Simulation time 834476152 ps
CPU time 2.65 seconds
Started Oct 12 06:25:06 AM UTC 24
Finished Oct 12 06:25:10 AM UTC 24
Peak memory 225796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1401436542 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 45.i2c_host_error_intr.1401436542
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/45.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/45.i2c_host_fifo_fmt_empty.2860799819
Short name T1551
Test name
Test status
Simulation time 746068530 ps
CPU time 9.94 seconds
Started Oct 12 06:24:58 AM UTC 24
Finished Oct 12 06:25:10 AM UTC 24
Peak memory 297788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2860799819 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_fmt_empty.2860799819
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/45.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/45.i2c_host_fifo_full.3232461228
Short name T1620
Test name
Test status
Simulation time 3583422146 ps
CPU time 75.14 seconds
Started Oct 12 06:25:00 AM UTC 24
Finished Oct 12 06:26:17 AM UTC 24
Peak memory 447436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3232461228 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_full.3232461228
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/45.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/45.i2c_host_fifo_overflow.2091191996
Short name T1650
Test name
Test status
Simulation time 3129975646 ps
CPU time 103.59 seconds
Started Oct 12 06:24:58 AM UTC 24
Finished Oct 12 06:26:44 AM UTC 24
Peak memory 605192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2091191996 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_overflow.2091191996
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/45.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/45.i2c_host_fifo_reset_fmt.159529520
Short name T1546
Test name
Test status
Simulation time 442164080 ps
CPU time 1.5 seconds
Started Oct 12 06:24:58 AM UTC 24
Finished Oct 12 06:25:01 AM UTC 24
Peak memory 213272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=159529520 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_fmt.159529520
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/45.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/45.i2c_host_fifo_reset_rx.3022363535
Short name T1548
Test name
Test status
Simulation time 124427511 ps
CPU time 5.27 seconds
Started Oct 12 06:24:59 AM UTC 24
Finished Oct 12 06:25:06 AM UTC 24
Peak memory 236504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3022363535 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_rx.3022363535
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/45.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/45.i2c_host_fifo_watermark.1660786727
Short name T1672
Test name
Test status
Simulation time 2510718453 ps
CPU time 123.21 seconds
Started Oct 12 06:24:58 AM UTC 24
Finished Oct 12 06:27:04 AM UTC 24
Peak memory 814084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1660786727 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_watermark.1660786727
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/45.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/45.i2c_host_may_nack.2038236255
Short name T1582
Test name
Test status
Simulation time 788430306 ps
CPU time 14.39 seconds
Started Oct 12 06:25:23 AM UTC 24
Finished Oct 12 06:25:38 AM UTC 24
Peak memory 215512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2038236255 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.i2c_host_may_nack.2038236255
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/45.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/45.i2c_host_override.1741374384
Short name T1544
Test name
Test status
Simulation time 234165722 ps
CPU time 1.07 seconds
Started Oct 12 06:24:56 AM UTC 24
Finished Oct 12 06:24:58 AM UTC 24
Peak memory 213212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1741374384 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.i2c_host_override.1741374384
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/45.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/45.i2c_host_perf.2334247910
Short name T1731
Test name
Test status
Simulation time 7418913425 ps
CPU time 319.82 seconds
Started Oct 12 06:25:00 AM UTC 24
Finished Oct 12 06:30:24 AM UTC 24
Peak memory 625728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2334247910 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 45.i2c_host_perf.2334247910
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/45.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/45.i2c_host_perf_precise.1623716329
Short name T1554
Test name
Test status
Simulation time 7249302847 ps
CPU time 11.62 seconds
Started Oct 12 06:25:01 AM UTC 24
Finished Oct 12 06:25:14 AM UTC 24
Peak memory 226084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1623716329 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_perf_precise.1623716329
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/45.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/45.i2c_host_smoke.435755767
Short name T1631
Test name
Test status
Simulation time 1877971090 ps
CPU time 93.92 seconds
Started Oct 12 06:24:56 AM UTC 24
Finished Oct 12 06:26:32 AM UTC 24
Peak memory 478464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=435755767 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 45.i2c_host_smoke.435755767
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/45.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/45.i2c_host_stretch_timeout.3077557081
Short name T1578
Test name
Test status
Simulation time 1180149759 ps
CPU time 29.32 seconds
Started Oct 12 06:25:02 AM UTC 24
Finished Oct 12 06:25:33 AM UTC 24
Peak memory 225760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3077557081 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_stretch_timeout.3077557081
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/45.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/45.i2c_target_bad_addr.4072651089
Short name T1571
Test name
Test status
Simulation time 6456119067 ps
CPU time 9.12 seconds
Started Oct 12 06:25:20 AM UTC 24
Finished Oct 12 06:25:30 AM UTC 24
Peak memory 227804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=4072651089 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_bad_ad
dr.4072651089
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/45.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/45.i2c_target_fifo_reset_acq.2046067944
Short name T1561
Test name
Test status
Simulation time 237729842 ps
CPU time 2.28 seconds
Started Oct 12 06:25:18 AM UTC 24
Finished Oct 12 06:25:21 AM UTC 24
Peak memory 215516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2046067
944 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_fifo_reset_acq.2046067944
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/45.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/45.i2c_target_fifo_reset_tx.2433808243
Short name T1562
Test name
Test status
Simulation time 511251279 ps
CPU time 1.37 seconds
Started Oct 12 06:25:19 AM UTC 24
Finished Oct 12 06:25:21 AM UTC 24
Peak memory 227480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2433808
243 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_fifo_reset_tx.2433808243
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/45.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/45.i2c_target_fifo_watermarks_acq.2134223253
Short name T1568
Test name
Test status
Simulation time 483630455 ps
CPU time 4.28 seconds
Started Oct 12 06:25:24 AM UTC 24
Finished Oct 12 06:25:29 AM UTC 24
Peak memory 215512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2134223
253 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_fifo_watermar
ks_acq.2134223253
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/45.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/45.i2c_target_fifo_watermarks_tx.240352850
Short name T1564
Test name
Test status
Simulation time 213701876 ps
CPU time 1.96 seconds
Started Oct 12 06:25:24 AM UTC 24
Finished Oct 12 06:25:27 AM UTC 24
Peak memory 215636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2403528
50 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_fifo_watermarks
_tx.240352850
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/45.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/45.i2c_target_hrst.2811310357
Short name T1497
Test name
Test status
Simulation time 260617507 ps
CPU time 3.32 seconds
Started Oct 12 06:25:20 AM UTC 24
Finished Oct 12 06:25:25 AM UTC 24
Peak memory 225636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2811310
357 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_hrst.2811310357
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/45.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/45.i2c_target_intr_smoke.2659641631
Short name T1560
Test name
Test status
Simulation time 903233227 ps
CPU time 6.03 seconds
Started Oct 12 06:25:13 AM UTC 24
Finished Oct 12 06:25:20 AM UTC 24
Peak memory 232296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=265964
1631 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_intr_smoke.2659641631
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/45.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/45.i2c_target_intr_stress_wr.2556734142
Short name T1559
Test name
Test status
Simulation time 739977590 ps
CPU time 3.51 seconds
Started Oct 12 06:25:15 AM UTC 24
Finished Oct 12 06:25:19 AM UTC 24
Peak memory 215572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2556734142 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_intr_stres
s_wr.2556734142
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/45.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/45.i2c_target_nack_acqfull.1041783272
Short name T1579
Test name
Test status
Simulation time 845211946 ps
CPU time 3.45 seconds
Started Oct 12 06:25:28 AM UTC 24
Finished Oct 12 06:25:33 AM UTC 24
Peak memory 225624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1041783
272 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_nack_acqfull.1041783272
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/45.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/45.i2c_target_nack_acqfull_addr.2009829490
Short name T1580
Test name
Test status
Simulation time 545358499 ps
CPU time 4.2 seconds
Started Oct 12 06:25:28 AM UTC 24
Finished Oct 12 06:25:34 AM UTC 24
Peak memory 215420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2009829
490 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_nack_acqfull_ad
dr.2009829490
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/45.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/45.i2c_target_nack_txstretch.3270135237
Short name T1576
Test name
Test status
Simulation time 349203064 ps
CPU time 2.13 seconds
Started Oct 12 06:25:28 AM UTC 24
Finished Oct 12 06:25:32 AM UTC 24
Peak memory 232716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3270135
237 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_nack_txstretch.3270135237
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/45.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/45.i2c_target_perf.904016284
Short name T1567
Test name
Test status
Simulation time 2344659001 ps
CPU time 6.9 seconds
Started Oct 12 06:25:20 AM UTC 24
Finished Oct 12 06:25:28 AM UTC 24
Peak memory 232528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9040162
84 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_perf.904016284
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/45.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/45.i2c_target_smbus_maxlen.2744996325
Short name T1574
Test name
Test status
Simulation time 1715675423 ps
CPU time 2.36 seconds
Started Oct 12 06:25:28 AM UTC 24
Finished Oct 12 06:25:31 AM UTC 24
Peak memory 214968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2744996
325 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_smbus_maxlen.2744996325
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/45.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/45.i2c_target_smoke.3417714590
Short name T1570
Test name
Test status
Simulation time 1120699108 ps
CPU time 19.88 seconds
Started Oct 12 06:25:09 AM UTC 24
Finished Oct 12 06:25:30 AM UTC 24
Peak memory 225768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3417714590 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_smoke.3417714590
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/45.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/45.i2c_target_stress_all.994553159
Short name T1736
Test name
Test status
Simulation time 53049427348 ps
CPU time 666.1 seconds
Started Oct 12 06:25:20 AM UTC 24
Finished Oct 12 06:36:33 AM UTC 24
Peak memory 7015440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=994553
159 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_stress_all.994553159
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/45.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/45.i2c_target_stress_rd.3049743871
Short name T1587
Test name
Test status
Simulation time 14137438007 ps
CPU time 34.57 seconds
Started Oct 12 06:25:10 AM UTC 24
Finished Oct 12 06:25:46 AM UTC 24
Peak memory 249028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3049743871 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_stress_rd.3049743871
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/45.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/45.i2c_target_stress_wr.2387682298
Short name T1637
Test name
Test status
Simulation time 30034122908 ps
CPU time 84.61 seconds
Started Oct 12 06:25:10 AM UTC 24
Finished Oct 12 06:26:37 AM UTC 24
Peak memory 1377468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2387682298 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_stress_wr.2387682298
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/45.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/45.i2c_target_stretch.3744755840
Short name T1558
Test name
Test status
Simulation time 4679505758 ps
CPU time 7.66 seconds
Started Oct 12 06:25:10 AM UTC 24
Finished Oct 12 06:25:19 AM UTC 24
Peak memory 265424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3744755840 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_stretch.3744755840
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/45.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/45.i2c_target_timeout.468571913
Short name T1565
Test name
Test status
Simulation time 2270705701 ps
CPU time 11.05 seconds
Started Oct 12 06:25:15 AM UTC 24
Finished Oct 12 06:25:27 AM UTC 24
Peak memory 226208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4685719
13 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_timeout.468571913
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/45.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/45.i2c_target_tx_stretch_ctrl.1153770030
Short name T1569
Test name
Test status
Simulation time 90859053 ps
CPU time 2.92 seconds
Started Oct 12 06:25:26 AM UTC 24
Finished Oct 12 06:25:30 AM UTC 24
Peak memory 215724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1153770
030 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_target_tx_stretch_ctrl.1153770030
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/45.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/46.i2c_alert_test.316744306
Short name T1604
Test name
Test status
Simulation time 41049962 ps
CPU time 1.01 seconds
Started Oct 12 06:25:57 AM UTC 24
Finished Oct 12 06:25:59 AM UTC 24
Peak memory 215628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=316744306 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_alert_test.316744306
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/46.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/46.i2c_host_error_intr.448095860
Short name T1583
Test name
Test status
Simulation time 222726893 ps
CPU time 2.94 seconds
Started Oct 12 06:25:34 AM UTC 24
Finished Oct 12 06:25:38 AM UTC 24
Peak memory 225788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=448095860 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 46.i2c_host_error_intr.448095860
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/46.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_fmt_empty.312589736
Short name T1585
Test name
Test status
Simulation time 1465842790 ps
CPU time 9.51 seconds
Started Oct 12 06:25:33 AM UTC 24
Finished Oct 12 06:25:44 AM UTC 24
Peak memory 299840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=312589736 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_fmt_empty.312589736
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/46.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_full.2840404644
Short name T1724
Test name
Test status
Simulation time 21118474366 ps
CPU time 212.24 seconds
Started Oct 12 06:25:33 AM UTC 24
Finished Oct 12 06:29:09 AM UTC 24
Peak memory 619376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2840404644 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_full.2840404644
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/46.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_overflow.2825785044
Short name T1647
Test name
Test status
Simulation time 31456358505 ps
CPU time 69.35 seconds
Started Oct 12 06:25:32 AM UTC 24
Finished Oct 12 06:26:43 AM UTC 24
Peak memory 859344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2825785044 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_overflow.2825785044
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/46.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_reset_fmt.25243359
Short name T1581
Test name
Test status
Simulation time 152642038 ps
CPU time 1.28 seconds
Started Oct 12 06:25:32 AM UTC 24
Finished Oct 12 06:25:34 AM UTC 24
Peak memory 213332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=25243359 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_fmt.25243359
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/46.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_reset_rx.34404728
Short name T1586
Test name
Test status
Simulation time 172077057 ps
CPU time 11.55 seconds
Started Oct 12 06:25:33 AM UTC 24
Finished Oct 12 06:25:46 AM UTC 24
Peak memory 244672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=34404728 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_rx.34404728
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/46.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_watermark.4194655054
Short name T1713
Test name
Test status
Simulation time 21943534518 ps
CPU time 127.91 seconds
Started Oct 12 06:25:32 AM UTC 24
Finished Oct 12 06:27:42 AM UTC 24
Peak memory 1608712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4194655054 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_watermark.4194655054
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/46.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/46.i2c_host_may_nack.2757458305
Short name T1606
Test name
Test status
Simulation time 469983263 ps
CPU time 7.92 seconds
Started Oct 12 06:25:51 AM UTC 24
Finished Oct 12 06:26:00 AM UTC 24
Peak memory 215768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2757458305 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.i2c_host_may_nack.2757458305
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/46.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/46.i2c_host_override.1785416616
Short name T1577
Test name
Test status
Simulation time 15247876 ps
CPU time 0.99 seconds
Started Oct 12 06:25:31 AM UTC 24
Finished Oct 12 06:25:33 AM UTC 24
Peak memory 213212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1785416616 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.i2c_host_override.1785416616
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/46.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/46.i2c_host_perf.670590507
Short name T1735
Test name
Test status
Simulation time 12795451009 ps
CPU time 433.43 seconds
Started Oct 12 06:25:33 AM UTC 24
Finished Oct 12 06:32:52 AM UTC 24
Peak memory 2829236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=670590507 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 46.i2c_host_perf.670590507
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/46.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/46.i2c_host_perf_precise.1449058938
Short name T1646
Test name
Test status
Simulation time 5865289042 ps
CPU time 67.51 seconds
Started Oct 12 06:25:33 AM UTC 24
Finished Oct 12 06:26:43 AM UTC 24
Peak memory 215720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1449058938 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_perf_precise.1449058938
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/46.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/46.i2c_host_smoke.1965511676
Short name T1594
Test name
Test status
Simulation time 5714979448 ps
CPU time 22.43 seconds
Started Oct 12 06:25:29 AM UTC 24
Finished Oct 12 06:25:53 AM UTC 24
Peak memory 400252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1965511676 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 46.i2c_host_smoke.1965511676
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/46.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/46.i2c_host_stretch_timeout.3762690116
Short name T1589
Test name
Test status
Simulation time 1213107530 ps
CPU time 11.52 seconds
Started Oct 12 06:25:34 AM UTC 24
Finished Oct 12 06:25:47 AM UTC 24
Peak memory 227872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3762690116 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_stretch_timeout.3762690116
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/46.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/46.i2c_target_bad_addr.2789298923
Short name T1599
Test name
Test status
Simulation time 2306442236 ps
CPU time 5.58 seconds
Started Oct 12 06:25:49 AM UTC 24
Finished Oct 12 06:25:55 AM UTC 24
Peak memory 230156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=2789298923 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_bad_ad
dr.2789298923
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/46.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/46.i2c_target_fifo_reset_acq.1842202271
Short name T1592
Test name
Test status
Simulation time 243599684 ps
CPU time 1.26 seconds
Started Oct 12 06:25:47 AM UTC 24
Finished Oct 12 06:25:50 AM UTC 24
Peak memory 215576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1842202
271 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_fifo_reset_acq.1842202271
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/46.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/46.i2c_target_fifo_reset_tx.3635727177
Short name T1593
Test name
Test status
Simulation time 578652733 ps
CPU time 2.02 seconds
Started Oct 12 06:25:47 AM UTC 24
Finished Oct 12 06:25:50 AM UTC 24
Peak memory 217520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3635727
177 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_fifo_reset_tx.3635727177
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/46.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/46.i2c_target_fifo_watermarks_acq.976628996
Short name T1603
Test name
Test status
Simulation time 793187060 ps
CPU time 2.73 seconds
Started Oct 12 06:25:54 AM UTC 24
Finished Oct 12 06:25:58 AM UTC 24
Peak memory 215248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9766289
96 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_fifo_watermark
s_acq.976628996
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/46.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/46.i2c_target_fifo_watermarks_tx.2847992633
Short name T1602
Test name
Test status
Simulation time 115643256 ps
CPU time 1.76 seconds
Started Oct 12 06:25:54 AM UTC 24
Finished Oct 12 06:25:57 AM UTC 24
Peak memory 215632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2847992
633 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_fifo_watermark
s_tx.2847992633
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/46.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/46.i2c_target_hrst.2553428657
Short name T1597
Test name
Test status
Simulation time 381429108 ps
CPU time 3.28 seconds
Started Oct 12 06:25:50 AM UTC 24
Finished Oct 12 06:25:54 AM UTC 24
Peak memory 225964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2553428
657 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_hrst.2553428657
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/46.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/46.i2c_target_intr_smoke.2653785077
Short name T1595
Test name
Test status
Simulation time 4396589862 ps
CPU time 10.48 seconds
Started Oct 12 06:25:42 AM UTC 24
Finished Oct 12 06:25:54 AM UTC 24
Peak memory 226032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=265378
5077 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_intr_smoke.2653785077
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/46.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/46.i2c_target_intr_stress_wr.840199942
Short name T1639
Test name
Test status
Simulation time 19102670562 ps
CPU time 53.55 seconds
Started Oct 12 06:25:44 AM UTC 24
Finished Oct 12 06:26:39 AM UTC 24
Peak memory 1223892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=840199942 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_intr_stress
_wr.840199942
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/46.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/46.i2c_target_nack_acqfull.1783001435
Short name T1605
Test name
Test status
Simulation time 558794587 ps
CPU time 3.09 seconds
Started Oct 12 06:25:55 AM UTC 24
Finished Oct 12 06:26:00 AM UTC 24
Peak memory 225968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1783001
435 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_nack_acqfull.1783001435
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/46.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/46.i2c_target_nack_acqfull_addr.339509493
Short name T1612
Test name
Test status
Simulation time 2025340653 ps
CPU time 4.75 seconds
Started Oct 12 06:25:57 AM UTC 24
Finished Oct 12 06:26:02 AM UTC 24
Peak memory 215412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3395094
93 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_nack_acqfull_addr.339509493
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/46.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/46.i2c_target_perf.108785389
Short name T1598
Test name
Test status
Simulation time 1157743435 ps
CPU time 5.49 seconds
Started Oct 12 06:25:49 AM UTC 24
Finished Oct 12 06:25:55 AM UTC 24
Peak memory 232080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1087853
89 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_perf.108785389
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/46.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/46.i2c_target_smbus_maxlen.1558446101
Short name T1607
Test name
Test status
Simulation time 1882299948 ps
CPU time 3.56 seconds
Started Oct 12 06:25:55 AM UTC 24
Finished Oct 12 06:26:00 AM UTC 24
Peak memory 215176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1558446
101 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_smbus_maxlen.1558446101
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/46.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/46.i2c_target_smoke.2967596484
Short name T1588
Test name
Test status
Simulation time 6858739339 ps
CPU time 9.97 seconds
Started Oct 12 06:25:36 AM UTC 24
Finished Oct 12 06:25:47 AM UTC 24
Peak memory 226216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2967596484 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_smoke.2967596484
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/46.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/46.i2c_target_stress_all.895179947
Short name T1653
Test name
Test status
Simulation time 65440950470 ps
CPU time 59.16 seconds
Started Oct 12 06:25:49 AM UTC 24
Finished Oct 12 06:26:49 AM UTC 24
Peak memory 527296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=895179
947 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_stress_all.895179947
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/46.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/46.i2c_target_stress_rd.1346997528
Short name T1591
Test name
Test status
Simulation time 737953396 ps
CPU time 8.29 seconds
Started Oct 12 06:25:39 AM UTC 24
Finished Oct 12 06:25:48 AM UTC 24
Peak memory 232084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1346997528 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_stress_rd.1346997528
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/46.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/46.i2c_target_stress_wr.1909564181
Short name T1628
Test name
Test status
Simulation time 35973794863 ps
CPU time 52.77 seconds
Started Oct 12 06:25:37 AM UTC 24
Finished Oct 12 06:26:31 AM UTC 24
Peak memory 1094520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1909564181 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_stress_wr.1909564181
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/46.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/46.i2c_target_stretch.1085242439
Short name T1617
Test name
Test status
Simulation time 2708539927 ps
CPU time 29.84 seconds
Started Oct 12 06:25:39 AM UTC 24
Finished Oct 12 06:26:10 AM UTC 24
Peak memory 588976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1085242439 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_stretch.1085242439
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/46.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/46.i2c_target_timeout.1949857316
Short name T1596
Test name
Test status
Simulation time 2855352136 ps
CPU time 7.78 seconds
Started Oct 12 06:25:45 AM UTC 24
Finished Oct 12 06:25:54 AM UTC 24
Peak memory 231964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1949857
316 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_timeout.1949857316
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/46.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/46.i2c_target_tx_stretch_ctrl.1234800721
Short name T1609
Test name
Test status
Simulation time 135176233 ps
CPU time 4.04 seconds
Started Oct 12 06:25:55 AM UTC 24
Finished Oct 12 06:26:00 AM UTC 24
Peak memory 215720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1234800
721 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_target_tx_stretch_ctrl.1234800721
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/46.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/47.i2c_alert_test.794815223
Short name T1640
Test name
Test status
Simulation time 49439099 ps
CPU time 1.02 seconds
Started Oct 12 06:26:37 AM UTC 24
Finished Oct 12 06:26:39 AM UTC 24
Peak memory 215628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=794815223 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_alert_test.794815223
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/47.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/47.i2c_host_error_intr.3304164218
Short name T1614
Test name
Test status
Simulation time 355649891 ps
CPU time 2.03 seconds
Started Oct 12 06:26:03 AM UTC 24
Finished Oct 12 06:26:06 AM UTC 24
Peak memory 225968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3304164218 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 47.i2c_host_error_intr.3304164218
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/47.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_fmt_empty.2313546864
Short name T1618
Test name
Test status
Simulation time 621209456 ps
CPU time 8.78 seconds
Started Oct 12 06:26:01 AM UTC 24
Finished Oct 12 06:26:11 AM UTC 24
Peak memory 277752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2313546864 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_fmt_empty.2313546864
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/47.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_full.4011745331
Short name T1689
Test name
Test status
Simulation time 12366388344 ps
CPU time 77.67 seconds
Started Oct 12 06:26:02 AM UTC 24
Finished Oct 12 06:27:21 AM UTC 24
Peak memory 447496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4011745331 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_full.4011745331
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/47.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_overflow.1885042608
Short name T1661
Test name
Test status
Simulation time 8832342015 ps
CPU time 56.94 seconds
Started Oct 12 06:25:59 AM UTC 24
Finished Oct 12 06:26:58 AM UTC 24
Peak memory 781268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1885042608 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_overflow.1885042608
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/47.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_reset_fmt.866406317
Short name T1613
Test name
Test status
Simulation time 189127758 ps
CPU time 1.6 seconds
Started Oct 12 06:26:00 AM UTC 24
Finished Oct 12 06:26:03 AM UTC 24
Peak memory 213332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=866406317 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_fmt.866406317
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/47.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_reset_rx.2681846736
Short name T1616
Test name
Test status
Simulation time 138967827 ps
CPU time 5.64 seconds
Started Oct 12 06:26:02 AM UTC 24
Finished Oct 12 06:26:08 AM UTC 24
Peak memory 236408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2681846736 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_rx.2681846736
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/47.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_watermark.2952443814
Short name T1710
Test name
Test status
Simulation time 14932191031 ps
CPU time 99.02 seconds
Started Oct 12 06:25:59 AM UTC 24
Finished Oct 12 06:27:40 AM UTC 24
Peak memory 1129392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2952443814 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_watermark.2952443814
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/47.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/47.i2c_host_may_nack.4283163043
Short name T1645
Test name
Test status
Simulation time 2458273328 ps
CPU time 9.45 seconds
Started Oct 12 06:26:32 AM UTC 24
Finished Oct 12 06:26:42 AM UTC 24
Peak memory 215832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4283163043 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.i2c_host_may_nack.4283163043
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/47.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/47.i2c_host_override.2858333064
Short name T1608
Test name
Test status
Simulation time 18396230 ps
CPU time 1.06 seconds
Started Oct 12 06:25:58 AM UTC 24
Finished Oct 12 06:26:00 AM UTC 24
Peak memory 213212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2858333064 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.i2c_host_override.2858333064
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/47.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/47.i2c_host_perf.3037000417
Short name T1730
Test name
Test status
Simulation time 24941999710 ps
CPU time 241.65 seconds
Started Oct 12 06:26:02 AM UTC 24
Finished Oct 12 06:30:07 AM UTC 24
Peak memory 283584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3037000417 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 47.i2c_host_perf.3037000417
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/47.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/47.i2c_host_perf_precise.1753408059
Short name T1651
Test name
Test status
Simulation time 2593229890 ps
CPU time 43.35 seconds
Started Oct 12 06:26:02 AM UTC 24
Finished Oct 12 06:26:46 AM UTC 24
Peak memory 615224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1753408059 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_perf_precise.1753408059
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/47.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/47.i2c_host_smoke.1839376330
Short name T1623
Test name
Test status
Simulation time 1146185314 ps
CPU time 23.33 seconds
Started Oct 12 06:25:57 AM UTC 24
Finished Oct 12 06:26:21 AM UTC 24
Peak memory 347136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1839376330 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.i2c_host_smoke.1839376330
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/47.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/47.i2c_host_stress_all.3808134224
Short name T279
Test name
Test status
Simulation time 101756640789 ps
CPU time 1504.12 seconds
Started Oct 12 06:26:04 AM UTC 24
Finished Oct 12 06:51:25 AM UTC 24
Peak memory 3109900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3808134224 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 47.i2c_host_stress_all.3808134224
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/47.i2c_host_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/47.i2c_host_stretch_timeout.668341371
Short name T1621
Test name
Test status
Simulation time 787238989 ps
CPU time 14.71 seconds
Started Oct 12 06:26:02 AM UTC 24
Finished Oct 12 06:26:18 AM UTC 24
Peak memory 232048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=668341371 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_stretch_timeout.668341371
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/47.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/47.i2c_target_bad_addr.3365821821
Short name T1633
Test name
Test status
Simulation time 4831486568 ps
CPU time 7.27 seconds
Started Oct 12 06:26:26 AM UTC 24
Finished Oct 12 06:26:35 AM UTC 24
Peak memory 229852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=3365821821 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_bad_ad
dr.3365821821
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/47.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/47.i2c_target_fifo_reset_acq.2326242925
Short name T1624
Test name
Test status
Simulation time 1117373739 ps
CPU time 2.18 seconds
Started Oct 12 06:26:20 AM UTC 24
Finished Oct 12 06:26:23 AM UTC 24
Peak memory 215728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2326242
925 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_fifo_reset_acq.2326242925
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/47.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/47.i2c_target_fifo_reset_tx.2277082331
Short name T1625
Test name
Test status
Simulation time 200274331 ps
CPU time 1.52 seconds
Started Oct 12 06:26:22 AM UTC 24
Finished Oct 12 06:26:25 AM UTC 24
Peak memory 215576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2277082
331 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_fifo_reset_tx.2277082331
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/47.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/47.i2c_target_fifo_watermarks_acq.741644200
Short name T1632
Test name
Test status
Simulation time 193865771 ps
CPU time 2.46 seconds
Started Oct 12 06:26:32 AM UTC 24
Finished Oct 12 06:26:35 AM UTC 24
Peak memory 215504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7416442
00 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_fifo_watermark
s_acq.741644200
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/47.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/47.i2c_target_fifo_watermarks_tx.1084720376
Short name T1634
Test name
Test status
Simulation time 374554525 ps
CPU time 1.66 seconds
Started Oct 12 06:26:33 AM UTC 24
Finished Oct 12 06:26:35 AM UTC 24
Peak memory 213628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1084720
376 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_fifo_watermark
s_tx.1084720376
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/47.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/47.i2c_target_intr_smoke.406545440
Short name T1622
Test name
Test status
Simulation time 5193395797 ps
CPU time 5.64 seconds
Started Oct 12 06:26:12 AM UTC 24
Finished Oct 12 06:26:19 AM UTC 24
Peak memory 232316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=406545
440 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_intr_smoke.406545440
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/47.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/47.i2c_target_intr_stress_wr.3583858199
Short name T1630
Test name
Test status
Simulation time 9644384067 ps
CPU time 17.73 seconds
Started Oct 12 06:26:13 AM UTC 24
Finished Oct 12 06:26:31 AM UTC 24
Peak memory 423044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3583858199 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_intr_stres
s_wr.3583858199
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/47.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/47.i2c_target_nack_acqfull.1833455713
Short name T1642
Test name
Test status
Simulation time 515781451 ps
CPU time 3.56 seconds
Started Oct 12 06:26:36 AM UTC 24
Finished Oct 12 06:26:41 AM UTC 24
Peak memory 225548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1833455
713 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_nack_acqfull.1833455713
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/47.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/47.i2c_target_nack_acqfull_addr.2451886240
Short name T1643
Test name
Test status
Simulation time 516405266 ps
CPU time 4.1 seconds
Started Oct 12 06:26:36 AM UTC 24
Finished Oct 12 06:26:41 AM UTC 24
Peak memory 215700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2451886
240 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_nack_acqfull_ad
dr.2451886240
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/47.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/47.i2c_target_perf.1496740612
Short name T1626
Test name
Test status
Simulation time 8038925880 ps
CPU time 3.85 seconds
Started Oct 12 06:26:23 AM UTC 24
Finished Oct 12 06:26:28 AM UTC 24
Peak memory 232384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1496740
612 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_perf.1496740612
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/47.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/47.i2c_target_smbus_maxlen.210637453
Short name T1638
Test name
Test status
Simulation time 539629121 ps
CPU time 2.85 seconds
Started Oct 12 06:26:34 AM UTC 24
Finished Oct 12 06:26:38 AM UTC 24
Peak memory 215168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2106374
53 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_smbus_maxlen.210637453
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/47.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/47.i2c_target_smoke.1787332943
Short name T1629
Test name
Test status
Simulation time 596723553 ps
CPU time 22.91 seconds
Started Oct 12 06:26:07 AM UTC 24
Finished Oct 12 06:26:31 AM UTC 24
Peak memory 225968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1787332943 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_smoke.1787332943
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/47.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/47.i2c_target_stress_all.412703499
Short name T1732
Test name
Test status
Simulation time 74667049536 ps
CPU time 239.04 seconds
Started Oct 12 06:26:24 AM UTC 24
Finished Oct 12 06:30:26 AM UTC 24
Peak memory 2161608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=412703
499 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_stress_all.412703499
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/47.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/47.i2c_target_stress_rd.399406397
Short name T1636
Test name
Test status
Simulation time 423291490 ps
CPU time 26.08 seconds
Started Oct 12 06:26:09 AM UTC 24
Finished Oct 12 06:26:37 AM UTC 24
Peak memory 226020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=399406397 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_stress_rd.399406397
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/47.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/47.i2c_target_stress_wr.4187040397
Short name T1723
Test name
Test status
Simulation time 40349881728 ps
CPU time 170.66 seconds
Started Oct 12 06:26:09 AM UTC 24
Finished Oct 12 06:29:03 AM UTC 24
Peak memory 2608384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4187040397 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_stress_wr.4187040397
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/47.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/47.i2c_target_stretch.1593920104
Short name T1644
Test name
Test status
Simulation time 1892733638 ps
CPU time 29 seconds
Started Oct 12 06:26:11 AM UTC 24
Finished Oct 12 06:26:42 AM UTC 24
Peak memory 631812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1593920104 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_stretch.1593920104
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/47.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/47.i2c_target_timeout.1861328094
Short name T1627
Test name
Test status
Simulation time 1408198108 ps
CPU time 10.69 seconds
Started Oct 12 06:26:18 AM UTC 24
Finished Oct 12 06:26:30 AM UTC 24
Peak memory 232536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1861328
094 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_timeout.1861328094
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/47.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/47.i2c_target_tx_stretch_ctrl.2132974466
Short name T1635
Test name
Test status
Simulation time 67634217 ps
CPU time 2 seconds
Started Oct 12 06:26:33 AM UTC 24
Finished Oct 12 06:26:36 AM UTC 24
Peak memory 215532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2132974
466 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_target_tx_stretch_ctrl.2132974466
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/47.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/48.i2c_alert_test.470661471
Short name T1673
Test name
Test status
Simulation time 16392145 ps
CPU time 0.97 seconds
Started Oct 12 06:27:03 AM UTC 24
Finished Oct 12 06:27:04 AM UTC 24
Peak memory 215628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=470661471 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_alert_test.470661471
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/48.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/48.i2c_host_error_intr.2301360288
Short name T1654
Test name
Test status
Simulation time 135426351 ps
CPU time 5.11 seconds
Started Oct 12 06:26:44 AM UTC 24
Finished Oct 12 06:26:50 AM UTC 24
Peak memory 232052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2301360288 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 48.i2c_host_error_intr.2301360288
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/48.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_fmt_empty.884337685
Short name T1659
Test name
Test status
Simulation time 1066775539 ps
CPU time 12.95 seconds
Started Oct 12 06:26:41 AM UTC 24
Finished Oct 12 06:26:55 AM UTC 24
Peak memory 338872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=884337685 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_fmt_empty.884337685
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/48.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_full.2838767177
Short name T1722
Test name
Test status
Simulation time 3221194632 ps
CPU time 132.8 seconds
Started Oct 12 06:26:41 AM UTC 24
Finished Oct 12 06:28:56 AM UTC 24
Peak memory 554240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2838767177 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_full.2838767177
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/48.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_overflow.766671975
Short name T1690
Test name
Test status
Simulation time 2754671767 ps
CPU time 41.55 seconds
Started Oct 12 06:26:41 AM UTC 24
Finished Oct 12 06:27:24 AM UTC 24
Peak memory 486360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=766671975 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_overflow.766671975
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/48.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_reset_fmt.3790618561
Short name T1648
Test name
Test status
Simulation time 346113873 ps
CPU time 1.75 seconds
Started Oct 12 06:26:41 AM UTC 24
Finished Oct 12 06:26:44 AM UTC 24
Peak memory 213332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3790618561 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_fmt.3790618561
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/48.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_reset_rx.71895554
Short name T1652
Test name
Test status
Simulation time 606635995 ps
CPU time 5.22 seconds
Started Oct 12 06:26:41 AM UTC 24
Finished Oct 12 06:26:47 AM UTC 24
Peak memory 240528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=71895554 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_rx.71895554
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/48.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_watermark.3342493687
Short name T1721
Test name
Test status
Simulation time 41467313137 ps
CPU time 128.52 seconds
Started Oct 12 06:26:39 AM UTC 24
Finished Oct 12 06:28:50 AM UTC 24
Peak memory 1428332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3342493687 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_watermark.3342493687
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/48.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/48.i2c_host_may_nack.3028061958
Short name T1679
Test name
Test status
Simulation time 5461838398 ps
CPU time 6.73 seconds
Started Oct 12 06:26:58 AM UTC 24
Finished Oct 12 06:27:06 AM UTC 24
Peak memory 215832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3028061958 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.i2c_host_may_nack.3028061958
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/48.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/48.i2c_host_mode_toggle.3819830054
Short name T1666
Test name
Test status
Simulation time 423458794 ps
CPU time 2.89 seconds
Started Oct 12 06:26:57 AM UTC 24
Finished Oct 12 06:27:00 AM UTC 24
Peak memory 215388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3819830054 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_mode_toggle.3819830054
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/48.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/48.i2c_host_override.2521511739
Short name T1590
Test name
Test status
Simulation time 25258638 ps
CPU time 1.15 seconds
Started Oct 12 06:26:38 AM UTC 24
Finished Oct 12 06:26:40 AM UTC 24
Peak memory 213212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2521511739 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.i2c_host_override.2521511739
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/48.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/48.i2c_host_perf.4273792561
Short name T1734
Test name
Test status
Simulation time 6594899987 ps
CPU time 362.18 seconds
Started Oct 12 06:26:42 AM UTC 24
Finished Oct 12 06:32:50 AM UTC 24
Peak memory 1627068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4273792561 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 48.i2c_host_perf.4273792561
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/48.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/48.i2c_host_perf_precise.331358838
Short name T1686
Test name
Test status
Simulation time 6138872012 ps
CPU time 31.67 seconds
Started Oct 12 06:26:42 AM UTC 24
Finished Oct 12 06:27:16 AM UTC 24
Peak memory 578372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=331358838 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_perf_precise.331358838
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/48.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/48.i2c_host_smoke.1839626870
Short name T1663
Test name
Test status
Simulation time 1467552853 ps
CPU time 20.34 seconds
Started Oct 12 06:26:37 AM UTC 24
Finished Oct 12 06:26:59 AM UTC 24
Peak memory 351116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1839626870 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.i2c_host_smoke.1839626870
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/48.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/48.i2c_host_stretch_timeout.2932255525
Short name T1664
Test name
Test status
Simulation time 3885554204 ps
CPU time 15.35 seconds
Started Oct 12 06:26:42 AM UTC 24
Finished Oct 12 06:26:59 AM UTC 24
Peak memory 227880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2932255525 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_stretch_timeout.2932255525
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/48.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/48.i2c_target_bad_addr.2876209940
Short name T1667
Test name
Test status
Simulation time 615736097 ps
CPU time 3.94 seconds
Started Oct 12 06:26:56 AM UTC 24
Finished Oct 12 06:27:01 AM UTC 24
Peak memory 217500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=2876209940 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_bad_ad
dr.2876209940
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/48.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/48.i2c_target_fifo_reset_acq.2859975675
Short name T1657
Test name
Test status
Simulation time 618581661 ps
CPU time 2.14 seconds
Started Oct 12 06:26:52 AM UTC 24
Finished Oct 12 06:26:55 AM UTC 24
Peak memory 225712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2859975
675 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_fifo_reset_acq.2859975675
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/48.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/48.i2c_target_fifo_reset_tx.2255232407
Short name T1658
Test name
Test status
Simulation time 506314902 ps
CPU time 1.42 seconds
Started Oct 12 06:26:53 AM UTC 24
Finished Oct 12 06:26:55 AM UTC 24
Peak memory 215576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2255232
407 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_fifo_reset_tx.2255232407
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/48.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/48.i2c_target_fifo_watermarks_acq.358078685
Short name T1674
Test name
Test status
Simulation time 1557573749 ps
CPU time 5.17 seconds
Started Oct 12 06:26:59 AM UTC 24
Finished Oct 12 06:27:05 AM UTC 24
Peak memory 215472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3580786
85 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_fifo_watermark
s_acq.358078685
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/48.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/48.i2c_target_fifo_watermarks_tx.3219843511
Short name T1670
Test name
Test status
Simulation time 196719994 ps
CPU time 1.94 seconds
Started Oct 12 06:27:00 AM UTC 24
Finished Oct 12 06:27:03 AM UTC 24
Peak memory 215260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3219843
511 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_fifo_watermark
s_tx.3219843511
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/48.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/48.i2c_target_hrst.2824000526
Short name T1668
Test name
Test status
Simulation time 752295952 ps
CPU time 4.48 seconds
Started Oct 12 06:26:56 AM UTC 24
Finished Oct 12 06:27:02 AM UTC 24
Peak memory 231780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2824000
526 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_hrst.2824000526
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/48.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/48.i2c_target_intr_smoke.2239147085
Short name T1662
Test name
Test status
Simulation time 2448147120 ps
CPU time 9.32 seconds
Started Oct 12 06:26:48 AM UTC 24
Finished Oct 12 06:26:58 AM UTC 24
Peak memory 225704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=223914
7085 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_intr_smoke.2239147085
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/48.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/48.i2c_target_intr_stress_wr.362884428
Short name T1660
Test name
Test status
Simulation time 3946550172 ps
CPU time 6.24 seconds
Started Oct 12 06:26:49 AM UTC 24
Finished Oct 12 06:26:57 AM UTC 24
Peak memory 215464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=362884428 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_intr_stress
_wr.362884428
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/48.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/48.i2c_target_nack_acqfull.4188434439
Short name T1680
Test name
Test status
Simulation time 2197319927 ps
CPU time 4.55 seconds
Started Oct 12 06:27:00 AM UTC 24
Finished Oct 12 06:27:06 AM UTC 24
Peak memory 225968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4188434
439 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_nack_acqfull.4188434439
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/48.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/48.i2c_target_nack_acqfull_addr.4212041950
Short name T1682
Test name
Test status
Simulation time 4750209719 ps
CPU time 4.14 seconds
Started Oct 12 06:27:01 AM UTC 24
Finished Oct 12 06:27:07 AM UTC 24
Peak memory 215808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4212041
950 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_nack_acqfull_ad
dr.4212041950
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/48.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/48.i2c_target_nack_txstretch.2609118858
Short name T1676
Test name
Test status
Simulation time 519268874 ps
CPU time 2.62 seconds
Started Oct 12 06:27:01 AM UTC 24
Finished Oct 12 06:27:05 AM UTC 24
Peak memory 232256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2609118
858 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_nack_txstretch.2609118858
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/48.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/48.i2c_target_perf.178659780
Short name T1671
Test name
Test status
Simulation time 1850909302 ps
CPU time 6.66 seconds
Started Oct 12 06:26:55 AM UTC 24
Finished Oct 12 06:27:03 AM UTC 24
Peak memory 225696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1786597
80 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_perf.178659780
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/48.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/48.i2c_target_smbus_maxlen.3706164325
Short name T1675
Test name
Test status
Simulation time 4642481407 ps
CPU time 3.84 seconds
Started Oct 12 06:27:00 AM UTC 24
Finished Oct 12 06:27:05 AM UTC 24
Peak memory 215440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3706164
325 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_smbus_maxlen.3706164325
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/48.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/48.i2c_target_smoke.356949649
Short name T1681
Test name
Test status
Simulation time 1858260195 ps
CPU time 20.73 seconds
Started Oct 12 06:26:44 AM UTC 24
Finished Oct 12 06:27:06 AM UTC 24
Peak memory 225716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=356949649 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_smoke.356949649
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/48.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/48.i2c_target_stress_all.1629485649
Short name T1714
Test name
Test status
Simulation time 29920893359 ps
CPU time 47.1 seconds
Started Oct 12 06:26:55 AM UTC 24
Finished Oct 12 06:27:44 AM UTC 24
Peak memory 291716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=162948
5649 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_stress_all.1629485649
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/48.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/48.i2c_target_stress_rd.3739584756
Short name T1656
Test name
Test status
Simulation time 297941249 ps
CPU time 5.82 seconds
Started Oct 12 06:26:45 AM UTC 24
Finished Oct 12 06:26:52 AM UTC 24
Peak memory 215400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3739584756 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_stress_rd.3739584756
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/48.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/48.i2c_target_stress_wr.1443567727
Short name T1696
Test name
Test status
Simulation time 35898078088 ps
CPU time 41.01 seconds
Started Oct 12 06:26:45 AM UTC 24
Finished Oct 12 06:27:28 AM UTC 24
Peak memory 883968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1443567727 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_stress_wr.1443567727
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/48.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/48.i2c_target_stretch.542137170
Short name T1655
Test name
Test status
Simulation time 188549044 ps
CPU time 2.07 seconds
Started Oct 12 06:26:47 AM UTC 24
Finished Oct 12 06:26:50 AM UTC 24
Peak memory 215656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=542137170 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_stretch.542137170
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/48.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/48.i2c_target_timeout.1207028184
Short name T1669
Test name
Test status
Simulation time 1203833679 ps
CPU time 11.38 seconds
Started Oct 12 06:26:50 AM UTC 24
Finished Oct 12 06:27:03 AM UTC 24
Peak memory 232644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1207028
184 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_timeout.1207028184
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/48.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/48.i2c_target_tx_stretch_ctrl.526995263
Short name T1677
Test name
Test status
Simulation time 156042446 ps
CPU time 4.24 seconds
Started Oct 12 06:27:00 AM UTC 24
Finished Oct 12 06:27:05 AM UTC 24
Peak memory 215172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5269952
63 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_target_tx_stretch_ctrl.526995263
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/48.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/49.i2c_alert_test.919353980
Short name T1705
Test name
Test status
Simulation time 38489509 ps
CPU time 0.77 seconds
Started Oct 12 06:27:33 AM UTC 24
Finished Oct 12 06:27:35 AM UTC 24
Peak memory 215628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=919353980 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_alert_test.919353980
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/49.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/49.i2c_host_error_intr.165100782
Short name T1685
Test name
Test status
Simulation time 183846896 ps
CPU time 3.45 seconds
Started Oct 12 06:27:07 AM UTC 24
Finished Oct 12 06:27:11 AM UTC 24
Peak memory 225792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=165100782 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 49.i2c_host_error_intr.165100782
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/49.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_fmt_empty.855431615
Short name T1688
Test name
Test status
Simulation time 547983569 ps
CPU time 14.19 seconds
Started Oct 12 06:27:05 AM UTC 24
Finished Oct 12 06:27:20 AM UTC 24
Peak memory 271500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=855431615 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_fmt_empty.855431615
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/49.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_full.2633690101
Short name T1725
Test name
Test status
Simulation time 2100364637 ps
CPU time 123.57 seconds
Started Oct 12 06:27:06 AM UTC 24
Finished Oct 12 06:29:12 AM UTC 24
Peak memory 629760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2633690101 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_full.2633690101
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/49.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_overflow.2522174735
Short name T1729
Test name
Test status
Simulation time 2365428341 ps
CPU time 157.09 seconds
Started Oct 12 06:27:04 AM UTC 24
Finished Oct 12 06:29:44 AM UTC 24
Peak memory 734212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2522174735 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_overflow.2522174735
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/49.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_reset_fmt.142348539
Short name T1683
Test name
Test status
Simulation time 704261617 ps
CPU time 2.02 seconds
Started Oct 12 06:27:05 AM UTC 24
Finished Oct 12 06:27:08 AM UTC 24
Peak memory 215500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=142348539 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_fmt.142348539
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/49.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_reset_rx.1177042092
Short name T1691
Test name
Test status
Simulation time 1496808962 ps
CPU time 16.93 seconds
Started Oct 12 06:27:06 AM UTC 24
Finished Oct 12 06:27:25 AM UTC 24
Peak memory 265028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1177042092 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_rx.1177042092
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/49.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_watermark.2393637190
Short name T1717
Test name
Test status
Simulation time 13532554470 ps
CPU time 71.11 seconds
Started Oct 12 06:27:04 AM UTC 24
Finished Oct 12 06:28:17 AM UTC 24
Peak memory 1010892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2393637190 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_watermark.2393637190
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/49.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/49.i2c_host_may_nack.424602601
Short name T1711
Test name
Test status
Simulation time 329212213 ps
CPU time 12.28 seconds
Started Oct 12 06:27:27 AM UTC 24
Finished Oct 12 06:27:41 AM UTC 24
Peak memory 215836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=424602601 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 49.i2c_host_may_nack.424602601
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/49.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/49.i2c_host_override.2106638877
Short name T1678
Test name
Test status
Simulation time 49570640 ps
CPU time 0.92 seconds
Started Oct 12 06:27:04 AM UTC 24
Finished Oct 12 06:27:06 AM UTC 24
Peak memory 213212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2106638877 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.i2c_host_override.2106638877
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/49.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/49.i2c_host_perf.3393417214
Short name T1741
Test name
Test status
Simulation time 50153134839 ps
CPU time 1645.76 seconds
Started Oct 12 06:27:07 AM UTC 24
Finished Oct 12 06:54:50 AM UTC 24
Peak memory 2641160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3393417214 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 49.i2c_host_perf.3393417214
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/49.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/49.i2c_host_perf_precise.2148124162
Short name T1718
Test name
Test status
Simulation time 6177353340 ps
CPU time 70.71 seconds
Started Oct 12 06:27:07 AM UTC 24
Finished Oct 12 06:28:19 AM UTC 24
Peak memory 871288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2148124162 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_perf_precise.2148124162
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/49.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/49.i2c_host_smoke.1641608059
Short name T1719
Test name
Test status
Simulation time 1774475759 ps
CPU time 82.57 seconds
Started Oct 12 06:27:03 AM UTC 24
Finished Oct 12 06:28:27 AM UTC 24
Peak memory 342924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1641608059 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.i2c_host_smoke.1641608059
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/49.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/49.i2c_host_stretch_timeout.3831050654
Short name T1716
Test name
Test status
Simulation time 2043276032 ps
CPU time 48.95 seconds
Started Oct 12 06:27:07 AM UTC 24
Finished Oct 12 06:27:57 AM UTC 24
Peak memory 227680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3831050654 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_stretch_timeout.3831050654
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/49.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/49.i2c_target_bad_addr.1193689946
Short name T1704
Test name
Test status
Simulation time 5089580117 ps
CPU time 8.05 seconds
Started Oct 12 06:27:25 AM UTC 24
Finished Oct 12 06:27:34 AM UTC 24
Peak memory 232228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=1193689946 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_bad_ad
dr.1193689946
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/49.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/49.i2c_target_fifo_reset_acq.299706726
Short name T1692
Test name
Test status
Simulation time 594577709 ps
CPU time 2.14 seconds
Started Oct 12 06:27:22 AM UTC 24
Finished Oct 12 06:27:25 AM UTC 24
Peak memory 215384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2997067
26 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_fifo_reset_acq.299706726
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/49.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/49.i2c_target_fifo_reset_tx.1223055326
Short name T1693
Test name
Test status
Simulation time 963869697 ps
CPU time 3 seconds
Started Oct 12 06:27:22 AM UTC 24
Finished Oct 12 06:27:26 AM UTC 24
Peak memory 215400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1223055
326 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_fifo_reset_tx.1223055326
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/49.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/49.i2c_target_fifo_watermarks_acq.2886942782
Short name T1702
Test name
Test status
Simulation time 1337224672 ps
CPU time 4.8 seconds
Started Oct 12 06:27:27 AM UTC 24
Finished Oct 12 06:27:33 AM UTC 24
Peak memory 215724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2886942
782 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_fifo_watermar
ks_acq.2886942782
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/49.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/49.i2c_target_fifo_watermarks_tx.696739689
Short name T1699
Test name
Test status
Simulation time 268410782 ps
CPU time 1.56 seconds
Started Oct 12 06:27:29 AM UTC 24
Finished Oct 12 06:27:31 AM UTC 24
Peak memory 213272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6967396
89 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_fifo_watermarks
_tx.696739689
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/49.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/49.i2c_target_hrst.654154745
Short name T1698
Test name
Test status
Simulation time 1475823123 ps
CPU time 2.91 seconds
Started Oct 12 06:27:26 AM UTC 24
Finished Oct 12 06:27:30 AM UTC 24
Peak memory 225700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6541547
45 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_hrst.654154745
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/49.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/49.i2c_target_intr_smoke.352545172
Short name T1687
Test name
Test status
Simulation time 2567138915 ps
CPU time 7.21 seconds
Started Oct 12 06:27:09 AM UTC 24
Finished Oct 12 06:27:17 AM UTC 24
Peak memory 229860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=352545
172 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_intr_smoke.352545172
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/49.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/49.i2c_target_intr_stress_wr.3119836546
Short name T1610
Test name
Test status
Simulation time 29137546471 ps
CPU time 53.6 seconds
Started Oct 12 06:27:12 AM UTC 24
Finished Oct 12 06:28:07 AM UTC 24
Peak memory 1215360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3119836546 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_intr_stres
s_wr.3119836546
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/49.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/49.i2c_target_nack_acqfull.1705078067
Short name T1708
Test name
Test status
Simulation time 2017627346 ps
CPU time 4.69 seconds
Started Oct 12 06:27:31 AM UTC 24
Finished Oct 12 06:27:37 AM UTC 24
Peak memory 225612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1705078
067 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_nack_acqfull.1705078067
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/49.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/49.i2c_target_nack_acqfull_addr.3100915024
Short name T1709
Test name
Test status
Simulation time 634571396 ps
CPU time 5.55 seconds
Started Oct 12 06:27:32 AM UTC 24
Finished Oct 12 06:27:39 AM UTC 24
Peak memory 215424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3100915
024 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_nack_acqfull_ad
dr.3100915024
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/49.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/49.i2c_target_nack_txstretch.1575923574
Short name T1707
Test name
Test status
Simulation time 507503549 ps
CPU time 1.83 seconds
Started Oct 12 06:27:33 AM UTC 24
Finished Oct 12 06:27:36 AM UTC 24
Peak memory 231192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1575923
574 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_nack_txstretch.1575923574
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/49.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/49.i2c_target_perf.3995010882
Short name T1700
Test name
Test status
Simulation time 1522603535 ps
CPU time 7.71 seconds
Started Oct 12 06:27:23 AM UTC 24
Finished Oct 12 06:27:32 AM UTC 24
Peak memory 229800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3995010
882 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_perf.3995010882
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/49.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/49.i2c_target_smbus_maxlen.2439668703
Short name T1706
Test name
Test status
Simulation time 471746080 ps
CPU time 3.62 seconds
Started Oct 12 06:27:31 AM UTC 24
Finished Oct 12 06:27:36 AM UTC 24
Peak memory 215172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2439668
703 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_smbus_maxlen.2439668703
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/49.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/49.i2c_target_smoke.1988726159
Short name T1715
Test name
Test status
Simulation time 1128320246 ps
CPU time 44.54 seconds
Started Oct 12 06:27:07 AM UTC 24
Finished Oct 12 06:27:53 AM UTC 24
Peak memory 225896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1988726159 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_smoke.1988726159
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/49.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/49.i2c_target_stress_all.2484388060
Short name T1727
Test name
Test status
Simulation time 26401803216 ps
CPU time 110.43 seconds
Started Oct 12 06:27:25 AM UTC 24
Finished Oct 12 06:29:18 AM UTC 24
Peak memory 1319800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=248438
8060 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_stress_all.2484388060
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/49.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/49.i2c_target_stress_rd.3075027135
Short name T1701
Test name
Test status
Simulation time 5949447348 ps
CPU time 23.37 seconds
Started Oct 12 06:27:08 AM UTC 24
Finished Oct 12 06:27:33 AM UTC 24
Peak memory 242616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3075027135 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_stress_rd.3075027135
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/49.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/49.i2c_target_stress_wr.3052024480
Short name T1694
Test name
Test status
Simulation time 10773907833 ps
CPU time 17.19 seconds
Started Oct 12 06:27:08 AM UTC 24
Finished Oct 12 06:27:26 AM UTC 24
Peak memory 215644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3052024480 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_stress_wr.3052024480
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/49.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/49.i2c_target_stretch.543991735
Short name T1695
Test name
Test status
Simulation time 1528840682 ps
CPU time 16.41 seconds
Started Oct 12 06:27:09 AM UTC 24
Finished Oct 12 06:27:27 AM UTC 24
Peak memory 361348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=543991735 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_stretch.543991735
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/49.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/49.i2c_target_timeout.644744919
Short name T1697
Test name
Test status
Simulation time 6947895268 ps
CPU time 10.71 seconds
Started Oct 12 06:27:16 AM UTC 24
Finished Oct 12 06:27:28 AM UTC 24
Peak memory 231976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6447449
19 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_timeout.644744919
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/49.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/49.i2c_target_tx_stretch_ctrl.1229161416
Short name T1703
Test name
Test status
Simulation time 87757637 ps
CPU time 3.71 seconds
Started Oct 12 06:27:29 AM UTC 24
Finished Oct 12 06:27:33 AM UTC 24
Peak memory 215724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1229161
416 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_target_tx_stretch_ctrl.1229161416
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/49.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/5.i2c_alert_test.861170116
Short name T97
Test name
Test status
Simulation time 56895872 ps
CPU time 1.02 seconds
Started Oct 12 05:58:18 AM UTC 24
Finished Oct 12 05:58:20 AM UTC 24
Peak memory 215632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=861170116 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_alert_test.861170116
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/5.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/5.i2c_host_fifo_fmt_empty.3052090302
Short name T311
Test name
Test status
Simulation time 475974805 ps
CPU time 25.57 seconds
Started Oct 12 05:57:27 AM UTC 24
Finished Oct 12 05:57:54 AM UTC 24
Peak memory 312184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3052090302 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_fmt_empty.3052090302
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/5.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/5.i2c_host_fifo_full.147712949
Short name T378
Test name
Test status
Simulation time 8894107283 ps
CPU time 127.6 seconds
Started Oct 12 05:57:29 AM UTC 24
Finished Oct 12 05:59:39 AM UTC 24
Peak memory 607288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=147712949 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_full.147712949
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/5.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/5.i2c_host_fifo_overflow.2217059593
Short name T94
Test name
Test status
Simulation time 1485924861 ps
CPU time 47.82 seconds
Started Oct 12 05:57:27 AM UTC 24
Finished Oct 12 05:58:17 AM UTC 24
Peak memory 582592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2217059593 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_overflow.2217059593
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/5.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/5.i2c_host_fifo_reset_fmt.3895334029
Short name T242
Test name
Test status
Simulation time 406430988 ps
CPU time 1.47 seconds
Started Oct 12 05:57:27 AM UTC 24
Finished Oct 12 05:57:30 AM UTC 24
Peak memory 213332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3895334029 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_fmt.3895334029
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/5.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/5.i2c_host_fifo_reset_rx.2806265899
Short name T172
Test name
Test status
Simulation time 123940788 ps
CPU time 3.55 seconds
Started Oct 12 05:57:29 AM UTC 24
Finished Oct 12 05:57:34 AM UTC 24
Peak memory 215400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2806265899 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_rx.2806265899
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/5.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/5.i2c_host_fifo_watermark.4211144754
Short name T375
Test name
Test status
Simulation time 17701752761 ps
CPU time 120.08 seconds
Started Oct 12 05:57:26 AM UTC 24
Finished Oct 12 05:59:29 AM UTC 24
Peak memory 1301456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4211144754 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_watermark.4211144754
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/5.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/5.i2c_host_may_nack.3557840943
Short name T253
Test name
Test status
Simulation time 2258684702 ps
CPU time 26.64 seconds
Started Oct 12 05:58:12 AM UTC 24
Finished Oct 12 05:58:40 AM UTC 24
Peak memory 215836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3557840943 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.i2c_host_may_nack.3557840943
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/5.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/5.i2c_host_override.1781354514
Short name T137
Test name
Test status
Simulation time 52336981 ps
CPU time 0.96 seconds
Started Oct 12 05:57:26 AM UTC 24
Finished Oct 12 05:57:29 AM UTC 24
Peak memory 213208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1781354514 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.i2c_host_override.1781354514
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/5.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/5.i2c_host_perf.59324724
Short name T15
Test name
Test status
Simulation time 7802563372 ps
CPU time 36.63 seconds
Started Oct 12 05:57:29 AM UTC 24
Finished Oct 12 05:58:07 AM UTC 24
Peak memory 377804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=59324724 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_ho
st_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 5.i2c_host_perf.59324724
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/5.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/5.i2c_host_perf_precise.4061610035
Short name T304
Test name
Test status
Simulation time 38006519 ps
CPU time 2.18 seconds
Started Oct 12 05:57:30 AM UTC 24
Finished Oct 12 05:57:34 AM UTC 24
Peak memory 236188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4061610035 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_perf_precise.4061610035
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/5.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/5.i2c_host_smoke.3447935434
Short name T343
Test name
Test status
Simulation time 1537303737 ps
CPU time 29.7 seconds
Started Oct 12 05:57:26 AM UTC 24
Finished Oct 12 05:57:58 AM UTC 24
Peak memory 279740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3447935434 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.i2c_host_smoke.3447935434
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/5.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/5.i2c_host_stretch_timeout.1541509870
Short name T285
Test name
Test status
Simulation time 661784310 ps
CPU time 15.6 seconds
Started Oct 12 05:57:31 AM UTC 24
Finished Oct 12 05:57:48 AM UTC 24
Peak memory 230008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1541509870 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_stretch_timeout.1541509870
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/5.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/5.i2c_target_bad_addr.1929929501
Short name T348
Test name
Test status
Simulation time 11943637354 ps
CPU time 5.03 seconds
Started Oct 12 05:58:03 AM UTC 24
Finished Oct 12 05:58:09 AM UTC 24
Peak memory 225824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=1929929501 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_bad_addr.1929929501
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/5.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/5.i2c_target_fifo_reset_acq.1604876707
Short name T345
Test name
Test status
Simulation time 326387355 ps
CPU time 1.41 seconds
Started Oct 12 05:57:59 AM UTC 24
Finished Oct 12 05:58:01 AM UTC 24
Peak memory 215512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1604876
707 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_fifo_reset_acq.1604876707
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/5.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/5.i2c_target_fifo_reset_tx.3162002141
Short name T346
Test name
Test status
Simulation time 401931898 ps
CPU time 1.66 seconds
Started Oct 12 05:58:00 AM UTC 24
Finished Oct 12 05:58:03 AM UTC 24
Peak memory 215632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3162002
141 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_fifo_reset_tx.3162002141
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/5.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/5.i2c_target_fifo_watermarks_acq.3732121419
Short name T93
Test name
Test status
Simulation time 515653026 ps
CPU time 3.9 seconds
Started Oct 12 05:58:12 AM UTC 24
Finished Oct 12 05:58:17 AM UTC 24
Peak memory 215576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3732121
419 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_fifo_watermark
s_acq.3732121419
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/5.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/5.i2c_target_fifo_watermarks_tx.3627240539
Short name T92
Test name
Test status
Simulation time 579410258 ps
CPU time 2.03 seconds
Started Oct 12 05:58:13 AM UTC 24
Finished Oct 12 05:58:16 AM UTC 24
Peak memory 215256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3627240
539 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_fifo_watermarks
_tx.3627240539
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/5.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/5.i2c_target_intr_smoke.4165637345
Short name T330
Test name
Test status
Simulation time 700331612 ps
CPU time 4.37 seconds
Started Oct 12 05:57:49 AM UTC 24
Finished Oct 12 05:57:54 AM UTC 24
Peak memory 225640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=416563
7345 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_intr_smoke.4165637345
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/5.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/5.i2c_target_intr_stress_wr.2368149314
Short name T365
Test name
Test status
Simulation time 19156867239 ps
CPU time 82.45 seconds
Started Oct 12 05:57:55 AM UTC 24
Finished Oct 12 05:59:19 AM UTC 24
Peak memory 1293180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2368149314 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_intr_stress
_wr.2368149314
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/5.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/5.i2c_target_nack_acqfull.71091805
Short name T53
Test name
Test status
Simulation time 622992712 ps
CPU time 4.67 seconds
Started Oct 12 05:58:16 AM UTC 24
Finished Oct 12 05:58:22 AM UTC 24
Peak memory 225644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7109180
5 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_nack_acqfull.71091805
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/5.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/5.i2c_target_nack_txstretch.2612243989
Short name T163
Test name
Test status
Simulation time 152292222 ps
CPU time 2.41 seconds
Started Oct 12 05:58:17 AM UTC 24
Finished Oct 12 05:58:21 AM UTC 24
Peak memory 232332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2612243
989 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_nack_txstretch.2612243989
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/5.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/5.i2c_target_perf.477860506
Short name T91
Test name
Test status
Simulation time 4539758881 ps
CPU time 11.99 seconds
Started Oct 12 05:58:02 AM UTC 24
Finished Oct 12 05:58:15 AM UTC 24
Peak memory 242884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4778605
06 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_perf.477860506
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/5.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/5.i2c_target_smbus_maxlen.1125953997
Short name T95
Test name
Test status
Simulation time 1305307437 ps
CPU time 3.83 seconds
Started Oct 12 05:58:14 AM UTC 24
Finished Oct 12 05:58:19 AM UTC 24
Peak memory 215432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1125953
997 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_smbus_maxlen.1125953997
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/5.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/5.i2c_target_smoke.1643405686
Short name T84
Test name
Test status
Simulation time 812163840 ps
CPU time 31.11 seconds
Started Oct 12 05:57:39 AM UTC 24
Finished Oct 12 05:58:12 AM UTC 24
Peak memory 225756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1643405686 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_smoke.1643405686
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/5.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/5.i2c_target_stress_all.3708140850
Short name T274
Test name
Test status
Simulation time 97229946535 ps
CPU time 110.17 seconds
Started Oct 12 05:58:03 AM UTC 24
Finished Oct 12 05:59:56 AM UTC 24
Peak memory 625876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=370814
0850 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_stress_all.3708140850
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/5.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/5.i2c_target_stress_rd.1612616562
Short name T90
Test name
Test status
Simulation time 479701834 ps
CPU time 23.73 seconds
Started Oct 12 05:57:48 AM UTC 24
Finished Oct 12 05:58:13 AM UTC 24
Peak memory 225632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1612616562 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_stress_rd.1612616562
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/5.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/5.i2c_target_stress_wr.3753433508
Short name T382
Test name
Test status
Simulation time 37729249058 ps
CPU time 127.59 seconds
Started Oct 12 05:57:40 AM UTC 24
Finished Oct 12 05:59:49 AM UTC 24
Peak memory 2335612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3753433508 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_stress_wr.3753433508
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/5.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/5.i2c_target_stretch.3962089673
Short name T349
Test name
Test status
Simulation time 1056154677 ps
CPU time 20.82 seconds
Started Oct 12 05:57:49 AM UTC 24
Finished Oct 12 05:58:11 AM UTC 24
Peak memory 437048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3962089673 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_stretch.3962089673
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/5.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/5.i2c_target_timeout.2674373090
Short name T347
Test name
Test status
Simulation time 4686337414 ps
CPU time 9.69 seconds
Started Oct 12 05:57:55 AM UTC 24
Finished Oct 12 05:58:06 AM UTC 24
Peak memory 232380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2674373
090 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_timeout.2674373090
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/5.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/5.i2c_target_tx_stretch_ctrl.1985707188
Short name T96
Test name
Test status
Simulation time 283440767 ps
CPU time 5.97 seconds
Started Oct 12 05:58:13 AM UTC 24
Finished Oct 12 05:58:20 AM UTC 24
Peak memory 225968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1985707
188 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_target_tx_stretch_ctrl.1985707188
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/5.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/6.i2c_alert_test.2323235584
Short name T370
Test name
Test status
Simulation time 18217645 ps
CPU time 0.99 seconds
Started Oct 12 05:59:23 AM UTC 24
Finished Oct 12 05:59:25 AM UTC 24
Peak memory 213392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2323235584 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_alert_test.2323235584
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/6.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/6.i2c_host_error_intr.762928436
Short name T20
Test name
Test status
Simulation time 156952857 ps
CPU time 5.58 seconds
Started Oct 12 05:58:32 AM UTC 24
Finished Oct 12 05:58:39 AM UTC 24
Peak memory 232416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=762928436 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 6.i2c_host_error_intr.762928436
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/6.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/6.i2c_host_fifo_fmt_empty.766292436
Short name T352
Test name
Test status
Simulation time 1527141731 ps
CPU time 22.36 seconds
Started Oct 12 05:58:22 AM UTC 24
Finished Oct 12 05:58:45 AM UTC 24
Peak memory 291976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=766292436 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_fmt_empty.766292436
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/6.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/6.i2c_host_fifo_full.4213734521
Short name T423
Test name
Test status
Simulation time 33034226673 ps
CPU time 153.55 seconds
Started Oct 12 05:58:23 AM UTC 24
Finished Oct 12 06:00:59 AM UTC 24
Peak memory 515388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4213734521 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_full.4213734521
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/6.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/6.i2c_host_fifo_overflow.1157157875
Short name T364
Test name
Test status
Simulation time 1949735688 ps
CPU time 56.18 seconds
Started Oct 12 05:58:21 AM UTC 24
Finished Oct 12 05:59:19 AM UTC 24
Peak memory 560324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1157157875 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_overflow.1157157875
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/6.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/6.i2c_host_fifo_reset_fmt.2667180689
Short name T350
Test name
Test status
Simulation time 605154496 ps
CPU time 2.16 seconds
Started Oct 12 05:58:21 AM UTC 24
Finished Oct 12 05:58:24 AM UTC 24
Peak memory 215696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2667180689 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_fmt.2667180689
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/6.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/6.i2c_host_fifo_reset_rx.622569223
Short name T161
Test name
Test status
Simulation time 676604040 ps
CPU time 8.09 seconds
Started Oct 12 05:58:22 AM UTC 24
Finished Oct 12 05:58:31 AM UTC 24
Peak memory 244608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=622569223 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_rx.622569223
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/6.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/6.i2c_host_fifo_watermark.318427040
Short name T403
Test name
Test status
Simulation time 18412494677 ps
CPU time 135.6 seconds
Started Oct 12 05:58:20 AM UTC 24
Finished Oct 12 06:00:38 AM UTC 24
Peak memory 1393604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=318427040 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_watermark.318427040
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/6.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/6.i2c_host_may_nack.3151980314
Short name T275
Test name
Test status
Simulation time 1022904697 ps
CPU time 5.23 seconds
Started Oct 12 05:59:13 AM UTC 24
Finished Oct 12 05:59:19 AM UTC 24
Peak memory 215520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3151980314 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.i2c_host_may_nack.3151980314
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/6.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/6.i2c_host_override.1225812692
Short name T98
Test name
Test status
Simulation time 16969459 ps
CPU time 0.99 seconds
Started Oct 12 05:58:19 AM UTC 24
Finished Oct 12 05:58:20 AM UTC 24
Peak memory 213208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1225812692 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.i2c_host_override.1225812692
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/6.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/6.i2c_host_perf.1649189634
Short name T16
Test name
Test status
Simulation time 8368598084 ps
CPU time 101.32 seconds
Started Oct 12 05:58:24 AM UTC 24
Finished Oct 12 06:00:08 AM UTC 24
Peak memory 235932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1649189634 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 6.i2c_host_perf.1649189634
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/6.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/6.i2c_host_perf_precise.2317380049
Short name T377
Test name
Test status
Simulation time 6084829438 ps
CPU time 66.91 seconds
Started Oct 12 05:58:25 AM UTC 24
Finished Oct 12 05:59:34 AM UTC 24
Peak memory 215580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2317380049 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_perf_precise.2317380049
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/6.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/6.i2c_host_smoke.1057065953
Short name T362
Test name
Test status
Simulation time 2342056808 ps
CPU time 52.73 seconds
Started Oct 12 05:58:18 AM UTC 24
Finished Oct 12 05:59:13 AM UTC 24
Peak memory 439164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1057065953 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.i2c_host_smoke.1057065953
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/6.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/6.i2c_host_stretch_timeout.3916628392
Short name T353
Test name
Test status
Simulation time 5691784039 ps
CPU time 19.21 seconds
Started Oct 12 05:58:32 AM UTC 24
Finished Oct 12 05:58:53 AM UTC 24
Peak memory 242696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3916628392 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_stretch_timeout.3916628392
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/6.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/6.i2c_target_bad_addr.401438433
Short name T360
Test name
Test status
Simulation time 1734096272 ps
CPU time 6.86 seconds
Started Oct 12 05:59:02 AM UTC 24
Finished Oct 12 05:59:10 AM UTC 24
Peak memory 225752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=401438433 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_bad_addr.401438433
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/6.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/6.i2c_target_fifo_reset_acq.362108719
Short name T356
Test name
Test status
Simulation time 193007893 ps
CPU time 1.89 seconds
Started Oct 12 05:58:56 AM UTC 24
Finished Oct 12 05:58:59 AM UTC 24
Peak memory 215512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3621087
19 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_fifo_reset_acq.362108719
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/6.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/6.i2c_target_fifo_reset_tx.2881319324
Short name T358
Test name
Test status
Simulation time 578409703 ps
CPU time 2.16 seconds
Started Oct 12 05:58:58 AM UTC 24
Finished Oct 12 05:59:01 AM UTC 24
Peak memory 215252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2881319
324 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_fifo_reset_tx.2881319324
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/6.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/6.i2c_target_fifo_watermarks_acq.1188353096
Short name T363
Test name
Test status
Simulation time 349283093 ps
CPU time 3.42 seconds
Started Oct 12 05:59:14 AM UTC 24
Finished Oct 12 05:59:18 AM UTC 24
Peak memory 215460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1188353
096 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_fifo_watermark
s_acq.1188353096
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/6.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/6.i2c_target_fifo_watermarks_tx.1469209951
Short name T366
Test name
Test status
Simulation time 328389867 ps
CPU time 1.5 seconds
Started Oct 12 05:59:18 AM UTC 24
Finished Oct 12 05:59:21 AM UTC 24
Peak memory 213512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1469209
951 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_fifo_watermarks
_tx.1469209951
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/6.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/6.i2c_target_intr_smoke.4062919288
Short name T355
Test name
Test status
Simulation time 9622206226 ps
CPU time 5.34 seconds
Started Oct 12 05:58:49 AM UTC 24
Finished Oct 12 05:58:55 AM UTC 24
Peak memory 232396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=406291
9288 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_intr_smoke.4062919288
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/6.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/6.i2c_target_intr_stress_wr.2951185102
Short name T433
Test name
Test status
Simulation time 13334143861 ps
CPU time 147.09 seconds
Started Oct 12 05:58:50 AM UTC 24
Finished Oct 12 06:01:20 AM UTC 24
Peak memory 3320968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2951185102 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_intr_stress
_wr.2951185102
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/6.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/6.i2c_target_nack_acqfull.2972514812
Short name T371
Test name
Test status
Simulation time 2308797223 ps
CPU time 4.56 seconds
Started Oct 12 05:59:20 AM UTC 24
Finished Oct 12 05:59:26 AM UTC 24
Peak memory 225696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2972514
812 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_nack_acqfull.2972514812
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/6.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/6.i2c_target_nack_acqfull_addr.2063059599
Short name T372
Test name
Test status
Simulation time 2099592018 ps
CPU time 4.58 seconds
Started Oct 12 05:59:20 AM UTC 24
Finished Oct 12 05:59:26 AM UTC 24
Peak memory 215484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2063059
599 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_nack_acqfull_addr.2063059599
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/6.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/6.i2c_target_nack_txstretch.3793541815
Short name T164
Test name
Test status
Simulation time 144703875 ps
CPU time 2.06 seconds
Started Oct 12 05:59:21 AM UTC 24
Finished Oct 12 05:59:25 AM UTC 24
Peak memory 232256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3793541
815 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_nack_txstretch.3793541815
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/6.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/6.i2c_target_perf.2980813901
Short name T361
Test name
Test status
Simulation time 989041406 ps
CPU time 10.17 seconds
Started Oct 12 05:59:00 AM UTC 24
Finished Oct 12 05:59:12 AM UTC 24
Peak memory 232324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2980813
901 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_perf.2980813901
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/6.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/6.i2c_target_smbus_maxlen.2129567908
Short name T369
Test name
Test status
Simulation time 449320234 ps
CPU time 3.66 seconds
Started Oct 12 05:59:20 AM UTC 24
Finished Oct 12 05:59:25 AM UTC 24
Peak memory 215500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2129567
908 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_smbus_maxlen.2129567908
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/6.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/6.i2c_target_smoke.411049486
Short name T367
Test name
Test status
Simulation time 18142427004 ps
CPU time 39.6 seconds
Started Oct 12 05:58:41 AM UTC 24
Finished Oct 12 05:59:22 AM UTC 24
Peak memory 226084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=411049486 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_smoke.411049486
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/6.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/6.i2c_target_stress_all.4050563484
Short name T381
Test name
Test status
Simulation time 27271188354 ps
CPU time 41.71 seconds
Started Oct 12 05:59:01 AM UTC 24
Finished Oct 12 05:59:44 AM UTC 24
Peak memory 248776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=405056
3484 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_stress_all.4050563484
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/6.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/6.i2c_target_stress_rd.97443226
Short name T359
Test name
Test status
Simulation time 1455448221 ps
CPU time 23.78 seconds
Started Oct 12 05:58:44 AM UTC 24
Finished Oct 12 05:59:09 AM UTC 24
Peak memory 248736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=97443226 -assert nopostpro
c +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_stress_rd.97443226
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/6.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/6.i2c_target_stress_wr.1083506651
Short name T178
Test name
Test status
Simulation time 21794682714 ps
CPU time 59.09 seconds
Started Oct 12 05:58:41 AM UTC 24
Finished Oct 12 05:59:41 AM UTC 24
Peak memory 664776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1083506651 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_stress_wr.1083506651
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/6.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/6.i2c_target_timeout.930675345
Short name T357
Test name
Test status
Simulation time 2621350104 ps
CPU time 7.5 seconds
Started Oct 12 05:58:52 AM UTC 24
Finished Oct 12 05:59:00 AM UTC 24
Peak memory 232172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9306753
45 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_timeout.930675345
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/6.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/6.i2c_target_tx_stretch_ctrl.3973754728
Short name T368
Test name
Test status
Simulation time 56196850 ps
CPU time 2.44 seconds
Started Oct 12 05:59:19 AM UTC 24
Finished Oct 12 05:59:22 AM UTC 24
Peak memory 215456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3973754
728 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_target_tx_stretch_ctrl.3973754728
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/6.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/7.i2c_alert_test.2125963275
Short name T390
Test name
Test status
Simulation time 42295227 ps
CPU time 0.91 seconds
Started Oct 12 06:00:08 AM UTC 24
Finished Oct 12 06:00:09 AM UTC 24
Peak memory 213392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2125963275 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_alert_test.2125963275
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/7.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/7.i2c_host_error_intr.3942116737
Short name T27
Test name
Test status
Simulation time 1125989211 ps
CPU time 7.42 seconds
Started Oct 12 05:59:34 AM UTC 24
Finished Oct 12 05:59:43 AM UTC 24
Peak memory 248712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3942116737 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 7.i2c_host_error_intr.3942116737
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/7.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/7.i2c_host_fifo_fmt_empty.2677373629
Short name T380
Test name
Test status
Simulation time 262942763 ps
CPU time 15.72 seconds
Started Oct 12 05:59:27 AM UTC 24
Finished Oct 12 05:59:43 AM UTC 24
Peak memory 265100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2677373629 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_fmt_empty.2677373629
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/7.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/7.i2c_host_fifo_full.276372554
Short name T454
Test name
Test status
Simulation time 2439065017 ps
CPU time 157.9 seconds
Started Oct 12 05:59:28 AM UTC 24
Finished Oct 12 06:02:08 AM UTC 24
Peak memory 539652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=276372554 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_full.276372554
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/7.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/7.i2c_host_fifo_overflow.3722204964
Short name T459
Test name
Test status
Simulation time 2578085201 ps
CPU time 178.79 seconds
Started Oct 12 05:59:26 AM UTC 24
Finished Oct 12 06:02:28 AM UTC 24
Peak memory 873868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3722204964 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_overflow.3722204964
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/7.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/7.i2c_host_fifo_reset_fmt.697499504
Short name T241
Test name
Test status
Simulation time 128910284 ps
CPU time 1.18 seconds
Started Oct 12 05:59:27 AM UTC 24
Finished Oct 12 05:59:29 AM UTC 24
Peak memory 213268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=697499504 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_fmt.697499504
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/7.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/7.i2c_host_fifo_reset_rx.4182004747
Short name T376
Test name
Test status
Simulation time 148774646 ps
CPU time 5 seconds
Started Oct 12 05:59:28 AM UTC 24
Finished Oct 12 05:59:34 AM UTC 24
Peak memory 215524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4182004747 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_rx.4182004747
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/7.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/7.i2c_host_fifo_watermark.332134823
Short name T135
Test name
Test status
Simulation time 15493320226 ps
CPU time 229.02 seconds
Started Oct 12 05:59:25 AM UTC 24
Finished Oct 12 06:03:18 AM UTC 24
Peak memory 1104836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=332134823 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_watermark.332134823
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/7.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/7.i2c_host_may_nack.1675065823
Short name T254
Test name
Test status
Simulation time 7346180850 ps
CPU time 35.13 seconds
Started Oct 12 05:59:57 AM UTC 24
Finished Oct 12 06:00:33 AM UTC 24
Peak memory 215780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1675065823 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.i2c_host_may_nack.1675065823
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/7.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/7.i2c_host_override.814052618
Short name T374
Test name
Test status
Simulation time 77209338 ps
CPU time 0.97 seconds
Started Oct 12 05:59:25 AM UTC 24
Finished Oct 12 05:59:27 AM UTC 24
Peak memory 213208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=814052618 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 7.i2c_host_override.814052618
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/7.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/7.i2c_host_perf.3222040739
Short name T399
Test name
Test status
Simulation time 32951875437 ps
CPU time 59.7 seconds
Started Oct 12 05:59:29 AM UTC 24
Finished Oct 12 06:00:30 AM UTC 24
Peak memory 715764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3222040739 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 7.i2c_host_perf.3222040739
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/7.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/7.i2c_host_perf_precise.1894557348
Short name T379
Test name
Test status
Simulation time 765397312 ps
CPU time 8.71 seconds
Started Oct 12 05:59:30 AM UTC 24
Finished Oct 12 05:59:40 AM UTC 24
Peak memory 215400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1894557348 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_perf_precise.1894557348
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/7.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/7.i2c_host_smoke.3966588568
Short name T430
Test name
Test status
Simulation time 2292771588 ps
CPU time 103.91 seconds
Started Oct 12 05:59:23 AM UTC 24
Finished Oct 12 06:01:10 AM UTC 24
Peak memory 363840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3966588568 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.i2c_host_smoke.3966588568
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/7.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/7.i2c_host_stretch_timeout.2819708890
Short name T387
Test name
Test status
Simulation time 7816367491 ps
CPU time 30.38 seconds
Started Oct 12 05:59:30 AM UTC 24
Finished Oct 12 06:00:02 AM UTC 24
Peak memory 225836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2819708890 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_stretch_timeout.2819708890
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/7.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/7.i2c_target_bad_addr.2905212314
Short name T354
Test name
Test status
Simulation time 2382167134 ps
CPU time 10.08 seconds
Started Oct 12 05:59:55 AM UTC 24
Finished Oct 12 06:00:07 AM UTC 24
Peak memory 225888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=2905212314 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_bad_addr.2905212314
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/7.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/7.i2c_target_fifo_reset_acq.4073265257
Short name T384
Test name
Test status
Simulation time 137856819 ps
CPU time 1.51 seconds
Started Oct 12 05:59:52 AM UTC 24
Finished Oct 12 05:59:55 AM UTC 24
Peak memory 215512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4073265
257 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_fifo_reset_acq.4073265257
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/7.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/7.i2c_target_fifo_reset_tx.227382324
Short name T385
Test name
Test status
Simulation time 353801977 ps
CPU time 1.71 seconds
Started Oct 12 05:59:53 AM UTC 24
Finished Oct 12 05:59:56 AM UTC 24
Peak memory 215572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2273823
24 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_fifo_reset_tx.227382324
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/7.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/7.i2c_target_fifo_watermarks_acq.3077076882
Short name T388
Test name
Test status
Simulation time 2923907158 ps
CPU time 3.33 seconds
Started Oct 12 06:00:00 AM UTC 24
Finished Oct 12 06:00:04 AM UTC 24
Peak memory 215448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3077076
882 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_fifo_watermark
s_acq.3077076882
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/7.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/7.i2c_target_fifo_watermarks_tx.2259522854
Short name T389
Test name
Test status
Simulation time 2043425372 ps
CPU time 1.73 seconds
Started Oct 12 06:00:01 AM UTC 24
Finished Oct 12 06:00:08 AM UTC 24
Peak memory 215516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2259522
854 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_fifo_watermarks
_tx.2259522854
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/7.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/7.i2c_target_hrst.1689749024
Short name T181
Test name
Test status
Simulation time 318162529 ps
CPU time 3.35 seconds
Started Oct 12 05:59:55 AM UTC 24
Finished Oct 12 06:00:00 AM UTC 24
Peak memory 232596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1689749
024 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_hrst.1689749024
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/7.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/7.i2c_target_intr_smoke.4070890628
Short name T286
Test name
Test status
Simulation time 835249395 ps
CPU time 7.5 seconds
Started Oct 12 05:59:44 AM UTC 24
Finished Oct 12 05:59:52 AM UTC 24
Peak memory 232532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=407089
0628 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_intr_smoke.4070890628
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/7.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/7.i2c_target_intr_stress_wr.761204940
Short name T179
Test name
Test status
Simulation time 20192797629 ps
CPU time 9.16 seconds
Started Oct 12 05:59:45 AM UTC 24
Finished Oct 12 05:59:55 AM UTC 24
Peak memory 215840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=761204940 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_intr_stress_wr.761204940
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/7.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/7.i2c_target_nack_acqfull.2728433742
Short name T394
Test name
Test status
Simulation time 483653462 ps
CPU time 4.67 seconds
Started Oct 12 06:00:06 AM UTC 24
Finished Oct 12 06:00:12 AM UTC 24
Peak memory 225664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2728433
742 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_nack_acqfull.2728433742
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/7.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/7.i2c_target_nack_acqfull_addr.3620193338
Short name T393
Test name
Test status
Simulation time 2797106924 ps
CPU time 3.55 seconds
Started Oct 12 06:00:06 AM UTC 24
Finished Oct 12 06:00:11 AM UTC 24
Peak memory 215320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3620193
338 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_nack_acqfull_addr.3620193338
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/7.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/7.i2c_target_nack_txstretch.3418326283
Short name T165
Test name
Test status
Simulation time 151760559 ps
CPU time 2.16 seconds
Started Oct 12 06:00:06 AM UTC 24
Finished Oct 12 06:00:10 AM UTC 24
Peak memory 232256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3418326
283 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_nack_txstretch.3418326283
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/7.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/7.i2c_target_perf.840310694
Short name T342
Test name
Test status
Simulation time 554189810 ps
CPU time 5.43 seconds
Started Oct 12 05:59:53 AM UTC 24
Finished Oct 12 06:00:00 AM UTC 24
Peak memory 232020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8403106
94 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_perf.840310694
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/7.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/7.i2c_target_smbus_maxlen.3889997050
Short name T391
Test name
Test status
Simulation time 3685627696 ps
CPU time 3.68 seconds
Started Oct 12 06:00:01 AM UTC 24
Finished Oct 12 06:00:10 AM UTC 24
Peak memory 215564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3889997
050 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_smbus_maxlen.3889997050
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/7.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/7.i2c_target_smoke.1816531100
Short name T273
Test name
Test status
Simulation time 1348230733 ps
CPU time 15.33 seconds
Started Oct 12 05:59:35 AM UTC 24
Finished Oct 12 05:59:52 AM UTC 24
Peak memory 226024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1816531100 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_smoke.1816531100
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/7.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/7.i2c_target_stress_all.2099079485
Short name T865
Test name
Test status
Simulation time 42894238740 ps
CPU time 690.32 seconds
Started Oct 12 05:59:53 AM UTC 24
Finished Oct 12 06:11:31 AM UTC 24
Peak memory 8942548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=209907
9485 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_stress_all.2099079485
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/7.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/7.i2c_target_stress_rd.2743226635
Short name T383
Test name
Test status
Simulation time 1016536360 ps
CPU time 12.71 seconds
Started Oct 12 05:59:41 AM UTC 24
Finished Oct 12 05:59:54 AM UTC 24
Peak memory 225768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2743226635 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_stress_rd.2743226635
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/7.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/7.i2c_target_stress_wr.2315298688
Short name T1083
Test name
Test status
Simulation time 54493259860 ps
CPU time 988.45 seconds
Started Oct 12 05:59:39 AM UTC 24
Finished Oct 12 06:16:17 AM UTC 24
Peak memory 9184452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2315298688 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_stress_wr.2315298688
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/7.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/7.i2c_target_stretch.2584479583
Short name T408
Test name
Test status
Simulation time 2726659357 ps
CPU time 56.39 seconds
Started Oct 12 05:59:43 AM UTC 24
Finished Oct 12 06:00:41 AM UTC 24
Peak memory 842628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2584479583 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_stretch.2584479583
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/7.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/7.i2c_target_timeout.2009833285
Short name T386
Test name
Test status
Simulation time 10269507697 ps
CPU time 12.49 seconds
Started Oct 12 05:59:45 AM UTC 24
Finished Oct 12 05:59:58 AM UTC 24
Peak memory 232768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2009833
285 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_timeout.2009833285
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/7.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/7.i2c_target_tx_stretch_ctrl.4209727993
Short name T412
Test name
Test status
Simulation time 1867815973 ps
CPU time 41.8 seconds
Started Oct 12 06:00:01 AM UTC 24
Finished Oct 12 06:00:48 AM UTC 24
Peak memory 225636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4209727
993 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_target_tx_stretch_ctrl.4209727993
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/7.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/8.i2c_alert_test.2510971932
Short name T421
Test name
Test status
Simulation time 22290943 ps
CPU time 0.92 seconds
Started Oct 12 06:00:57 AM UTC 24
Finished Oct 12 06:00:59 AM UTC 24
Peak memory 213392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2510971932 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_alert_test.2510971932
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/8.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/8.i2c_host_error_intr.688185033
Short name T397
Test name
Test status
Simulation time 491115170 ps
CPU time 1.79 seconds
Started Oct 12 06:00:18 AM UTC 24
Finished Oct 12 06:00:20 AM UTC 24
Peak memory 225456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=688185033 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 8.i2c_host_error_intr.688185033
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/8.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/8.i2c_host_fifo_fmt_empty.124467237
Short name T401
Test name
Test status
Simulation time 1444679058 ps
CPU time 18.57 seconds
Started Oct 12 06:00:12 AM UTC 24
Finished Oct 12 06:00:32 AM UTC 24
Peak memory 295812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=124467237 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_fmt_empty.124467237
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/8.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/8.i2c_host_fifo_full.770648778
Short name T440
Test name
Test status
Simulation time 10302163235 ps
CPU time 76.58 seconds
Started Oct 12 06:00:13 AM UTC 24
Finished Oct 12 06:01:32 AM UTC 24
Peak memory 466180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=770648778 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_full.770648778
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/8.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/8.i2c_host_fifo_overflow.1780727671
Short name T487
Test name
Test status
Simulation time 2526923324 ps
CPU time 160.86 seconds
Started Oct 12 06:00:11 AM UTC 24
Finished Oct 12 06:02:54 AM UTC 24
Peak memory 773120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1780727671 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_overflow.1780727671
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/8.i2c_host_fifo_overflow/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/8.i2c_host_fifo_reset_fmt.2406133519
Short name T395
Test name
Test status
Simulation time 462584532 ps
CPU time 1.57 seconds
Started Oct 12 06:00:11 AM UTC 24
Finished Oct 12 06:00:14 AM UTC 24
Peak memory 213332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2406133519 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_fmt.2406133519
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/8.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/8.i2c_host_fifo_reset_rx.2037533133
Short name T398
Test name
Test status
Simulation time 171372633 ps
CPU time 11.08 seconds
Started Oct 12 06:00:12 AM UTC 24
Finished Oct 12 06:00:24 AM UTC 24
Peak memory 246596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2037533133 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_rx.2037533133
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/8.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/8.i2c_host_fifo_watermark.1224017216
Short name T498
Test name
Test status
Simulation time 2899940576 ps
CPU time 171.39 seconds
Started Oct 12 06:00:10 AM UTC 24
Finished Oct 12 06:03:04 AM UTC 24
Peak memory 898056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1224017216 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_watermark.1224017216
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/8.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/8.i2c_host_may_nack.3750771985
Short name T259
Test name
Test status
Simulation time 494275265 ps
CPU time 6.51 seconds
Started Oct 12 06:00:49 AM UTC 24
Finished Oct 12 06:00:57 AM UTC 24
Peak memory 215388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3750771985 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.i2c_host_may_nack.3750771985
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/8.i2c_host_may_nack/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/8.i2c_host_mode_toggle.1236717856
Short name T23
Test name
Test status
Simulation time 531217351 ps
CPU time 3.24 seconds
Started Oct 12 06:00:45 AM UTC 24
Finished Oct 12 06:00:49 AM UTC 24
Peak memory 225708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1236717856 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_mode_toggle.1236717856
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/8.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/8.i2c_host_override.3756418202
Short name T392
Test name
Test status
Simulation time 27372992 ps
CPU time 1.03 seconds
Started Oct 12 06:00:09 AM UTC 24
Finished Oct 12 06:00:11 AM UTC 24
Peak memory 213208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3756418202 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.i2c_host_override.3756418202
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/8.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/8.i2c_host_perf.913706602
Short name T34
Test name
Test status
Simulation time 51222727549 ps
CPU time 140.74 seconds
Started Oct 12 06:00:13 AM UTC 24
Finished Oct 12 06:02:36 AM UTC 24
Peak memory 215840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=913706602 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 8.i2c_host_perf.913706602
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/8.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/8.i2c_host_perf_precise.1769843898
Short name T396
Test name
Test status
Simulation time 70131129 ps
CPU time 1.54 seconds
Started Oct 12 06:00:14 AM UTC 24
Finished Oct 12 06:00:17 AM UTC 24
Peak memory 235596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1769843898 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_perf_precise.1769843898
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/8.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/8.i2c_host_smoke.1781937147
Short name T405
Test name
Test status
Simulation time 1661391767 ps
CPU time 30.09 seconds
Started Oct 12 06:00:09 AM UTC 24
Finished Oct 12 06:00:40 AM UTC 24
Peak memory 346960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1781937147 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.i2c_host_smoke.1781937147
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/8.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/8.i2c_host_stretch_timeout.822815544
Short name T400
Test name
Test status
Simulation time 789452871 ps
CPU time 14.25 seconds
Started Oct 12 06:00:15 AM UTC 24
Finished Oct 12 06:00:31 AM UTC 24
Peak memory 231976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=822815544 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_stretch_timeout.822815544
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/8.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/8.i2c_target_bad_addr.2867873070
Short name T414
Test name
Test status
Simulation time 1584959128 ps
CPU time 7.67 seconds
Started Oct 12 06:00:42 AM UTC 24
Finished Oct 12 06:00:51 AM UTC 24
Peak memory 225752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=2867873070 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_bad_addr.2867873070
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/8.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/8.i2c_target_fifo_reset_acq.3822832308
Short name T410
Test name
Test status
Simulation time 173281082 ps
CPU time 1.12 seconds
Started Oct 12 06:00:40 AM UTC 24
Finished Oct 12 06:00:42 AM UTC 24
Peak memory 215512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3822832
308 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_fifo_reset_acq.3822832308
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/8.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/8.i2c_target_fifo_reset_tx.1551055867
Short name T166
Test name
Test status
Simulation time 758396576 ps
CPU time 2.49 seconds
Started Oct 12 06:00:41 AM UTC 24
Finished Oct 12 06:00:44 AM UTC 24
Peak memory 227748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1551055
867 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_fifo_reset_tx.1551055867
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/8.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/8.i2c_target_fifo_watermarks_acq.806442544
Short name T418
Test name
Test status
Simulation time 3963507639 ps
CPU time 4.75 seconds
Started Oct 12 06:00:50 AM UTC 24
Finished Oct 12 06:00:56 AM UTC 24
Peak memory 215900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8064425
44 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_fifo_watermarks
_acq.806442544
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/8.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/8.i2c_target_fifo_watermarks_tx.3674224890
Short name T416
Test name
Test status
Simulation time 474150221 ps
CPU time 2.05 seconds
Started Oct 12 06:00:50 AM UTC 24
Finished Oct 12 06:00:54 AM UTC 24
Peak memory 215256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3674224
890 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_fifo_watermarks
_tx.3674224890
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/8.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/8.i2c_target_intr_smoke.2639122459
Short name T411
Test name
Test status
Simulation time 1824918391 ps
CPU time 9.16 seconds
Started Oct 12 06:00:33 AM UTC 24
Finished Oct 12 06:00:44 AM UTC 24
Peak memory 232332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=263912
2459 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_intr_smoke.2639122459
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/8.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/8.i2c_target_intr_stress_wr.1316687374
Short name T407
Test name
Test status
Simulation time 4727935406 ps
CPU time 4.89 seconds
Started Oct 12 06:00:34 AM UTC 24
Finished Oct 12 06:00:40 AM UTC 24
Peak memory 215844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1316687374 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_intr_stress
_wr.1316687374
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/8.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/8.i2c_target_nack_acqfull.1141615062
Short name T422
Test name
Test status
Simulation time 2303074444 ps
CPU time 5.09 seconds
Started Oct 12 06:00:53 AM UTC 24
Finished Oct 12 06:00:59 AM UTC 24
Peak memory 225888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1141615
062 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_nack_acqfull.1141615062
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/8.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/8.i2c_target_nack_acqfull_addr.2910461521
Short name T424
Test name
Test status
Simulation time 4538205417 ps
CPU time 3.68 seconds
Started Oct 12 06:00:55 AM UTC 24
Finished Oct 12 06:01:00 AM UTC 24
Peak memory 215552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2910461
521 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_nack_acqfull_addr.2910461521
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/8.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/8.i2c_target_nack_txstretch.2757126512
Short name T167
Test name
Test status
Simulation time 150940928 ps
CPU time 1.82 seconds
Started Oct 12 06:00:57 AM UTC 24
Finished Oct 12 06:01:00 AM UTC 24
Peak memory 231188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2757126
512 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_nack_txstretch.2757126512
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/8.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/8.i2c_target_perf.2680369595
Short name T415
Test name
Test status
Simulation time 5524079487 ps
CPU time 10.33 seconds
Started Oct 12 06:00:41 AM UTC 24
Finished Oct 12 06:00:52 AM UTC 24
Peak memory 232372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2680369
595 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_perf.2680369595
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/8.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/8.i2c_target_smbus_maxlen.4146555379
Short name T417
Test name
Test status
Simulation time 2043830589 ps
CPU time 3.02 seconds
Started Oct 12 06:00:52 AM UTC 24
Finished Oct 12 06:00:56 AM UTC 24
Peak memory 215244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4146555
379 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_smbus_maxlen.4146555379
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/8.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/8.i2c_target_smoke.4209000452
Short name T402
Test name
Test status
Simulation time 2039841451 ps
CPU time 15.39 seconds
Started Oct 12 06:00:21 AM UTC 24
Finished Oct 12 06:00:37 AM UTC 24
Peak memory 226020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4209000452 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_smoke.4209000452
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/8.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/8.i2c_target_stress_rd.1107208502
Short name T427
Test name
Test status
Simulation time 5151806149 ps
CPU time 31.34 seconds
Started Oct 12 06:00:31 AM UTC 24
Finished Oct 12 06:01:04 AM UTC 24
Peak memory 232520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1107208502 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_stress_rd.1107208502
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/8.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/8.i2c_target_stress_wr.1620955528
Short name T426
Test name
Test status
Simulation time 9526864413 ps
CPU time 36.86 seconds
Started Oct 12 06:00:25 AM UTC 24
Finished Oct 12 06:01:03 AM UTC 24
Peak memory 215788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1620955528 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_stress_wr.1620955528
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/8.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/8.i2c_target_stretch.1250610950
Short name T404
Test name
Test status
Simulation time 1303864801 ps
CPU time 6.63 seconds
Started Oct 12 06:00:32 AM UTC 24
Finished Oct 12 06:00:40 AM UTC 24
Peak memory 248700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1250610950 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_stretch.1250610950
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/8.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/8.i2c_target_timeout.2938748552
Short name T413
Test name
Test status
Simulation time 5535700176 ps
CPU time 10.23 seconds
Started Oct 12 06:00:38 AM UTC 24
Finished Oct 12 06:00:50 AM UTC 24
Peak memory 242640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2938748
552 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_timeout.2938748552
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/8.i2c_target_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/8.i2c_target_tx_stretch_ctrl.348034750
Short name T419
Test name
Test status
Simulation time 83143900 ps
CPU time 3.54 seconds
Started Oct 12 06:00:52 AM UTC 24
Finished Oct 12 06:00:56 AM UTC 24
Peak memory 215396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3480347
50 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_target_tx_stretch_ctrl.348034750
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/8.i2c_target_tx_stretch_ctrl/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/9.i2c_alert_test.1745630391
Short name T450
Test name
Test status
Simulation time 44154682 ps
CPU time 0.93 seconds
Started Oct 12 06:01:45 AM UTC 24
Finished Oct 12 06:01:47 AM UTC 24
Peak memory 213392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1745630391 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_alert_test.1745630391
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/9.i2c_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/9.i2c_host_error_intr.3147505431
Short name T432
Test name
Test status
Simulation time 281952237 ps
CPU time 7.75 seconds
Started Oct 12 06:01:05 AM UTC 24
Finished Oct 12 06:01:14 AM UTC 24
Peak memory 246740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3147505431 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_error_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 9.i2c_host_error_intr.3147505431
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/9.i2c_host_error_intr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/9.i2c_host_fifo_fmt_empty.424494829
Short name T431
Test name
Test status
Simulation time 559836760 ps
CPU time 8.22 seconds
Started Oct 12 06:01:01 AM UTC 24
Finished Oct 12 06:01:10 AM UTC 24
Peak memory 275652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=424494829 -assert nopostproc +UVM_TESTNAME=i2c_b
ase_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_fmt_empty.424494829
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/9.i2c_host_fifo_fmt_empty/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/9.i2c_host_fifo_full.3590571423
Short name T479
Test name
Test status
Simulation time 7322183914 ps
CPU time 105.11 seconds
Started Oct 12 06:01:01 AM UTC 24
Finished Oct 12 06:02:48 AM UTC 24
Peak memory 225752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3590571423 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_full.3590571423
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/9.i2c_host_fifo_full/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/9.i2c_host_fifo_reset_fmt.1066149010
Short name T425
Test name
Test status
Simulation time 454687793 ps
CPU time 1.76 seconds
Started Oct 12 06:01:01 AM UTC 24
Finished Oct 12 06:01:03 AM UTC 24
Peak memory 213332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1066149010 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_fmt.1066149010
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/9.i2c_host_fifo_reset_fmt/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/9.i2c_host_fifo_reset_rx.2807728083
Short name T428
Test name
Test status
Simulation time 152554821 ps
CPU time 6.28 seconds
Started Oct 12 06:01:01 AM UTC 24
Finished Oct 12 06:01:08 AM UTC 24
Peak memory 242632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2807728083 -assert nopostproc +UVM_TESTNAME=i2c_
base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_rx.2807728083
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/9.i2c_host_fifo_reset_rx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/9.i2c_host_fifo_watermark.423937685
Short name T115
Test name
Test status
Simulation time 5473803829 ps
CPU time 115.8 seconds
Started Oct 12 06:00:59 AM UTC 24
Finished Oct 12 06:02:57 AM UTC 24
Peak memory 1420164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=423937685 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_fifo_watermark_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_watermark.423937685
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/9.i2c_host_fifo_watermark/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/9.i2c_host_mode_toggle.593270613
Short name T24
Test name
Test status
Simulation time 79702660 ps
CPU time 2.47 seconds
Started Oct 12 06:01:35 AM UTC 24
Finished Oct 12 06:01:38 AM UTC 24
Peak memory 225772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=593270613 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_mode_toggle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 9.i2c_host_mode_toggle.593270613
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/9.i2c_host_mode_toggle/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/9.i2c_host_override.1113155739
Short name T138
Test name
Test status
Simulation time 122430710 ps
CPU time 1.09 seconds
Started Oct 12 06:00:58 AM UTC 24
Finished Oct 12 06:01:00 AM UTC 24
Peak memory 213208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1113155739 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.i2c_host_override.1113155739
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/9.i2c_host_override/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/9.i2c_host_perf.4242177638
Short name T602
Test name
Test status
Simulation time 28008401465 ps
CPU time 366.41 seconds
Started Oct 12 06:01:02 AM UTC 24
Finished Oct 12 06:07:13 AM UTC 24
Peak memory 369584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4242177638 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 9.i2c_host_perf.4242177638
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/9.i2c_host_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/9.i2c_host_perf_precise.2127483434
Short name T429
Test name
Test status
Simulation time 228144844 ps
CPU time 3.84 seconds
Started Oct 12 06:01:04 AM UTC 24
Finished Oct 12 06:01:09 AM UTC 24
Peak memory 215384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2127483434 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_perf_precise_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_perf_precise.2127483434
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/9.i2c_host_perf_precise/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/9.i2c_host_smoke.2214509585
Short name T409
Test name
Test status
Simulation time 4813149324 ps
CPU time 64.98 seconds
Started Oct 12 06:00:57 AM UTC 24
Finished Oct 12 06:02:04 AM UTC 24
Peak memory 324564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2214509585 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_
host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.i2c_host_smoke.2214509585
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/9.i2c_host_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/9.i2c_host_stretch_timeout.314666304
Short name T436
Test name
Test status
Simulation time 409382552 ps
CPU time 22.85 seconds
Started Oct 12 06:01:04 AM UTC 24
Finished Oct 12 06:01:28 AM UTC 24
Peak memory 225756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=314666304 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_h
ost_stretch_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_stretch_timeout.314666304
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/9.i2c_host_stretch_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/9.i2c_target_bad_addr.2206910669
Short name T443
Test name
Test status
Simulation time 4294179765 ps
CPU time 5.97 seconds
Started Oct 12 06:01:32 AM UTC 24
Finished Oct 12 06:01:39 AM UTC 24
Peak memory 225832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_b
ad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=2206910669 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_bad_addr.2206910669
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/9.i2c_target_bad_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/9.i2c_target_fifo_reset_acq.2189250473
Short name T437
Test name
Test status
Simulation time 203763947 ps
CPU time 1.49 seconds
Started Oct 12 06:01:26 AM UTC 24
Finished Oct 12 06:01:29 AM UTC 24
Peak memory 215512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2189250
473 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_fifo_reset_acq.2189250473
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/9.i2c_target_fifo_reset_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/9.i2c_target_fifo_reset_tx.99721035
Short name T438
Test name
Test status
Simulation time 1759466063 ps
CPU time 2.18 seconds
Started Oct 12 06:01:28 AM UTC 24
Finished Oct 12 06:01:31 AM UTC 24
Peak memory 215260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9972103
5 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_fifo_reset_tx.99721035
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/9.i2c_target_fifo_reset_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/9.i2c_target_fifo_watermarks_acq.1927876819
Short name T446
Test name
Test status
Simulation time 470881313 ps
CPU time 5.05 seconds
Started Oct 12 06:01:38 AM UTC 24
Finished Oct 12 06:01:44 AM UTC 24
Peak memory 215772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1927876
819 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_fifo_watermark
s_acq.1927876819
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/9.i2c_target_fifo_watermarks_acq/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/9.i2c_target_fifo_watermarks_tx.670620081
Short name T445
Test name
Test status
Simulation time 441578509 ps
CPU time 1.84 seconds
Started Oct 12 06:01:39 AM UTC 24
Finished Oct 12 06:01:42 AM UTC 24
Peak memory 213276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6706200
81 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_fifo_watermarks_tx.670620081
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/9.i2c_target_fifo_watermarks_tx/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/9.i2c_target_hrst.2248450783
Short name T182
Test name
Test status
Simulation time 1387598916 ps
CPU time 3.97 seconds
Started Oct 12 06:01:32 AM UTC 24
Finished Oct 12 06:01:38 AM UTC 24
Peak memory 225712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2248450
783 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_hrst.2248450783
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/9.i2c_target_hrst/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/9.i2c_target_intr_smoke.204465056
Short name T434
Test name
Test status
Simulation time 3556782789 ps
CPU time 5.86 seconds
Started Oct 12 06:01:15 AM UTC 24
Finished Oct 12 06:01:22 AM UTC 24
Peak memory 225776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=204465
056 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_intr_smoke.204465056
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/9.i2c_target_intr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/9.i2c_target_intr_stress_wr.1223975352
Short name T435
Test name
Test status
Simulation time 431222200 ps
CPU time 3.55 seconds
Started Oct 12 06:01:21 AM UTC 24
Finished Oct 12 06:01:25 AM UTC 24
Peak memory 215392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow
_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1223975352 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_intr_stress
_wr.1223975352
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/9.i2c_target_intr_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/9.i2c_target_nack_acqfull.260604972
Short name T54
Test name
Test status
Simulation time 2904334882 ps
CPU time 5.02 seconds
Started Oct 12 06:01:41 AM UTC 24
Finished Oct 12 06:01:47 AM UTC 24
Peak memory 225780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2606049
72 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_nack_acqfull.260604972
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/9.i2c_target_nack_acqfull/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/9.i2c_target_nack_acqfull_addr.3073104306
Short name T451
Test name
Test status
Simulation time 2182137814 ps
CPU time 4.04 seconds
Started Oct 12 06:01:42 AM UTC 24
Finished Oct 12 06:01:47 AM UTC 24
Peak memory 215808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3073104
306 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_nack_acqfull_addr.3073104306
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/9.i2c_target_nack_acqfull_addr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/9.i2c_target_nack_txstretch.3336305197
Short name T168
Test name
Test status
Simulation time 172963548 ps
CPU time 1.97 seconds
Started Oct 12 06:01:44 AM UTC 24
Finished Oct 12 06:01:47 AM UTC 24
Peak memory 232712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3336305
197 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_nack_txstretch.3336305197
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/9.i2c_target_nack_txstretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/9.i2c_target_perf.27686654
Short name T442
Test name
Test status
Simulation time 3041425999 ps
CPU time 6.84 seconds
Started Oct 12 06:01:29 AM UTC 24
Finished Oct 12 06:01:37 AM UTC 24
Peak memory 232764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2768665
4 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_perf.27686654
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/9.i2c_target_perf/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/9.i2c_target_smbus_maxlen.4160110497
Short name T447
Test name
Test status
Simulation time 503099643 ps
CPU time 3.08 seconds
Started Oct 12 06:01:40 AM UTC 24
Finished Oct 12 06:01:44 AM UTC 24
Peak memory 215500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4160110
497 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_smbus_maxlen.4160110497
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/9.i2c_target_smbus_maxlen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/9.i2c_target_smoke.1365069474
Short name T444
Test name
Test status
Simulation time 893760887 ps
CPU time 28.62 seconds
Started Oct 12 06:01:10 AM UTC 24
Finished Oct 12 06:01:40 AM UTC 24
Peak memory 225640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1365069474 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_smoke.1365069474
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/9.i2c_target_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/9.i2c_target_stress_all.3083217521
Short name T785
Test name
Test status
Simulation time 34689155286 ps
CPU time 492.2 seconds
Started Oct 12 06:01:29 AM UTC 24
Finished Oct 12 06:09:47 AM UTC 24
Peak memory 6097992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=308321
7521 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_stress_all.3083217521
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/9.i2c_target_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/9.i2c_target_stress_rd.2610480803
Short name T439
Test name
Test status
Simulation time 6243679302 ps
CPU time 20.21 seconds
Started Oct 12 06:01:10 AM UTC 24
Finished Oct 12 06:01:32 AM UTC 24
Peak memory 232396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2610480803 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_stress_rd.2610480803
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/9.i2c_target_stress_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/9.i2c_target_stress_wr.3671060947
Short name T636
Test name
Test status
Simulation time 37019277297 ps
CPU time 321.89 seconds
Started Oct 12 06:01:10 AM UTC 24
Finished Oct 12 06:06:36 AM UTC 24
Peak memory 4295548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3671060947 -assert nopostp
roc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_stress_wr.3671060947
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/9.i2c_target_stress_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/9.i2c_target_stretch.970915464
Short name T467
Test name
Test status
Simulation time 4163794425 ps
CPU time 80.58 seconds
Started Oct 12 06:01:14 AM UTC 24
Finished Oct 12 06:02:36 AM UTC 24
Peak memory 1172604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=970915464 -assert nopostpr
oc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_stretch.970915464
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/9.i2c_target_stretch/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default/9.i2c_target_timeout.3297246706
Short name T441
Test name
Test status
Simulation time 2406611217 ps
CPU time 9.75 seconds
Started Oct 12 06:01:23 AM UTC 24
Finished Oct 12 06:01:34 AM UTC 24
Peak memory 225696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3297246
706 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_target_timeout.3297246706
Directory /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/9.i2c_target_timeout/latest
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