7e34e67ade| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | host_smoke | i2c_host_smoke | 1.809m | 8.210ms | 50 | 50 | 100.00 |
| V1 | target_smoke | i2c_target_smoke | 58.740s | 1.579ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | i2c_csr_hw_reset | 1.190s | 64.930us | 5 | 5 | 100.00 |
| V1 | csr_rw | i2c_csr_rw | 1.200s | 27.943us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | i2c_csr_bit_bash | 7.130s | 2.063ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | i2c_csr_aliasing | 2.460s | 954.022us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | i2c_csr_mem_rw_with_rand_reset | 2.020s | 172.402us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | i2c_csr_rw | 1.200s | 27.943us | 20 | 20 | 100.00 |
| i2c_csr_aliasing | 2.460s | 954.022us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 155 | 155 | 100.00 | |||
| V2 | host_error_intr | i2c_host_error_intr | 9.910s | 207.426us | 50 | 50 | 100.00 |
| V2 | host_stress_all | i2c_host_stress_all | 57.950m | 35.994ms | 15 | 50 | 30.00 |
| V2 | host_maxperf | i2c_host_perf | 36.989m | 26.424ms | 50 | 50 | 100.00 |
| V2 | host_override | i2c_host_override | 1.160s | 49.156us | 50 | 50 | 100.00 |
| V2 | host_fifo_watermark | i2c_host_fifo_watermark | 4.817m | 4.745ms | 50 | 50 | 100.00 |
| V2 | host_fifo_overflow | i2c_host_fifo_overflow | 2.792m | 2.547ms | 50 | 50 | 100.00 |
| V2 | host_fifo_reset | i2c_host_fifo_reset_fmt | 2.140s | 572.333us | 50 | 50 | 100.00 |
| i2c_host_fifo_fmt_empty | 29.790s | 1.054ms | 50 | 50 | 100.00 | ||
| i2c_host_fifo_reset_rx | 18.980s | 494.392us | 50 | 50 | 100.00 | ||
| V2 | host_fifo_full | i2c_host_fifo_full | 4.392m | 15.542ms | 50 | 50 | 100.00 |
| V2 | host_timeout | i2c_host_stretch_timeout | 53.610s | 1.031ms | 50 | 50 | 100.00 |
| V2 | host_rx_oversample | i2c_host_rx_oversample | 0 | 0 | -- | ||
| V2 | i2c_host_mode_toggle | i2c_host_mode_toggle | 8.240s | 181.097us | 21 | 50 | 42.00 |
| V2 | target_glitch | i2c_target_glitch | 17.440s | 8.460ms | 2 | 2 | 100.00 |
| V2 | target_stress_all | i2c_target_stress_all | 18.648m | 60.222ms | 48 | 50 | 96.00 |
| V2 | target_maxperf | i2c_target_perf | 10.990s | 969.740us | 50 | 50 | 100.00 |
| V2 | target_fifo_empty | i2c_target_stress_rd | 1.318m | 6.181ms | 50 | 50 | 100.00 |
| i2c_target_intr_smoke | 17.540s | 1.617ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_reset | i2c_target_fifo_reset_acq | 2.830s | 274.461us | 50 | 50 | 100.00 |
| i2c_target_fifo_reset_tx | 2.900s | 276.076us | 50 | 50 | 100.00 | ||
| V2 | target_fifo_full | i2c_target_stress_wr | 25.962m | 70.463ms | 50 | 50 | 100.00 |
| i2c_target_stress_rd | 1.318m | 6.181ms | 50 | 50 | 100.00 | ||
| i2c_target_intr_stress_wr | 5.270m | 20.274ms | 50 | 50 | 100.00 | ||
| V2 | target_timeout | i2c_target_timeout | 13.680s | 1.487ms | 50 | 50 | 100.00 |
| V2 | target_clock_stretch | i2c_target_stretch | 3.407m | 5.876ms | 47 | 50 | 94.00 |
| V2 | bad_address | i2c_target_bad_addr | 12.690s | 3.414ms | 50 | 50 | 100.00 |
| V2 | target_mode_glitch | i2c_target_hrst | 1.048m | 10.010ms | 24 | 50 | 48.00 |
| V2 | target_fifo_watermark | i2c_target_fifo_watermarks_acq | 5.700s | 1.009ms | 50 | 50 | 100.00 |
| i2c_target_fifo_watermarks_tx | 2.530s | 156.688us | 49 | 50 | 98.00 | ||
| V2 | host_mode_config_perf | i2c_host_perf | 36.989m | 26.424ms | 50 | 50 | 100.00 |
| i2c_host_perf_precise | 17.053m | 24.310ms | 50 | 50 | 100.00 | ||
| V2 | host_mode_clock_stretching | i2c_host_stretch_timeout | 53.610s | 1.031ms | 50 | 50 | 100.00 |
| V2 | target_mode_tx_stretch_ctrl | i2c_target_tx_stretch_ctrl | 27.930s | 1.466ms | 48 | 50 | 96.00 |
| V2 | target_mode_nack_generation | i2c_target_nack_acqfull | 6.020s | 2.469ms | 50 | 50 | 100.00 |
| i2c_target_nack_acqfull_addr | 5.450s | 2.579ms | 50 | 50 | 100.00 | ||
| i2c_target_nack_txstretch | 2.990s | 841.734us | 33 | 50 | 66.00 | ||
| V2 | host_mode_halt_on_nak | i2c_host_may_nack | 31.120s | 591.652us | 50 | 50 | 100.00 |
| V2 | target_mode_n_byte_ack_control | target_mode_n_byte_ack_control | 0 | 0 | -- | ||
| V2 | target_mode_bus_timeout | target_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_timeout | controller_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_idle_delay | controller_mode_bus_idle_delay | 0 | 0 | -- | ||
| V2 | loopback_test | loopback_test | 0 | 0 | -- | ||
| V2 | multi_controller_clock_synchronization | multi_controller_clock_synchronization | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost_interference | multi_controller_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost | multi_controller_arbitration_lost | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost_interference | target_mode_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost | target_mode_arbitration_lost | 0 | 0 | -- | ||
| V2 | target_mode_smbus_maxlen | i2c_target_smbus_maxlen | 4.670s | 2.424ms | 50 | 50 | 100.00 |
| V2 | alert_test | i2c_alert_test | 1.060s | 49.411us | 50 | 50 | 100.00 |
| V2 | intr_test | i2c_intr_test | 1.130s | 19.314us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | i2c_tl_errors | 4.220s | 1.547ms | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | i2c_tl_errors | 4.220s | 1.547ms | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | i2c_csr_hw_reset | 1.190s | 64.930us | 5 | 5 | 100.00 |
| i2c_csr_rw | 1.200s | 27.943us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 2.460s | 954.022us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.760s | 62.109us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | i2c_csr_hw_reset | 1.190s | 64.930us | 5 | 5 | 100.00 |
| i2c_csr_rw | 1.200s | 27.943us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 2.460s | 954.022us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.760s | 62.109us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 1677 | 1792 | 93.58 | |||
| V2S | tl_intg_err | i2c_tl_intg_err | 3.080s | 645.441us | 20 | 20 | 100.00 |
| i2c_sec_cm | 1.630s | 801.128us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | i2c_tl_intg_err | 3.080s | 645.441us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | host_stress_all_with_rand_reset | i2c_host_stress_all_with_rand_reset | 44.180s | 3.322ms | 0 | 10 | 0.00 |
| V3 | target_error_intr | i2c_target_unexp_stop | 3.160s | 490.599us | 0 | 50 | 0.00 |
| V3 | target_stress_all_with_rand_reset | i2c_target_stress_all_with_rand_reset | 32.670s | 10.684ms | 0 | 10 | 0.00 |
| V3 | target_loopback | 0 | 0 | -- | |||
| V3 | TOTAL | 0 | 70 | 0.00 | |||
| TOTAL | 1857 | 2042 | 90.94 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 7 | 7 | 7 | 100.00 |
| V2 | 49 | 38 | 30 | 61.22 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 4 | 3 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 91.26 | 97.20 | 89.46 | 97.22 | 72.02 | 94.23 | 98.47 | 90.21 |
UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 42 failures:
1.i2c_host_stress_all.64240069367879294270280073741324299583894330247701608904622400878975420476656
Line 120, in log /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/1.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 35156705611 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @3136417
3.i2c_host_stress_all.8266249678992263193182405720983637223110728517393795963723550418898546818364
Line 242, in log /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/3.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 65467871676 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @2284783
... and 23 more failures.
2.i2c_host_mode_toggle.99830866393486971488201748815016206868377920700030396581726938598163541684738
Line 72, in log /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/2.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 285190177 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @38742
5.i2c_host_mode_toggle.15314144066060371072683275557130603400053421882339041719541122803113989399548
Line 72, in log /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/5.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 88558025 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @11524
... and 15 more failures.
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 32 failures:
1.i2c_target_unexp_stop.96875262686446750577319319868787044462150258727320260353735800363746500833670
Line 65, in log /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 152589984 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 140 [0x8c])
UVM_INFO @ 152589984 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_unexp_stop.56192260463287927870713891265932513432878176163656944935457952812397670700449
Line 65, in log /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/2.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 124435278 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 6 [0x6])
UVM_INFO @ 124435278 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 28 more failures.
4.i2c_target_stress_all_with_rand_reset.71873249683747512685635924913269540167364312002964672588696622678203667560649
Line 120, in log /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/4.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 339488665 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 66 [0x42])
UVM_INFO @ 339488665 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.i2c_target_stress_all_with_rand_reset.73423508331809710361566744080384560534102846800237449726766904308932403640017
Line 109, in log /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/6.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2519418949 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 228 [0xe4])
UVM_INFO @ 2519418949 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 26 failures:
1.i2c_target_hrst.99061721411099870379951978857345431105293169842448693233195023638544039470507
Line 66, in log /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/1.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10218979414 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10218979414 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_hrst.48129946554540277801068034640286348703049864773644684969193968302354408455221
Line 66, in log /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/2.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10505598696 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10505598696 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 24 more failures.
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 20 failures:
0.i2c_target_unexp_stop.94736486367756734273427041597577693241280437987047446037869932479412820629157
Line 65, in log /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 519540599 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 519540599 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.i2c_target_unexp_stop.13827304495443450959558617827943266952391828403705940175141402540346055466864
Line 65, in log /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/4.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 330126154 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 330126154 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 18 more failures.
UVM_ERROR (cip_base_vseq.sv:867) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 18 failures:
0.i2c_host_stress_all_with_rand_reset.16693860987122783799484618647709829124624086253639599786275293196261149372411
Line 73, in log /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1094949720 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1094949720 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_host_stress_all_with_rand_reset.34715077279922063935261396226965543653460919907289976118181817963429084553724
Line 76, in log /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 876942892 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 876942892 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
0.i2c_target_stress_all_with_rand_reset.22053146146702890077679204402928335163679500406922377829791393021690322504461
Line 82, in log /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 10683720783 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 10683720783 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_stress_all_with_rand_reset.42012179571711060508778511059625721198281224713118767012293458835987853796098
Line 74, in log /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 562642977 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 562642977 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 17 failures:
0.i2c_target_nack_txstretch.103117702477004529380830160405796638474082582149319288806967073937136406318391
Line 65, in log /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/0.i2c_target_nack_txstretch/latest/run.log
UVM_ERROR @ 230178224 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 230178224 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.i2c_target_nack_txstretch.65417717849767799131517965293808678741425290618071260063768813466006535111396
Line 65, in log /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/4.i2c_target_nack_txstretch/latest/run.log
UVM_ERROR @ 148003032 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 148003032 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 15 more failures.
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 8 failures:
4.i2c_host_mode_toggle.2461514326925081438421714972782114516396338312530876580655390658427239470455
Line 74, in log /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/4.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 95883436 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
11.i2c_host_mode_toggle.28372188871258467129144143838375401118815501521318746417932634772892143638382
Line 74, in log /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/11.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 255183618 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
... and 6 more failures.
Job timed out after * minutes has 6 failures:
0.i2c_host_stress_all.44199634037955167180762329192039913580063535015016896003444886427138297416569
Log /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log
Job timed out after 60 minutes
12.i2c_host_stress_all.46538397130435749761364483917233594350294199760547472056867667866989864781438
Log /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/12.i2c_host_stress_all/latest/run.log
Job timed out after 60 minutes
... and 4 more failures.
UVM_ERROR (i2c_scoreboard.sv:717) [scoreboard] controller_mode_wr_obs_fifo item uncompared: has 4 failures:
10.i2c_host_stress_all.94363854795482932908690507232107928022430496010945576991334113271440754893253
Line 141, in log /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/10.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 81489748881 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @13996149
14.i2c_host_stress_all.76962339955302717749038668402647546594006612481896363166744734158995170414089
Line 205, in log /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/14.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 41703430435 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @2688579
... and 2 more failures.
UVM_FATAL (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 3 failures:
0.i2c_host_mode_toggle.77258322674743704546982792613709102001280937419059883170586383721240762914145
Line 66, in log /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log
UVM_FATAL @ 143419406 ps: (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0x8538a294, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 143419406 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
16.i2c_host_mode_toggle.12411493805508578049006101548815781026283034012028532346877756295810656992397
Line 66, in log /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/16.i2c_host_mode_toggle/latest/run.log
UVM_FATAL @ 30221313 ps: (csr_utils_pkg.sv:584) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0xfe4aaa14, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 30221313 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Error-[CNST-CIF] Constraints inconsistency failure has 3 failures:
Test i2c_target_tx_stretch_ctrl has 2 failures.
7.i2c_target_tx_stretch_ctrl.25522922300819191007464214961585964604048354855646839619639789072214598794716
Line 117, in log /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/7.i2c_target_tx_stretch_ctrl/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
19.i2c_target_tx_stretch_ctrl.33021871229400697090360653331041624494565715913109449785572322895701499773187
Line 111, in log /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/19.i2c_target_tx_stretch_ctrl/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
Test i2c_target_fifo_watermarks_tx has 1 failures.
36.i2c_target_fifo_watermarks_tx.85494017679760824460363827924727558716202897368168498105760420997860076707418
Line 108, in log /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/36.i2c_target_fifo_watermarks_tx/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 845
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred! has 3 failures:
12.i2c_target_stretch.20974437004575406986305273784023189332987797049239578646567299499613813720721
Line 65, in log /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/12.i2c_target_stretch/latest/run.log
UVM_FATAL @ 10002425771 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
UVM_INFO @ 10002425771 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
20.i2c_target_stretch.18201990711093944491092589656591795887862204360668610280534937247274213105604
Line 65, in log /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/20.i2c_target_stretch/latest/run.log
UVM_FATAL @ 10012267909 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
UVM_INFO @ 10012267909 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred! has 2 failures:
6.i2c_target_stress_all.46201150726703383922460362575913668624743446738622956170653373800558338664360
Line 92, in log /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/6.i2c_target_stress_all/latest/run.log
UVM_FATAL @ 60126472878 ps: (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!
UVM_INFO @ 60126472878 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
21.i2c_target_stress_all.11025490089892780984733041664029416656256648625330321147444738991775211710360
Line 84, in log /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/21.i2c_target_stress_all/latest/run.log
UVM_FATAL @ 60221530747 ps: (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!
UVM_INFO @ 60221530747 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Error-[NOA] Null object access has 1 failures:
1.i2c_host_mode_toggle.110283791879592252676112194890249946408070924739668901513118600657301873170196
Line 73, in log /workspaces/repo/scratch/os_regression_2024_09_17/i2c-sim-vcs/1.i2c_host_mode_toggle/latest/run.log
Error-[NOA] Null object access
../src/lowrisc_dv_i2c_env_0.1/i2c_reference_model.sv, 584
The object at dereference depth 0 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.