8a1401d614| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | host_smoke | i2c_host_smoke | 1.732m | 2.293ms | 50 | 50 | 100.00 |
| V1 | target_smoke | i2c_target_smoke | 49.260s | 9.687ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | i2c_csr_hw_reset | 1.070s | 77.563us | 5 | 5 | 100.00 |
| V1 | csr_rw | i2c_csr_rw | 1.150s | 29.985us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | i2c_csr_bit_bash | 5.610s | 707.159us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | i2c_csr_aliasing | 2.760s | 396.626us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | i2c_csr_mem_rw_with_rand_reset | 2.070s | 58.207us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | i2c_csr_rw | 1.150s | 29.985us | 20 | 20 | 100.00 |
| i2c_csr_aliasing | 2.760s | 396.626us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 155 | 155 | 100.00 | |||
| V2 | host_error_intr | i2c_host_error_intr | 26.210s | 3.076ms | 49 | 50 | 98.00 |
| V2 | host_stress_all | i2c_host_stress_all | 34.730m | 600.000ms | 15 | 50 | 30.00 |
| V2 | host_maxperf | i2c_host_perf | 27.429m | 50.153ms | 50 | 50 | 100.00 |
| V2 | host_override | i2c_host_override | 1.160s | 27.642us | 50 | 50 | 100.00 |
| V2 | host_fifo_watermark | i2c_host_fifo_watermark | 5.096m | 21.519ms | 50 | 50 | 100.00 |
| V2 | host_fifo_overflow | i2c_host_fifo_overflow | 3.164m | 9.509ms | 50 | 50 | 100.00 |
| V2 | host_fifo_reset | i2c_host_fifo_reset_fmt | 2.220s | 616.528us | 50 | 50 | 100.00 |
| i2c_host_fifo_fmt_empty | 26.440s | 2.945ms | 50 | 50 | 100.00 | ||
| i2c_host_fifo_reset_rx | 16.930s | 1.497ms | 50 | 50 | 100.00 | ||
| V2 | host_fifo_full | i2c_host_fifo_full | 3.903m | 45.936ms | 50 | 50 | 100.00 |
| V2 | host_timeout | i2c_host_stretch_timeout | 48.950s | 2.043ms | 50 | 50 | 100.00 |
| V2 | host_rx_oversample | i2c_host_rx_oversample | 0 | 0 | -- | ||
| V2 | i2c_host_mode_toggle | i2c_host_mode_toggle | 7.300s | 600.393us | 17 | 50 | 34.00 |
| V2 | target_glitch | i2c_target_glitch | 16.660s | 6.879ms | 2 | 2 | 100.00 |
| V2 | target_stress_all | i2c_target_stress_all | 30.251m | 66.535ms | 49 | 50 | 98.00 |
| V2 | target_maxperf | i2c_target_perf | 11.990s | 4.540ms | 50 | 50 | 100.00 |
| V2 | target_fifo_empty | i2c_target_stress_rd | 1.483m | 9.918ms | 50 | 50 | 100.00 |
| i2c_target_intr_smoke | 15.100s | 12.984ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_reset | i2c_target_fifo_reset_acq | 3.230s | 306.210us | 50 | 50 | 100.00 |
| i2c_target_fifo_reset_tx | 3.000s | 963.870us | 50 | 50 | 100.00 | ||
| V2 | target_fifo_full | i2c_target_stress_wr | 19.786m | 59.792ms | 50 | 50 | 100.00 |
| i2c_target_stress_rd | 1.483m | 9.918ms | 50 | 50 | 100.00 | ||
| i2c_target_intr_stress_wr | 6.557m | 26.087ms | 50 | 50 | 100.00 | ||
| V2 | target_timeout | i2c_target_timeout | 13.490s | 1.408ms | 50 | 50 | 100.00 |
| V2 | target_clock_stretch | i2c_target_stretch | 2.739m | 3.811ms | 41 | 50 | 82.00 |
| V2 | bad_address | i2c_target_bad_addr | 11.960s | 5.381ms | 49 | 50 | 98.00 |
| V2 | target_mode_glitch | i2c_target_hrst | 59.920s | 10.103ms | 24 | 50 | 48.00 |
| V2 | target_fifo_watermark | i2c_target_fifo_watermarks_acq | 5.890s | 665.203us | 50 | 50 | 100.00 |
| i2c_target_fifo_watermarks_tx | 2.680s | 316.808us | 49 | 50 | 98.00 | ||
| V2 | host_mode_config_perf | i2c_host_perf | 27.429m | 50.153ms | 50 | 50 | 100.00 |
| i2c_host_perf_precise | 9.691m | 23.153ms | 50 | 50 | 100.00 | ||
| V2 | host_mode_clock_stretching | i2c_host_stretch_timeout | 48.950s | 2.043ms | 50 | 50 | 100.00 |
| V2 | target_mode_tx_stretch_ctrl | i2c_target_tx_stretch_ctrl | 41.800s | 1.868ms | 49 | 50 | 98.00 |
| V2 | target_mode_nack_generation | i2c_target_nack_acqfull | 5.850s | 563.039us | 50 | 50 | 100.00 |
| i2c_target_nack_acqfull_addr | 5.580s | 536.633us | 50 | 50 | 100.00 | ||
| i2c_target_nack_txstretch | 2.960s | 354.340us | 37 | 50 | 74.00 | ||
| V2 | host_mode_halt_on_nak | i2c_host_may_nack | 35.130s | 7.346ms | 50 | 50 | 100.00 |
| V2 | target_mode_n_byte_ack_control | target_mode_n_byte_ack_control | 0 | 0 | -- | ||
| V2 | target_mode_bus_timeout | target_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_timeout | controller_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_idle_delay | controller_mode_bus_idle_delay | 0 | 0 | -- | ||
| V2 | loopback_test | loopback_test | 0 | 0 | -- | ||
| V2 | multi_controller_clock_synchronization | multi_controller_clock_synchronization | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost_interference | multi_controller_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost | multi_controller_arbitration_lost | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost_interference | target_mode_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost | target_mode_arbitration_lost | 0 | 0 | -- | ||
| V2 | target_mode_smbus_maxlen | i2c_target_smbus_maxlen | 5.280s | 591.348us | 50 | 50 | 100.00 |
| V2 | alert_test | i2c_alert_test | 1.050s | 44.149us | 50 | 50 | 100.00 |
| V2 | intr_test | i2c_intr_test | 1.020s | 17.313us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | i2c_tl_errors | 3.160s | 252.193us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | i2c_tl_errors | 3.160s | 252.193us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | i2c_csr_hw_reset | 1.070s | 77.563us | 5 | 5 | 100.00 |
| i2c_csr_rw | 1.150s | 29.985us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 2.760s | 396.626us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.460s | 56.367us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | i2c_csr_hw_reset | 1.070s | 77.563us | 5 | 5 | 100.00 |
| i2c_csr_rw | 1.150s | 29.985us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 2.760s | 396.626us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.460s | 56.367us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 1671 | 1792 | 93.25 | |||
| V2S | tl_intg_err | i2c_tl_intg_err | 2.750s | 85.496us | 20 | 20 | 100.00 |
| i2c_sec_cm | 1.560s | 64.065us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | i2c_tl_intg_err | 2.750s | 85.496us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | host_stress_all_with_rand_reset | i2c_host_stress_all_with_rand_reset | 1.013m | 16.512ms | 0 | 10 | 0.00 |
| V3 | target_error_intr | i2c_target_unexp_stop | 4.080s | 413.262us | 0 | 50 | 0.00 |
| V3 | target_stress_all_with_rand_reset | i2c_target_stress_all_with_rand_reset | 1.002m | 3.210ms | 0 | 10 | 0.00 |
| V3 | target_loopback | 0 | 0 | -- | |||
| V3 | TOTAL | 0 | 70 | 0.00 | |||
| TOTAL | 1851 | 2042 | 90.65 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 7 | 7 | 7 | 100.00 |
| V2 | 49 | 38 | 28 | 57.14 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 4 | 3 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 91.28 | 97.26 | 89.57 | 97.22 | 72.02 | 94.30 | 98.47 | 90.11 |
UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 44 failures:
0.i2c_host_mode_toggle.111999206286372789834822874972470126682608176915802459301534100473177350626452
Line 72, in log /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 495823987 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @118036
5.i2c_host_mode_toggle.70604141757438583296773393241709378920626312583758844540514123569655471059500
Line 72, in log /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/5.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 126311312 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @85270
... and 13 more failures.
1.i2c_host_stress_all.40560248379241425443604726997372555126683330689235700951571736710433410069142
Line 137, in log /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/1.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 18368959113 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @12004557
2.i2c_host_stress_all.28311610940770233023006277277431469997200310865360234045650457106437354077465
Line 192, in log /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/2.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 10379693997 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @3051989
... and 27 more failures.
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 28 failures:
1.i2c_target_unexp_stop.44570976547304544378685247188874256847199796625713874741247688754578630038708
Line 65, in log /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 198927522 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 28 [0x1c])
UVM_INFO @ 198927522 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_unexp_stop.6228662883084392904847541403150371053533391933471632560951578941205526541050
Line 65, in log /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/2.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 117686549 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 111 [0x6f])
UVM_INFO @ 117686549 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 25 more failures.
5.i2c_target_stress_all_with_rand_reset.88207794134027999140980110648482636490412749648332912588559250016610693572614
Line 83, in log /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/5.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 89335478 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 45 [0x2d])
UVM_INFO @ 89335478 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 26 failures:
0.i2c_target_hrst.58972506584562681072485979295838275538323445547196757717243193362904083699314
Line 66, in log /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10205269080 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10205269080 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_hrst.44645513203966867168950566524604992268483161698435721225143410553065821803776
Line 66, in log /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/1.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10153120608 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10153120608 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 24 more failures.
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 16 failures:
0.i2c_target_unexp_stop.112855772397140230573107906598193359360840432834340147948667493657740857092746
Line 65, in log /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 411979773 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 411979773 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.i2c_target_unexp_stop.101795918816448891619200547463243236687829530525792756986755238215261660919018
Line 65, in log /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/7.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 324064922 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 324064922 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 14 more failures.
UVM_ERROR (cip_base_vseq.sv:867) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 15 failures:
0.i2c_host_stress_all_with_rand_reset.54551262441757049978019177516364686275012469797244986192269467755475479710820
Line 86, in log /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 17064596449 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 17064596449 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_host_stress_all_with_rand_reset.111816013999550798791723871669817962459558279943775532564833284206355520852324
Line 74, in log /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 611876486 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 611876486 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
1.i2c_target_stress_all_with_rand_reset.90221822210390702565871251225976918014053415276344038497728723437170167496129
Line 79, in log /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 382979857 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 382979857 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.i2c_target_stress_all_with_rand_reset.113233346687998275990891674176081624431339673628707935007216757508515603589481
Line 128, in log /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 14591267323 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 14591267323 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 15 failures:
2.i2c_host_mode_toggle.113451784855636611538851964375456491782543669757065868187981514860988180984632
Line 74, in log /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/2.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 20872654 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
3.i2c_host_mode_toggle.99674095565858566574638770027444772104677741448851182852306169280810477011595
Line 74, in log /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/3.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 150720436 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
... and 13 more failures.
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 13 failures:
0.i2c_target_nack_txstretch.83928333886175113299567698790886833433456912139361695666099237909755583082119
Line 65, in log /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/0.i2c_target_nack_txstretch/latest/run.log
UVM_ERROR @ 1396135711 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 1396135711 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.i2c_target_nack_txstretch.67021166745575566572575655167639338220475646001289884713144427540265183116004
Line 65, in log /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/3.i2c_target_nack_txstretch/latest/run.log
UVM_ERROR @ 162071519 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 162071519 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 11 more failures.
UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred! has 9 failures:
2.i2c_target_stretch.3498944054947445115707396648419971759118771563776140794542982566884283455763
Line 65, in log /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/2.i2c_target_stretch/latest/run.log
UVM_FATAL @ 10002338113 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
UVM_INFO @ 10002338113 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.i2c_target_stretch.72929900598822673941377694603036714165066998637817360149608048498460091882792
Line 65, in log /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/3.i2c_target_stretch/latest/run.log
UVM_FATAL @ 10024745806 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
UVM_INFO @ 10024745806 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 7 failures:
3.i2c_target_unexp_stop.21855419241751399409949509075952701375770269435877448831148940196156100424109
Line 66, in log /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/3.i2c_target_unexp_stop/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 666156265 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 666156265 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
12.i2c_target_unexp_stop.33530537537643030902739082884514429133840469012312191381811928508553525118767
Line 66, in log /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/12.i2c_target_unexp_stop/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 206252106 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 206252106 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
UVM_ERROR (i2c_scoreboard.sv:717) [scoreboard] controller_mode_wr_obs_fifo item uncompared: has 3 failures:
0.i2c_host_stress_all.113103843674809450404976354862005355451055838299349890635200712872569195610497
Line 209, in log /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 93559070673 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @6823025
15.i2c_host_stress_all.12103800448858204695039509334076227625984981859222457297353308705627949397619
Line 262, in log /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/15.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 49283708685 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @8550843
... and 1 more failures.
Job timed out after * minutes has 3 failures:
Test i2c_host_error_intr has 1 failures.
2.i2c_host_error_intr.40343260319458280405917115120152206591716187990700312726375084352811500597364
Log /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/2.i2c_host_error_intr/latest/run.log
Job timed out after 60 minutes
Test i2c_host_stress_all has 2 failures.
11.i2c_host_stress_all.23691928378448735516498420237426975527324850719909035357686052883050191321091
Log /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/11.i2c_host_stress_all/latest/run.log
Job timed out after 60 minutes
35.i2c_host_stress_all.88551136422970382300438390635203618411021361398956329402070527040149334407457
Log /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/35.i2c_host_stress_all/latest/run.log
Job timed out after 60 minutes
UVM_ERROR (cip_base_vseq.sv:771) [i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 3 failures:
2.i2c_target_stress_all_with_rand_reset.49418537847495523247380192552369539829488708116778545051085680611864771173030
Line 80, in log /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 3948095444 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 3948095444 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.i2c_target_stress_all_with_rand_reset.22949840556956113493889975451209599755465009855161178796832086607543862291578
Line 115, in log /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/4.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1339388141 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1339388141 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 3 failures:
4.i2c_host_mode_toggle.64768157692459825051200833382973222395924927014347142432085729593233582504081
Line 66, in log /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/4.i2c_host_mode_toggle/latest/run.log
UVM_FATAL @ 86018327 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0x1e69ee14, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 86018327 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
15.i2c_host_mode_toggle.102652315528045672477963364191379420007045063410207854217507198042638108228844
Line 66, in log /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/15.i2c_host_mode_toggle/latest/run.log
UVM_FATAL @ 34421379 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0xba5a2694, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 34421379 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Error-[CNST-CIF] Constraints inconsistency failure has 2 failures:
Test i2c_target_tx_stretch_ctrl has 1 failures.
9.i2c_target_tx_stretch_ctrl.4614705124934051040211474093887002358095342110106531702258211838984571374581
Line 119, in log /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/9.i2c_target_tx_stretch_ctrl/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
Test i2c_target_fifo_watermarks_tx has 1 failures.
41.i2c_target_fifo_watermarks_tx.33585007839812966381585283632594029345853337057665131378089147199955149936746
Line 108, in log /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/41.i2c_target_fifo_watermarks_tx/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 845
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
Test i2c_target_bad_addr has 1 failures.
28.i2c_target_bad_addr.42452844537524436147419286779180010395864575322577585987091712266163914264548
Line 65, in log /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/28.i2c_target_bad_addr/latest/run.log
UVM_FATAL @ 20000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 20000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 20000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test i2c_host_stress_all has 1 failures.
46.i2c_host_stress_all.80972475613543833435313813942814826115076857867959246141257852731017183713402
Line 195, in log /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/46.i2c_host_stress_all/latest/run.log
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_base_vseq.sv:760) [i2c_target_smoke_vseq] Check failed (cfg.m_i2c_agent_cfg.rcvd_rd_byte == *) has 1 failures:
0.i2c_target_stress_all_with_rand_reset.101167570250227677095967808574513999453803582557452196272144928195417093673202
Line 105, in log /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 306186566 ps: (i2c_base_vseq.sv:760) [uvm_test_top.env.virtual_sequencer.i2c_target_smoke_vseq] Check failed (cfg.m_i2c_agent_cfg.rcvd_rd_byte == 0)
UVM_INFO @ 306186566 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred! has 1 failures:
23.i2c_target_stress_all.27792324017243442989121012075594125501099574331740063822167457475178032984385
Line 76, in log /workspaces/repo/scratch/os_regression_2024_10_11/i2c-sim-vcs/23.i2c_target_stress_all/latest/run.log
UVM_FATAL @ 28343112643 ps: (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!
UVM_INFO @ 28343112643 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---