78ad89d1aa| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | host_smoke | i2c_host_smoke | 1.567m | 13.572ms | 50 | 50 | 100.00 |
| V1 | target_smoke | i2c_target_smoke | 51.120s | 1.325ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | i2c_csr_hw_reset | 1.200s | 18.878us | 5 | 5 | 100.00 |
| V1 | csr_rw | i2c_csr_rw | 16.210s | 13.601ms | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | i2c_csr_bit_bash | 7.070s | 1.393ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | i2c_csr_aliasing | 2.630s | 75.643us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | i2c_csr_mem_rw_with_rand_reset | 2.210s | 102.840us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | i2c_csr_rw | 16.210s | 13.601ms | 20 | 20 | 100.00 |
| i2c_csr_aliasing | 2.630s | 75.643us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 155 | 155 | 100.00 | |||
| V2 | host_error_intr | i2c_host_error_intr | 12.960s | 630.144us | 31 | 50 | 62.00 |
| V2 | host_stress_all | i2c_host_stress_all | 38.278m | 29.752ms | 11 | 50 | 22.00 |
| V2 | host_maxperf | i2c_host_perf | 38.638m | 49.057ms | 50 | 50 | 100.00 |
| V2 | host_override | i2c_host_override | 1.180s | 28.572us | 50 | 50 | 100.00 |
| V2 | host_fifo_watermark | i2c_host_fifo_watermark | 4.922m | 5.150ms | 50 | 50 | 100.00 |
| V2 | host_fifo_overflow | i2c_host_fifo_overflow | 2.719m | 5.166ms | 50 | 50 | 100.00 |
| V2 | host_fifo_reset | i2c_host_fifo_reset_fmt | 2.620s | 201.771us | 50 | 50 | 100.00 |
| i2c_host_fifo_fmt_empty | 43.030s | 707.485us | 50 | 50 | 100.00 | ||
| i2c_host_fifo_reset_rx | 16.070s | 226.652us | 50 | 50 | 100.00 | ||
| V2 | host_fifo_full | i2c_host_fifo_full | 4.188m | 6.624ms | 50 | 50 | 100.00 |
| V2 | host_timeout | i2c_host_stretch_timeout | 47.300s | 1.602ms | 50 | 50 | 100.00 |
| V2 | host_rx_oversample | i2c_host_rx_oversample | 0 | 0 | -- | ||
| V2 | i2c_host_mode_toggle | i2c_host_mode_toggle | 7.350s | 308.606us | 17 | 50 | 34.00 |
| V2 | target_glitch | i2c_target_glitch | 16.150s | 10.435ms | 2 | 2 | 100.00 |
| V2 | target_stress_all | i2c_target_stress_all | 29.551m | 80.569ms | 50 | 50 | 100.00 |
| V2 | target_maxperf | i2c_target_perf | 13.000s | 7.825ms | 50 | 50 | 100.00 |
| V2 | target_fifo_empty | i2c_target_stress_rd | 1.313m | 4.384ms | 50 | 50 | 100.00 |
| i2c_target_intr_smoke | 14.250s | 2.517ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_reset | i2c_target_fifo_reset_acq | 2.970s | 450.033us | 50 | 50 | 100.00 |
| i2c_target_fifo_reset_tx | 3.540s | 277.799us | 50 | 50 | 100.00 | ||
| V2 | target_fifo_full | i2c_target_stress_wr | 25.371m | 63.626ms | 50 | 50 | 100.00 |
| i2c_target_stress_rd | 1.313m | 4.384ms | 50 | 50 | 100.00 | ||
| i2c_target_intr_stress_wr | 8.413m | 34.216ms | 49 | 50 | 98.00 | ||
| V2 | target_timeout | i2c_target_timeout | 14.620s | 1.298ms | 50 | 50 | 100.00 |
| V2 | target_clock_stretch | i2c_target_stretch | 2.029m | 2.858ms | 43 | 50 | 86.00 |
| V2 | bad_address | i2c_target_bad_addr | 14.440s | 1.614ms | 50 | 50 | 100.00 |
| V2 | target_mode_glitch | i2c_target_hrst | 54.180s | 10.093ms | 22 | 50 | 44.00 |
| V2 | target_fifo_watermark | i2c_target_fifo_watermarks_acq | 6.230s | 1.322ms | 50 | 50 | 100.00 |
| i2c_target_fifo_watermarks_tx | 2.820s | 358.102us | 49 | 50 | 98.00 | ||
| V2 | host_mode_config_perf | i2c_host_perf | 38.638m | 49.057ms | 50 | 50 | 100.00 |
| i2c_host_perf_precise | 2.567m | 23.148ms | 50 | 50 | 100.00 | ||
| V2 | host_mode_clock_stretching | i2c_host_stretch_timeout | 47.300s | 1.602ms | 50 | 50 | 100.00 |
| V2 | target_mode_tx_stretch_ctrl | i2c_target_tx_stretch_ctrl | 51.700s | 2.332ms | 46 | 50 | 92.00 |
| V2 | target_mode_nack_generation | i2c_target_nack_acqfull | 6.050s | 2.382ms | 50 | 50 | 100.00 |
| i2c_target_nack_acqfull_addr | 6.200s | 3.090ms | 50 | 50 | 100.00 | ||
| i2c_target_nack_txstretch | 2.940s | 135.482us | 39 | 50 | 78.00 | ||
| V2 | host_mode_halt_on_nak | i2c_host_may_nack | 31.990s | 2.358ms | 50 | 50 | 100.00 |
| V2 | target_mode_n_byte_ack_control | target_mode_n_byte_ack_control | 0 | 0 | -- | ||
| V2 | target_mode_bus_timeout | target_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_timeout | controller_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_idle_delay | controller_mode_bus_idle_delay | 0 | 0 | -- | ||
| V2 | loopback_test | loopback_test | 0 | 0 | -- | ||
| V2 | multi_controller_clock_synchronization | multi_controller_clock_synchronization | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost_interference | multi_controller_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost | multi_controller_arbitration_lost | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost_interference | target_mode_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost | target_mode_arbitration_lost | 0 | 0 | -- | ||
| V2 | target_mode_smbus_maxlen | i2c_target_smbus_maxlen | 5.110s | 587.537us | 50 | 50 | 100.00 |
| V2 | alert_test | i2c_alert_test | 1.060s | 31.232us | 50 | 50 | 100.00 |
| V2 | intr_test | i2c_intr_test | 1.160s | 19.758us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | i2c_tl_errors | 4.380s | 507.142us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | i2c_tl_errors | 4.380s | 507.142us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | i2c_csr_hw_reset | 1.200s | 18.878us | 5 | 5 | 100.00 |
| i2c_csr_rw | 16.210s | 13.601ms | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 2.630s | 75.643us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.790s | 62.698us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | i2c_csr_hw_reset | 1.200s | 18.878us | 5 | 5 | 100.00 |
| i2c_csr_rw | 16.210s | 13.601ms | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 2.630s | 75.643us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.790s | 62.698us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 1649 | 1792 | 92.02 | |||
| V2S | tl_intg_err | i2c_tl_intg_err | 3.480s | 462.968us | 20 | 20 | 100.00 |
| i2c_sec_cm | 1.720s | 123.375us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | i2c_tl_intg_err | 3.480s | 462.968us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | host_stress_all_with_rand_reset | i2c_host_stress_all_with_rand_reset | 38.410s | 2.931ms | 0 | 10 | 0.00 |
| V3 | target_error_intr | i2c_target_unexp_stop | 5.360s | 435.366us | 0 | 50 | 0.00 |
| V3 | target_stress_all_with_rand_reset | i2c_target_stress_all_with_rand_reset | 47.700s | 10.235ms | 0 | 10 | 0.00 |
| V3 | target_loopback | 0 | 0 | -- | |||
| V3 | TOTAL | 0 | 70 | 0.00 | |||
| TOTAL | 1829 | 2042 | 89.57 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 7 | 7 | 7 | 100.00 |
| V2 | 49 | 38 | 29 | 59.18 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 4 | 3 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 91.26 | 97.26 | 89.54 | 97.22 | 72.02 | 94.30 | 98.47 | 90.00 |
UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 36 failures:
0.i2c_host_stress_all.54103635834666799801138289323151116509269704556583292007299037750276036177902
Line 214, in log /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 42136227026 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @14616357
2.i2c_host_stress_all.79479181192408030371788868536945977962618411135201275370339297691433943666654
Line 201, in log /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/2.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 10094201689 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @10868247
... and 14 more failures.
2.i2c_host_mode_toggle.20054374409375289164509798136270911280643718020932307895240422441833164961697
Line 72, in log /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/2.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 147494365 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @13840
3.i2c_host_mode_toggle.44256340705822436639925531415641625420728154185648486278382305351906483783018
Line 72, in log /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/3.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 96092291 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @56648
... and 18 more failures.
UVM_ERROR (tl_host_driver.sv:67) [driver] Check failed cfg.a_source_pend_q.size() == * (* [*] vs * [*]) has 35 failures:
1.i2c_host_error_intr.106803987495633304566265553296919534719577591897639356622861527448508052730264
Line 77, in log /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/1.i2c_host_error_intr/latest/run.log
UVM_ERROR @ 3302479 ps: (tl_host_driver.sv:67) [uvm_test_top.env.m_tl_agent_i2c_reg_block.driver] Check failed cfg.a_source_pend_q.size() == 0 (1 [0x1] vs 0 [0x0])
UVM_INFO @ 3302479 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_host_error_intr.91991954314364109331531839710828911300943507290684723845601205996524960543232
Line 77, in log /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/2.i2c_host_error_intr/latest/run.log
UVM_ERROR @ 17625677 ps: (tl_host_driver.sv:67) [uvm_test_top.env.m_tl_agent_i2c_reg_block.driver] Check failed cfg.a_source_pend_q.size() == 0 (1 [0x1] vs 0 [0x0])
UVM_INFO @ 17625677 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 16 more failures.
3.i2c_host_stress_all.94073422900921941688401671628642657105311846588275673429898931323637250926969
Line 157, in log /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/3.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 29567209404 ps: (tl_host_driver.sv:67) [uvm_test_top.env.m_tl_agent_i2c_reg_block.driver] Check failed cfg.a_source_pend_q.size() == 0 (1 [0x1] vs 0 [0x0])
UVM_INFO @ 29567209404 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.i2c_host_stress_all.96012336811133870166050452260770188555114628933521995150931455782482319699818
Line 135, in log /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/4.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 23823268613 ps: (tl_host_driver.sv:67) [uvm_test_top.env.m_tl_agent_i2c_reg_block.driver] Check failed cfg.a_source_pend_q.size() == 0 (1 [0x1] vs 0 [0x0])
UVM_INFO @ 23823268613 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 15 more failures.
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 28 failures:
0.i2c_target_hrst.75074268331997302896574691579530488486172175903555296289536687402312996097880
Line 66, in log /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10555918726 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10555918726 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.i2c_target_hrst.107048047806526261933418006998471254201562215100251840274954702347192439696118
Line 66, in log /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/4.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10089909188 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10089909188 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 26 more failures.
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 27 failures:
0.i2c_target_unexp_stop.538943399299418916591390083367884484337430434302253403670088543627919020778
Line 65, in log /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 227267841 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 182 [0xb6])
UVM_INFO @ 227267841 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.i2c_target_unexp_stop.97655382319879751234958483553275516471913985274014665212854385993600893593991
Line 65, in log /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/4.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 300573104 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 53 [0x35])
UVM_INFO @ 300573104 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 22 more failures.
2.i2c_target_stress_all_with_rand_reset.27846157002609204663224683353954786604345950986688390252318883482756339223528
Line 83, in log /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 106924512 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 253 [0xfd])
UVM_INFO @ 106924512 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.i2c_target_stress_all_with_rand_reset.111853242309254263255080686830734948187058225998844441721219267244599757499501
Line 89, in log /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/6.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1313219935 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 2 [0x2])
UVM_INFO @ 1313219935 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 21 failures:
1.i2c_target_unexp_stop.42204931900026769064842132751654638782555518626049302959526428601155033506921
Line 65, in log /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 181495047 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 181495047 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_unexp_stop.47942771838369807182077818744360660215790038368117468440496515491463042145638
Line 65, in log /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/2.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 78224572 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 78224572 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 19 more failures.
UVM_ERROR (cip_base_vseq.sv:867) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 14 failures:
0.i2c_host_stress_all_with_rand_reset.92065510477823255017373106648272914097058040067125793951437375368384573371454
Line 71, in log /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 103177924 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 103177924 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_host_stress_all_with_rand_reset.28970768275246079173325098724041450997574994650867015068429463812602376455070
Line 97, in log /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 4403080255 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 4403080255 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
0.i2c_target_stress_all_with_rand_reset.75639637432722470888794136521477771709693979171292945532350597818577939100272
Line 79, in log /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 856852932 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 856852932 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_stress_all_with_rand_reset.69165859716354265350981828211052711933168181321497668912246906335926771295705
Line 79, in log /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 3874207325 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3874207325 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 12 failures:
1.i2c_host_mode_toggle.9427124993073236881069908716865473595249960642457039138072023750886777011689
Line 74, in log /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/1.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 72401709 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
5.i2c_host_mode_toggle.73419331753766918652540591473648663614182655521201827024484067999191579181190
Line 74, in log /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/5.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 502881884 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
... and 10 more failures.
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 11 failures:
0.i2c_target_nack_txstretch.97528237935088354007957286252737083046615028492654824220558507264202443935921
Line 65, in log /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/0.i2c_target_nack_txstretch/latest/run.log
UVM_ERROR @ 513867525 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 513867525 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_nack_txstretch.30158810419656002156679892154070177710723357381184143947628562096527747608947
Line 65, in log /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/2.i2c_target_nack_txstretch/latest/run.log
UVM_ERROR @ 155810724 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 155810724 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 9 more failures.
UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred! has 7 failures:
10.i2c_target_stretch.67621940625637246264080450919422086020236728534570130027117990860979204940622
Line 65, in log /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/10.i2c_target_stretch/latest/run.log
UVM_FATAL @ 10012196175 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
UVM_INFO @ 10012196175 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
11.i2c_target_stretch.14192657129601357742037833266949526672475375582327833684348108179280181079106
Line 65, in log /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/11.i2c_target_stretch/latest/run.log
UVM_FATAL @ 10031816614 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
UVM_INFO @ 10031816614 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
Error-[CNST-CIF] Constraints inconsistency failure has 5 failures:
Test i2c_target_fifo_watermarks_tx has 1 failures.
5.i2c_target_fifo_watermarks_tx.33200049187200796431271367318564432207293511013310241634567995661851146868688
Line 108, in log /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/5.i2c_target_fifo_watermarks_tx/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 845
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
Test i2c_target_tx_stretch_ctrl has 4 failures.
7.i2c_target_tx_stretch_ctrl.84028797371244406073491683806341449636502535484362189237490958848558704477302
Line 117, in log /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/7.i2c_target_tx_stretch_ctrl/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
22.i2c_target_tx_stretch_ctrl.77451216606207327532184700809111520849335535267896004000746606047596939386697
Line 117, in log /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/22.i2c_target_tx_stretch_ctrl/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
... and 2 more failures.
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 5 failures:
29.i2c_target_unexp_stop.86999706766976514238915937582570523692942014341034956645919324711845325049447
Line 66, in log /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/29.i2c_target_unexp_stop/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 636726853 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 636726853 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
33.i2c_target_unexp_stop.111334559019525789560538356293485496681288523459839196253342960143875915349448
Line 66, in log /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/33.i2c_target_unexp_stop/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 293789566 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 293789566 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
Job timed out after * minutes has 4 failures:
1.i2c_host_stress_all.59636953768547185017383504962829061468174185924933828679578053628591171910878
Log /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/1.i2c_host_stress_all/latest/run.log
Job timed out after 60 minutes
37.i2c_host_stress_all.94335862121952366258596755575656954444122016359671468298847934706292911283996
Log /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/37.i2c_host_stress_all/latest/run.log
Job timed out after 60 minutes
... and 1 more failures.
47.i2c_host_error_intr.36942434946435007631269948485385778011089550513427782810950224893536353981506
Log /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/47.i2c_host_error_intr/latest/run.log
Job timed out after 60 minutes
UVM_ERROR (i2c_scoreboard.sv:717) [scoreboard] controller_mode_wr_obs_fifo item uncompared: has 3 failures:
6.i2c_host_stress_all.111623689772203753940115426605782466034502627985473812846533060265565016803878
Line 270, in log /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/6.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 19387982515 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @21070839
18.i2c_host_stress_all.37769515640445003815077504060484124899380889084689910163277938174127516824898
Line 157, in log /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/18.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 135773655377 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @13804085
... and 1 more failures.
UVM_ERROR (cip_base_vseq.sv:771) [i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 2 failures:
3.i2c_target_stress_all_with_rand_reset.83406567153628671777157030459322894627945466274532535327303999317228458870283
Line 74, in log /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 638050919 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 638050919 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.i2c_target_stress_all_with_rand_reset.50607236143989564771139188370621758361878355033448855931369347329681708672598
Line 70, in log /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/7.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 348021484 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 348021484 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_base_vseq.sv:760) [i2c_target_timeout_vseq] Check failed (cfg.m_i2c_agent_cfg.rcvd_rd_byte == *) has 1 failures:
4.i2c_target_stress_all_with_rand_reset.108714168763036426434385554212137228621859341035739170359056960614015859900594
Line 83, in log /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/4.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 29273738 ps: (i2c_base_vseq.sv:760) [uvm_test_top.env.virtual_sequencer.i2c_target_timeout_vseq] Check failed (cfg.m_i2c_agent_cfg.rcvd_rd_byte == 0)
UVM_INFO @ 29273738 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred! has 1 failures:
5.i2c_target_intr_stress_wr.80693158105235279114775490559416403736744185046262925537435866070256474726105
Line 65, in log /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/5.i2c_target_intr_stress_wr/latest/run.log
UVM_FATAL @ 51244153511 ps: (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!
UVM_INFO @ 51244153511 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:608) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 1 failures:
45.i2c_host_mode_toggle.48783952684756116970237374286489591172215407517580778247937067877801490264857
Line 66, in log /workspaces/repo/scratch/os_regression_2024_09_23/i2c-sim-vcs/45.i2c_host_mode_toggle/latest/run.log
UVM_FATAL @ 37276378 ps: (csr_utils_pkg.sv:608) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0xe7af3494, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 37276378 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---