1cb1c3d135| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | host_smoke | i2c_host_smoke | 1.952m | 2.021ms | 50 | 50 | 100.00 |
| V1 | target_smoke | i2c_target_smoke | 54.500s | 1.474ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | i2c_csr_hw_reset | 0.990s | 35.650us | 5 | 5 | 100.00 |
| V1 | csr_rw | i2c_csr_rw | 1.020s | 17.580us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | i2c_csr_bit_bash | 5.110s | 2.085ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | i2c_csr_aliasing | 2.140s | 190.911us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | i2c_csr_mem_rw_with_rand_reset | 1.760s | 37.999us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | i2c_csr_rw | 1.020s | 17.580us | 20 | 20 | 100.00 |
| i2c_csr_aliasing | 2.140s | 190.911us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 155 | 155 | 100.00 | |||
| V2 | host_error_intr | i2c_host_error_intr | 24.100s | 6.740ms | 33 | 50 | 66.00 |
| V2 | host_stress_all | i2c_host_stress_all | 49.404m | 57.315ms | 16 | 50 | 32.00 |
| V2 | host_maxperf | i2c_host_perf | 18.553m | 29.441ms | 49 | 50 | 98.00 |
| V2 | host_override | i2c_host_override | 1.140s | 87.265us | 50 | 50 | 100.00 |
| V2 | host_fifo_watermark | i2c_host_fifo_watermark | 5.933m | 42.716ms | 50 | 50 | 100.00 |
| V2 | host_fifo_overflow | i2c_host_fifo_overflow | 4.285m | 5.197ms | 50 | 50 | 100.00 |
| V2 | host_fifo_reset | i2c_host_fifo_reset_fmt | 2.090s | 132.884us | 50 | 50 | 100.00 |
| i2c_host_fifo_fmt_empty | 33.590s | 1.883ms | 50 | 50 | 100.00 | ||
| i2c_host_fifo_reset_rx | 17.300s | 878.948us | 50 | 50 | 100.00 | ||
| V2 | host_fifo_full | i2c_host_fifo_full | 4.134m | 7.553ms | 50 | 50 | 100.00 |
| V2 | host_timeout | i2c_host_stretch_timeout | 54.700s | 3.915ms | 50 | 50 | 100.00 |
| V2 | host_rx_oversample | i2c_host_rx_oversample | 0 | 0 | -- | ||
| V2 | i2c_host_mode_toggle | i2c_host_mode_toggle | 6.650s | 204.050us | 13 | 50 | 26.00 |
| V2 | target_glitch | i2c_target_glitch | 19.820s | 2.107ms | 2 | 2 | 100.00 |
| V2 | target_stress_all | i2c_target_stress_all | 31.458m | 65.713ms | 48 | 50 | 96.00 |
| V2 | target_maxperf | i2c_target_perf | 10.410s | 1.973ms | 50 | 50 | 100.00 |
| V2 | target_fifo_empty | i2c_target_stress_rd | 1.433m | 1.708ms | 50 | 50 | 100.00 |
| i2c_target_intr_smoke | 14.240s | 1.651ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_reset | i2c_target_fifo_reset_acq | 3.210s | 297.825us | 50 | 50 | 100.00 |
| i2c_target_fifo_reset_tx | 3.590s | 1.082ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_full | i2c_target_stress_wr | 29.951m | 61.103ms | 50 | 50 | 100.00 |
| i2c_target_stress_rd | 1.433m | 1.708ms | 50 | 50 | 100.00 | ||
| i2c_target_intr_stress_wr | 25.038m | 54.606ms | 49 | 50 | 98.00 | ||
| V2 | target_timeout | i2c_target_timeout | 14.910s | 5.761ms | 50 | 50 | 100.00 |
| V2 | target_clock_stretch | i2c_target_stretch | 2.859m | 3.176ms | 45 | 50 | 90.00 |
| V2 | bad_address | i2c_target_bad_addr | 12.780s | 2.391ms | 50 | 50 | 100.00 |
| V2 | target_mode_glitch | i2c_target_hrst | 55.610s | 10.112ms | 20 | 50 | 40.00 |
| V2 | target_fifo_watermark | i2c_target_fifo_watermarks_acq | 5.630s | 558.574us | 50 | 50 | 100.00 |
| i2c_target_fifo_watermarks_tx | 2.520s | 646.088us | 49 | 50 | 98.00 | ||
| V2 | host_mode_config_perf | i2c_host_perf | 18.553m | 29.441ms | 49 | 50 | 98.00 |
| i2c_host_perf_precise | 35.002m | 23.214ms | 50 | 50 | 100.00 | ||
| V2 | host_mode_clock_stretching | i2c_host_stretch_timeout | 54.700s | 3.915ms | 50 | 50 | 100.00 |
| V2 | target_mode_tx_stretch_ctrl | i2c_target_tx_stretch_ctrl | 22.390s | 2.065ms | 48 | 50 | 96.00 |
| V2 | target_mode_nack_generation | i2c_target_nack_acqfull | 5.970s | 2.255ms | 50 | 50 | 100.00 |
| i2c_target_nack_acqfull_addr | 5.510s | 979.088us | 50 | 50 | 100.00 | ||
| i2c_target_nack_txstretch | 2.940s | 382.519us | 30 | 50 | 60.00 | ||
| V2 | host_mode_halt_on_nak | i2c_host_may_nack | 28.370s | 2.579ms | 50 | 50 | 100.00 |
| V2 | target_mode_n_byte_ack_control | target_mode_n_byte_ack_control | 0 | 0 | -- | ||
| V2 | target_mode_bus_timeout | target_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_timeout | controller_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_idle_delay | controller_mode_bus_idle_delay | 0 | 0 | -- | ||
| V2 | loopback_test | loopback_test | 0 | 0 | -- | ||
| V2 | multi_controller_clock_synchronization | multi_controller_clock_synchronization | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost_interference | multi_controller_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost | multi_controller_arbitration_lost | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost_interference | target_mode_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost | target_mode_arbitration_lost | 0 | 0 | -- | ||
| V2 | target_mode_smbus_maxlen | i2c_target_smbus_maxlen | 5.360s | 2.230ms | 50 | 50 | 100.00 |
| V2 | alert_test | i2c_alert_test | 1.090s | 40.059us | 50 | 50 | 100.00 |
| V2 | intr_test | i2c_intr_test | 0.950s | 17.566us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | i2c_tl_errors | 2.630s | 335.876us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | i2c_tl_errors | 2.630s | 335.876us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | i2c_csr_hw_reset | 0.990s | 35.650us | 5 | 5 | 100.00 |
| i2c_csr_rw | 1.020s | 17.580us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 2.140s | 190.911us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.390s | 54.286us | 19 | 20 | 95.00 | ||
| V2 | tl_d_partial_access | i2c_csr_hw_reset | 0.990s | 35.650us | 5 | 5 | 100.00 |
| i2c_csr_rw | 1.020s | 17.580us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 2.140s | 190.911us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.390s | 54.286us | 19 | 20 | 95.00 | ||
| V2 | TOTAL | 1641 | 1792 | 91.57 | |||
| V2S | tl_intg_err | i2c_tl_intg_err | 2.430s | 150.722us | 20 | 20 | 100.00 |
| i2c_sec_cm | 1.420s | 40.821us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | i2c_tl_intg_err | 2.430s | 150.722us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | host_stress_all_with_rand_reset | i2c_host_stress_all_with_rand_reset | 56.810s | 20.152ms | 0 | 10 | 0.00 |
| V3 | target_error_intr | i2c_target_unexp_stop | 4.360s | 1.667ms | 0 | 50 | 0.00 |
| V3 | target_stress_all_with_rand_reset | i2c_target_stress_all_with_rand_reset | 17.042m | 600.000ms | 0 | 10 | 0.00 |
| V3 | target_loopback | 0 | 0 | -- | |||
| V3 | TOTAL | 0 | 70 | 0.00 | |||
| TOTAL | 1821 | 2042 | 89.18 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 7 | 7 | 7 | 100.00 |
| V2 | 49 | 38 | 26 | 53.06 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 4 | 3 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 91.19 | 97.14 | 89.39 | 97.22 | 72.02 | 94.08 | 98.47 | 90.00 |
UVM_ERROR (tl_host_driver.sv:67) [driver] Check failed cfg.a_source_pend_q.size() == * (* [*] vs * [*]) has 35 failures:
0.i2c_host_stress_all.33025898653627805028924765051409857341262666985042512805720488447044195701455
Line 108, in log /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 4941135896 ps: (tl_host_driver.sv:67) [uvm_test_top.env.m_tl_agent_i2c_reg_block.driver] Check failed cfg.a_source_pend_q.size() == 0 (1 [0x1] vs 0 [0x0])
UVM_INFO @ 4941135896 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_host_stress_all.52326557058108209882094405943378260764632232593505485757927781936788134068164
Line 119, in log /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/2.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 8484983730 ps: (tl_host_driver.sv:67) [uvm_test_top.env.m_tl_agent_i2c_reg_block.driver] Check failed cfg.a_source_pend_q.size() == 0 (1 [0x1] vs 0 [0x0])
UVM_INFO @ 8484983730 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 17 more failures.
7.i2c_host_error_intr.16156815263098903631528891895447581145949219716382764257991547776619243838103
Line 125, in log /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/7.i2c_host_error_intr/latest/run.log
UVM_ERROR @ 137728017 ps: (tl_host_driver.sv:67) [uvm_test_top.env.m_tl_agent_i2c_reg_block.driver] Check failed cfg.a_source_pend_q.size() == 0 (1 [0x1] vs 0 [0x0])
UVM_INFO @ 137728017 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.i2c_host_error_intr.39103485905742210482954033956184126296193055511694104117784098508706805317125
Line 109, in log /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/8.i2c_host_error_intr/latest/run.log
UVM_ERROR @ 522635984 ps: (tl_host_driver.sv:67) [uvm_test_top.env.m_tl_agent_i2c_reg_block.driver] Check failed cfg.a_source_pend_q.size() == 0 (1 [0x1] vs 0 [0x0])
UVM_INFO @ 522635984 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 14 more failures.
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 30 failures:
2.i2c_target_hrst.76129730519007538133920185521497404740199344485845265238453985173396480314011
Line 66, in log /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/2.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10390557877 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10390557877 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.i2c_target_hrst.26458102967186960853361126936450115526980868898030670901666107631895603518655
Line 66, in log /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/3.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10112496761 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10112496761 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 28 more failures.
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 29 failures:
1.i2c_target_unexp_stop.84595420230337152117294066502117668535119234071241141380765517286180840000051
Line 65, in log /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 383818722 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 116 [0x74])
UVM_INFO @ 383818722 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_unexp_stop.13304219755935154422083703193405651489017052459825494060362152468008160354861
Line 65, in log /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/2.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 336782408 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 182 [0xb6])
UVM_INFO @ 336782408 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 27 more failures.
UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 28 failures:
1.i2c_host_mode_toggle.58824096827429477489802278932122064011186113410217015630663882709344644834681
Line 72, in log /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/1.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 406625519 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @62908
2.i2c_host_mode_toggle.72022855404897452283520393679493829952960775473517247287658905363501642501520
Line 72, in log /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/2.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 169573616 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @22916
... and 16 more failures.
6.i2c_host_stress_all.68713341304299022290922564710746849599537944324208402235574602499513994106587
Line 228, in log /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/6.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 11213325939 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @459539
8.i2c_host_stress_all.114346598351977730865728303447183538153107666634932215224462570264405851036726
Line 126, in log /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/8.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 21013904331 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @4343813
... and 8 more failures.
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 20 failures:
1.i2c_target_nack_txstretch.108017351528096803648675258493771437187659942281846892992751124882469621173119
Line 65, in log /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/1.i2c_target_nack_txstretch/latest/run.log
UVM_ERROR @ 382518525 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 382518525 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.i2c_target_nack_txstretch.38234375715026613195006329409565788740115391299538421799703538271673276312727
Line 65, in log /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/5.i2c_target_nack_txstretch/latest/run.log
UVM_ERROR @ 279856144 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 279856144 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 18 more failures.
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 19 failures:
0.i2c_target_unexp_stop.13739941376193905981647973798048925917229687372950554259620414512033351631690
Line 65, in log /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 40857038 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 40857038 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.i2c_target_unexp_stop.45049009789387345541704279376036352526180821006480105219651648211960905080753
Line 65, in log /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/5.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 180847540 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 180847540 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 17 more failures.
UVM_ERROR (cip_base_vseq.sv:867) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 18 failures:
0.i2c_host_stress_all_with_rand_reset.41984662978654285632676772072218777864586995015649108043174645510048599250532
Line 123, in log /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 20151514538 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 20151514538 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_host_stress_all_with_rand_reset.96495198656839998629461379837939092989043558856119804426209734257307483358993
Line 71, in log /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 202783271 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 202783271 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
1.i2c_target_stress_all_with_rand_reset.110065840542579063035698654403992086773426792333280432429150283638018974393385
Line 110, in log /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 3205590349 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3205590349 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_stress_all_with_rand_reset.27513243063689296207557521489848647631916472984536062141996682545898268819818
Line 74, in log /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 699530983 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 699530983 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 15 failures:
0.i2c_host_mode_toggle.23140994543354711645499608791434239254887709703224599982670059924777864636658
Line 74, in log /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 45421063 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
3.i2c_host_mode_toggle.89102236218689849328114302914402363664121638653267253710476922859689237442181
Line 74, in log /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/3.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 51367140 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
... and 13 more failures.
UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred! has 5 failures:
0.i2c_target_stretch.61636989508833071987435782465484511628605546475345326810194156831765053135188
Line 65, in log /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/0.i2c_target_stretch/latest/run.log
UVM_FATAL @ 10004025076 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
UVM_INFO @ 10004025076 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
28.i2c_target_stretch.77264168573351252385944092273449069956821996572148584050705187786534054047188
Line 65, in log /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/28.i2c_target_stretch/latest/run.log
UVM_FATAL @ 10018947930 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
UVM_INFO @ 10018947930 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
Error-[CNST-CIF] Constraints inconsistency failure has 3 failures:
Test i2c_target_tx_stretch_ctrl has 2 failures.
0.i2c_target_tx_stretch_ctrl.97095863888479268403526493158355219833411797634583015546396949540952182389668
Line 111, in log /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/0.i2c_target_tx_stretch_ctrl/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
49.i2c_target_tx_stretch_ctrl.92661418549825666416178082627182167938181400533672389731541605979318461546236
Line 111, in log /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/49.i2c_target_tx_stretch_ctrl/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
Test i2c_target_fifo_watermarks_tx has 1 failures.
46.i2c_target_fifo_watermarks_tx.75464162300704417271859391712923147258439729035977992557950303981135417637874
Line 108, in log /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/46.i2c_target_fifo_watermarks_tx/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 845
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
Job timed out after * minutes has 3 failures:
Test i2c_host_stress_all has 2 failures.
1.i2c_host_stress_all.1570305066840497491068034812905048809847928177417847026522401456004057999996
Log /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/1.i2c_host_stress_all/latest/run.log
Job timed out after 60 minutes
42.i2c_host_stress_all.31179764759916175609334198139977971773187227809631237136885492724575659247624
Log /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/42.i2c_host_stress_all/latest/run.log
Job timed out after 60 minutes
Test i2c_host_perf has 1 failures.
47.i2c_host_perf.11834359209977210798722353479702108892316196543937006450592411724924939790072
Log /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/47.i2c_host_perf/latest/run.log
Job timed out after 60 minutes
UVM_FATAL (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred! has 3 failures:
Test i2c_target_stress_all has 2 failures.
11.i2c_target_stress_all.45874308880173822180683478719769617264319554776601623451548476452708426922419
Line 92, in log /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/11.i2c_target_stress_all/latest/run.log
UVM_FATAL @ 56919919516 ps: (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!
UVM_INFO @ 56919919516 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
38.i2c_target_stress_all.115537067754549971162273980336139664465440014933187754151422091494575929038784
Line 84, in log /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/38.i2c_target_stress_all/latest/run.log
UVM_FATAL @ 38271730439 ps: (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!
UVM_INFO @ 38271730439 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test i2c_target_intr_stress_wr has 1 failures.
18.i2c_target_intr_stress_wr.78439072267088038010263064943782322800946876818798531551574780117684365170274
Line 65, in log /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/18.i2c_target_intr_stress_wr/latest/run.log
UVM_FATAL @ 54605692262 ps: (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!
UVM_INFO @ 54605692262 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:717) [scoreboard] controller_mode_wr_obs_fifo item uncompared: has 3 failures:
19.i2c_host_stress_all.68322594253168350468688076005171482488887550645957099082515860616355875681527
Line 135, in log /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/19.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 83842758549 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @26287797
43.i2c_host_stress_all.20962352995232518575694348197299404527822114367869303099322852356139234409124
Line 185, in log /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/43.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 88090769553 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @24612885
... and 1 more failures.
Error-[NOA] Null object access has 2 failures:
10.i2c_host_mode_toggle.71867407156153467501716103731703341365965320934154205825613043522083736455391
Line 73, in log /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/10.i2c_host_mode_toggle/latest/run.log
Error-[NOA] Null object access
../src/lowrisc_dv_i2c_env_0.1/i2c_reference_model.sv, 584
The object at dereference depth 0 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
48.i2c_host_mode_toggle.57754044255173294108418754432772999764556852846205701499259141726851332913739
Line 73, in log /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/48.i2c_host_mode_toggle/latest/run.log
Error-[NOA] Null object access
../src/lowrisc_dv_i2c_env_0.1/i2c_reference_model.sv, 584
The object at dereference depth 0 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
UVM_FATAL (csr_utils_pkg.sv:608) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 2 failures:
17.i2c_host_mode_toggle.75016892973667233858984530678561062726128569866632774782648201838380606858702
Line 66, in log /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/17.i2c_host_mode_toggle/latest/run.log
UVM_FATAL @ 53570158 ps: (csr_utils_pkg.sv:608) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0x7313af94, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 53570158 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
49.i2c_host_mode_toggle.83883493978020539690274271063053042014303883644098872895060381044459539598771
Line 66, in log /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/49.i2c_host_mode_toggle/latest/run.log
UVM_FATAL @ 70382063 ps: (csr_utils_pkg.sv:608) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0x7e381b94, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 70382063 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 2 failures:
38.i2c_target_unexp_stop.76369092575044427360185928909630986647818249775226695657840869866845564086569
Line 66, in log /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/38.i2c_target_unexp_stop/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 300576804 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 300576804 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
45.i2c_target_unexp_stop.31131257441330389686617747142012971588388467961637830764326703242782668130284
Line 66, in log /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/45.i2c_target_unexp_stop/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 439974659 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 439974659 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:771) [i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
0.i2c_target_stress_all_with_rand_reset.51847070460312253839578462616523383576872848121384044607608941860945739277828
Line 88, in log /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 986460823 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 986460823 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite has 1 failures:
1.i2c_host_error_intr.33866209681629144765887270888722530195984054276988825607026507093540503025325
Line 73, in log /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/1.i2c_host_error_intr/latest/run.log
UVM_ERROR @ 34467310 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite
--> EXP:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
5.i2c_target_stress_all_with_rand_reset.86872100406490972070618872363622090790562956142103790001753205429202648754956
Line 149, in log /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/5.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:501) [i2c_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) has 1 failures:
10.i2c_same_csr_outstanding.2015190119679486031324999350907432198267912455391915848052715116201842769149
Line 65, in log /workspaces/repo/scratch/os_regression_2024_10_02/i2c-sim-vcs/10.i2c_same_csr_outstanding/latest/run.log
UVM_ERROR @ 54286208 ps: (cip_base_vseq.sv:501) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed data & ~ro_mask == 0 (64 [0x40] vs 0 [0x0])
UVM_INFO @ 54286208 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---