29d22a60a2| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | host_smoke | i2c_host_smoke | 2.101m | 7.958ms | 50 | 50 | 100.00 |
| V1 | target_smoke | i2c_target_smoke | 54.840s | 1.199ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | i2c_csr_hw_reset | 1.150s | 27.019us | 5 | 5 | 100.00 |
| V1 | csr_rw | i2c_csr_rw | 1.140s | 96.698us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | i2c_csr_bit_bash | 5.160s | 357.260us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | i2c_csr_aliasing | 2.450s | 138.729us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | i2c_csr_mem_rw_with_rand_reset | 1.920s | 32.560us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | i2c_csr_rw | 1.140s | 96.698us | 20 | 20 | 100.00 |
| i2c_csr_aliasing | 2.450s | 138.729us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 155 | 155 | 100.00 | |||
| V2 | host_error_intr | i2c_host_error_intr | 18.420s | 1.110ms | 50 | 50 | 100.00 |
| V2 | host_stress_all | i2c_host_stress_all | 29.652m | 132.210ms | 11 | 50 | 22.00 |
| V2 | host_maxperf | i2c_host_perf | 19.140m | 27.647ms | 48 | 50 | 96.00 |
| V2 | host_override | i2c_host_override | 1.180s | 83.628us | 50 | 50 | 100.00 |
| V2 | host_fifo_watermark | i2c_host_fifo_watermark | 6.057m | 21.808ms | 50 | 50 | 100.00 |
| V2 | host_fifo_overflow | i2c_host_fifo_overflow | 3.090m | 6.446ms | 50 | 50 | 100.00 |
| V2 | host_fifo_reset | i2c_host_fifo_reset_fmt | 2.250s | 2.071ms | 50 | 50 | 100.00 |
| i2c_host_fifo_fmt_empty | 31.620s | 1.895ms | 50 | 50 | 100.00 | ||
| i2c_host_fifo_reset_rx | 16.770s | 216.183us | 50 | 50 | 100.00 | ||
| V2 | host_fifo_full | i2c_host_fifo_full | 3.878m | 3.637ms | 50 | 50 | 100.00 |
| V2 | host_timeout | i2c_host_stretch_timeout | 53.880s | 816.873us | 50 | 50 | 100.00 |
| V2 | host_rx_oversample | i2c_host_rx_oversample | 0 | 0 | -- | ||
| V2 | i2c_host_mode_toggle | i2c_host_mode_toggle | 8.130s | 183.825us | 15 | 50 | 30.00 |
| V2 | target_glitch | i2c_target_glitch | 12.780s | 10.428ms | 2 | 2 | 100.00 |
| V2 | target_stress_all | i2c_target_stress_all | 30.318m | 64.155ms | 49 | 50 | 98.00 |
| V2 | target_maxperf | i2c_target_perf | 11.620s | 1.200ms | 50 | 50 | 100.00 |
| V2 | target_fifo_empty | i2c_target_stress_rd | 1.328m | 7.772ms | 50 | 50 | 100.00 |
| i2c_target_intr_smoke | 15.610s | 1.510ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_reset | i2c_target_fifo_reset_acq | 3.210s | 823.738us | 50 | 50 | 100.00 |
| i2c_target_fifo_reset_tx | 3.220s | 261.812us | 50 | 50 | 100.00 | ||
| V2 | target_fifo_full | i2c_target_stress_wr | 41.191m | 75.637ms | 50 | 50 | 100.00 |
| i2c_target_stress_rd | 1.328m | 7.772ms | 50 | 50 | 100.00 | ||
| i2c_target_intr_stress_wr | 6.585m | 22.026ms | 50 | 50 | 100.00 | ||
| V2 | target_timeout | i2c_target_timeout | 14.990s | 5.674ms | 50 | 50 | 100.00 |
| V2 | target_clock_stretch | i2c_target_stretch | 3.169m | 4.329ms | 44 | 50 | 88.00 |
| V2 | bad_address | i2c_target_bad_addr | 13.240s | 14.396ms | 50 | 50 | 100.00 |
| V2 | target_mode_glitch | i2c_target_hrst | 54.270s | 10.268ms | 27 | 50 | 54.00 |
| V2 | target_fifo_watermark | i2c_target_fifo_watermarks_acq | 6.400s | 3.027ms | 50 | 50 | 100.00 |
| i2c_target_fifo_watermarks_tx | 2.790s | 145.923us | 48 | 50 | 96.00 | ||
| V2 | host_mode_config_perf | i2c_host_perf | 19.140m | 27.647ms | 48 | 50 | 96.00 |
| i2c_host_perf_precise | 14.765m | 24.336ms | 50 | 50 | 100.00 | ||
| V2 | host_mode_clock_stretching | i2c_host_stretch_timeout | 53.880s | 816.873us | 50 | 50 | 100.00 |
| V2 | target_mode_tx_stretch_ctrl | i2c_target_tx_stretch_ctrl | 22.510s | 1.208ms | 48 | 50 | 96.00 |
| V2 | target_mode_nack_generation | i2c_target_nack_acqfull | 5.880s | 8.671ms | 50 | 50 | 100.00 |
| i2c_target_nack_acqfull_addr | 5.300s | 818.970us | 50 | 50 | 100.00 | ||
| i2c_target_nack_txstretch | 3.030s | 190.781us | 36 | 50 | 72.00 | ||
| V2 | host_mode_halt_on_nak | i2c_host_may_nack | 30.930s | 1.194ms | 50 | 50 | 100.00 |
| V2 | target_mode_n_byte_ack_control | target_mode_n_byte_ack_control | 0 | 0 | -- | ||
| V2 | target_mode_bus_timeout | target_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_timeout | controller_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_idle_delay | controller_mode_bus_idle_delay | 0 | 0 | -- | ||
| V2 | loopback_test | loopback_test | 0 | 0 | -- | ||
| V2 | multi_controller_clock_synchronization | multi_controller_clock_synchronization | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost_interference | multi_controller_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost | multi_controller_arbitration_lost | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost_interference | target_mode_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost | target_mode_arbitration_lost | 0 | 0 | -- | ||
| V2 | target_mode_smbus_maxlen | i2c_target_smbus_maxlen | 5.020s | 576.445us | 50 | 50 | 100.00 |
| V2 | alert_test | i2c_alert_test | 1.100s | 24.839us | 50 | 50 | 100.00 |
| V2 | intr_test | i2c_intr_test | 1.030s | 20.348us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | i2c_tl_errors | 3.030s | 145.895us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | i2c_tl_errors | 3.030s | 145.895us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | i2c_csr_hw_reset | 1.150s | 27.019us | 5 | 5 | 100.00 |
| i2c_csr_rw | 1.140s | 96.698us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 2.450s | 138.729us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.620s | 88.372us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | i2c_csr_hw_reset | 1.150s | 27.019us | 5 | 5 | 100.00 |
| i2c_csr_rw | 1.140s | 96.698us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 2.450s | 138.729us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 1.620s | 88.372us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 1668 | 1792 | 93.08 | |||
| V2S | tl_intg_err | i2c_tl_intg_err | 3.060s | 214.551us | 20 | 20 | 100.00 |
| i2c_sec_cm | 1.640s | 404.124us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | i2c_tl_intg_err | 3.060s | 214.551us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | host_stress_all_with_rand_reset | i2c_host_stress_all_with_rand_reset | 1.233m | 6.611ms | 0 | 10 | 0.00 |
| V3 | target_error_intr | i2c_target_unexp_stop | 4.210s | 374.893us | 0 | 50 | 0.00 |
| V3 | target_stress_all_with_rand_reset | i2c_target_stress_all_with_rand_reset | 1.184m | 2.090ms | 0 | 10 | 0.00 |
| V3 | target_loopback | 0 | 0 | -- | |||
| V3 | TOTAL | 0 | 70 | 0.00 | |||
| TOTAL | 1848 | 2042 | 90.50 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 7 | 7 | 7 | 100.00 |
| V2 | 49 | 38 | 29 | 59.18 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 4 | 3 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 91.18 | 97.23 | 89.50 | 97.22 | 72.02 | 94.23 | 98.47 | 89.58 |
UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 50 failures:
1.i2c_host_stress_all.53436620963514574119138303405935756383574492280752644852928919959393367563968
Line 190, in log /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/1.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 24668489484 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @5089477
3.i2c_host_stress_all.92431731256835412161308736136291601167814400701665324511126095733247722229226
Line 137, in log /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/3.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 60828495895 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @8956933
... and 29 more failures.
1.i2c_host_mode_toggle.108141119879437784365032639040171912415576559547117341153347417395118357332491
Line 72, in log /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/1.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 196486474 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @40372
2.i2c_host_mode_toggle.92118230729357387890412821816704482096228695641553262658493095785210395258973
Line 72, in log /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/2.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 246816535 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @25290
... and 17 more failures.
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 33 failures:
0.i2c_target_unexp_stop.67943110727712195167855709868532325306819265728269967412192176282109908880398
Line 65, in log /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 311058026 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 37 [0x25])
UVM_INFO @ 311058026 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_unexp_stop.53159496349182081837552466511636785732453076740347637450199934210102798220954
Line 65, in log /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/2.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 2917841247 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 223 [0xdf])
UVM_INFO @ 2917841247 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 30 more failures.
3.i2c_target_stress_all_with_rand_reset.106883736553062035529030783345139639948601893970055846807868199117048276809569
Line 97, in log /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 986681850 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 223 [0xdf])
UVM_INFO @ 986681850 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 23 failures:
3.i2c_target_hrst.87917165429517749355753651625901364022624680566971109951947025566842426189248
Line 66, in log /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/3.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10439839957 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10439839957 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.i2c_target_hrst.84040591318400097472027460740115806494756188392866388423574962412390590216481
Line 66, in log /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/4.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10256633894 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10256633894 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 21 more failures.
UVM_ERROR (cip_base_vseq.sv:867) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 17 failures:
0.i2c_host_stress_all_with_rand_reset.32153645775807878533240026497872217283349697588332546276478318649814101713852
Line 71, in log /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 250662293 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 250662293 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_host_stress_all_with_rand_reset.4571581997804936031990846835060868196394313760832686732137326307789693738016
Line 72, in log /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1020685691 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1020685691 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
1.i2c_target_stress_all_with_rand_reset.24767718980698571610905433027003587553458472147888672912301391479486197898602
Line 119, in log /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 3226413207 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3226413207 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_stress_all_with_rand_reset.32758011007027022372559098651385705697988518602369977005721030217822443746497
Line 129, in log /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2090377427 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2090377427 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 14 failures:
2.i2c_target_nack_txstretch.9725372747811746898293114002298266311618895987576399849104322177318006094409
Line 65, in log /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/2.i2c_target_nack_txstretch/latest/run.log
UVM_ERROR @ 184976327 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 184976327 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.i2c_target_nack_txstretch.71719521552157486052873979383776200918148899503673220908400543853064344233700
Line 65, in log /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/3.i2c_target_nack_txstretch/latest/run.log
UVM_ERROR @ 133435683 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 133435683 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 12 more failures.
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 9 failures:
1.i2c_target_unexp_stop.88573813384041135292604294223500407784206567007505325935100769317374929360576
Line 66, in log /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 294942463 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 294942463 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.i2c_target_unexp_stop.78172476909007448330251781427899071444434820245235515535718939158383406983660
Line 66, in log /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/4.i2c_target_unexp_stop/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 665757842 ps: (i2c_fifos.sv:316) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 665757842 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 9 failures:
10.i2c_target_unexp_stop.4338944524466854519060371324911339775340940410691747580573820522045237042585
Line 65, in log /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/10.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 504835178 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 504835178 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
11.i2c_target_unexp_stop.65811936945519807028816297236216190339929021900629545993955659282270835898240
Line 65, in log /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/11.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 62032802 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 62032802 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 8 failures:
0.i2c_host_mode_toggle.72418147913996865146309021901375790209716639088867381214498905191984945610957
Line 74, in log /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 45222343 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
8.i2c_host_mode_toggle.76365966038007134376542465511918754559635996236016203469502636886345002264509
Line 74, in log /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/8.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 75868590 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
... and 6 more failures.
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 8 failures:
3.i2c_host_mode_toggle.110246352188069591386060195229463840108083805519183601595859095536111343688364
Line 66, in log /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/3.i2c_host_mode_toggle/latest/run.log
UVM_FATAL @ 104875236 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0x7eb69b14, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 104875236 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.i2c_host_mode_toggle.53459187185833236446379441523526987949724486708704652413046637223580147616204
Line 66, in log /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/7.i2c_host_mode_toggle/latest/run.log
UVM_FATAL @ 116486904 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0xbbc36a14, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 116486904 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred! has 6 failures:
1.i2c_target_stretch.40049433659369688466686914207800535548484702941729593842260126725147315394093
Line 65, in log /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/1.i2c_target_stretch/latest/run.log
UVM_FATAL @ 10011071650 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
UVM_INFO @ 10011071650 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
15.i2c_target_stretch.68473753141730320638066558326421168888876062180416546522897453123751364953854
Line 65, in log /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/15.i2c_target_stretch/latest/run.log
UVM_FATAL @ 10018157308 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
UVM_INFO @ 10018157308 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
Job timed out after * minutes has 5 failures:
Test i2c_host_perf has 1 failures.
4.i2c_host_perf.37238046309360718175058162275651163391348811404615705937292841537654113001845
Log /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/4.i2c_host_perf/latest/run.log
Job timed out after 60 minutes
Test i2c_host_stress_all has 4 failures.
6.i2c_host_stress_all.47223687496628141157754411429758060645102742579911516507971633688780049632571
Log /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/6.i2c_host_stress_all/latest/run.log
Job timed out after 60 minutes
29.i2c_host_stress_all.75418603772094124972209784597036468374060443498221547998509289248345635636935
Log /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/29.i2c_host_stress_all/latest/run.log
Job timed out after 60 minutes
... and 2 more failures.
Error-[CNST-CIF] Constraints inconsistency failure has 4 failures:
Test i2c_target_fifo_watermarks_tx has 2 failures.
6.i2c_target_fifo_watermarks_tx.6171543451166926855234919813321903915562065860546959325624892254334471943737
Line 108, in log /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/6.i2c_target_fifo_watermarks_tx/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 845
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
47.i2c_target_fifo_watermarks_tx.103610273562007788496357428289866196923296561102616481555437599257072082336328
Line 108, in log /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/47.i2c_target_fifo_watermarks_tx/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 845
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
Test i2c_target_tx_stretch_ctrl has 2 failures.
10.i2c_target_tx_stretch_ctrl.92900306876737640854985327802020863311286272036048345199745390298403494151833
Line 111, in log /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/10.i2c_target_tx_stretch_ctrl/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
17.i2c_target_tx_stretch_ctrl.75339041646074698011186195416108646933377749611790289812807373773525119486503
Line 111, in log /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/17.i2c_target_tx_stretch_ctrl/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
UVM_ERROR (i2c_scoreboard.sv:717) [scoreboard] controller_mode_wr_obs_fifo item uncompared: has 4 failures:
8.i2c_host_stress_all.51609472559855749017173730213678099778153499678753802728973775758619535316825
Line 213, in log /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/8.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 14785604154 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @1738597
10.i2c_host_stress_all.107940893171136150800887828232643576810462174756815579251735470960763561469845
Line 280, in log /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/10.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 79465864732 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @13370063
... and 2 more failures.
UVM_ERROR (cip_base_vseq.sv:771) [i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 2 failures:
0.i2c_target_stress_all_with_rand_reset.12228648454329307910278373340125034701913195685485414030573181959736021670987
Line 75, in log /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 499002555 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 499002555 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
9.i2c_target_stress_all_with_rand_reset.80633823405290165395329421801790073511332183072868943068900855834308402653918
Line 83, in log /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/9.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2251686184 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 2251686184 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred! has 1 failures:
10.i2c_target_stress_all.25055156385092288934507498354482191051137936837362451118125932743819900787141
Line 68, in log /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/10.i2c_target_stress_all/latest/run.log
UVM_FATAL @ 39427060101 ps: (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!
UVM_INFO @ 39427060101 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
34.i2c_host_perf.50249086735900425802969830759049907450712506076870749338367975737814791757904
Line 67, in log /workspaces/repo/scratch/os_regression_2024_10_08/i2c-sim-vcs/34.i2c_host_perf/latest/run.log
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---