00fe426038
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | keymgr_smoke | 41.590s | 2.803ms | 50 | 50 | 100.00 |
V1 | random | keymgr_random | 1.109m | 2.880ms | 50 | 50 | 100.00 |
V1 | csr_hw_reset | keymgr_csr_hw_reset | 1.360s | 54.313us | 5 | 5 | 100.00 |
V1 | csr_rw | keymgr_csr_rw | 1.480s | 46.549us | 20 | 20 | 100.00 |
V1 | csr_bit_bash | keymgr_csr_bit_bash | 15.980s | 1.791ms | 5 | 5 | 100.00 |
V1 | csr_aliasing | keymgr_csr_aliasing | 8.120s | 1.651ms | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | keymgr_csr_mem_rw_with_rand_reset | 2.410s | 47.692us | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | keymgr_csr_rw | 1.480s | 46.549us | 20 | 20 | 100.00 |
keymgr_csr_aliasing | 8.120s | 1.651ms | 5 | 5 | 100.00 | ||
V1 | TOTAL | 155 | 155 | 100.00 | |||
V2 | cfgen_during_op | keymgr_cfg_regwen | 2.060m | 41.532ms | 49 | 50 | 98.00 |
V2 | sideload | keymgr_sideload | 25.500s | 1.140ms | 50 | 50 | 100.00 |
keymgr_sideload_kmac | 55.440s | 8.487ms | 50 | 50 | 100.00 | ||
keymgr_sideload_aes | 1.065m | 7.011ms | 50 | 50 | 100.00 | ||
keymgr_sideload_otbn | 1.016m | 4.377ms | 50 | 50 | 100.00 | ||
V2 | direct_to_disabled_state | keymgr_direct_to_disabled | 47.530s | 4.748ms | 50 | 50 | 100.00 |
V2 | lc_disable | keymgr_lc_disable | 21.530s | 1.397ms | 49 | 50 | 98.00 |
V2 | kmac_error_response | keymgr_kmac_rsp_err | 17.110s | 2.458ms | 49 | 50 | 98.00 |
V2 | invalid_sw_input | keymgr_sw_invalid_input | 55.810s | 5.300ms | 50 | 50 | 100.00 |
V2 | invalid_hw_input | keymgr_hwsw_invalid_input | 42.970s | 2.573ms | 50 | 50 | 100.00 |
V2 | sync_async_fault_cross | keymgr_sync_async_fault_cross | 25.970s | 5.071ms | 50 | 50 | 100.00 |
V2 | stress_all | keymgr_stress_all | 4.919m | 13.214ms | 47 | 50 | 94.00 |
V2 | intr_test | keymgr_intr_test | 0.950s | 14.717us | 50 | 50 | 100.00 |
V2 | alert_test | keymgr_alert_test | 1.120s | 26.002us | 50 | 50 | 100.00 |
V2 | tl_d_oob_addr_access | keymgr_tl_errors | 4.340s | 410.022us | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | keymgr_tl_errors | 4.340s | 410.022us | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | keymgr_csr_hw_reset | 1.360s | 54.313us | 5 | 5 | 100.00 |
keymgr_csr_rw | 1.480s | 46.549us | 20 | 20 | 100.00 | ||
keymgr_csr_aliasing | 8.120s | 1.651ms | 5 | 5 | 100.00 | ||
keymgr_same_csr_outstanding | 4.870s | 467.697us | 20 | 20 | 100.00 | ||
V2 | tl_d_partial_access | keymgr_csr_hw_reset | 1.360s | 54.313us | 5 | 5 | 100.00 |
keymgr_csr_rw | 1.480s | 46.549us | 20 | 20 | 100.00 | ||
keymgr_csr_aliasing | 8.120s | 1.651ms | 5 | 5 | 100.00 | ||
keymgr_same_csr_outstanding | 4.870s | 467.697us | 20 | 20 | 100.00 | ||
V2 | TOTAL | 734 | 740 | 99.19 | |||
V2S | sec_cm_additional_check | keymgr_sec_cm | 12.320s | 1.077ms | 5 | 5 | 100.00 |
V2S | tl_intg_err | keymgr_sec_cm | 12.320s | 1.077ms | 5 | 5 | 100.00 |
keymgr_tl_intg_err | 9.010s | 819.794us | 20 | 20 | 100.00 | ||
V2S | shadow_reg_update_error | keymgr_shadow_reg_errors | 5.100s | 652.496us | 20 | 20 | 100.00 |
V2S | shadow_reg_read_clear_staged_value | keymgr_shadow_reg_errors | 5.100s | 652.496us | 20 | 20 | 100.00 |
V2S | shadow_reg_storage_error | keymgr_shadow_reg_errors | 5.100s | 652.496us | 20 | 20 | 100.00 |
V2S | shadowed_reset_glitch | keymgr_shadow_reg_errors | 5.100s | 652.496us | 20 | 20 | 100.00 |
V2S | shadow_reg_update_error_with_csr_rw | keymgr_shadow_reg_errors_with_csr_rw | 15.580s | 2.138ms | 20 | 20 | 100.00 |
V2S | prim_count_check | keymgr_sec_cm | 12.320s | 1.077ms | 5 | 5 | 100.00 |
V2S | prim_fsm_check | keymgr_sec_cm | 12.320s | 1.077ms | 5 | 5 | 100.00 |
V2S | sec_cm_bus_integrity | keymgr_tl_intg_err | 9.010s | 819.794us | 20 | 20 | 100.00 |
V2S | sec_cm_config_shadow | keymgr_shadow_reg_errors | 5.100s | 652.496us | 20 | 20 | 100.00 |
V2S | sec_cm_op_config_regwen | keymgr_cfg_regwen | 2.060m | 41.532ms | 49 | 50 | 98.00 |
V2S | sec_cm_reseed_config_regwen | keymgr_random | 1.109m | 2.880ms | 50 | 50 | 100.00 |
keymgr_csr_rw | 1.480s | 46.549us | 20 | 20 | 100.00 | ||
V2S | sec_cm_sw_binding_config_regwen | keymgr_random | 1.109m | 2.880ms | 50 | 50 | 100.00 |
keymgr_csr_rw | 1.480s | 46.549us | 20 | 20 | 100.00 | ||
V2S | sec_cm_max_key_ver_config_regwen | keymgr_random | 1.109m | 2.880ms | 50 | 50 | 100.00 |
keymgr_csr_rw | 1.480s | 46.549us | 20 | 20 | 100.00 | ||
V2S | sec_cm_lc_ctrl_intersig_mubi | keymgr_lc_disable | 21.530s | 1.397ms | 49 | 50 | 98.00 |
V2S | sec_cm_constants_consistency | keymgr_hwsw_invalid_input | 42.970s | 2.573ms | 50 | 50 | 100.00 |
V2S | sec_cm_intersig_consistency | keymgr_hwsw_invalid_input | 42.970s | 2.573ms | 50 | 50 | 100.00 |
V2S | sec_cm_hw_key_sw_noaccess | keymgr_random | 1.109m | 2.880ms | 50 | 50 | 100.00 |
V2S | sec_cm_output_keys_ctrl_redun | keymgr_sideload_protect | 22.670s | 1.759ms | 50 | 50 | 100.00 |
V2S | sec_cm_ctrl_fsm_sparse | keymgr_sec_cm | 12.320s | 1.077ms | 5 | 5 | 100.00 |
V2S | sec_cm_data_fsm_sparse | keymgr_sec_cm | 12.320s | 1.077ms | 5 | 5 | 100.00 |
V2S | sec_cm_ctrl_fsm_local_esc | keymgr_sec_cm | 12.320s | 1.077ms | 5 | 5 | 100.00 |
V2S | sec_cm_ctrl_fsm_consistency | keymgr_custom_cm | 10.990s | 977.117us | 49 | 50 | 98.00 |
V2S | sec_cm_ctrl_fsm_global_esc | keymgr_lc_disable | 21.530s | 1.397ms | 49 | 50 | 98.00 |
V2S | sec_cm_ctrl_ctr_redun | keymgr_sec_cm | 12.320s | 1.077ms | 5 | 5 | 100.00 |
V2S | sec_cm_kmac_if_fsm_sparse | keymgr_sec_cm | 12.320s | 1.077ms | 5 | 5 | 100.00 |
V2S | sec_cm_kmac_if_ctr_redun | keymgr_sec_cm | 12.320s | 1.077ms | 5 | 5 | 100.00 |
V2S | sec_cm_kmac_if_cmd_ctrl_consistency | keymgr_custom_cm | 10.990s | 977.117us | 49 | 50 | 98.00 |
V2S | sec_cm_kmac_if_done_ctrl_consistency | keymgr_custom_cm | 10.990s | 977.117us | 49 | 50 | 98.00 |
V2S | sec_cm_reseed_ctr_redun | keymgr_sec_cm | 12.320s | 1.077ms | 5 | 5 | 100.00 |
V2S | sec_cm_side_load_sel_ctrl_consistency | keymgr_custom_cm | 10.990s | 977.117us | 49 | 50 | 98.00 |
V2S | sec_cm_sideload_ctrl_fsm_sparse | keymgr_sec_cm | 12.320s | 1.077ms | 5 | 5 | 100.00 |
V2S | sec_cm_ctrl_key_integrity | keymgr_custom_cm | 10.990s | 977.117us | 49 | 50 | 98.00 |
V2S | TOTAL | 164 | 165 | 99.39 | |||
V3 | stress_all_with_rand_reset | keymgr_stress_all_with_rand_reset | 46.860s | 10.306ms | 25 | 50 | 50.00 |
V3 | TOTAL | 25 | 50 | 50.00 | |||
TOTAL | 1078 | 1110 | 97.12 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 7 | 7 | 7 | 100.00 |
V2 | 16 | 16 | 12 | 75.00 |
V2S | 6 | 6 | 5 | 83.33 |
V3 | 1 | 1 | 0 | 0.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
---|---|---|---|---|---|---|---|
97.38 | 99.00 | 98.07 | 98.43 | 97.67 | 98.93 | 98.41 | 91.17 |
UVM_ERROR (cip_base_vseq.sv:829) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
has 24 failures:
0.keymgr_stress_all_with_rand_reset.92215468433931845032861628459666861928065405172590943082586244919156304403976
Line 745, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/0.keymgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 263338306 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 263338306 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.keymgr_stress_all_with_rand_reset.63884586665904343415728340880516704779740534786112119654294241764816921809958
Line 305, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/2.keymgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 111826132 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10002 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 111826132 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 22 more failures.
UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:*
has 3 failures:
Test keymgr_custom_cm has 1 failures.
1.keymgr_custom_cm.61621211033657343472837865539656456761084883374077791294363094443525193601223
Line 266, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/1.keymgr_custom_cm/latest/run.log
UVM_ERROR @ 6410372 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
UVM_INFO @ 6410372 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test keymgr_stress_all has 1 failures.
10.keymgr_stress_all.87926706489213808857770246311570821196034976958882894147328232046695538938759
Line 2759, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/10.keymgr_stress_all/latest/run.log
UVM_ERROR @ 1743145764 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
UVM_INFO @ 1743145764 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test keymgr_lc_disable has 1 failures.
29.keymgr_lc_disable.109843496187722894640382033647854002475799633325477287349486816188790821673834
Line 342, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/29.keymgr_lc_disable/latest/run.log
UVM_ERROR @ 43266375 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:2000
UVM_INFO @ 43266375 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:794) [scoreboard] Check failed item.d_data ==
gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.start` has 1 failures:
2.keymgr_cfg_regwen.107611658402460491624833052599872046089533190074047419984173661869961663478587
Line 276, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/2.keymgr_cfg_regwen/latest/run.log
UVM_ERROR @ 25399002 ps: (keymgr_scoreboard.sv:794) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (0 [0x0] vs 1 [0x1]) reg name: keymgr_reg_block.start
UVM_INFO @ 25399002 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:241) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_operation_err triggered unexpectedly
has 1 failures:
2.keymgr_kmac_rsp_err.113034577037989666522225068249877169845679238823837132508138209894939994450028
Line 456, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/2.keymgr_kmac_rsp_err/latest/run.log
UVM_ERROR @ 21590216 ps: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_operation_err triggered unexpectedly
UVM_INFO @ 21590216 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:753) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
has 1 failures:
6.keymgr_stress_all_with_rand_reset.32946227106669275651386406031606326452985466147349136447000669201050167948965
Line 316, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/6.keymgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 661389778 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 661389778 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout keymgr_reg_block.working_state (addr=*) == *
has 1 failures:
8.keymgr_stress_all.4977801217517792554482609722560643778678336631027708994626530774492443439164
Line 735, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/8.keymgr_stress_all/latest/run.log
UVM_FATAL @ 58821773391 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout keymgr_reg_block.working_state (addr=0xa169fbe8) == 0x3
UVM_INFO @ 58821773391 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data !=
gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.sw_share0_output_*` has 1 failures:
37.keymgr_stress_all.12875362700280047201437878451149438645886958201345871563962901857850666978530
Line 1490, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/37.keymgr_stress_all/latest/run.log
UVM_ERROR @ 849916356 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (0 [0x0] vs 0 [0x0]) reg name: keymgr_reg_block.sw_share0_output_0
UVM_INFO @ 849916356 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---