349bab6601
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | keymgr_smoke | 39.540s | 7.463ms | 50 | 50 | 100.00 |
V1 | random | keymgr_random | 51.570s | 1.616ms | 50 | 50 | 100.00 |
V1 | csr_hw_reset | keymgr_csr_hw_reset | 1.420s | 106.270us | 5 | 5 | 100.00 |
V1 | csr_rw | keymgr_csr_rw | 1.610s | 77.128us | 20 | 20 | 100.00 |
V1 | csr_bit_bash | keymgr_csr_bit_bash | 32.660s | 5.111ms | 5 | 5 | 100.00 |
V1 | csr_aliasing | keymgr_csr_aliasing | 10.510s | 493.019us | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | keymgr_csr_mem_rw_with_rand_reset | 2.330s | 49.310us | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | keymgr_csr_rw | 1.610s | 77.128us | 20 | 20 | 100.00 |
keymgr_csr_aliasing | 10.510s | 493.019us | 5 | 5 | 100.00 | ||
V1 | TOTAL | 155 | 155 | 100.00 | |||
V2 | cfgen_during_op | keymgr_cfg_regwen | 2.050m | 2.214ms | 50 | 50 | 100.00 |
V2 | sideload | keymgr_sideload | 1.530m | 29.820ms | 50 | 50 | 100.00 |
keymgr_sideload_kmac | 1.067m | 6.209ms | 50 | 50 | 100.00 | ||
keymgr_sideload_aes | 1.061m | 17.704ms | 50 | 50 | 100.00 | ||
keymgr_sideload_otbn | 1.139m | 2.488ms | 50 | 50 | 100.00 | ||
V2 | direct_to_disabled_state | keymgr_direct_to_disabled | 33.290s | 1.909ms | 50 | 50 | 100.00 |
V2 | lc_disable | keymgr_lc_disable | 12.310s | 1.400ms | 47 | 50 | 94.00 |
V2 | kmac_error_response | keymgr_kmac_rsp_err | 8.580s | 653.240us | 50 | 50 | 100.00 |
V2 | invalid_sw_input | keymgr_sw_invalid_input | 1.914m | 18.537ms | 50 | 50 | 100.00 |
V2 | invalid_hw_input | keymgr_hwsw_invalid_input | 28.910s | 1.866ms | 50 | 50 | 100.00 |
V2 | sync_async_fault_cross | keymgr_sync_async_fault_cross | 25.080s | 2.063ms | 50 | 50 | 100.00 |
V2 | stress_all | keymgr_stress_all | 9.474m | 56.648ms | 49 | 50 | 98.00 |
V2 | intr_test | keymgr_intr_test | 1.020s | 20.634us | 50 | 50 | 100.00 |
V2 | alert_test | keymgr_alert_test | 1.050s | 19.046us | 50 | 50 | 100.00 |
V2 | tl_d_oob_addr_access | keymgr_tl_errors | 5.910s | 345.063us | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | keymgr_tl_errors | 5.910s | 345.063us | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | keymgr_csr_hw_reset | 1.420s | 106.270us | 5 | 5 | 100.00 |
keymgr_csr_rw | 1.610s | 77.128us | 20 | 20 | 100.00 | ||
keymgr_csr_aliasing | 10.510s | 493.019us | 5 | 5 | 100.00 | ||
keymgr_same_csr_outstanding | 4.560s | 121.619us | 20 | 20 | 100.00 | ||
V2 | tl_d_partial_access | keymgr_csr_hw_reset | 1.420s | 106.270us | 5 | 5 | 100.00 |
keymgr_csr_rw | 1.610s | 77.128us | 20 | 20 | 100.00 | ||
keymgr_csr_aliasing | 10.510s | 493.019us | 5 | 5 | 100.00 | ||
keymgr_same_csr_outstanding | 4.560s | 121.619us | 20 | 20 | 100.00 | ||
V2 | TOTAL | 736 | 740 | 99.46 | |||
V2S | sec_cm_additional_check | keymgr_sec_cm | 17.040s | 2.165ms | 5 | 5 | 100.00 |
V2S | tl_intg_err | keymgr_sec_cm | 17.040s | 2.165ms | 5 | 5 | 100.00 |
keymgr_tl_intg_err | 8.940s | 1.167ms | 20 | 20 | 100.00 | ||
V2S | shadow_reg_update_error | keymgr_shadow_reg_errors | 6.870s | 573.384us | 20 | 20 | 100.00 |
V2S | shadow_reg_read_clear_staged_value | keymgr_shadow_reg_errors | 6.870s | 573.384us | 20 | 20 | 100.00 |
V2S | shadow_reg_storage_error | keymgr_shadow_reg_errors | 6.870s | 573.384us | 20 | 20 | 100.00 |
V2S | shadowed_reset_glitch | keymgr_shadow_reg_errors | 6.870s | 573.384us | 20 | 20 | 100.00 |
V2S | shadow_reg_update_error_with_csr_rw | keymgr_shadow_reg_errors_with_csr_rw | 15.370s | 1.728ms | 20 | 20 | 100.00 |
V2S | prim_count_check | keymgr_sec_cm | 17.040s | 2.165ms | 5 | 5 | 100.00 |
V2S | prim_fsm_check | keymgr_sec_cm | 17.040s | 2.165ms | 5 | 5 | 100.00 |
V2S | sec_cm_bus_integrity | keymgr_tl_intg_err | 8.940s | 1.167ms | 20 | 20 | 100.00 |
V2S | sec_cm_config_shadow | keymgr_shadow_reg_errors | 6.870s | 573.384us | 20 | 20 | 100.00 |
V2S | sec_cm_op_config_regwen | keymgr_cfg_regwen | 2.050m | 2.214ms | 50 | 50 | 100.00 |
V2S | sec_cm_reseed_config_regwen | keymgr_random | 51.570s | 1.616ms | 50 | 50 | 100.00 |
keymgr_csr_rw | 1.610s | 77.128us | 20 | 20 | 100.00 | ||
V2S | sec_cm_sw_binding_config_regwen | keymgr_random | 51.570s | 1.616ms | 50 | 50 | 100.00 |
keymgr_csr_rw | 1.610s | 77.128us | 20 | 20 | 100.00 | ||
V2S | sec_cm_max_key_ver_config_regwen | keymgr_random | 51.570s | 1.616ms | 50 | 50 | 100.00 |
keymgr_csr_rw | 1.610s | 77.128us | 20 | 20 | 100.00 | ||
V2S | sec_cm_lc_ctrl_intersig_mubi | keymgr_lc_disable | 12.310s | 1.400ms | 47 | 50 | 94.00 |
V2S | sec_cm_constants_consistency | keymgr_hwsw_invalid_input | 28.910s | 1.866ms | 50 | 50 | 100.00 |
V2S | sec_cm_intersig_consistency | keymgr_hwsw_invalid_input | 28.910s | 1.866ms | 50 | 50 | 100.00 |
V2S | sec_cm_hw_key_sw_noaccess | keymgr_random | 51.570s | 1.616ms | 50 | 50 | 100.00 |
V2S | sec_cm_output_keys_ctrl_redun | keymgr_sideload_protect | 40.350s | 1.082ms | 50 | 50 | 100.00 |
V2S | sec_cm_ctrl_fsm_sparse | keymgr_sec_cm | 17.040s | 2.165ms | 5 | 5 | 100.00 |
V2S | sec_cm_data_fsm_sparse | keymgr_sec_cm | 17.040s | 2.165ms | 5 | 5 | 100.00 |
V2S | sec_cm_ctrl_fsm_local_esc | keymgr_sec_cm | 17.040s | 2.165ms | 5 | 5 | 100.00 |
V2S | sec_cm_ctrl_fsm_consistency | keymgr_custom_cm | 28.070s | 8.410ms | 50 | 50 | 100.00 |
V2S | sec_cm_ctrl_fsm_global_esc | keymgr_lc_disable | 12.310s | 1.400ms | 47 | 50 | 94.00 |
V2S | sec_cm_ctrl_ctr_redun | keymgr_sec_cm | 17.040s | 2.165ms | 5 | 5 | 100.00 |
V2S | sec_cm_kmac_if_fsm_sparse | keymgr_sec_cm | 17.040s | 2.165ms | 5 | 5 | 100.00 |
V2S | sec_cm_kmac_if_ctr_redun | keymgr_sec_cm | 17.040s | 2.165ms | 5 | 5 | 100.00 |
V2S | sec_cm_kmac_if_cmd_ctrl_consistency | keymgr_custom_cm | 28.070s | 8.410ms | 50 | 50 | 100.00 |
V2S | sec_cm_kmac_if_done_ctrl_consistency | keymgr_custom_cm | 28.070s | 8.410ms | 50 | 50 | 100.00 |
V2S | sec_cm_reseed_ctr_redun | keymgr_sec_cm | 17.040s | 2.165ms | 5 | 5 | 100.00 |
V2S | sec_cm_side_load_sel_ctrl_consistency | keymgr_custom_cm | 28.070s | 8.410ms | 50 | 50 | 100.00 |
V2S | sec_cm_sideload_ctrl_fsm_sparse | keymgr_sec_cm | 17.040s | 2.165ms | 5 | 5 | 100.00 |
V2S | sec_cm_ctrl_key_integrity | keymgr_custom_cm | 28.070s | 8.410ms | 50 | 50 | 100.00 |
V2S | TOTAL | 165 | 165 | 100.00 | |||
V3 | stress_all_with_rand_reset | keymgr_stress_all_with_rand_reset | 35.630s | 2.913ms | 32 | 50 | 64.00 |
V3 | TOTAL | 32 | 50 | 64.00 | |||
TOTAL | 1088 | 1110 | 98.02 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 7 | 7 | 7 | 100.00 |
V2 | 16 | 16 | 14 | 87.50 |
V2S | 6 | 6 | 6 | 100.00 |
V3 | 1 | 1 | 0 | 0.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
---|---|---|---|---|---|---|---|
97.70 | 99.04 | 97.68 | 98.65 | 100.00 | 99.02 | 98.41 | 91.14 |
UVM_ERROR (cip_base_vseq.sv:829) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
has 14 failures:
0.keymgr_stress_all_with_rand_reset.55136760968236552061110847042319340508550488926349563199576285389514722738898
Line 398, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/0.keymgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 244432738 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10002 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 244432738 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.keymgr_stress_all_with_rand_reset.18543588447852714801965187929850550608443162415225392933780118558046881919462
Line 477, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/5.keymgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 173079270 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 173079270 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 12 more failures.
UVM_ERROR (keymgr_scoreboard.sv:692) [scoreboard] Check failed item.d_data == addr_phase_op_status (* [*] vs * [*])
has 2 failures:
16.keymgr_stress_all_with_rand_reset.109512449310368388973623015402743365157302498309657760845247823962871273190285
Line 669, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/16.keymgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 780481493 ps: (keymgr_scoreboard.sv:692) [uvm_test_top.env.scoreboard] Check failed item.d_data == addr_phase_op_status (1 [0x1] vs 3 [0x3])
UVM_INFO @ 780481493 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
44.keymgr_stress_all_with_rand_reset.29769582998374130122355349980713098396341398668608012253032439324131618331827
Line 1116, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/44.keymgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 243002566 ps: (keymgr_scoreboard.sv:692) [uvm_test_top.env.scoreboard] Check failed item.d_data == addr_phase_op_status (1 [0x1] vs 2 [0x2])
UVM_INFO @ 243002566 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:*
has 1 failures:
3.keymgr_stress_all_with_rand_reset.74732755300392150905867323114224092246468634798139880461596195169869727543982
Line 495, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/3.keymgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1091258872 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
UVM_INFO @ 1091258872 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[*], act_key.key[*]} !== keys_a_array[state][cdi][dest] (* [*] vs * [*]) AES key at state StOwnerKey for Attestation Aes
has 1 failures:
22.keymgr_lc_disable.67616463048446142749056569858218543307443982739009280735625432756306206727632
Line 372, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/22.keymgr_lc_disable/latest/run.log
UVM_ERROR @ 87541980 ps: (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[1], act_key.key[0]} !== keys_a_array[state][cdi][dest] (10149654602860465921975251469182803682915849055110649767752478628181195611609950682061623844380916704485160283135774969443172169405883048093508909244136948 [0xc1ca7a705f9cca43fcd52ade4f159a67a21217f40983cc5bdee7e569cdc6037611340a1e283fab4847c40f66858bc0096f6fe5f1723b88f1bbfecf6fa874bdf4] vs 10149654602860465921975251469182803682915849055110649767752478628181195611609950682061623844380916704485160283135774969443172169405883048093508909244136948 [0xc1ca7a705f9cca43fcd52ade4f159a67a21217f40983cc5bdee7e569cdc6037611340a1e283fab4847c40f66858bc0096f6fe5f1723b88f1bbfecf6fa874bdf4]) AES key at state StOwnerKey for Attestation Aes
UVM_INFO @ 87541980 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:651) [scoreboard] Check failed act_state == addr_phase_working_state (* [*] vs * [*])
has 1 failures:
29.keymgr_lc_disable.52943160301755954951066119151686392008679912375412739274459145488364559782159
Line 450, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/29.keymgr_lc_disable/latest/run.log
UVM_ERROR @ 148787556 ps: (keymgr_scoreboard.sv:651) [uvm_test_top.env.scoreboard] Check failed act_state == addr_phase_working_state (1 [0x1] vs 6 [0x6])
UVM_INFO @ 148787556 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:1066) [scoreboard] Check failed act == exp (* [*] vs * [*]) cdi_type: Attestation
has 1 failures:
32.keymgr_stress_all_with_rand_reset.90263484255680742496900885150113198641743548368251320384873173559556344795861
Line 1007, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/32.keymgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 314144387 ps: (keymgr_scoreboard.sv:1066) [uvm_test_top.env.scoreboard] Check failed act == exp (5500441857743866868511316537307677004834229257794966802536996763607336295011735150169805972740785173387445727131443100306699006597253112520858267779249040979348091504157989339252329487607447152804646331169596377291869200698950755521298481944205420794875148160643320172695382142620193623923805752900839183576168362453116471489415251736154531569747025801669852737857460804643422205863807048538787176194437146170103275860182226 [0xc6cb4ee0000000000000000000000000000000000000000000000000000000003a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f98e3b8d82922b12dbed874d3d39f5c1b77ae7cc6c1f59a1a7783bc29d52b5970f84e179b14f3171f4322254d739100cc2e8df85331a971572e7f94dd5d829922289391f1cbbcb28be3bbeeaa45767f2f3b4b36b93a8b28cc2ea4cbd103992eedc1e6ae77fb2ebd079506b95dbf4eec4d2] vs 1401991727574223770776179959533654309078864552450602076326120066348179481000132592976633084193185574333475508124886772065522820734429109039730692912595254211978205145445084734917930696975463104618343013666257823797734381955042369203742626582259196251867661458715792741349764235249628382865914942164276470103797800491978963463564343454279894237986342635506995187148693945447711951978585932804730996585870567624590546 [0xd9a0555700000000f3eab19000000000fa0e5e8500000000000000003a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f98e3b8d82922b12dbed874d3d39f5c1b77ae7cc6c1f59a1a7783bc29d52b5970f84e179b14f3171f4322254d739100cc2e8df85331a971572e7f94dd5d829922289391f1cbbcb28be3bbeeaa45767f2f3b4b36b93a8b28cc2ea4cbd103992eedc1e6ae77fb2ebd079506b95dbf4eec4d2]) cdi_type: Attestation
DiversificationKey act: 0xb4b36b93a8b28cc2ea4cbd103992eedc1e6ae77fb2ebd079506b95dbf4eec4d2, exp: 0xb4b36b93a8b28cc2ea4cbd103992eedc1e6ae77fb2ebd079506b95dbf4eec4d2
RomDigest act: 0xe8df85331a971572e7f94dd5d829922289391f1cbbcb28be3bbeeaa45767f2f3, exp: 0xe8df85331a971572e7f94dd5d829922289391f1cbbcb28be3bbeeaa45767f2f3
HealthMeasurement act: 0x84e179b14f3171f4322254d739100cc2, exp: 0x84e179b14f3171f4322254d739100cc2
UVM_ERROR (keymgr_scoreboard.sv:689) [scoreboard] Check failed edn_fifos[*].used() == * (* [*] vs * [*])
has 1 failures:
47.keymgr_lc_disable.50102251644626389298224784717448208472732809158596943871637143439698162088776
Line 295, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/47.keymgr_lc_disable/latest/run.log
UVM_ERROR @ 40766344 ps: (keymgr_scoreboard.sv:689) [uvm_test_top.env.scoreboard] Check failed edn_fifos[0].used() == 2 (0 [0x0] vs 2 [0x2])
UVM_INFO @ 40766344 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data !=
gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.sw_share0_output_*` has 1 failures:
47.keymgr_stress_all.15947893069691589205661016963103031965817308502097479976262485234660459967147
Line 453, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/47.keymgr_stress_all/latest/run.log
UVM_ERROR @ 67329291 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (0 [0x0] vs 0 [0x0]) reg name: keymgr_reg_block.sw_share0_output_5
UVM_INFO @ 67329291 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---