eb776817a5
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | keymgr_smoke | 45.770s | 5.715ms | 50 | 50 | 100.00 |
V1 | random | keymgr_random | 57.140s | 5.116ms | 50 | 50 | 100.00 |
V1 | csr_hw_reset | keymgr_csr_hw_reset | 1.420s | 54.434us | 5 | 5 | 100.00 |
V1 | csr_rw | keymgr_csr_rw | 1.610s | 31.556us | 20 | 20 | 100.00 |
V1 | csr_bit_bash | keymgr_csr_bit_bash | 32.340s | 4.755ms | 5 | 5 | 100.00 |
V1 | csr_aliasing | keymgr_csr_aliasing | 17.170s | 1.827ms | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | keymgr_csr_mem_rw_with_rand_reset | 2.180s | 199.224us | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | keymgr_csr_rw | 1.610s | 31.556us | 20 | 20 | 100.00 |
keymgr_csr_aliasing | 17.170s | 1.827ms | 5 | 5 | 100.00 | ||
V1 | TOTAL | 155 | 155 | 100.00 | |||
V2 | cfgen_during_op | keymgr_cfg_regwen | 1.664m | 7.620ms | 50 | 50 | 100.00 |
V2 | sideload | keymgr_sideload | 56.530s | 3.204ms | 50 | 50 | 100.00 |
keymgr_sideload_kmac | 39.600s | 4.338ms | 50 | 50 | 100.00 | ||
keymgr_sideload_aes | 58.030s | 5.763ms | 50 | 50 | 100.00 | ||
keymgr_sideload_otbn | 47.630s | 1.988ms | 50 | 50 | 100.00 | ||
V2 | direct_to_disabled_state | keymgr_direct_to_disabled | 28.810s | 2.212ms | 50 | 50 | 100.00 |
V2 | lc_disable | keymgr_lc_disable | 14.170s | 2.377ms | 49 | 50 | 98.00 |
V2 | kmac_error_response | keymgr_kmac_rsp_err | 7.390s | 439.187us | 50 | 50 | 100.00 |
V2 | invalid_sw_input | keymgr_sw_invalid_input | 1.192m | 10.700ms | 50 | 50 | 100.00 |
V2 | invalid_hw_input | keymgr_hwsw_invalid_input | 1.539m | 5.769ms | 50 | 50 | 100.00 |
V2 | sync_async_fault_cross | keymgr_sync_async_fault_cross | 27.690s | 4.361ms | 50 | 50 | 100.00 |
V2 | stress_all | keymgr_stress_all | 7.862m | 42.864ms | 50 | 50 | 100.00 |
V2 | intr_test | keymgr_intr_test | 0.920s | 42.980us | 50 | 50 | 100.00 |
V2 | alert_test | keymgr_alert_test | 1.010s | 72.208us | 50 | 50 | 100.00 |
V2 | tl_d_oob_addr_access | keymgr_tl_errors | 4.000s | 104.737us | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | keymgr_tl_errors | 4.000s | 104.737us | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | keymgr_csr_hw_reset | 1.420s | 54.434us | 5 | 5 | 100.00 |
keymgr_csr_rw | 1.610s | 31.556us | 20 | 20 | 100.00 | ||
keymgr_csr_aliasing | 17.170s | 1.827ms | 5 | 5 | 100.00 | ||
keymgr_same_csr_outstanding | 4.620s | 123.704us | 20 | 20 | 100.00 | ||
V2 | tl_d_partial_access | keymgr_csr_hw_reset | 1.420s | 54.434us | 5 | 5 | 100.00 |
keymgr_csr_rw | 1.610s | 31.556us | 20 | 20 | 100.00 | ||
keymgr_csr_aliasing | 17.170s | 1.827ms | 5 | 5 | 100.00 | ||
keymgr_same_csr_outstanding | 4.620s | 123.704us | 20 | 20 | 100.00 | ||
V2 | TOTAL | 739 | 740 | 99.86 | |||
V2S | sec_cm_additional_check | keymgr_sec_cm | 23.710s | 1.022ms | 5 | 5 | 100.00 |
V2S | tl_intg_err | keymgr_sec_cm | 23.710s | 1.022ms | 5 | 5 | 100.00 |
keymgr_tl_intg_err | 10.830s | 443.363us | 20 | 20 | 100.00 | ||
V2S | shadow_reg_update_error | keymgr_shadow_reg_errors | 4.250s | 140.635us | 20 | 20 | 100.00 |
V2S | shadow_reg_read_clear_staged_value | keymgr_shadow_reg_errors | 4.250s | 140.635us | 20 | 20 | 100.00 |
V2S | shadow_reg_storage_error | keymgr_shadow_reg_errors | 4.250s | 140.635us | 20 | 20 | 100.00 |
V2S | shadowed_reset_glitch | keymgr_shadow_reg_errors | 4.250s | 140.635us | 20 | 20 | 100.00 |
V2S | shadow_reg_update_error_with_csr_rw | keymgr_shadow_reg_errors_with_csr_rw | 16.530s | 1.081ms | 20 | 20 | 100.00 |
V2S | prim_count_check | keymgr_sec_cm | 23.710s | 1.022ms | 5 | 5 | 100.00 |
V2S | prim_fsm_check | keymgr_sec_cm | 23.710s | 1.022ms | 5 | 5 | 100.00 |
V2S | sec_cm_bus_integrity | keymgr_tl_intg_err | 10.830s | 443.363us | 20 | 20 | 100.00 |
V2S | sec_cm_config_shadow | keymgr_shadow_reg_errors | 4.250s | 140.635us | 20 | 20 | 100.00 |
V2S | sec_cm_op_config_regwen | keymgr_cfg_regwen | 1.664m | 7.620ms | 50 | 50 | 100.00 |
V2S | sec_cm_reseed_config_regwen | keymgr_random | 57.140s | 5.116ms | 50 | 50 | 100.00 |
keymgr_csr_rw | 1.610s | 31.556us | 20 | 20 | 100.00 | ||
V2S | sec_cm_sw_binding_config_regwen | keymgr_random | 57.140s | 5.116ms | 50 | 50 | 100.00 |
keymgr_csr_rw | 1.610s | 31.556us | 20 | 20 | 100.00 | ||
V2S | sec_cm_max_key_ver_config_regwen | keymgr_random | 57.140s | 5.116ms | 50 | 50 | 100.00 |
keymgr_csr_rw | 1.610s | 31.556us | 20 | 20 | 100.00 | ||
V2S | sec_cm_lc_ctrl_intersig_mubi | keymgr_lc_disable | 14.170s | 2.377ms | 49 | 50 | 98.00 |
V2S | sec_cm_constants_consistency | keymgr_hwsw_invalid_input | 1.539m | 5.769ms | 50 | 50 | 100.00 |
V2S | sec_cm_intersig_consistency | keymgr_hwsw_invalid_input | 1.539m | 5.769ms | 50 | 50 | 100.00 |
V2S | sec_cm_hw_key_sw_noaccess | keymgr_random | 57.140s | 5.116ms | 50 | 50 | 100.00 |
V2S | sec_cm_output_keys_ctrl_redun | keymgr_sideload_protect | 34.600s | 4.377ms | 49 | 50 | 98.00 |
V2S | sec_cm_ctrl_fsm_sparse | keymgr_sec_cm | 23.710s | 1.022ms | 5 | 5 | 100.00 |
V2S | sec_cm_data_fsm_sparse | keymgr_sec_cm | 23.710s | 1.022ms | 5 | 5 | 100.00 |
V2S | sec_cm_ctrl_fsm_local_esc | keymgr_sec_cm | 23.710s | 1.022ms | 5 | 5 | 100.00 |
V2S | sec_cm_ctrl_fsm_consistency | keymgr_custom_cm | 17.750s | 3.722ms | 50 | 50 | 100.00 |
V2S | sec_cm_ctrl_fsm_global_esc | keymgr_lc_disable | 14.170s | 2.377ms | 49 | 50 | 98.00 |
V2S | sec_cm_ctrl_ctr_redun | keymgr_sec_cm | 23.710s | 1.022ms | 5 | 5 | 100.00 |
V2S | sec_cm_kmac_if_fsm_sparse | keymgr_sec_cm | 23.710s | 1.022ms | 5 | 5 | 100.00 |
V2S | sec_cm_kmac_if_ctr_redun | keymgr_sec_cm | 23.710s | 1.022ms | 5 | 5 | 100.00 |
V2S | sec_cm_kmac_if_cmd_ctrl_consistency | keymgr_custom_cm | 17.750s | 3.722ms | 50 | 50 | 100.00 |
V2S | sec_cm_kmac_if_done_ctrl_consistency | keymgr_custom_cm | 17.750s | 3.722ms | 50 | 50 | 100.00 |
V2S | sec_cm_reseed_ctr_redun | keymgr_sec_cm | 23.710s | 1.022ms | 5 | 5 | 100.00 |
V2S | sec_cm_side_load_sel_ctrl_consistency | keymgr_custom_cm | 17.750s | 3.722ms | 50 | 50 | 100.00 |
V2S | sec_cm_sideload_ctrl_fsm_sparse | keymgr_sec_cm | 23.710s | 1.022ms | 5 | 5 | 100.00 |
V2S | sec_cm_ctrl_key_integrity | keymgr_custom_cm | 17.750s | 3.722ms | 50 | 50 | 100.00 |
V2S | TOTAL | 164 | 165 | 99.39 | |||
V3 | stress_all_with_rand_reset | keymgr_stress_all_with_rand_reset | 25.490s | 2.411ms | 26 | 50 | 52.00 |
V3 | TOTAL | 26 | 50 | 52.00 | |||
TOTAL | 1084 | 1110 | 97.66 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 7 | 7 | 7 | 100.00 |
V2 | 16 | 16 | 15 | 93.75 |
V2S | 6 | 6 | 5 | 83.33 |
V3 | 1 | 1 | 0 | 0.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
---|---|---|---|---|---|---|---|
97.75 | 99.04 | 97.99 | 98.61 | 100.00 | 99.02 | 98.41 | 91.19 |
UVM_ERROR (cip_base_vseq.sv:829) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
has 23 failures:
0.keymgr_stress_all_with_rand_reset.76844318143271701496111583907701834208609683650304379837750600892556718410573
Line 319, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/0.keymgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 123775953 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 123775953 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.keymgr_stress_all_with_rand_reset.74478215240967500177568218873037228038031595401467177198900226776209206059835
Line 374, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/4.keymgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 302904615 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 302904615 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 21 more failures.
UVM_ERROR (keymgr_scoreboard.sv:1066) [scoreboard] Check failed act == exp (* [*] vs * [*]) cdi_type: Attestation
has 1 failures:
16.keymgr_stress_all_with_rand_reset.32979552082940709565221943291744879208536317138033533851579975935083714910717
Line 671, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/16.keymgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 161824679 ps: (keymgr_scoreboard.sv:1066) [uvm_test_top.env.scoreboard] Check failed act == exp (6792886892766032042550411589270635882633611997175944979236155240060845275935456332195353653401656494727134668100890616512316663576507597409152772802121840325077462878837860770844741947076796226181775198050982966223116150445796460914258281527760993040931170617131281090548501020672488800341953086242651904828026403931825920928367674732635953185892013559300373188630085471178627964141597014442908445558762096227458575644244786 [0xf5814bd696acc3e820edeea498b6d5f5331e77f059a4345227438c316fb012953a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f999739ef187ea1744bdce2d52412bf26590fc4d0970281314a16502fff318ecc514394c9ac0b5728e332841bde96b926dc7f7101a54d52920bf70ecd8770014ec239a6a0a850233b3c993c1716dc73df6960ef9963ad96e3d5dd14fc40a45fcd585b50c9860e7a2d1009dfc0936243b32] vs 255735660038288093283024411979437971292600248220227082989304213761205804421005630055302172724394853158679506278587442211370257383605387644519255807973675379650697842863900578623432465742449813634021308382643429558617721190382805804201554461154276864022622510105666896491517381035043412648743042390123229478511922959201372023563314771025956012854606262730458913665172634733971298920789039149808003604521500633635329554004786 [0x93e1f803fee97d350d4677e7945b5cca255623111fa8d36b07fe95647c5d2b53a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f999739ef187ea1744bdce2d52412bf26590fc4d0970281314a16502fff318ecc514394c9ac0b5728e332841bde96b926dc7f7101a54d52920bf70ecd8770014ec239a6a0a850233b3c993c1716dc73df6960ef9963ad96e3d5dd14fc40a45fcd585b50c9860e7a2d1009dfc0936243b32]) cdi_type: Attestation
DiversificationKey act: 0x960ef9963ad96e3d5dd14fc40a45fcd585b50c9860e7a2d1009dfc0936243b32, exp: 0x960ef9963ad96e3d5dd14fc40a45fcd585b50c9860e7a2d1009dfc0936243b32
RomDigest act: 0xc7f7101a54d52920bf70ecd8770014ec239a6a0a850233b3c993c1716dc73df6, exp: 0xc7f7101a54d52920bf70ecd8770014ec239a6a0a850233b3c993c1716dc73df6
HealthMeasurement act: 0x14394c9ac0b5728e332841bde96b926d, exp: 0x14394c9ac0b5728e332841bde96b926d
UVM_ERROR (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[*], act_key.key[*]} !== keys_a_array[state][cdi][dest] (* [*] vs * [*]) AES key at state StDisabled for Attestation Aes
has 1 failures:
21.keymgr_lc_disable.22682377938523745322449790326583893839714958305812768201979907384809879182193
Line 659, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/21.keymgr_lc_disable/latest/run.log
UVM_ERROR @ 112606476 ps: (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[1], act_key.key[0]} !== keys_a_array[state][cdi][dest] (3740472737801492344301455258483290010918985217910803808434581507499061507012552200071903446143607203602955099475682508370002338506995602578787116125854815 [0x476b0cc5d0b770ea6ffd36c1d64be44a968e284b978cc33ee42e02288c0096dbf630ba12b047c606ba1993ab66fa7a3e81bb1edcbc4ad688213f1d7bbc491c5f] vs 3740472737801492344301455258483290010918985217910803808434581507499061507012552200071903446143607203602955099475682508370002338506995602578787116125854815 [0x476b0cc5d0b770ea6ffd36c1d64be44a968e284b978cc33ee42e02288c0096dbf630ba12b047c606ba1993ab66fa7a3e81bb1edcbc4ad688213f1d7bbc491c5f]) AES key at state StDisabled for Attestation Aes
UVM_INFO @ 112606476 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:*
has 1 failures:
33.keymgr_sideload_protect.93363339080326984204766814015401024386045253107136247283303597963583990409437
Line 283, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/33.keymgr_sideload_protect/latest/run.log
UVM_ERROR @ 7421558 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
UVM_INFO @ 7421558 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---