KEYMGR Simulation Results

Thursday June 06 2024 19:04:47 UTC

GitHub Revision: 32d52b8d41

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 59908589074363629542901507660786833114562191729708937078847065421241135561861

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	48.740s	3.274ms	49	50	98.00
V1	random	keymgr_random	1.222m	8.047ms	50	50	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.250s	139.345us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	1.580s	34.028us	20	20	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	15.740s	931.692us	5	5	100.00
V1	csr_aliasing	keymgr_csr_aliasing	8.820s	241.025us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	1.990s	29.773us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.580s	34.028us	20	20	100.00
		keymgr_csr_aliasing	8.820s	241.025us	5	5	100.00
V1		TOTAL			154	155	99.35
V2	cfgen_during_op	keymgr_cfg_regwen	2.005m	4.266ms	50	50	100.00
V2	sideload	keymgr_sideload	49.500s	3.525ms	50	50	100.00
		keymgr_sideload_kmac	57.490s	6.202ms	50	50	100.00
		keymgr_sideload_aes	1.235m	6.382ms	50	50	100.00
		keymgr_sideload_otbn	1.129m	7.925ms	50	50	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	51.730s	26.470ms	50	50	100.00
V2	lc_disable	keymgr_lc_disable	23.190s	1.131ms	50	50	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	23.760s	2.344ms	48	50	96.00
V2	invalid_sw_input	keymgr_sw_invalid_input	1.325m	7.949ms	50	50	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	54.130s	4.378ms	50	50	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	15.350s	1.705ms	50	50	100.00
V2	stress_all	keymgr_stress_all	9.122m	75.295ms	48	50	96.00
V2	intr_test	keymgr_intr_test	1.040s	25.241us	50	50	100.00
V2	alert_test	keymgr_alert_test	1.030s	53.237us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	3.770s	2.401ms	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	3.770s	2.401ms	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.250s	139.345us	5	5	100.00
		keymgr_csr_rw	1.580s	34.028us	20	20	100.00
		keymgr_csr_aliasing	8.820s	241.025us	5	5	100.00
		keymgr_same_csr_outstanding	3.850s	1.707ms	20	20	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.250s	139.345us	5	5	100.00
		keymgr_csr_rw	1.580s	34.028us	20	20	100.00
		keymgr_csr_aliasing	8.820s	241.025us	5	5	100.00
		keymgr_same_csr_outstanding	3.850s	1.707ms	20	20	100.00
V2		TOTAL			736	740	99.46
V2S	sec_cm_additional_check	keymgr_sec_cm	13.120s	1.864ms	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	13.120s	1.864ms	5	5	100.00
		keymgr_tl_intg_err	11.060s	2.135ms	20	20	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	4.290s	582.307us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	4.290s	582.307us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	4.290s	582.307us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	4.290s	582.307us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	12.630s	400.839us	20	20	100.00
V2S	prim_count_check	keymgr_sec_cm	13.120s	1.864ms	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	13.120s	1.864ms	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	11.060s	2.135ms	20	20	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	4.290s	582.307us	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	2.005m	4.266ms	50	50	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	1.222m	8.047ms	50	50	100.00
		keymgr_csr_rw	1.580s	34.028us	20	20	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	1.222m	8.047ms	50	50	100.00
		keymgr_csr_rw	1.580s	34.028us	20	20	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	1.222m	8.047ms	50	50	100.00
		keymgr_csr_rw	1.580s	34.028us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	23.190s	1.131ms	50	50	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	54.130s	4.378ms	50	50	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	54.130s	4.378ms	50	50	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	1.222m	8.047ms	50	50	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	34.670s	8.692ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	13.120s	1.864ms	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	13.120s	1.864ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	13.120s	1.864ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	31.460s	1.071ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	23.190s	1.131ms	50	50	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	13.120s	1.864ms	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	13.120s	1.864ms	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	13.120s	1.864ms	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	31.460s	1.071ms	50	50	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	31.460s	1.071ms	50	50	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	13.120s	1.864ms	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	31.460s	1.071ms	50	50	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	13.120s	1.864ms	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	31.460s	1.071ms	50	50	100.00
V2S		TOTAL			165	165	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	32.720s	4.794ms	29	50	58.00
V3		TOTAL			29	50	58.00
		TOTAL			1084	1110	97.66

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	6	85.71
V2	16	16	14	87.50
V2S	6	6	6	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.77	99.04	98.15	98.52	100.00	99.02	98.41	91.24

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:828) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 21 failures:

  • Test keymgr_stress_all_with_rand_reset has 21 failures.

    • 0.keymgr_stress_all_with_rand_reset.66803721261890066938909102619169328431372574892594201330883806612079500403420
      Line 1517, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/0.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 524642772 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10008 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 524642772 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.keymgr_stress_all_with_rand_reset.84058220139280353677639932055627645132422299225049143922338209813108280272317
      Line 705, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/2.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 833008044 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 833008044 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 19 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 3 failures:

  • Test keymgr_kmac_rsp_err has 1 failures.

    • 6.keymgr_kmac_rsp_err.52256004436761223301581685118523981942963965156862170180895083205449821967768
      Line 713, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/6.keymgr_kmac_rsp_err/latest/run.log

        UVM_ERROR @  37509274 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
        UVM_INFO @  37509274 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test keymgr_stress_all has 1 failures.

    • 14.keymgr_stress_all.103712106094002447914904422045437299198879629122897132429420257108502257575266
      Line 1704, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/14.keymgr_stress_all/latest/run.log

        UVM_ERROR @ 12424193086 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
        UVM_INFO @ 12424193086 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test keymgr_smoke has 1 failures.

    • 48.keymgr_smoke.79840009727658274880237373045868172870210430517146000943756825107760093581515
      Line 354, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/48.keymgr_smoke/latest/run.log

        UVM_ERROR @  49669194 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
        UVM_INFO @  49669194 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_scoreboard.sv:241) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_operation_err triggered unexpectedly has 1 failures:

  • Test keymgr_kmac_rsp_err has 1 failures.

    • 14.keymgr_kmac_rsp_err.20457142429641983090930022976187811903343295677644981759847987437504956702775
      Line 351, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/14.keymgr_kmac_rsp_err/latest/run.log

        UVM_ERROR @  35407053 ps: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_operation_err triggered unexpectedly
        UVM_INFO @  35407053 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data !=gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.sw_share1_output_*` has 1 failures:

  • Test keymgr_stress_all has 1 failures.

    • 36.keymgr_stress_all.19429781640672462427436320499100010816879466149145591825518441290313077597975
      Line 3331, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/36.keymgr_stress_all/latest/run.log

        UVM_ERROR @ 3732947860 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (0 [0x0] vs 0 [0x0]) reg name: keymgr_reg_block.sw_share1_output_0
        UVM_INFO @ 3732947860 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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• 2024.06.06_10.55.13
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