302b24f3c6
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | keymgr_smoke | 23.750s | 1.704ms | 49 | 50 | 98.00 |
V1 | random | keymgr_random | 1.363m | 4.466ms | 50 | 50 | 100.00 |
V1 | csr_hw_reset | keymgr_csr_hw_reset | 1.370s | 159.515us | 5 | 5 | 100.00 |
V1 | csr_rw | keymgr_csr_rw | 1.670s | 31.794us | 20 | 20 | 100.00 |
V1 | csr_bit_bash | keymgr_csr_bit_bash | 32.260s | 1.354ms | 5 | 5 | 100.00 |
V1 | csr_aliasing | keymgr_csr_aliasing | 11.290s | 5.105ms | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | keymgr_csr_mem_rw_with_rand_reset | 2.460s | 337.422us | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | keymgr_csr_rw | 1.670s | 31.794us | 20 | 20 | 100.00 |
keymgr_csr_aliasing | 11.290s | 5.105ms | 5 | 5 | 100.00 | ||
V1 | TOTAL | 154 | 155 | 99.35 | |||
V2 | cfgen_during_op | keymgr_cfg_regwen | 2.211m | 2.490ms | 50 | 50 | 100.00 |
V2 | sideload | keymgr_sideload | 32.470s | 3.217ms | 50 | 50 | 100.00 |
keymgr_sideload_kmac | 58.150s | 6.039ms | 50 | 50 | 100.00 | ||
keymgr_sideload_aes | 48.340s | 3.917ms | 50 | 50 | 100.00 | ||
keymgr_sideload_otbn | 41.300s | 6.580ms | 50 | 50 | 100.00 | ||
V2 | direct_to_disabled_state | keymgr_direct_to_disabled | 17.190s | 657.494us | 50 | 50 | 100.00 |
V2 | lc_disable | keymgr_lc_disable | 20.200s | 2.873ms | 48 | 50 | 96.00 |
V2 | kmac_error_response | keymgr_kmac_rsp_err | 17.960s | 10.595ms | 48 | 50 | 96.00 |
V2 | invalid_sw_input | keymgr_sw_invalid_input | 21.080s | 886.394us | 50 | 50 | 100.00 |
V2 | invalid_hw_input | keymgr_hwsw_invalid_input | 13.330s | 929.197us | 50 | 50 | 100.00 |
V2 | sync_async_fault_cross | keymgr_sync_async_fault_cross | 13.840s | 915.228us | 50 | 50 | 100.00 |
V2 | stress_all | keymgr_stress_all | 9.067m | 118.221ms | 48 | 50 | 96.00 |
V2 | intr_test | keymgr_intr_test | 0.910s | 36.297us | 50 | 50 | 100.00 |
V2 | alert_test | keymgr_alert_test | 1.030s | 31.960us | 50 | 50 | 100.00 |
V2 | tl_d_oob_addr_access | keymgr_tl_errors | 5.760s | 537.137us | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | keymgr_tl_errors | 5.760s | 537.137us | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | keymgr_csr_hw_reset | 1.370s | 159.515us | 5 | 5 | 100.00 |
keymgr_csr_rw | 1.670s | 31.794us | 20 | 20 | 100.00 | ||
keymgr_csr_aliasing | 11.290s | 5.105ms | 5 | 5 | 100.00 | ||
keymgr_same_csr_outstanding | 3.870s | 206.792us | 20 | 20 | 100.00 | ||
V2 | tl_d_partial_access | keymgr_csr_hw_reset | 1.370s | 159.515us | 5 | 5 | 100.00 |
keymgr_csr_rw | 1.670s | 31.794us | 20 | 20 | 100.00 | ||
keymgr_csr_aliasing | 11.290s | 5.105ms | 5 | 5 | 100.00 | ||
keymgr_same_csr_outstanding | 3.870s | 206.792us | 20 | 20 | 100.00 | ||
V2 | TOTAL | 734 | 740 | 99.19 | |||
V2S | sec_cm_additional_check | keymgr_sec_cm | 30.030s | 1.624ms | 5 | 5 | 100.00 |
V2S | tl_intg_err | keymgr_sec_cm | 30.030s | 1.624ms | 5 | 5 | 100.00 |
keymgr_tl_intg_err | 8.730s | 407.680us | 20 | 20 | 100.00 | ||
V2S | shadow_reg_update_error | keymgr_shadow_reg_errors | 4.390s | 623.851us | 20 | 20 | 100.00 |
V2S | shadow_reg_read_clear_staged_value | keymgr_shadow_reg_errors | 4.390s | 623.851us | 20 | 20 | 100.00 |
V2S | shadow_reg_storage_error | keymgr_shadow_reg_errors | 4.390s | 623.851us | 20 | 20 | 100.00 |
V2S | shadowed_reset_glitch | keymgr_shadow_reg_errors | 4.390s | 623.851us | 20 | 20 | 100.00 |
V2S | shadow_reg_update_error_with_csr_rw | keymgr_shadow_reg_errors_with_csr_rw | 17.030s | 429.103us | 20 | 20 | 100.00 |
V2S | prim_count_check | keymgr_sec_cm | 30.030s | 1.624ms | 5 | 5 | 100.00 |
V2S | prim_fsm_check | keymgr_sec_cm | 30.030s | 1.624ms | 5 | 5 | 100.00 |
V2S | sec_cm_bus_integrity | keymgr_tl_intg_err | 8.730s | 407.680us | 20 | 20 | 100.00 |
V2S | sec_cm_config_shadow | keymgr_shadow_reg_errors | 4.390s | 623.851us | 20 | 20 | 100.00 |
V2S | sec_cm_op_config_regwen | keymgr_cfg_regwen | 2.211m | 2.490ms | 50 | 50 | 100.00 |
V2S | sec_cm_reseed_config_regwen | keymgr_random | 1.363m | 4.466ms | 50 | 50 | 100.00 |
keymgr_csr_rw | 1.670s | 31.794us | 20 | 20 | 100.00 | ||
V2S | sec_cm_sw_binding_config_regwen | keymgr_random | 1.363m | 4.466ms | 50 | 50 | 100.00 |
keymgr_csr_rw | 1.670s | 31.794us | 20 | 20 | 100.00 | ||
V2S | sec_cm_max_key_ver_config_regwen | keymgr_random | 1.363m | 4.466ms | 50 | 50 | 100.00 |
keymgr_csr_rw | 1.670s | 31.794us | 20 | 20 | 100.00 | ||
V2S | sec_cm_lc_ctrl_intersig_mubi | keymgr_lc_disable | 20.200s | 2.873ms | 48 | 50 | 96.00 |
V2S | sec_cm_constants_consistency | keymgr_hwsw_invalid_input | 13.330s | 929.197us | 50 | 50 | 100.00 |
V2S | sec_cm_intersig_consistency | keymgr_hwsw_invalid_input | 13.330s | 929.197us | 50 | 50 | 100.00 |
V2S | sec_cm_hw_key_sw_noaccess | keymgr_random | 1.363m | 4.466ms | 50 | 50 | 100.00 |
V2S | sec_cm_output_keys_ctrl_redun | keymgr_sideload_protect | 14.970s | 499.726us | 50 | 50 | 100.00 |
V2S | sec_cm_ctrl_fsm_sparse | keymgr_sec_cm | 30.030s | 1.624ms | 5 | 5 | 100.00 |
V2S | sec_cm_data_fsm_sparse | keymgr_sec_cm | 30.030s | 1.624ms | 5 | 5 | 100.00 |
V2S | sec_cm_ctrl_fsm_local_esc | keymgr_sec_cm | 30.030s | 1.624ms | 5 | 5 | 100.00 |
V2S | sec_cm_ctrl_fsm_consistency | keymgr_custom_cm | 46.640s | 1.458ms | 50 | 50 | 100.00 |
V2S | sec_cm_ctrl_fsm_global_esc | keymgr_lc_disable | 20.200s | 2.873ms | 48 | 50 | 96.00 |
V2S | sec_cm_ctrl_ctr_redun | keymgr_sec_cm | 30.030s | 1.624ms | 5 | 5 | 100.00 |
V2S | sec_cm_kmac_if_fsm_sparse | keymgr_sec_cm | 30.030s | 1.624ms | 5 | 5 | 100.00 |
V2S | sec_cm_kmac_if_ctr_redun | keymgr_sec_cm | 30.030s | 1.624ms | 5 | 5 | 100.00 |
V2S | sec_cm_kmac_if_cmd_ctrl_consistency | keymgr_custom_cm | 46.640s | 1.458ms | 50 | 50 | 100.00 |
V2S | sec_cm_kmac_if_done_ctrl_consistency | keymgr_custom_cm | 46.640s | 1.458ms | 50 | 50 | 100.00 |
V2S | sec_cm_reseed_ctr_redun | keymgr_sec_cm | 30.030s | 1.624ms | 5 | 5 | 100.00 |
V2S | sec_cm_side_load_sel_ctrl_consistency | keymgr_custom_cm | 46.640s | 1.458ms | 50 | 50 | 100.00 |
V2S | sec_cm_sideload_ctrl_fsm_sparse | keymgr_sec_cm | 30.030s | 1.624ms | 5 | 5 | 100.00 |
V2S | sec_cm_ctrl_key_integrity | keymgr_custom_cm | 46.640s | 1.458ms | 50 | 50 | 100.00 |
V2S | TOTAL | 165 | 165 | 100.00 | |||
V3 | stress_all_with_rand_reset | keymgr_stress_all_with_rand_reset | 31.880s | 1.981ms | 30 | 50 | 60.00 |
V3 | TOTAL | 30 | 50 | 60.00 | |||
TOTAL | 1083 | 1110 | 97.57 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 7 | 7 | 6 | 85.71 |
V2 | 16 | 16 | 13 | 81.25 |
V2S | 6 | 6 | 6 | 100.00 |
V3 | 1 | 1 | 0 | 0.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
---|---|---|---|---|---|---|---|
97.37 | 99.00 | 98.11 | 98.33 | 97.67 | 98.93 | 98.41 | 91.14 |
UVM_ERROR (cip_base_vseq.sv:828) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
has 19 failures:
0.keymgr_stress_all_with_rand_reset.36592024583498935059914867518034269728729996301001034394290985845699904460210
Line 2093, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/0.keymgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2791532966 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2791532966 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.keymgr_stress_all_with_rand_reset.50757717784669050075255558000937518803781765493698713705417253838012757595781
Line 336, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/4.keymgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 403098885 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 403098885 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 17 more failures.
UVM_ERROR (cip_base_scoreboard.sv:241) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_operation_err triggered unexpectedly
has 2 failures:
6.keymgr_kmac_rsp_err.92620300864834944608325403316376262048804041480635252790658197788201655426014
Line 691, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/6.keymgr_kmac_rsp_err/latest/run.log
UVM_ERROR @ 27156214 ps: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_operation_err triggered unexpectedly
UVM_INFO @ 27156214 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
17.keymgr_kmac_rsp_err.76928956066709188672597147136511245949719544485262620737020482562341539798688
Line 519, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/17.keymgr_kmac_rsp_err/latest/run.log
UVM_ERROR @ 55225113 ps: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_operation_err triggered unexpectedly
UVM_INFO @ 55225113 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:*
has 2 failures:
Test keymgr_smoke has 1 failures.
17.keymgr_smoke.7340093296659602175159211420247560482207761725459451183959079172797963876256
Line 268, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/17.keymgr_smoke/latest/run.log
UVM_ERROR @ 10715888 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
UVM_INFO @ 10715888 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test keymgr_lc_disable has 1 failures.
30.keymgr_lc_disable.74922249198654294203297563228669607744167744218021321489408503166330490380000
Line 361, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/30.keymgr_lc_disable/latest/run.log
UVM_ERROR @ 100312868 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:2000
UVM_INFO @ 100312868 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data !=
gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.sw_share1_output_*` has 1 failures:
15.keymgr_stress_all.13445538368765912839943316442159036190628393834794831553017210344233109433091
Line 731, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/15.keymgr_stress_all/latest/run.log
UVM_ERROR @ 1065676214 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (1703058815 [0x65829d7f] vs 1703058815 [0x65829d7f]) reg name: keymgr_reg_block.sw_share1_output_1
UVM_INFO @ 1065676214 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[*], act_key.key[*]} !== keys_a_array[state][cdi][dest] (* [*] vs * [*]) KMAC key at state StDisabled for Attestation Kmac
has 1 failures:
24.keymgr_lc_disable.59426029104403730528664236461450998247107019901642344199654697648961774856488
Line 724, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/24.keymgr_lc_disable/latest/run.log
UVM_ERROR @ 76448301 ps: (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[1], act_key.key[0]} !== keys_a_array[state][cdi][dest] (11192921120040081442102063416973545381054783967606903083786252940620892067023250387684803554670372200771376760036874506102485849260436793357912322888756318 [0xd5b5dbd99fc00155d4605f9c133484f385f454c0efd09944b109b1b60f7479ca8e6e1d752c82e57f01a292b3763c41ba8a3fe06b86920c1faeacab995bc8ec5e] vs 11192921120040081442102063416973545381054783967606903083786252940620892067023250387684803554670372200771376760036874506102485849260436793357912322888756318 [0xd5b5dbd99fc00155d4605f9c133484f385f454c0efd09944b109b1b60f7479ca8e6e1d752c82e57f01a292b3763c41ba8a3fe06b86920c1faeacab995bc8ec5e]) KMAC key at state StDisabled for Attestation Kmac
UVM_INFO @ 76448301 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:692) [scoreboard] Check failed item.d_data == addr_phase_op_status (* [*] vs * [*])
has 1 failures:
32.keymgr_stress_all.49832875311606851093458120097385899649883505840811504854681557244805545541412
Line 1426, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/32.keymgr_stress_all/latest/run.log
UVM_ERROR @ 4376919483 ps: (keymgr_scoreboard.sv:692) [uvm_test_top.env.scoreboard] Check failed item.d_data == addr_phase_op_status (1 [0x1] vs 2 [0x2])
UVM_INFO @ 4376919483 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:1064) [scoreboard] Check failed act == exp (* [*] vs * [*]) cdi_type: Attestation
has 1 failures:
42.keymgr_stress_all_with_rand_reset.99196744085669627616905550582692093563500727056068704749598852247382171130222
Line 562, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/42.keymgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 256939975 ps: (keymgr_scoreboard.sv:1064) [uvm_test_top.env.scoreboard] Check failed act == exp (2543808759293604397993531668896972415349556631721119931151905356623706962918586413689315575486843926975389691184403704283665645844598268313264785753332559676484408190243608908662800104766870518226593455100540200916345759127598299166716136605038745503349235120494603102427030327145274527663380270846321931324877158152847243784953 [0xc460573843c0cd9600000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f0f000000000000000005cfbd765ce33f34ea20a046cf42e6eac560a3f82bfa76285b5c1d4aea7c915e49a32d1c89be0f5073a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f9] vs 4756133562816085478188046056783101631173483549736152691326365855048391693912039776896441171983714978466515233471588401577006637911289917368564288521172399431479155718911236539850876316721421065768033774107865074772150540845682976720108577200949521765632441938652227174505859038313538337959683383334960700022287014542886288750545117295353 [0x557c9c62a79e54160000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f0f000000000000000005cfbd765ce33f34ea20a046cf42e6eac560a3f82bfa76285b5c1d4aea7c915e49a32d1c89be0f5073a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f9]) cdi_type: Attestation
HardwareRevisionSecret act: 0x3a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f9, exp: 0x3a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f9
RomDigest act: 0xa20a046cf42e6eac560a3f82bfa76285b5c1d4aea7c915e49a32d1c89be0f507, exp: 0xa20a046cf42e6eac560a3f82bfa76285b5c1d4aea7c915e49a32d1c89be0f507
HealthMeasurement act: 0x5cfbd765ce33f34e, exp: 0x5cfbd765ce33f34e