f92a5ee77b
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | keymgr_smoke | 27.450s | 1.500ms | 50 | 50 | 100.00 |
V1 | random | keymgr_random | 1.257m | 9.962ms | 50 | 50 | 100.00 |
V1 | csr_hw_reset | keymgr_csr_hw_reset | 1.400s | 104.225us | 5 | 5 | 100.00 |
V1 | csr_rw | keymgr_csr_rw | 1.620s | 59.822us | 20 | 20 | 100.00 |
V1 | csr_bit_bash | keymgr_csr_bit_bash | 26.490s | 5.761ms | 5 | 5 | 100.00 |
V1 | csr_aliasing | keymgr_csr_aliasing | 10.930s | 1.016ms | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | keymgr_csr_mem_rw_with_rand_reset | 2.380s | 451.744us | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | keymgr_csr_rw | 1.620s | 59.822us | 20 | 20 | 100.00 |
keymgr_csr_aliasing | 10.930s | 1.016ms | 5 | 5 | 100.00 | ||
V1 | TOTAL | 155 | 155 | 100.00 | |||
V2 | cfgen_during_op | keymgr_cfg_regwen | 1.778m | 1.980ms | 49 | 50 | 98.00 |
V2 | sideload | keymgr_sideload | 54.550s | 10.142ms | 50 | 50 | 100.00 |
keymgr_sideload_kmac | 1.096m | 6.694ms | 50 | 50 | 100.00 | ||
keymgr_sideload_aes | 53.050s | 3.428ms | 50 | 50 | 100.00 | ||
keymgr_sideload_otbn | 23.830s | 1.820ms | 50 | 50 | 100.00 | ||
V2 | direct_to_disabled_state | keymgr_direct_to_disabled | 16.370s | 1.684ms | 49 | 50 | 98.00 |
V2 | lc_disable | keymgr_lc_disable | 32.490s | 6.085ms | 50 | 50 | 100.00 |
V2 | kmac_error_response | keymgr_kmac_rsp_err | 6.960s | 319.287us | 50 | 50 | 100.00 |
V2 | invalid_sw_input | keymgr_sw_invalid_input | 28.550s | 1.795ms | 50 | 50 | 100.00 |
V2 | invalid_hw_input | keymgr_hwsw_invalid_input | 1.302m | 31.944ms | 50 | 50 | 100.00 |
V2 | sync_async_fault_cross | keymgr_sync_async_fault_cross | 22.130s | 6.942ms | 50 | 50 | 100.00 |
V2 | stress_all | keymgr_stress_all | 1.935m | 3.959ms | 49 | 50 | 98.00 |
V2 | intr_test | keymgr_intr_test | 0.950s | 18.128us | 50 | 50 | 100.00 |
V2 | alert_test | keymgr_alert_test | 1.000s | 19.659us | 50 | 50 | 100.00 |
V2 | tl_d_oob_addr_access | keymgr_tl_errors | 5.290s | 160.863us | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | keymgr_tl_errors | 5.290s | 160.863us | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | keymgr_csr_hw_reset | 1.400s | 104.225us | 5 | 5 | 100.00 |
keymgr_csr_rw | 1.620s | 59.822us | 20 | 20 | 100.00 | ||
keymgr_csr_aliasing | 10.930s | 1.016ms | 5 | 5 | 100.00 | ||
keymgr_same_csr_outstanding | 4.260s | 237.280us | 20 | 20 | 100.00 | ||
V2 | tl_d_partial_access | keymgr_csr_hw_reset | 1.400s | 104.225us | 5 | 5 | 100.00 |
keymgr_csr_rw | 1.620s | 59.822us | 20 | 20 | 100.00 | ||
keymgr_csr_aliasing | 10.930s | 1.016ms | 5 | 5 | 100.00 | ||
keymgr_same_csr_outstanding | 4.260s | 237.280us | 20 | 20 | 100.00 | ||
V2 | TOTAL | 737 | 740 | 99.59 | |||
V2S | sec_cm_additional_check | keymgr_sec_cm | 12.900s | 618.865us | 5 | 5 | 100.00 |
V2S | tl_intg_err | keymgr_sec_cm | 12.900s | 618.865us | 5 | 5 | 100.00 |
keymgr_tl_intg_err | 13.490s | 515.494us | 20 | 20 | 100.00 | ||
V2S | shadow_reg_update_error | keymgr_shadow_reg_errors | 5.760s | 223.767us | 20 | 20 | 100.00 |
V2S | shadow_reg_read_clear_staged_value | keymgr_shadow_reg_errors | 5.760s | 223.767us | 20 | 20 | 100.00 |
V2S | shadow_reg_storage_error | keymgr_shadow_reg_errors | 5.760s | 223.767us | 20 | 20 | 100.00 |
V2S | shadowed_reset_glitch | keymgr_shadow_reg_errors | 5.760s | 223.767us | 20 | 20 | 100.00 |
V2S | shadow_reg_update_error_with_csr_rw | keymgr_shadow_reg_errors_with_csr_rw | 13.180s | 2.796ms | 20 | 20 | 100.00 |
V2S | prim_count_check | keymgr_sec_cm | 12.900s | 618.865us | 5 | 5 | 100.00 |
V2S | prim_fsm_check | keymgr_sec_cm | 12.900s | 618.865us | 5 | 5 | 100.00 |
V2S | sec_cm_bus_integrity | keymgr_tl_intg_err | 13.490s | 515.494us | 20 | 20 | 100.00 |
V2S | sec_cm_config_shadow | keymgr_shadow_reg_errors | 5.760s | 223.767us | 20 | 20 | 100.00 |
V2S | sec_cm_op_config_regwen | keymgr_cfg_regwen | 1.778m | 1.980ms | 49 | 50 | 98.00 |
V2S | sec_cm_reseed_config_regwen | keymgr_random | 1.257m | 9.962ms | 50 | 50 | 100.00 |
keymgr_csr_rw | 1.620s | 59.822us | 20 | 20 | 100.00 | ||
V2S | sec_cm_sw_binding_config_regwen | keymgr_random | 1.257m | 9.962ms | 50 | 50 | 100.00 |
keymgr_csr_rw | 1.620s | 59.822us | 20 | 20 | 100.00 | ||
V2S | sec_cm_max_key_ver_config_regwen | keymgr_random | 1.257m | 9.962ms | 50 | 50 | 100.00 |
keymgr_csr_rw | 1.620s | 59.822us | 20 | 20 | 100.00 | ||
V2S | sec_cm_lc_ctrl_intersig_mubi | keymgr_lc_disable | 32.490s | 6.085ms | 50 | 50 | 100.00 |
V2S | sec_cm_constants_consistency | keymgr_hwsw_invalid_input | 1.302m | 31.944ms | 50 | 50 | 100.00 |
V2S | sec_cm_intersig_consistency | keymgr_hwsw_invalid_input | 1.302m | 31.944ms | 50 | 50 | 100.00 |
V2S | sec_cm_hw_key_sw_noaccess | keymgr_random | 1.257m | 9.962ms | 50 | 50 | 100.00 |
V2S | sec_cm_output_keys_ctrl_redun | keymgr_sideload_protect | 53.970s | 2.732ms | 50 | 50 | 100.00 |
V2S | sec_cm_ctrl_fsm_sparse | keymgr_sec_cm | 12.900s | 618.865us | 5 | 5 | 100.00 |
V2S | sec_cm_data_fsm_sparse | keymgr_sec_cm | 12.900s | 618.865us | 5 | 5 | 100.00 |
V2S | sec_cm_ctrl_fsm_local_esc | keymgr_sec_cm | 12.900s | 618.865us | 5 | 5 | 100.00 |
V2S | sec_cm_ctrl_fsm_consistency | keymgr_custom_cm | 10.030s | 585.612us | 50 | 50 | 100.00 |
V2S | sec_cm_ctrl_fsm_global_esc | keymgr_lc_disable | 32.490s | 6.085ms | 50 | 50 | 100.00 |
V2S | sec_cm_ctrl_ctr_redun | keymgr_sec_cm | 12.900s | 618.865us | 5 | 5 | 100.00 |
V2S | sec_cm_kmac_if_fsm_sparse | keymgr_sec_cm | 12.900s | 618.865us | 5 | 5 | 100.00 |
V2S | sec_cm_kmac_if_ctr_redun | keymgr_sec_cm | 12.900s | 618.865us | 5 | 5 | 100.00 |
V2S | sec_cm_kmac_if_cmd_ctrl_consistency | keymgr_custom_cm | 10.030s | 585.612us | 50 | 50 | 100.00 |
V2S | sec_cm_kmac_if_done_ctrl_consistency | keymgr_custom_cm | 10.030s | 585.612us | 50 | 50 | 100.00 |
V2S | sec_cm_reseed_ctr_redun | keymgr_sec_cm | 12.900s | 618.865us | 5 | 5 | 100.00 |
V2S | sec_cm_side_load_sel_ctrl_consistency | keymgr_custom_cm | 10.030s | 585.612us | 50 | 50 | 100.00 |
V2S | sec_cm_sideload_ctrl_fsm_sparse | keymgr_sec_cm | 12.900s | 618.865us | 5 | 5 | 100.00 |
V2S | sec_cm_ctrl_key_integrity | keymgr_custom_cm | 10.030s | 585.612us | 50 | 50 | 100.00 |
V2S | TOTAL | 165 | 165 | 100.00 | |||
V3 | stress_all_with_rand_reset | keymgr_stress_all_with_rand_reset | 27.800s | 2.893ms | 30 | 50 | 60.00 |
V3 | TOTAL | 30 | 50 | 60.00 | |||
TOTAL | 1087 | 1110 | 97.93 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 7 | 7 | 7 | 100.00 |
V2 | 16 | 16 | 13 | 81.25 |
V2S | 6 | 6 | 6 | 100.00 |
V3 | 1 | 1 | 0 | 0.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
---|---|---|---|---|---|---|---|
97.72 | 99.04 | 98.15 | 98.24 | 100.00 | 99.02 | 98.41 | 91.17 |
UVM_ERROR (cip_base_vseq.sv:828) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
has 20 failures:
0.keymgr_stress_all_with_rand_reset.32846038625364760467054762404198811696705258458971282325061809279324132493707
Line 805, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/0.keymgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 3017666340 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3017666340 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.keymgr_stress_all_with_rand_reset.9342694932750926060143133519809647657695712126448382642264372143918678752596
Line 465, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/1.keymgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 230414067 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 230414067 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 18 more failures.
UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:*
has 1 failures:
32.keymgr_direct_to_disabled.68429520420835514996034599852406501900660140987917214678518351512552007095207
Line 419, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/32.keymgr_direct_to_disabled/latest/run.log
UVM_ERROR @ 17343848 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
UVM_INFO @ 17343848 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:794) [scoreboard] Check failed item.d_data ==
gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.start` has 1 failures:
48.keymgr_cfg_regwen.39459281621379222117762636177181982588348786093169208029942538303736496581817
Line 310, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/48.keymgr_cfg_regwen/latest/run.log
UVM_ERROR @ 5746877 ps: (keymgr_scoreboard.sv:794) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (0 [0x0] vs 1 [0x1]) reg name: keymgr_reg_block.start
UVM_INFO @ 5746877 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[*], act_key.key[*]} !== keys_a_array[state][cdi][dest] (* [*] vs * [*]) AES key at state StCreatorRootKey for Attestation Aes
has 1 failures:
49.keymgr_stress_all.10069035450404196580482161725824343396635426869646295798451177632471536731292
Line 605, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/49.keymgr_stress_all/latest/run.log
UVM_ERROR @ 1741312673 ps: (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[1], act_key.key[0]} !== keys_a_array[state][cdi][dest] (8396709691253347857259335173623699230518357588105204937750516233491604479528993115189390086465290626049642563946576860452569397774132443958333996933436237 [0xa05243147ba2a9a858cb1b10e316e59b8e6ff91b4688afc83c9cebb898cfe6cdd115d8a5db659c87612d66ead71242e77dcedbc572fdfe704b4fd49399f1d34d] vs 8396709691253347857259335173623699230518357588105204937750516233491604479528993115189390086465290626049642563946576860452569397774132443958333996933436237 [0xa05243147ba2a9a858cb1b10e316e59b8e6ff91b4688afc83c9cebb898cfe6cdd115d8a5db659c87612d66ead71242e77dcedbc572fdfe704b4fd49399f1d34d]) AES key at state StCreatorRootKey for Attestation Aes
UVM_INFO @ 1741312673 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---