KEYMGR Simulation Results

Monday June 10 2024 23:28:43 UTC

GitHub Revision: a8c9c17a8c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 72227341233107832543509484606850665418885932500709631655793413524197290927900

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	50.450s	1.576ms	50	50	100.00
V1	random	keymgr_random	1.027m	3.584ms	50	50	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.440s	99.381us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	1.480s	27.630us	20	20	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	14.950s	257.390us	5	5	100.00
V1	csr_aliasing	keymgr_csr_aliasing	10.640s	734.773us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.260s	184.479us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.480s	27.630us	20	20	100.00
		keymgr_csr_aliasing	10.640s	734.773us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	2.134m	2.567ms	49	50	98.00
V2	sideload	keymgr_sideload	48.300s	20.288ms	50	50	100.00
		keymgr_sideload_kmac	1.128m	11.539ms	50	50	100.00
		keymgr_sideload_aes	40.810s	1.277ms	50	50	100.00
		keymgr_sideload_otbn	49.340s	6.763ms	49	50	98.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	53.430s	10.832ms	50	50	100.00
V2	lc_disable	keymgr_lc_disable	7.430s	235.194us	50	50	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	6.790s	167.133us	49	50	98.00
V2	invalid_sw_input	keymgr_sw_invalid_input	52.480s	2.114ms	50	50	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	58.580s	8.257ms	50	50	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	10.670s	2.132ms	50	50	100.00
V2	stress_all	keymgr_stress_all	5.915m	112.360ms	49	50	98.00
V2	intr_test	keymgr_intr_test	0.930s	14.899us	50	50	100.00
V2	alert_test	keymgr_alert_test	1.160s	195.919us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	5.330s	511.447us	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	5.330s	511.447us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.440s	99.381us	5	5	100.00
		keymgr_csr_rw	1.480s	27.630us	20	20	100.00
		keymgr_csr_aliasing	10.640s	734.773us	5	5	100.00
		keymgr_same_csr_outstanding	4.660s	124.823us	20	20	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.440s	99.381us	5	5	100.00
		keymgr_csr_rw	1.480s	27.630us	20	20	100.00
		keymgr_csr_aliasing	10.640s	734.773us	5	5	100.00
		keymgr_same_csr_outstanding	4.660s	124.823us	20	20	100.00
V2		TOTAL			736	740	99.46
V2S	sec_cm_additional_check	keymgr_sec_cm	14.430s	2.524ms	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	14.430s	2.524ms	5	5	100.00
		keymgr_tl_intg_err	10.870s	3.230ms	20	20	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	4.600s	584.638us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	4.600s	584.638us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	4.600s	584.638us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	4.600s	584.638us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	14.620s	808.271us	20	20	100.00
V2S	prim_count_check	keymgr_sec_cm	14.430s	2.524ms	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	14.430s	2.524ms	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	10.870s	3.230ms	20	20	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	4.600s	584.638us	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	2.134m	2.567ms	49	50	98.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	1.027m	3.584ms	50	50	100.00
		keymgr_csr_rw	1.480s	27.630us	20	20	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	1.027m	3.584ms	50	50	100.00
		keymgr_csr_rw	1.480s	27.630us	20	20	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	1.027m	3.584ms	50	50	100.00
		keymgr_csr_rw	1.480s	27.630us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	7.430s	235.194us	50	50	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	58.580s	8.257ms	50	50	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	58.580s	8.257ms	50	50	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	1.027m	3.584ms	50	50	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	19.050s	1.042ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	14.430s	2.524ms	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	14.430s	2.524ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	14.430s	2.524ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	1.240m	9.337ms	49	50	98.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	7.430s	235.194us	50	50	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	14.430s	2.524ms	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	14.430s	2.524ms	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	14.430s	2.524ms	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	1.240m	9.337ms	49	50	98.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	1.240m	9.337ms	49	50	98.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	14.430s	2.524ms	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	1.240m	9.337ms	49	50	98.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	14.430s	2.524ms	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	1.240m	9.337ms	49	50	98.00
V2S		TOTAL			164	165	99.39
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	31.300s	6.348ms	34	50	68.00
V3		TOTAL			34	50	68.00
		TOTAL			1089	1110	98.11

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	16	16	12	75.00
V2S	6	6	5	83.33
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.37	99.00	97.99	98.38	97.67	98.93	98.41	91.22

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:828) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 16 failures:

  • Test keymgr_stress_all_with_rand_reset has 16 failures.

    • 5.keymgr_stress_all_with_rand_reset.65806076113238066795173248666639903988138924012651024040783753491759522744907
      Line 286, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/5.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 144798574 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 144798574 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 10.keymgr_stress_all_with_rand_reset.5340796519351810896826984579023902866971439504903588571882233372945929663471
      Line 333, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/10.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 119656752 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 119656752 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 14 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 3 failures:

  • Test keymgr_custom_cm has 1 failures.

    • 8.keymgr_custom_cm.33919836686977141638742598790777682147448612027722085526097121490676965330521
      Line 306, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/8.keymgr_custom_cm/latest/run.log

        UVM_ERROR @  58469733 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
        UVM_INFO @  58469733 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test keymgr_sideload_otbn has 1 failures.

    • 10.keymgr_sideload_otbn.102705441372233155908003056536268328891558717607756508622467757269763285649370
      Line 271, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/10.keymgr_sideload_otbn/latest/run.log

        UVM_ERROR @  15639529 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
        UVM_INFO @  15639529 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test keymgr_stress_all has 1 failures.

    • 25.keymgr_stress_all.78750974343902508640274479212059692230682619778610593108844714132126130073612
      Line 551, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/25.keymgr_stress_all/latest/run.log

        UVM_ERROR @ 111989018 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:2000
        UVM_INFO @ 111989018 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (keymgr_scoreboard.sv:794) [scoreboard] Check failed item.d_data ==gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.start` has 1 failures:

  • Test keymgr_cfg_regwen has 1 failures.

    • 24.keymgr_cfg_regwen.12953108016319714544492027018153823150024412425780322359052831252324602418573
      Line 336, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/24.keymgr_cfg_regwen/latest/run.log

        UVM_ERROR @  19279304 ps: (keymgr_scoreboard.sv:794) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (0 [0x0] vs 1 [0x1]) reg name: keymgr_reg_block.start
        UVM_INFO @  19279304 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_scoreboard.sv:241) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_operation_err triggered unexpectedly has 1 failures:

  • Test keymgr_kmac_rsp_err has 1 failures.

    • 33.keymgr_kmac_rsp_err.99916841309648250734430761603500077961714026705664050228243758172322363859877
      Line 499, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/33.keymgr_kmac_rsp_err/latest/run.log

        UVM_ERROR @  61863360 ps: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_operation_err triggered unexpectedly
        UVM_INFO @  61863360 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
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• 2024.06.10_06.34.43
• 2024.06.08_13.01.13
• 2024.06.07_04.44.40
• 2024.06.06_10.55.13
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