KEYMGR Simulation Results

Sunday July 21 2024 23:02:06 UTC

GitHub Revision: `e971cd9798`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 60538554475599760039478308558126864941531727393021608909386829062452482962039

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	25.940s	1.672ms	50	50	100.00
V1	random	keymgr_random	1.054m	2.314ms	49	50	98.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.430s	30.367us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	1.620s	122.693us	20	20	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	32.200s	1.290ms	5	5	100.00
V1	csr_aliasing	keymgr_csr_aliasing	12.150s	1.265ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.420s	36.435us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.620s	122.693us	20	20	100.00
		keymgr_csr_aliasing	12.150s	1.265ms	5	5	100.00
V1		TOTAL			154	155	99.35
V2	cfgen_during_op	keymgr_cfg_regwen	1.722m	2.027ms	49	50	98.00
V2	sideload	keymgr_sideload	1.011m	5.867ms	50	50	100.00
		keymgr_sideload_kmac	59.930s	5.768ms	50	50	100.00
		keymgr_sideload_aes	54.690s	3.219ms	50	50	100.00
		keymgr_sideload_otbn	43.190s	5.268ms	50	50	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	28.810s	4.498ms	50	50	100.00
V2	lc_disable	keymgr_lc_disable	17.390s	1.244ms	50	50	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	32.770s	3.245ms	48	50	96.00
V2	invalid_sw_input	keymgr_sw_invalid_input	44.640s	1.773ms	50	50	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	21.090s	2.450ms	50	50	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	23.370s	4.102ms	49	50	98.00
V2	stress_all	keymgr_stress_all	2.502m	6.144ms	48	50	96.00
V2	intr_test	keymgr_intr_test	0.940s	140.427us	50	50	100.00
V2	alert_test	keymgr_alert_test	1.040s	182.950us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	5.500s	334.029us	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	5.500s	334.029us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.430s	30.367us	5	5	100.00
		keymgr_csr_rw	1.620s	122.693us	20	20	100.00
		keymgr_csr_aliasing	12.150s	1.265ms	5	5	100.00
		keymgr_same_csr_outstanding	3.810s	110.733us	20	20	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.430s	30.367us	5	5	100.00
		keymgr_csr_rw	1.620s	122.693us	20	20	100.00
		keymgr_csr_aliasing	12.150s	1.265ms	5	5	100.00
		keymgr_same_csr_outstanding	3.810s	110.733us	20	20	100.00
V2		TOTAL			734	740	99.19
V2S	sec_cm_additional_check	keymgr_sec_cm	19.530s	682.207us	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	19.530s	682.207us	5	5	100.00
		keymgr_tl_intg_err	8.140s	770.494us	20	20	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	4.560s	311.130us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	4.560s	311.130us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	4.560s	311.130us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	4.560s	311.130us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	13.900s	2.868ms	20	20	100.00
V2S	prim_count_check	keymgr_sec_cm	19.530s	682.207us	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	19.530s	682.207us	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	8.140s	770.494us	20	20	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	4.560s	311.130us	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	1.722m	2.027ms	49	50	98.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	1.054m	2.314ms	49	50	98.00
		keymgr_csr_rw	1.620s	122.693us	20	20	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	1.054m	2.314ms	49	50	98.00
		keymgr_csr_rw	1.620s	122.693us	20	20	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	1.054m	2.314ms	49	50	98.00
		keymgr_csr_rw	1.620s	122.693us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	17.390s	1.244ms	50	50	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	21.090s	2.450ms	50	50	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	21.090s	2.450ms	50	50	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	1.054m	2.314ms	49	50	98.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	14.970s	557.920us	50	50	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	19.530s	682.207us	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	19.530s	682.207us	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	19.530s	682.207us	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	29.370s	1.218ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	17.390s	1.244ms	50	50	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	19.530s	682.207us	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	19.530s	682.207us	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	19.530s	682.207us	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	29.370s	1.218ms	50	50	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	29.370s	1.218ms	50	50	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	19.530s	682.207us	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	29.370s	1.218ms	50	50	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	19.530s	682.207us	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	29.370s	1.218ms	50	50	100.00
V2S		TOTAL			165	165	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	28.930s	2.638ms	28	50	56.00
V3		TOTAL			28	50	56.00
		TOTAL			1081	1110	97.39

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	6	85.71
V2	16	16	12	75.00
V2S	6	6	6	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.76	99.04	98.11	98.60	100.00	99.02	98.41	91.14

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:839) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 22 failures:
- Test keymgr_stress_all_with_rand_reset has 22 failures.
  - 2.keymgr_stress_all_with_rand_reset.60207126351172522649646671094120020980448342647300363114599277685428949111301
    Line 1006, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/2.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 581243527 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 581243527 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 6.keymgr_stress_all_with_rand_reset.3816253350451604618549658366943436679426132837352127181878351593344888255398
    Line 305, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/6.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 174797967 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 174797967 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 20 more failures.

UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 4 failures:

Test keymgr_cfg_regwen has 1 failures.

1.keymgr_cfg_regwen.77560393810755041685026660252699389925717116076858850023071585156243772881701
Line 310, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/1.keymgr_cfg_regwen/latest/run.log

  UVM_ERROR @   2932723 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @   2932723 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_random has 1 failures.

4.keymgr_random.78500252179476717318008758843328012808164007976156966462302372271199205084457
Line 443, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/4.keymgr_random/latest/run.log

  UVM_ERROR @  34978190 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @  34978190 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_stress_all has 1 failures.

20.keymgr_stress_all.7766324560306890115684352881040338491229311863735990933214878758251521767974
Line 703, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/20.keymgr_stress_all/latest/run.log

  UVM_ERROR @ 2852424714 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @ 2852424714 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_kmac_rsp_err has 1 failures.

40.keymgr_kmac_rsp_err.65886250151543226674209510195593661097144657657652858831023324074890644661061
Line 268, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/40.keymgr_kmac_rsp_err/latest/run.log

  UVM_ERROR @   6986844 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @   6986844 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data !=gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.sw_share1_output_*` has 1 failures:
- Test keymgr_stress_all has 1 failures.
  - 8.keymgr_stress_all.30423044615984833478390126352100067148941561422533270573645762399654092086699
    Line 676, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/8.keymgr_stress_all/latest/run.log
```
  UVM_ERROR @ 203967942 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (0 [0x0] vs 0 [0x0]) reg name: keymgr_reg_block.sw_share1_output_2
  UVM_INFO @ 203967942 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_scoreboard.sv:261) scoreboard [scoreboard] alert recov_operation_err is not received! has 1 failures:
- Test keymgr_sync_async_fault_cross has 1 failures.
  - 11.keymgr_sync_async_fault_cross.88973510201925537739829688826915123801872249169356880833202332330942297015965
    Line 317, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/11.keymgr_sync_async_fault_cross/latest/run.log
```
  UVM_ERROR @  88262351 ps: (cip_base_scoreboard.sv:261) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err is not received!
  UVM_INFO @  88262351 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_scoreboard.sv:241) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_operation_err triggered unexpectedly has 1 failures:
- Test keymgr_kmac_rsp_err has 1 failures.
  - 30.keymgr_kmac_rsp_err.50642045781659737243646815365544113362546086773242143991617328878689866615674
    Line 472, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/30.keymgr_kmac_rsp_err/latest/run.log
```
  UVM_ERROR @  34546390 ps: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_operation_err triggered unexpectedly
  UVM_INFO @  34546390 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```