KEYMGR Simulation Results

Tuesday July 16 2024 23:15:02 UTC

GitHub Revision: aad711e1bc

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 38297581588405771015102977205739484163575733999253050480227719508149669635625

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	40.230s	2.705ms	50	50	100.00
V1	random	keymgr_random	1.402m	4.328ms	50	50	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.560s	37.867us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	1.570s	56.546us	20	20	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	31.860s	5.113ms	5	5	100.00
V1	csr_aliasing	keymgr_csr_aliasing	16.200s	1.981ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.140s	52.909us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.570s	56.546us	20	20	100.00
		keymgr_csr_aliasing	16.200s	1.981ms	5	5	100.00
V1		TOTAL			155	155	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	2.302m	10.156ms	50	50	100.00
V2	sideload	keymgr_sideload	43.600s	8.919ms	50	50	100.00
		keymgr_sideload_kmac	49.090s	1.512ms	50	50	100.00
		keymgr_sideload_aes	1.061m	6.527ms	50	50	100.00
		keymgr_sideload_otbn	56.710s	1.855ms	50	50	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	21.260s	3.203ms	50	50	100.00
V2	lc_disable	keymgr_lc_disable	8.970s	480.832us	50	50	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	7.480s	646.774us	50	50	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	56.930s	1.534ms	50	50	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	56.820s	1.931ms	50	50	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	30.800s	5.851ms	49	50	98.00
V2	stress_all	keymgr_stress_all	9.170m	20.184ms	49	50	98.00
V2	intr_test	keymgr_intr_test	0.960s	85.712us	50	50	100.00
V2	alert_test	keymgr_alert_test	1.060s	77.551us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	5.010s	1.175ms	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	5.010s	1.175ms	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.560s	37.867us	5	5	100.00
		keymgr_csr_rw	1.570s	56.546us	20	20	100.00
		keymgr_csr_aliasing	16.200s	1.981ms	5	5	100.00
		keymgr_same_csr_outstanding	3.740s	99.576us	20	20	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.560s	37.867us	5	5	100.00
		keymgr_csr_rw	1.570s	56.546us	20	20	100.00
		keymgr_csr_aliasing	16.200s	1.981ms	5	5	100.00
		keymgr_same_csr_outstanding	3.740s	99.576us	20	20	100.00
V2		TOTAL			738	740	99.73
V2S	sec_cm_additional_check	keymgr_sec_cm	24.160s	3.506ms	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	24.160s	3.506ms	5	5	100.00
		keymgr_tl_intg_err	9.930s	478.832us	20	20	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	4.400s	798.145us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	4.400s	798.145us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	4.400s	798.145us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	4.400s	798.145us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	19.200s	650.607us	20	20	100.00
V2S	prim_count_check	keymgr_sec_cm	24.160s	3.506ms	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	24.160s	3.506ms	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	9.930s	478.832us	20	20	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	4.400s	798.145us	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	2.302m	10.156ms	50	50	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	1.402m	4.328ms	50	50	100.00
		keymgr_csr_rw	1.570s	56.546us	20	20	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	1.402m	4.328ms	50	50	100.00
		keymgr_csr_rw	1.570s	56.546us	20	20	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	1.402m	4.328ms	50	50	100.00
		keymgr_csr_rw	1.570s	56.546us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	8.970s	480.832us	50	50	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	56.820s	1.931ms	50	50	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	56.820s	1.931ms	50	50	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	1.402m	4.328ms	50	50	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	29.560s	1.064ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	24.160s	3.506ms	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	24.160s	3.506ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	24.160s	3.506ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	19.570s	2.447ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	8.970s	480.832us	50	50	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	24.160s	3.506ms	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	24.160s	3.506ms	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	24.160s	3.506ms	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	19.570s	2.447ms	50	50	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	19.570s	2.447ms	50	50	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	24.160s	3.506ms	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	19.570s	2.447ms	50	50	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	24.160s	3.506ms	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	19.570s	2.447ms	50	50	100.00
V2S		TOTAL			165	165	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	28.000s	718.970us	26	50	52.00
V3		TOTAL			26	50	52.00
		TOTAL			1084	1110	97.66

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	16	16	14	87.50
V2S	6	6	6	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.74	99.04	97.95	98.44	100.00	99.11	98.41	91.22

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:825) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 22 failures:

  • Test keymgr_stress_all_with_rand_reset has 22 failures.

    • 1.keymgr_stress_all_with_rand_reset.101138868305409642804939031694553382706538061782864305148182594364925763417672
      Line 487, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/1.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1301226635 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1301226635 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.keymgr_stress_all_with_rand_reset.70879368432450957361093119759072551722746780775417330661267680233530833795511
      Line 350, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/2.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 436437677 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 436437677 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 20 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 2 failures:

  • Test keymgr_stress_all_with_rand_reset has 1 failures.

    • 12.keymgr_stress_all_with_rand_reset.53689553196681957307475774968842202807939724094511769132485797909827312191879
      Line 262, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/12.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @  28362389 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:2000
        UVM_INFO @  28362389 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test keymgr_stress_all has 1 failures.

    • 44.keymgr_stress_all.85747775175882863343657477225737098281552887398377659094129951079418237921987
      Line 781, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/44.keymgr_stress_all/latest/run.log

        UVM_ERROR @ 234427198 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
        UVM_INFO @ 234427198 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (keymgr_sync_async_fault_cross_vseq.sv:38) [keymgr_sync_async_fault_cross_vseq] Check failed act_fault_status[keymgr_pkg::FaultKmacOp] || act_fault_status[keymgr_pkg::FaultKmacOut] == * (* [*] vs * [*]) has 1 failures:

  • Test keymgr_sync_async_fault_cross has 1 failures.

    • 3.keymgr_sync_async_fault_cross.41094059765068274596103345750112741383334502553093740804366450487237321946596
      Line 298, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/3.keymgr_sync_async_fault_cross/latest/run.log

        UVM_ERROR @ 298276893 ps: (keymgr_sync_async_fault_cross_vseq.sv:38) [uvm_test_top.env.virtual_sequencer.keymgr_sync_async_fault_cross_vseq] Check failed act_fault_status[keymgr_pkg::FaultKmacOp] ||                 act_fault_status[keymgr_pkg::FaultKmacOut] == 1 (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 298276893 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data !=gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.sw_share0_output_*` has 1 failures:

  • Test keymgr_stress_all_with_rand_reset has 1 failures.

    • 44.keymgr_stress_all_with_rand_reset.13424216781250396874510538323334122625720048083141455455625032340248664231914
      Line 1884, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/44.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 548618260 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (0 [0x0] vs 0 [0x0]) reg name: keymgr_reg_block.sw_share0_output_0
        UVM_INFO @ 548618260 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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