KEYMGR Simulation Results

Friday July 19 2024 23:02:26 UTC

GitHub Revision: `e971cd9798`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 26138077499038500271813583950138268511494909685260487774440110801232111361107

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	26.110s	11.862ms	50	50	100.00
V1	random	keymgr_random	48.480s	8.130ms	50	50	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.450s	33.316us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	1.490s	96.718us	20	20	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	15.920s	891.732us	5	5	100.00
V1	csr_aliasing	keymgr_csr_aliasing	12.940s	398.142us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.150s	190.194us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.490s	96.718us	20	20	100.00
		keymgr_csr_aliasing	12.940s	398.142us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	1.239m	5.095ms	50	50	100.00
V2	sideload	keymgr_sideload	56.180s	1.835ms	50	50	100.00
		keymgr_sideload_kmac	37.820s	8.009ms	50	50	100.00
		keymgr_sideload_aes	36.060s	3.257ms	50	50	100.00
		keymgr_sideload_otbn	42.950s	1.582ms	50	50	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	24.720s	3.963ms	50	50	100.00
V2	lc_disable	keymgr_lc_disable	6.540s	188.040us	49	50	98.00
V2	kmac_error_response	keymgr_kmac_rsp_err	15.680s	2.703ms	49	50	98.00
V2	invalid_sw_input	keymgr_sw_invalid_input	1.043m	3.407ms	50	50	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	1.492m	7.112ms	48	50	96.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	13.660s	1.046ms	50	50	100.00
V2	stress_all	keymgr_stress_all	4.271m	14.803ms	47	50	94.00
V2	intr_test	keymgr_intr_test	0.940s	14.670us	50	50	100.00
V2	alert_test	keymgr_alert_test	1.040s	37.461us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	5.100s	143.597us	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	5.100s	143.597us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.450s	33.316us	5	5	100.00
		keymgr_csr_rw	1.490s	96.718us	20	20	100.00
		keymgr_csr_aliasing	12.940s	398.142us	5	5	100.00
		keymgr_same_csr_outstanding	4.610s	344.840us	20	20	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.450s	33.316us	5	5	100.00
		keymgr_csr_rw	1.490s	96.718us	20	20	100.00
		keymgr_csr_aliasing	12.940s	398.142us	5	5	100.00
		keymgr_same_csr_outstanding	4.610s	344.840us	20	20	100.00
V2		TOTAL			733	740	99.05
V2S	sec_cm_additional_check	keymgr_sec_cm	13.890s	562.655us	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	13.890s	562.655us	5	5	100.00
		keymgr_tl_intg_err	10.630s	315.162us	20	20	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	4.190s	140.047us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	4.190s	140.047us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	4.190s	140.047us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	4.190s	140.047us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	14.600s	413.243us	20	20	100.00
V2S	prim_count_check	keymgr_sec_cm	13.890s	562.655us	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	13.890s	562.655us	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	10.630s	315.162us	20	20	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	4.190s	140.047us	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	1.239m	5.095ms	50	50	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	48.480s	8.130ms	50	50	100.00
		keymgr_csr_rw	1.490s	96.718us	20	20	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	48.480s	8.130ms	50	50	100.00
		keymgr_csr_rw	1.490s	96.718us	20	20	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	48.480s	8.130ms	50	50	100.00
		keymgr_csr_rw	1.490s	96.718us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	6.540s	188.040us	49	50	98.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	1.492m	7.112ms	48	50	96.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	1.492m	7.112ms	48	50	96.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	48.480s	8.130ms	50	50	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	15.290s	618.734us	50	50	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	13.890s	562.655us	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	13.890s	562.655us	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	13.890s	562.655us	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	21.850s	2.015ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	6.540s	188.040us	49	50	98.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	13.890s	562.655us	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	13.890s	562.655us	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	13.890s	562.655us	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	21.850s	2.015ms	50	50	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	21.850s	2.015ms	50	50	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	13.890s	562.655us	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	21.850s	2.015ms	50	50	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	13.890s	562.655us	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	21.850s	2.015ms	50	50	100.00
V2S		TOTAL			165	165	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	26.400s	714.614us	26	50	52.00
V3		TOTAL			26	50	52.00
		TOTAL			1079	1110	97.21

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	16	16	12	75.00
V2S	6	6	6	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.80	99.04	97.99	98.94	100.00	99.02	98.41	91.19

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:839) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 22 failures:
- Test keymgr_stress_all_with_rand_reset has 22 failures.
  - 1.keymgr_stress_all_with_rand_reset.107831438779750095649917232064182466577803582342181849338877183952970208747975
    Line 344, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/1.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 299364789 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 299364789 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.keymgr_stress_all_with_rand_reset.53273774662596299795250437322239615488249808196038340893340245810740352098955
    Line 485, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/4.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 107142333 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 107142333 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 20 more failures.
UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 3 failures:
- Test keymgr_stress_all has 3 failures.
  - 3.keymgr_stress_all.9979316701676230044128758513709147388887091805509661164715679448521083315041
    Line 841, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/3.keymgr_stress_all/latest/run.log
```
  UVM_ERROR @ 1197416445 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @ 1197416445 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 24.keymgr_stress_all.67811881529823271191842733839488482500110641942240552858600532376848504620254
    Line 2371, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/24.keymgr_stress_all/latest/run.log
```
  UVM_ERROR @ 14803040360 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @ 14803040360 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.

UVM_ERROR (cip_base_scoreboard.sv:241) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_operation_err triggered unexpectedly has 3 failures:

Test keymgr_kmac_rsp_err has 1 failures.

12.keymgr_kmac_rsp_err.32017702204111672804057708994942667231065714479735694235144567368093054360596
Line 481, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/12.keymgr_kmac_rsp_err/latest/run.log

  UVM_ERROR @ 136499468 ps: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_operation_err triggered unexpectedly
  UVM_INFO @ 136499468 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_hwsw_invalid_input has 2 failures.

35.keymgr_hwsw_invalid_input.34762623412286070139653454442713107431897913569687750107944516181709793432695
Line 489, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/35.keymgr_hwsw_invalid_input/latest/run.log

  UVM_ERROR @  39042190 ps: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_operation_err triggered unexpectedly
  UVM_INFO @  39042190 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

46.keymgr_hwsw_invalid_input.67031629545300887913839668083950835580382772733855364962994983726807186021459
Line 603, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/46.keymgr_hwsw_invalid_input/latest/run.log

  UVM_ERROR @  34996648 ps: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_operation_err triggered unexpectedly
  UVM_INFO @  34996648 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data !=gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.sw_share1_output_*` has 1 failures:
- Test keymgr_stress_all_with_rand_reset has 1 failures.
  - 3.keymgr_stress_all_with_rand_reset.36341662567306054815862749129488863043677925781232641427464977616361196855811
    Line 2298, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/3.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 597936269 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (0 [0x0] vs 0 [0x0]) reg name: keymgr_reg_block.sw_share1_output_2
  UVM_INFO @ 597936269 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data !=gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.sw_share0_output_*` has 1 failures:
- Test keymgr_lc_disable has 1 failures.
  - 4.keymgr_lc_disable.29791250037230220236179630945271860506985054015671072365070031860056756214524
    Line 412, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/4.keymgr_lc_disable/latest/run.log
```
  UVM_ERROR @  48328222 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (1096414867 [0x4159f693] vs 1096414867 [0x4159f693]) reg name: keymgr_reg_block.sw_share0_output_3
  UVM_INFO @  48328222 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:758) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test keymgr_stress_all_with_rand_reset has 1 failures.
  - 38.keymgr_stress_all_with_rand_reset.100546805950886464843065431483177194378165857428385767874748600568257001971483
    Line 389, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/38.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 108309690 ps: (cip_base_vseq.sv:758) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 108309690 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```