KEYMGR Simulation Results

Thursday July 18 2024 23:02:12 UTC

GitHub Revision: `974aaab627`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 46057207235241274571178436692064798722168129065126426307050395083305588858879

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	25.070s	5.596ms	50	50	100.00
V1	random	keymgr_random	58.130s	10.701ms	50	50	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.470s	91.498us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	1.430s	21.026us	20	20	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	17.850s	1.350ms	5	5	100.00
V1	csr_aliasing	keymgr_csr_aliasing	18.380s	5.708ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.390s	58.747us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.430s	21.026us	20	20	100.00
		keymgr_csr_aliasing	18.380s	5.708ms	5	5	100.00
V1		TOTAL			155	155	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	1.718m	1.995ms	50	50	100.00
V2	sideload	keymgr_sideload	49.400s	6.841ms	50	50	100.00
		keymgr_sideload_kmac	1.444m	24.225ms	50	50	100.00
		keymgr_sideload_aes	43.980s	2.480ms	50	50	100.00
		keymgr_sideload_otbn	44.340s	4.194ms	50	50	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	48.800s	4.282ms	50	50	100.00
V2	lc_disable	keymgr_lc_disable	17.740s	617.640us	49	50	98.00
V2	kmac_error_response	keymgr_kmac_rsp_err	7.320s	189.315us	48	50	96.00
V2	invalid_sw_input	keymgr_sw_invalid_input	1.224m	15.335ms	50	50	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	46.210s	1.506ms	50	50	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	20.070s	900.893us	50	50	100.00
V2	stress_all	keymgr_stress_all	8.019m	82.438ms	48	50	96.00
V2	intr_test	keymgr_intr_test	0.910s	52.251us	50	50	100.00
V2	alert_test	keymgr_alert_test	0.990s	79.276us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	4.510s	1.121ms	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	4.510s	1.121ms	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.470s	91.498us	5	5	100.00
		keymgr_csr_rw	1.430s	21.026us	20	20	100.00
		keymgr_csr_aliasing	18.380s	5.708ms	5	5	100.00
		keymgr_same_csr_outstanding	3.290s	155.913us	20	20	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.470s	91.498us	5	5	100.00
		keymgr_csr_rw	1.430s	21.026us	20	20	100.00
		keymgr_csr_aliasing	18.380s	5.708ms	5	5	100.00
		keymgr_same_csr_outstanding	3.290s	155.913us	20	20	100.00
V2		TOTAL			735	740	99.32
V2S	sec_cm_additional_check	keymgr_sec_cm	14.480s	999.532us	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	14.480s	999.532us	5	5	100.00
		keymgr_tl_intg_err	9.590s	235.908us	20	20	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	6.260s	231.177us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	6.260s	231.177us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	6.260s	231.177us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	6.260s	231.177us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	16.680s	473.584us	20	20	100.00
V2S	prim_count_check	keymgr_sec_cm	14.480s	999.532us	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	14.480s	999.532us	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	9.590s	235.908us	20	20	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	6.260s	231.177us	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	1.718m	1.995ms	50	50	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	58.130s	10.701ms	50	50	100.00
		keymgr_csr_rw	1.430s	21.026us	20	20	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	58.130s	10.701ms	50	50	100.00
		keymgr_csr_rw	1.430s	21.026us	20	20	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	58.130s	10.701ms	50	50	100.00
		keymgr_csr_rw	1.430s	21.026us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	17.740s	617.640us	49	50	98.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	46.210s	1.506ms	50	50	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	46.210s	1.506ms	50	50	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	58.130s	10.701ms	50	50	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	31.610s	1.890ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	14.480s	999.532us	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	14.480s	999.532us	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	14.480s	999.532us	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	24.000s	772.540us	50	50	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	17.740s	617.640us	49	50	98.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	14.480s	999.532us	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	14.480s	999.532us	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	14.480s	999.532us	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	24.000s	772.540us	50	50	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	24.000s	772.540us	50	50	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	14.480s	999.532us	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	24.000s	772.540us	50	50	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	14.480s	999.532us	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	24.000s	772.540us	50	50	100.00
V2S		TOTAL			165	165	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	23.980s	336.041us	28	50	56.00
V3		TOTAL			28	50	56.00
		TOTAL			1083	1110	97.57

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	16	16	13	81.25
V2S	6	6	6	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.67	99.04	97.91	98.14	100.00	99.02	98.41	91.19

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:839) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 20 failures:
- Test keymgr_stress_all_with_rand_reset has 20 failures.
  - 1.keymgr_stress_all_with_rand_reset.107289813551095215030519851534700231313351547344841330162356182445393864835819
    Line 1150, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/1.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 792544749 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 792544749 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 12.keymgr_stress_all_with_rand_reset.62287817229443860956959448879679642922672863799710727889457753409835564474617
    Line 1199, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/12.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 378997312 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 378997312 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 18 more failures.

UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 3 failures:

Test keymgr_stress_all has 2 failures.

5.keymgr_stress_all.96678875267892473640143398067917365263770684331589518316523834704256737486047
Line 548, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/5.keymgr_stress_all/latest/run.log

  UVM_ERROR @  87712142 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:2000
  UVM_INFO @  87712142 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

21.keymgr_stress_all.5531741269387166913697083233897585554128710216120391007872936976661831643805
Line 366, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/21.keymgr_stress_all/latest/run.log

  UVM_ERROR @  54056590 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @  54056590 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_kmac_rsp_err has 1 failures.

32.keymgr_kmac_rsp_err.76794377959923975519865204061300123386927073108747049645316275806686114106042
Line 288, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/32.keymgr_kmac_rsp_err/latest/run.log

  UVM_ERROR @  50788534 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @  50788534 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[*], act_key.key[*]} !== keys_a_array[state][cdi][dest] (* [*] vs * [*]) KMAC key at state StDisabled for Sealing Kmac has 1 failures:

Test keymgr_lc_disable has 1 failures.

13.keymgr_lc_disable.89301841824996844035378456029798912931933339262027489174555762407033974273008
Line 679, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/13.keymgr_lc_disable/latest/run.log

  UVM_ERROR @ 357676500 ps: (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[1], act_key.key[0]} !== keys_a_array[state][cdi][dest] (2274785969991860605097530914994921446111049084602032220054299235314744851794222002800643358918928711519657753151069351378799586698847376246715763997341588 [0x2b6eec15b57813e760abe8efb8c156d8a8c55f3bbd28fbc3fe965f19126a64e515868c4e96e705b709284351658c9144f6c6a7c1afcb4d3c759895dd59ccf794] vs 2274785969991860605097530914994921446111049084602032220054299235314744851794222002800643358918928711519657753151069351378799586698847376246715763997341588 [0x2b6eec15b57813e760abe8efb8c156d8a8c55f3bbd28fbc3fe965f19126a64e515868c4e96e705b709284351658c9144f6c6a7c1afcb4d3c759895dd59ccf794]) KMAC key at state StDisabled for Sealing Kmac
  UVM_INFO @ 357676500 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (keymgr_scoreboard.sv:689) [scoreboard] Check failed edn_fifos[*].used() == * (* [*] vs * [*]) has 1 failures:
- Test keymgr_stress_all_with_rand_reset has 1 failures.
  - 30.keymgr_stress_all_with_rand_reset.36644583155942960627901721140107913279714381546741009763350922790743857470014
    Line 1611, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/30.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1586892317 ps: (keymgr_scoreboard.sv:689) [uvm_test_top.env.scoreboard] Check failed edn_fifos[0].used() == 2 (0 [0x0] vs 2 [0x2])
  UVM_INFO @ 1586892317 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data !=gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.sw_share0_output_*` has 1 failures:
- Test keymgr_stress_all_with_rand_reset has 1 failures.
  - 33.keymgr_stress_all_with_rand_reset.26841387321401603870315057941411545566023771672719752876006720362394720874997
    Line 1211, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/33.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 332942717 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (0 [0x0] vs 0 [0x0]) reg name: keymgr_reg_block.sw_share0_output_2
  UVM_INFO @ 332942717 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_scoreboard.sv:241) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_operation_err triggered unexpectedly has 1 failures:
- Test keymgr_kmac_rsp_err has 1 failures.
  - 43.keymgr_kmac_rsp_err.27000489896467092595042268602863564789904407102675412435541529147634438338039
    Line 515, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/43.keymgr_kmac_rsp_err/latest/run.log
```
  UVM_ERROR @  45855833 ps: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_operation_err triggered unexpectedly
  UVM_INFO @  45855833 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```