KEYMGR Simulation Results

Wednesday July 17 2024 23:02:16 UTC

GitHub Revision: `8b2da8db5e`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 31877364624131593519988921539075110140045739991215723614576185349550879231344

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	33.220s	15.340ms	50	50	100.00
V1	random	keymgr_random	46.940s	17.426ms	50	50	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.280s	24.011us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	1.640s	33.269us	20	20	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	17.280s	2.598ms	5	5	100.00
V1	csr_aliasing	keymgr_csr_aliasing	10.150s	454.792us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.580s	124.953us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.640s	33.269us	20	20	100.00
		keymgr_csr_aliasing	10.150s	454.792us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	1.353m	6.492ms	50	50	100.00
V2	sideload	keymgr_sideload	58.280s	3.092ms	50	50	100.00
		keymgr_sideload_kmac	39.620s	1.319ms	50	50	100.00
		keymgr_sideload_aes	49.920s	1.708ms	50	50	100.00
		keymgr_sideload_otbn	45.810s	1.602ms	50	50	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	24.200s	3.142ms	50	50	100.00
V2	lc_disable	keymgr_lc_disable	18.590s	3.665ms	50	50	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	26.520s	1.539ms	50	50	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	58.600s	9.515ms	50	50	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	48.870s	1.856ms	50	50	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	22.890s	1.298ms	50	50	100.00
V2	stress_all	keymgr_stress_all	8.541m	52.140ms	48	50	96.00
V2	intr_test	keymgr_intr_test	1.000s	21.554us	50	50	100.00
V2	alert_test	keymgr_alert_test	1.020s	261.862us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	4.150s	127.441us	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	4.150s	127.441us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.280s	24.011us	5	5	100.00
		keymgr_csr_rw	1.640s	33.269us	20	20	100.00
		keymgr_csr_aliasing	10.150s	454.792us	5	5	100.00
		keymgr_same_csr_outstanding	3.010s	186.404us	20	20	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.280s	24.011us	5	5	100.00
		keymgr_csr_rw	1.640s	33.269us	20	20	100.00
		keymgr_csr_aliasing	10.150s	454.792us	5	5	100.00
		keymgr_same_csr_outstanding	3.010s	186.404us	20	20	100.00
V2		TOTAL			738	740	99.73
V2S	sec_cm_additional_check	keymgr_sec_cm	24.410s	991.982us	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	24.410s	991.982us	5	5	100.00
		keymgr_tl_intg_err	9.140s	252.304us	20	20	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	4.680s	1.155ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	4.680s	1.155ms	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	4.680s	1.155ms	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	4.680s	1.155ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	9.770s	409.134us	20	20	100.00
V2S	prim_count_check	keymgr_sec_cm	24.410s	991.982us	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	24.410s	991.982us	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	9.140s	252.304us	20	20	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	4.680s	1.155ms	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	1.353m	6.492ms	50	50	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	46.940s	17.426ms	50	50	100.00
		keymgr_csr_rw	1.640s	33.269us	20	20	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	46.940s	17.426ms	50	50	100.00
		keymgr_csr_rw	1.640s	33.269us	20	20	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	46.940s	17.426ms	50	50	100.00
		keymgr_csr_rw	1.640s	33.269us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	18.590s	3.665ms	50	50	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	48.870s	1.856ms	50	50	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	48.870s	1.856ms	50	50	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	46.940s	17.426ms	50	50	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	25.210s	1.388ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	24.410s	991.982us	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	24.410s	991.982us	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	24.410s	991.982us	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	38.460s	1.676ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	18.590s	3.665ms	50	50	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	24.410s	991.982us	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	24.410s	991.982us	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	24.410s	991.982us	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	38.460s	1.676ms	50	50	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	38.460s	1.676ms	50	50	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	24.410s	991.982us	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	38.460s	1.676ms	50	50	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	24.410s	991.982us	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	38.460s	1.676ms	50	50	100.00
V2S		TOTAL			165	165	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	25.470s	2.040ms	22	50	44.00
V3		TOTAL			22	50	44.00
		TOTAL			1080	1110	97.30

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	16	16	15	93.75
V2S	6	6	6	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.73	99.04	98.11	98.39	100.00	99.02	98.41	91.12

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:839) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 24 failures:
- Test keymgr_stress_all_with_rand_reset has 24 failures.
  - 5.keymgr_stress_all_with_rand_reset.30415501971734996470083797903404462925051032035178832438867903632775394267787
    Line 271, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/5.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 117126479 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 117126479 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 6.keymgr_stress_all_with_rand_reset.101364178295839211535458871805387991287710384781178949808139911678994518939565
    Line 353, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/6.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 396021342 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 396021342 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 22 more failures.
UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 2 failures:
- Test keymgr_stress_all_with_rand_reset has 1 failures.
  - 23.keymgr_stress_all_with_rand_reset.110114151694462126708115866815986501770629049279285352444403233063092726247937
    Line 433, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/23.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  21606257 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @  21606257 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test keymgr_stress_all has 1 failures.
  - 38.keymgr_stress_all.72231471482830648480955751900456231767634579094565250577550241336200787062494
    Line 2228, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/38.keymgr_stress_all/latest/run.log
```
  UVM_ERROR @ 8984662141 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @ 8984662141 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[*], act_key.key[*]} !== keys_a_array[state][cdi][dest] (* [*] vs * [*]) AES key at state StDisabled for Attestation Aes has 1 failures:

Test keymgr_stress_all has 1 failures.

23.keymgr_stress_all.4508507328512926630648252838935318566997757168329682244867641614680743010862
Line 868, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/23.keymgr_stress_all/latest/run.log

  UVM_ERROR @ 192724948 ps: (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[1], act_key.key[0]} !== keys_a_array[state][cdi][dest] (10586406423948530683281537002776308818771432095933664551863882959593033534896175932598676221292092358320113152593682453446594030965213582847382529239107917 [0xca2146d66b868f1a999219aedf6e554c2af7acb7f64c27f4bd3e7858b83053c75dfc4ae463a47560d93ee2954641cfc1f55add0f2f59f0e53ed7a82411a3494d] vs 10586406423948530683281537002776308818771432095933664551863882959593033534896175932598676221292092358320113152593682453446594030965213582847382529239107917 [0xca2146d66b868f1a999219aedf6e554c2af7acb7f64c27f4bd3e7858b83053c75dfc4ae463a47560d93ee2954641cfc1f55add0f2f59f0e53ed7a82411a3494d]) AES key at state StDisabled for Attestation Aes
  UVM_INFO @ 192724948 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data !=gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.sw_share0_output_*` has 1 failures:
- Test keymgr_stress_all_with_rand_reset has 1 failures.
  - 34.keymgr_stress_all_with_rand_reset.1006617448510173668507356444234221633352027232600088964935065270295271462911
    Line 1224, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/34.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 838490561 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (0 [0x0] vs 0 [0x0]) reg name: keymgr_reg_block.sw_share0_output_2
  UVM_INFO @ 838490561 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data !=gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.sw_share1_output_*` has 1 failures:
- Test keymgr_stress_all_with_rand_reset has 1 failures.
  - 40.keymgr_stress_all_with_rand_reset.15951937406649524406680439334928337609164543249866025518395775040447451037867
    Line 605, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/40.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  74184924 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (0 [0x0] vs 0 [0x0]) reg name: keymgr_reg_block.sw_share1_output_6
  UVM_INFO @  74184924 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:758) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test keymgr_stress_all_with_rand_reset has 1 failures.
  - 45.keymgr_stress_all_with_rand_reset.92967127336929071775118299608266413753466246757316888785902309380427677517108
    Line 891, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/45.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 527388112 ps: (cip_base_vseq.sv:758) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 527388112 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```