KEYMGR Simulation Results

Monday July 15 2024 23:02:37 UTC

GitHub Revision: `a04e34f557`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 78455839157994684327892029952813991699715169368132023215715425571513813941951

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	27.080s	1.289ms	50	50	100.00
V1	random	keymgr_random	1.350m	8.839ms	50	50	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.130s	27.312us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	1.520s	92.416us	20	20	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	31.540s	2.845ms	5	5	100.00
V1	csr_aliasing	keymgr_csr_aliasing	11.320s	363.873us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.260s	62.255us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.520s	92.416us	20	20	100.00
		keymgr_csr_aliasing	11.320s	363.873us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	2.178m	9.355ms	50	50	100.00
V2	sideload	keymgr_sideload	40.610s	4.505ms	50	50	100.00
		keymgr_sideload_kmac	1.123m	4.470ms	50	50	100.00
		keymgr_sideload_aes	41.330s	4.056ms	50	50	100.00
		keymgr_sideload_otbn	42.300s	6.644ms	50	50	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	16.990s	1.007ms	50	50	100.00
V2	lc_disable	keymgr_lc_disable	7.690s	835.207us	49	50	98.00
V2	kmac_error_response	keymgr_kmac_rsp_err	11.790s	960.169us	50	50	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	55.240s	6.754ms	50	50	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	1.141m	8.161ms	49	50	98.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	19.290s	2.584ms	49	50	98.00
V2	stress_all	keymgr_stress_all	9.757m	94.692ms	47	50	94.00
V2	intr_test	keymgr_intr_test	0.940s	17.133us	50	50	100.00
V2	alert_test	keymgr_alert_test	1.010s	69.423us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	5.490s	164.757us	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	5.490s	164.757us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.130s	27.312us	5	5	100.00
		keymgr_csr_rw	1.520s	92.416us	20	20	100.00
		keymgr_csr_aliasing	11.320s	363.873us	5	5	100.00
		keymgr_same_csr_outstanding	3.360s	335.175us	20	20	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.130s	27.312us	5	5	100.00
		keymgr_csr_rw	1.520s	92.416us	20	20	100.00
		keymgr_csr_aliasing	11.320s	363.873us	5	5	100.00
		keymgr_same_csr_outstanding	3.360s	335.175us	20	20	100.00
V2		TOTAL			734	740	99.19
V2S	sec_cm_additional_check	keymgr_sec_cm	15.470s	735.155us	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	15.470s	735.155us	5	5	100.00
		keymgr_tl_intg_err	9.690s	1.079ms	20	20	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	5.930s	214.994us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	5.930s	214.994us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	5.930s	214.994us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	5.930s	214.994us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	15.960s	916.764us	20	20	100.00
V2S	prim_count_check	keymgr_sec_cm	15.470s	735.155us	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	15.470s	735.155us	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	9.690s	1.079ms	20	20	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	5.930s	214.994us	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	2.178m	9.355ms	50	50	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	1.350m	8.839ms	50	50	100.00
		keymgr_csr_rw	1.520s	92.416us	20	20	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	1.350m	8.839ms	50	50	100.00
		keymgr_csr_rw	1.520s	92.416us	20	20	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	1.350m	8.839ms	50	50	100.00
		keymgr_csr_rw	1.520s	92.416us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	7.690s	835.207us	49	50	98.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	1.141m	8.161ms	49	50	98.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	1.141m	8.161ms	49	50	98.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	1.350m	8.839ms	50	50	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	19.620s	3.281ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	15.470s	735.155us	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	15.470s	735.155us	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	15.470s	735.155us	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	6.990s	317.666us	50	50	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	7.690s	835.207us	49	50	98.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	15.470s	735.155us	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	15.470s	735.155us	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	15.470s	735.155us	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	6.990s	317.666us	50	50	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	6.990s	317.666us	50	50	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	15.470s	735.155us	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	6.990s	317.666us	50	50	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	15.470s	735.155us	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	6.990s	317.666us	50	50	100.00
V2S		TOTAL			165	165	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	26.590s	689.521us	37	50	74.00
V3		TOTAL			37	50	74.00
		TOTAL			1091	1110	98.29

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	16	16	12	75.00
V2S	6	6	6	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.71	99.04	97.95	98.48	100.00	99.02	98.41	91.09

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:825) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 13 failures:
- Test keymgr_stress_all_with_rand_reset has 13 failures.
  - 1.keymgr_stress_all_with_rand_reset.1286620492985988081660741626519590167970337146372831973716130301365624707732
    Line 790, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/1.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1022505547 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1022505547 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 16.keymgr_stress_all_with_rand_reset.83126536598676245427034482511869799812253627660336943112493366223262447668143
    Line 629, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/16.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1440564535 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1440564535 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 11 more failures.
UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 2 failures:
- Test keymgr_stress_all has 2 failures.
  - 6.keymgr_stress_all.77467718148025044675771468100488044155863995138280727349140101353673999256815
    Line 614, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/6.keymgr_stress_all/latest/run.log
```
  UVM_ERROR @  65716267 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @  65716267 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 26.keymgr_stress_all.75636524578164483333720205862998053443199245248378730687023505983556717246311
    Line 367, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/26.keymgr_stress_all/latest/run.log
```
  UVM_ERROR @   9860369 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @   9860369 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[*], act_key.key[*]} !== keys_a_array[state][cdi][dest] (* [*] vs * [*]) AES key at state StDisabled for Attestation Aes has 1 failures:

Test keymgr_lc_disable has 1 failures.

13.keymgr_lc_disable.40974058323915622784242757500686455079088970048933319690081123124410004999100
Line 582, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/13.keymgr_lc_disable/latest/run.log

  UVM_ERROR @ 135145231 ps: (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[1], act_key.key[0]} !== keys_a_array[state][cdi][dest] (4459903248554528753696002473656912546002503081623409964657867647867377191473962771119882499289834867394093341236433387886603126222215726412925365473062314 [0x55278d9003689992ee001d22470fe650c46efb143967248a7661427e84cc221ea900c7faa07725850a9a585f494f59a51633850c2629f1e3e2177735dbbd2daa] vs 4459903248554528753696002473656912546002503081623409964657867647867377191473962771119882499289834867394093341236433387886603126222215726412925365473062314 [0x55278d9003689992ee001d22470fe650c46efb143967248a7661427e84cc221ea900c7faa07725850a9a585f494f59a51633850c2629f1e3e2177735dbbd2daa]) AES key at state StDisabled for Attestation Aes
  UVM_INFO @ 135145231 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_scoreboard.sv:241) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_operation_err triggered unexpectedly has 1 failures:
- Test keymgr_hwsw_invalid_input has 1 failures.
  - 15.keymgr_hwsw_invalid_input.55565256138171198554539779320010202639261016880486097673381189276976928717369
    Line 584, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/15.keymgr_hwsw_invalid_input/latest/run.log
```
  UVM_ERROR @  66729228 ps: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_operation_err triggered unexpectedly
  UVM_INFO @  66729228 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data !=gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.sw_share1_output_*` has 1 failures:
- Test keymgr_stress_all has 1 failures.
  - 22.keymgr_stress_all.92928961818836962653233811996746931311669769875355883903353649537224004973125
    Line 348, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/22.keymgr_stress_all/latest/run.log
```
  UVM_ERROR @  54398137 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (0 [0x0] vs 0 [0x0]) reg name: keymgr_reg_block.sw_share1_output_1
  UVM_INFO @  54398137 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_scoreboard.sv:261) scoreboard [scoreboard] alert recov_operation_err is not received! has 1 failures:
- Test keymgr_sync_async_fault_cross has 1 failures.
  - 39.keymgr_sync_async_fault_cross.112378579966760229270959718016141502478549930389890352857534627770441764805045
    Line 338, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/39.keymgr_sync_async_fault_cross/latest/run.log
```
  UVM_ERROR @  33390256 ps: (cip_base_scoreboard.sv:261) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err is not received!
  UVM_INFO @  33390256 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```