KEYMGR Simulation Results

Monday July 22 2024 23:02:17 UTC

GitHub Revision: 3e0219a2c5

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 78193674045195286552709223969981662100934453993551616519215297815848091296886

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	40.680s	2.538ms	50	50	100.00
V1	random	keymgr_random	1.132m	2.220ms	50	50	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.160s	64.265us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	1.480s	99.048us	20	20	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	17.870s	1.333ms	5	5	100.00
V1	csr_aliasing	keymgr_csr_aliasing	9.020s	236.373us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.270s	32.099us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.480s	99.048us	20	20	100.00
		keymgr_csr_aliasing	9.020s	236.373us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	1.592m	3.824ms	50	50	100.00
V2	sideload	keymgr_sideload	50.630s	26.626ms	50	50	100.00
		keymgr_sideload_kmac	58.290s	3.805ms	50	50	100.00
		keymgr_sideload_aes	40.130s	1.664ms	50	50	100.00
		keymgr_sideload_otbn	1.048m	7.396ms	49	50	98.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	14.440s	529.476us	50	50	100.00
V2	lc_disable	keymgr_lc_disable	7.610s	244.642us	49	50	98.00
V2	kmac_error_response	keymgr_kmac_rsp_err	7.960s	983.037us	50	50	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	56.440s	4.164ms	50	50	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	30.150s	1.393ms	50	50	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	16.050s	3.754ms	50	50	100.00
V2	stress_all	keymgr_stress_all	5.225m	33.262ms	50	50	100.00
V2	intr_test	keymgr_intr_test	0.890s	11.841us	50	50	100.00
V2	alert_test	keymgr_alert_test	1.010s	152.484us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	4.300s	519.137us	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	4.300s	519.137us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.160s	64.265us	5	5	100.00
		keymgr_csr_rw	1.480s	99.048us	20	20	100.00
		keymgr_csr_aliasing	9.020s	236.373us	5	5	100.00
		keymgr_same_csr_outstanding	4.220s	918.270us	20	20	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.160s	64.265us	5	5	100.00
		keymgr_csr_rw	1.480s	99.048us	20	20	100.00
		keymgr_csr_aliasing	9.020s	236.373us	5	5	100.00
		keymgr_same_csr_outstanding	4.220s	918.270us	20	20	100.00
V2		TOTAL			738	740	99.73
V2S	sec_cm_additional_check	keymgr_sec_cm	15.830s	1.830ms	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	15.830s	1.830ms	5	5	100.00
		keymgr_tl_intg_err	8.100s	2.825ms	20	20	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	4.970s	723.231us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	4.970s	723.231us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	4.970s	723.231us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	4.970s	723.231us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	12.460s	450.710us	20	20	100.00
V2S	prim_count_check	keymgr_sec_cm	15.830s	1.830ms	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	15.830s	1.830ms	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	8.100s	2.825ms	20	20	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	4.970s	723.231us	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	1.592m	3.824ms	50	50	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	1.132m	2.220ms	50	50	100.00
		keymgr_csr_rw	1.480s	99.048us	20	20	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	1.132m	2.220ms	50	50	100.00
		keymgr_csr_rw	1.480s	99.048us	20	20	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	1.132m	2.220ms	50	50	100.00
		keymgr_csr_rw	1.480s	99.048us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	7.610s	244.642us	49	50	98.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	30.150s	1.393ms	50	50	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	30.150s	1.393ms	50	50	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	1.132m	2.220ms	50	50	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	25.800s	2.995ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	15.830s	1.830ms	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	15.830s	1.830ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	15.830s	1.830ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	30.690s	2.473ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	7.610s	244.642us	49	50	98.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	15.830s	1.830ms	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	15.830s	1.830ms	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	15.830s	1.830ms	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	30.690s	2.473ms	50	50	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	30.690s	2.473ms	50	50	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	15.830s	1.830ms	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	30.690s	2.473ms	50	50	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	15.830s	1.830ms	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	30.690s	2.473ms	50	50	100.00
V2S		TOTAL			165	165	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	27.940s	735.731us	28	50	56.00
V3		TOTAL			28	50	56.00
		TOTAL			1086	1110	97.84

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	16	16	14	87.50
V2S	6	6	6	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.74	99.04	98.07	98.43	100.00	99.11	98.41	91.14

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:839) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 21 failures:

  • Test keymgr_stress_all_with_rand_reset has 21 failures.

    • 0.keymgr_stress_all_with_rand_reset.18517838084641041900123771662512476851414664555051670912012738306727330162727
      Line 2036, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/0.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 6572246376 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 6572246376 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.keymgr_stress_all_with_rand_reset.95991570989939065031104870425424292697779608179140875936905512128905364961524
      Line 376, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/2.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 119958579 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 119958579 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 19 more failures.

• UVM_ERROR (keymgr_scoreboard.sv:692) [scoreboard] Check failed item.d_data == addr_phase_op_status (* [*] vs * [*]) has 1 failures:

  • Test keymgr_stress_all_with_rand_reset has 1 failures.

    • 24.keymgr_stress_all_with_rand_reset.91076208119682470931686219246778026865557813800436113990868825304369307386670
      Line 455, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/24.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 151658417 ps: (keymgr_scoreboard.sv:692) [uvm_test_top.env.scoreboard] Check failed item.d_data == addr_phase_op_status (1 [0x1] vs 2 [0x2])
        UVM_INFO @ 151658417 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data !=gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.sw_share0_output_*` has 1 failures:

  • Test keymgr_lc_disable has 1 failures.

    • 37.keymgr_lc_disable.108627108719071832517978245360360982920612773557759955884636557243332976077664
      Line 527, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/37.keymgr_lc_disable/latest/run.log

        UVM_ERROR @  83311894 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (0 [0x0] vs 0 [0x0]) reg name: keymgr_reg_block.sw_share0_output_1
        UVM_INFO @  83311894 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 1 failures:

  • Test keymgr_sideload_otbn has 1 failures.

    • 39.keymgr_sideload_otbn.96794226499882035933386871841153083609597872483151165984438631590084016009767
      Line 260, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/39.keymgr_sideload_otbn/latest/run.log

        UVM_ERROR @  21423786 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
        UVM_INFO @  21423786 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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