KEYMGR Simulation Results

Tuesday July 23 2024 23:02:17 UTC

GitHub Revision: 0bfa990ddc

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 18885947517810151702135064218189465175127531856323617115052940021793720055953

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	31.740s	6.373ms	50	50	100.00
V1	random	keymgr_random	40.820s	2.400ms	50	50	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.380s	106.860us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	1.460s	255.974us	20	20	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	32.310s	5.358ms	5	5	100.00
V1	csr_aliasing	keymgr_csr_aliasing	10.170s	367.437us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.190s	56.331us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.460s	255.974us	20	20	100.00
		keymgr_csr_aliasing	10.170s	367.437us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	1.799m	12.411ms	50	50	100.00
V2	sideload	keymgr_sideload	1.103m	6.658ms	50	50	100.00
		keymgr_sideload_kmac	54.840s	3.231ms	50	50	100.00
		keymgr_sideload_aes	12.660s	977.619us	50	50	100.00
		keymgr_sideload_otbn	35.250s	9.485ms	50	50	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	29.260s	1.263ms	50	50	100.00
V2	lc_disable	keymgr_lc_disable	35.910s	4.271ms	49	50	98.00
V2	kmac_error_response	keymgr_kmac_rsp_err	6.500s	236.232us	50	50	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	35.470s	4.871ms	50	50	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	1.052m	5.229ms	49	50	98.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	6.600s	329.675us	49	50	98.00
V2	stress_all	keymgr_stress_all	4.045m	13.012ms	50	50	100.00
V2	intr_test	keymgr_intr_test	0.970s	19.532us	50	50	100.00
V2	alert_test	keymgr_alert_test	1.040s	19.810us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	3.690s	91.056us	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	3.690s	91.056us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.380s	106.860us	5	5	100.00
		keymgr_csr_rw	1.460s	255.974us	20	20	100.00
		keymgr_csr_aliasing	10.170s	367.437us	5	5	100.00
		keymgr_same_csr_outstanding	4.190s	2.005ms	20	20	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.380s	106.860us	5	5	100.00
		keymgr_csr_rw	1.460s	255.974us	20	20	100.00
		keymgr_csr_aliasing	10.170s	367.437us	5	5	100.00
		keymgr_same_csr_outstanding	4.190s	2.005ms	20	20	100.00
V2		TOTAL			737	740	99.59
V2S	sec_cm_additional_check	keymgr_sec_cm	12.390s	1.128ms	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	12.390s	1.128ms	5	5	100.00
		keymgr_tl_intg_err	9.300s	314.710us	20	20	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	5.280s	623.102us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	5.280s	623.102us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	5.280s	623.102us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	5.280s	623.102us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	13.740s	800.406us	20	20	100.00
V2S	prim_count_check	keymgr_sec_cm	12.390s	1.128ms	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	12.390s	1.128ms	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	9.300s	314.710us	20	20	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	5.280s	623.102us	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	1.799m	12.411ms	50	50	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	40.820s	2.400ms	50	50	100.00
		keymgr_csr_rw	1.460s	255.974us	20	20	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	40.820s	2.400ms	50	50	100.00
		keymgr_csr_rw	1.460s	255.974us	20	20	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	40.820s	2.400ms	50	50	100.00
		keymgr_csr_rw	1.460s	255.974us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	35.910s	4.271ms	49	50	98.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	1.052m	5.229ms	49	50	98.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	1.052m	5.229ms	49	50	98.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	40.820s	2.400ms	50	50	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	43.090s	13.145ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	12.390s	1.128ms	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	12.390s	1.128ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	12.390s	1.128ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	56.350s	2.007ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	35.910s	4.271ms	49	50	98.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	12.390s	1.128ms	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	12.390s	1.128ms	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	12.390s	1.128ms	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	56.350s	2.007ms	50	50	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	56.350s	2.007ms	50	50	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	12.390s	1.128ms	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	56.350s	2.007ms	50	50	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	12.390s	1.128ms	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	56.350s	2.007ms	50	50	100.00
V2S		TOTAL			165	165	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	26.910s	2.073ms	33	50	66.00
V3		TOTAL			33	50	66.00
		TOTAL			1090	1110	98.20

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	16	16	13	81.25
V2S	6	6	6	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.71	99.04	97.99	98.34	100.00	99.02	98.41	91.17

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:839) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 16 failures:

  • Test keymgr_stress_all_with_rand_reset has 16 failures.

    • 1.keymgr_stress_all_with_rand_reset.71629839190622537136067732491506047419260376800351273173450424498349506805277
      Line 366, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/1.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 106009892 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 106009892 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 5.keymgr_stress_all_with_rand_reset.96160769205257042975398301273193824180043169287045393793543427521523267072481
      Line 739, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/5.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 218384721 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 218384721 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 14 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 3 failures:

  • Test keymgr_hwsw_invalid_input has 1 failures.

    • 11.keymgr_hwsw_invalid_input.54410725912596418827809791790631047889311753797763153754091764817537831784077
      Line 280, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/11.keymgr_hwsw_invalid_input/latest/run.log

        UVM_ERROR @  17335642 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
        UVM_INFO @  17335642 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test keymgr_stress_all_with_rand_reset has 1 failures.

    • 24.keymgr_stress_all_with_rand_reset.96364231842547090073601209402630514324402518602811938566447163684141013078597
      Line 663, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/24.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @  78086653 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
        UVM_INFO @  78086653 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test keymgr_lc_disable has 1 failures.

    • 43.keymgr_lc_disable.45511091826315236244809652894811790512491392469064814374953202247393780373470
      Line 461, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/43.keymgr_lc_disable/latest/run.log

        UVM_ERROR @  52895255 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:2000
        UVM_INFO @  52895255 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_scoreboard.sv:261) scoreboard [scoreboard] alert recov_operation_err is not received! has 1 failures:

  • Test keymgr_sync_async_fault_cross has 1 failures.

    • 26.keymgr_sync_async_fault_cross.100260982475326245914740904646505800304917100130840906133126054879766849546392
      Line 304, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/26.keymgr_sync_async_fault_cross/latest/run.log

        UVM_ERROR @  41972006 ps: (cip_base_scoreboard.sv:261) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err is not received!
        UVM_INFO @  41972006 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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