KEYMGR Simulation Results

Tuesday August 06 2024 23:02:29 UTC

GitHub Revision: `5fd4ecc0fc`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 56304622830272859824235340993951659280265419461975949533183046575604373639200

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	28.800s	5.909ms	50	50	100.00
V1	random	keymgr_random	1.635m	11.520ms	50	50	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.220s	17.279us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	1.540s	144.043us	20	20	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	19.080s	2.303ms	5	5	100.00
V1	csr_aliasing	keymgr_csr_aliasing	12.990s	2.043ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.490s	102.513us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.540s	144.043us	20	20	100.00
		keymgr_csr_aliasing	12.990s	2.043ms	5	5	100.00
V1		TOTAL			155	155	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	2.042m	2.482ms	50	50	100.00
V2	sideload	keymgr_sideload	40.590s	1.476ms	50	50	100.00
		keymgr_sideload_kmac	1.005m	3.455ms	50	50	100.00
		keymgr_sideload_aes	54.400s	6.959ms	50	50	100.00
		keymgr_sideload_otbn	46.400s	2.047ms	50	50	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	41.320s	5.602ms	50	50	100.00
V2	lc_disable	keymgr_lc_disable	13.150s	299.641us	49	50	98.00
V2	kmac_error_response	keymgr_kmac_rsp_err	32.900s	2.974ms	50	50	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	1.069m	2.082ms	49	50	98.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	33.080s	11.136ms	50	50	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	23.890s	1.900ms	50	50	100.00
V2	stress_all	keymgr_stress_all	7.478m	123.220ms	47	50	94.00
V2	intr_test	keymgr_intr_test	0.940s	19.283us	50	50	100.00
V2	alert_test	keymgr_alert_test	1.020s	21.745us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	4.660s	618.154us	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	4.660s	618.154us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.220s	17.279us	5	5	100.00
		keymgr_csr_rw	1.540s	144.043us	20	20	100.00
		keymgr_csr_aliasing	12.990s	2.043ms	5	5	100.00
		keymgr_same_csr_outstanding	4.000s	519.163us	20	20	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.220s	17.279us	5	5	100.00
		keymgr_csr_rw	1.540s	144.043us	20	20	100.00
		keymgr_csr_aliasing	12.990s	2.043ms	5	5	100.00
		keymgr_same_csr_outstanding	4.000s	519.163us	20	20	100.00
V2		TOTAL			735	740	99.32
V2S	sec_cm_additional_check	keymgr_sec_cm	18.230s	703.413us	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	18.230s	703.413us	5	5	100.00
		keymgr_tl_intg_err	8.880s	215.769us	20	20	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	4.150s	228.274us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	4.150s	228.274us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	4.150s	228.274us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	4.150s	228.274us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	14.940s	1.657ms	20	20	100.00
V2S	prim_count_check	keymgr_sec_cm	18.230s	703.413us	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	18.230s	703.413us	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	8.880s	215.769us	20	20	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	4.150s	228.274us	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	2.042m	2.482ms	50	50	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	1.635m	11.520ms	50	50	100.00
		keymgr_csr_rw	1.540s	144.043us	20	20	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	1.635m	11.520ms	50	50	100.00
		keymgr_csr_rw	1.540s	144.043us	20	20	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	1.635m	11.520ms	50	50	100.00
		keymgr_csr_rw	1.540s	144.043us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	13.150s	299.641us	49	50	98.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	33.080s	11.136ms	50	50	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	33.080s	11.136ms	50	50	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	1.635m	11.520ms	50	50	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	10.030s	827.295us	50	50	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	18.230s	703.413us	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	18.230s	703.413us	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	18.230s	703.413us	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	45.220s	1.648ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	13.150s	299.641us	49	50	98.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	18.230s	703.413us	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	18.230s	703.413us	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	18.230s	703.413us	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	45.220s	1.648ms	50	50	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	45.220s	1.648ms	50	50	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	18.230s	703.413us	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	45.220s	1.648ms	50	50	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	18.230s	703.413us	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	45.220s	1.648ms	50	50	100.00
V2S		TOTAL			165	165	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	23.130s	738.100us	26	50	52.00
V3		TOTAL			26	50	52.00
		TOTAL			1081	1110	97.39

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	16	16	13	81.25
V2S	6	6	6	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.88	99.04	98.19	99.29	100.00	99.02	98.41	91.24

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:836) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 24 failures:
- Test keymgr_stress_all_with_rand_reset has 24 failures.
  - 2.keymgr_stress_all_with_rand_reset.79022006803817850616702506951085117217617096137702093846339676017160526901379
    Line 331, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/2.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 225578843 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 225578843 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.keymgr_stress_all_with_rand_reset.60354451037898473128813840713196669612656161950265531020016127022389231497338
    Line 426, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/4.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 439612079 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 439612079 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 22 more failures.
UVM_ERROR (cip_base_scoreboard.sv:304) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 2 failures:
- Test keymgr_stress_all has 1 failures.
  - 8.keymgr_stress_all.74708160315483911397433858233188577037489266565518437227871012006350674090618
    Line 2418, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/8.keymgr_stress_all/latest/run.log
```
  UVM_ERROR @ 1447579712 ps: (cip_base_scoreboard.sv:304) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:2000
  UVM_INFO @ 1447579712 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test keymgr_sw_invalid_input has 1 failures.
  - 9.keymgr_sw_invalid_input.12314238265396234917696318507104274014525404312050243150232188728203838398105
    Line 524, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/9.keymgr_sw_invalid_input/latest/run.log
```
  UVM_ERROR @ 154139050 ps: (cip_base_scoreboard.sv:304) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @ 154139050 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (keymgr_scoreboard.sv:651) [scoreboard] Check failed act_state == addr_phase_working_state (* [*] vs * [*]) has 1 failures:
- Test keymgr_stress_all has 1 failures.
  - 25.keymgr_stress_all.45801638083382619749365145373346792573787359650223936656257577709694157627187
    Line 4786, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/25.keymgr_stress_all/latest/run.log
```
  UVM_ERROR @ 9332275813 ps: (keymgr_scoreboard.sv:651) [uvm_test_top.env.scoreboard] Check failed act_state == addr_phase_working_state (1 [0x1] vs 6 [0x6])
  UVM_INFO @ 9332275813 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[*], act_key.key[*]} !== keys_a_array[state][cdi][dest] (* [*] vs * [*]) KMAC key at state StOwnerKey for Attestation Kmac has 1 failures:

Test keymgr_lc_disable has 1 failures.

33.keymgr_lc_disable.76942869274679538615046450332987333760469495884963861435717834018135225542429
Line 534, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/33.keymgr_lc_disable/latest/run.log

  UVM_ERROR @  56496496 ps: (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[1], act_key.key[0]} !== keys_a_array[state][cdi][dest] (2524193594073568532425392529172516644512678887958850276599383618165066681919839551444695288160389702691155700286201612586923930974174567656867534460473559 [0x30320053c948c3b604124637a29c1f9c6bbcb45807716391507e2742ab0664363937795a27eb938c8b07c700e9f24fe791e09d1e28dd92ad59de9086053cd0d7] vs 2524193594073568532425392529172516644512678887958850276599383618165066681919839551444695288160389702691155700286201612586923930974174567656867534460473559 [0x30320053c948c3b604124637a29c1f9c6bbcb45807716391507e2742ab0664363937795a27eb938c8b07c700e9f24fe791e09d1e28dd92ad59de9086053cd0d7]) KMAC key at state StOwnerKey for Attestation Kmac
  UVM_INFO @  56496496 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data !=gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.sw_share1_output_*` has 1 failures:
- Test keymgr_stress_all has 1 failures.
  - 35.keymgr_stress_all.5216716064569166175918248714427888383539978176892914682216778084037466806479
    Line 2195, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/35.keymgr_stress_all/latest/run.log
```
  UVM_ERROR @ 593147718 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (705178879 [0x2a082cff] vs 705178879 [0x2a082cff]) reg name: keymgr_reg_block.sw_share1_output_6
  UVM_INFO @ 593147718 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```