KEYMGR Simulation Results

Wednesday August 07 2024 23:02:33 UTC

GitHub Revision: `bbf435ceff`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 6888687353677204195542416712589698377810102273194685652880785004967849651007

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	29.750s	1.815ms	50	50	100.00
V1	random	keymgr_random	1.393m	4.732ms	50	50	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.560s	46.910us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	1.630s	29.124us	20	20	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	26.150s	3.060ms	5	5	100.00
V1	csr_aliasing	keymgr_csr_aliasing	15.940s	909.076us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.440s	35.185us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.630s	29.124us	20	20	100.00
		keymgr_csr_aliasing	15.940s	909.076us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	1.560m	11.721ms	49	50	98.00
V2	sideload	keymgr_sideload	36.120s	2.879ms	50	50	100.00
		keymgr_sideload_kmac	1.087m	6.162ms	50	50	100.00
		keymgr_sideload_aes	54.560s	18.092ms	50	50	100.00
		keymgr_sideload_otbn	23.170s	1.146ms	50	50	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	17.260s	1.624ms	50	50	100.00
V2	lc_disable	keymgr_lc_disable	7.460s	788.554us	48	50	96.00
V2	kmac_error_response	keymgr_kmac_rsp_err	6.880s	326.471us	50	50	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	1.019m	24.214ms	50	50	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	1.029m	2.781ms	49	50	98.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	6.920s	1.380ms	49	50	98.00
V2	stress_all	keymgr_stress_all	7.393m	134.635ms	48	50	96.00
V2	intr_test	keymgr_intr_test	1.020s	17.021us	50	50	100.00
V2	alert_test	keymgr_alert_test	1.080s	25.508us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	6.810s	1.102ms	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	6.810s	1.102ms	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.560s	46.910us	5	5	100.00
		keymgr_csr_rw	1.630s	29.124us	20	20	100.00
		keymgr_csr_aliasing	15.940s	909.076us	5	5	100.00
		keymgr_same_csr_outstanding	3.310s	113.169us	20	20	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.560s	46.910us	5	5	100.00
		keymgr_csr_rw	1.630s	29.124us	20	20	100.00
		keymgr_csr_aliasing	15.940s	909.076us	5	5	100.00
		keymgr_same_csr_outstanding	3.310s	113.169us	20	20	100.00
V2		TOTAL			733	740	99.05
V2S	sec_cm_additional_check	keymgr_sec_cm	15.770s	1.026ms	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	15.770s	1.026ms	5	5	100.00
		keymgr_tl_intg_err	9.620s	490.642us	20	20	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	5.730s	361.715us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	5.730s	361.715us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	5.730s	361.715us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	5.730s	361.715us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	14.680s	444.435us	20	20	100.00
V2S	prim_count_check	keymgr_sec_cm	15.770s	1.026ms	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	15.770s	1.026ms	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	9.620s	490.642us	20	20	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	5.730s	361.715us	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	1.560m	11.721ms	49	50	98.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	1.393m	4.732ms	50	50	100.00
		keymgr_csr_rw	1.630s	29.124us	20	20	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	1.393m	4.732ms	50	50	100.00
		keymgr_csr_rw	1.630s	29.124us	20	20	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	1.393m	4.732ms	50	50	100.00
		keymgr_csr_rw	1.630s	29.124us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	7.460s	788.554us	48	50	96.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	1.029m	2.781ms	49	50	98.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	1.029m	2.781ms	49	50	98.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	1.393m	4.732ms	50	50	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	34.200s	17.151ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	15.770s	1.026ms	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	15.770s	1.026ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	15.770s	1.026ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	38.560s	2.409ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	7.460s	788.554us	48	50	96.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	15.770s	1.026ms	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	15.770s	1.026ms	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	15.770s	1.026ms	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	38.560s	2.409ms	50	50	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	38.560s	2.409ms	50	50	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	15.770s	1.026ms	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	38.560s	2.409ms	50	50	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	15.770s	1.026ms	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	38.560s	2.409ms	50	50	100.00
V2S		TOTAL			165	165	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	33.230s	5.303ms	26	50	52.00
V3		TOTAL			26	50	52.00
		TOTAL			1079	1110	97.21

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	16	16	11	68.75
V2S	6	6	6	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.75	99.04	98.07	98.53	100.00	99.02	98.41	91.22

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:836) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 23 failures:
- Test keymgr_stress_all_with_rand_reset has 23 failures.
  - 1.keymgr_stress_all_with_rand_reset.97564424782345134327682325707607192247286599863235239096091427790506163337014
    Line 510, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/1.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 234319584 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 234319584 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.keymgr_stress_all_with_rand_reset.89811388669196690827993518218509727811482926521477340444021590859365071108130
    Line 320, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/3.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 120063932 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 120063932 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 21 more failures.
UVM_ERROR (cip_base_scoreboard.sv:304) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 3 failures:
- Test keymgr_hwsw_invalid_input has 1 failures.
  - 1.keymgr_hwsw_invalid_input.1035307684319898010944683829139634494095005191626771474907590672072638153965
    Line 410, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/1.keymgr_hwsw_invalid_input/latest/run.log
```
  UVM_ERROR @   9733658 ps: (cip_base_scoreboard.sv:304) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @   9733658 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test keymgr_lc_disable has 1 failures.
  - 5.keymgr_lc_disable.71974054776763746156189178899005471414273251941412125287320448011362866545466
    Line 350, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/5.keymgr_lc_disable/latest/run.log
```
  UVM_ERROR @  12423655 ps: (cip_base_scoreboard.sv:304) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @  12423655 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test keymgr_stress_all has 1 failures.
  - 8.keymgr_stress_all.17792026055300410353941017921942782183271672203152951130929921240590030229328
    Line 1220, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/8.keymgr_stress_all/latest/run.log
```
  UVM_ERROR @ 1926039042 ps: (cip_base_scoreboard.sv:304) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @ 1926039042 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_scoreboard.sv:262) scoreboard [scoreboard] alert recov_operation_err is not received! has 1 failures:
- Test keymgr_sync_async_fault_cross has 1 failures.
  - 1.keymgr_sync_async_fault_cross.19477614107407943160391848625013180689978528940291600589873896844555207762249
    Line 324, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/1.keymgr_sync_async_fault_cross/latest/run.log
```
  UVM_ERROR @  66695298 ps: (cip_base_scoreboard.sv:262) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err is not received!
  UVM_INFO @  66695298 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data !=gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.sw_share0_output_*` has 1 failures:
- Test keymgr_stress_all_with_rand_reset has 1 failures.
  - 12.keymgr_stress_all_with_rand_reset.65052712253363211302858184607493488191063522542519350734798794660263211310521
    Line 751, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/12.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 362875726 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (1673018920 [0x63b83e28] vs 1673018920 [0x63b83e28]) reg name: keymgr_reg_block.sw_share0_output_3
  UVM_INFO @ 362875726 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (keymgr_scoreboard.sv:689) [scoreboard] Check failed edn_fifos[*].used() == * (* [*] vs * [*]) has 1 failures:
- Test keymgr_stress_all has 1 failures.
  - 27.keymgr_stress_all.71878512553196202047559424755305518810849084618746649932384530340102073980604
    Line 1488, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/27.keymgr_stress_all/latest/run.log
```
  UVM_ERROR @ 235584566 ps: (keymgr_scoreboard.sv:689) [uvm_test_top.env.scoreboard] Check failed edn_fifos[0].used() == 2 (0 [0x0] vs 2 [0x2])
  UVM_INFO @ 235584566 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[*], act_key.key[*]} !== keys_a_array[state][cdi][dest] (* [*] vs * [*]) AES key at state StCreatorRootKey for Attestation Aes has 1 failures:

Test keymgr_lc_disable has 1 failures.

28.keymgr_lc_disable.25628190886744942854552350435191170620744094465422331731953979595582657943389
Line 438, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/28.keymgr_lc_disable/latest/run.log

  UVM_ERROR @  96955070 ps: (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[1], act_key.key[0]} !== keys_a_array[state][cdi][dest] (12482219684827921451236602703670747790961109081507121213379717387239214864845807375110494886654870927464646710502687307086510914283625784169603450165983367 [0xee53d1a36abae83e5687f640aab724b879b3c364d4a5ff5cf7fa794890afca81822cffb924ae0b50f892f76867adda99feb4b0b50138bf618e0dff9269b2f887] vs 12482219684827921451236602703670747790961109081507121213379717387239214864845807375110494886654870927464646710502687307086510914283625784169603450165983367 [0xee53d1a36abae83e5687f640aab724b879b3c364d4a5ff5cf7fa794890afca81822cffb924ae0b50f892f76867adda99feb4b0b50138bf618e0dff9269b2f887]) AES key at state StCreatorRootKey for Attestation Aes
  UVM_INFO @  96955070 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (keymgr_scoreboard.sv:794) [scoreboard] Check failed item.d_data ==gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.start` has 1 failures:
- Test keymgr_cfg_regwen has 1 failures.
  - 46.keymgr_cfg_regwen.29645070599795087133282842409892447319771332670246489088789624681392138597931
    Line 264, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/46.keymgr_cfg_regwen/latest/run.log
```
  UVM_ERROR @   5572182 ps: (keymgr_scoreboard.sv:794) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (0 [0x0] vs 1 [0x1]) reg name: keymgr_reg_block.start
  UVM_INFO @   5572182 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```