KEYMGR Simulation Results

Thursday August 08 2024 23:02:08 UTC

GitHub Revision: `3707c48f56`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 96859198578252641766218135484681220968075710602306197013001824903089223290045

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	48.230s	5.743ms	50	50	100.00
V1	random	keymgr_random	1.317m	22.075ms	50	50	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.530s	139.760us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	1.620s	268.107us	20	20	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	24.600s	2.860ms	5	5	100.00
V1	csr_aliasing	keymgr_csr_aliasing	18.750s	9.131ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.390s	306.843us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.620s	268.107us	20	20	100.00
		keymgr_csr_aliasing	18.750s	9.131ms	5	5	100.00
V1		TOTAL			155	155	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	1.012m	2.434ms	50	50	100.00
V2	sideload	keymgr_sideload	41.280s	3.187ms	50	50	100.00
		keymgr_sideload_kmac	39.480s	1.580ms	50	50	100.00
		keymgr_sideload_aes	56.940s	25.787ms	50	50	100.00
		keymgr_sideload_otbn	41.620s	2.213ms	50	50	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	27.860s	4.399ms	50	50	100.00
V2	lc_disable	keymgr_lc_disable	1.011m	3.929ms	50	50	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	12.270s	1.223ms	50	50	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	1.416m	7.645ms	50	50	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	1.265m	17.912ms	48	50	96.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	24.540s	2.390ms	50	50	100.00
V2	stress_all	keymgr_stress_all	9.001m	146.104ms	48	50	96.00
V2	intr_test	keymgr_intr_test	0.940s	18.390us	50	50	100.00
V2	alert_test	keymgr_alert_test	1.060s	79.903us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	4.620s	135.246us	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	4.620s	135.246us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.530s	139.760us	5	5	100.00
		keymgr_csr_rw	1.620s	268.107us	20	20	100.00
		keymgr_csr_aliasing	18.750s	9.131ms	5	5	100.00
		keymgr_same_csr_outstanding	4.120s	117.397us	20	20	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.530s	139.760us	5	5	100.00
		keymgr_csr_rw	1.620s	268.107us	20	20	100.00
		keymgr_csr_aliasing	18.750s	9.131ms	5	5	100.00
		keymgr_same_csr_outstanding	4.120s	117.397us	20	20	100.00
V2		TOTAL			736	740	99.46
V2S	sec_cm_additional_check	keymgr_sec_cm	17.040s	1.086ms	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	17.040s	1.086ms	5	5	100.00
		keymgr_tl_intg_err	9.100s	279.313us	20	20	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	4.380s	160.697us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	4.380s	160.697us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	4.380s	160.697us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	4.380s	160.697us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	15.440s	2.565ms	20	20	100.00
V2S	prim_count_check	keymgr_sec_cm	17.040s	1.086ms	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	17.040s	1.086ms	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	9.100s	279.313us	20	20	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	4.380s	160.697us	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	1.012m	2.434ms	50	50	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	1.317m	22.075ms	50	50	100.00
		keymgr_csr_rw	1.620s	268.107us	20	20	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	1.317m	22.075ms	50	50	100.00
		keymgr_csr_rw	1.620s	268.107us	20	20	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	1.317m	22.075ms	50	50	100.00
		keymgr_csr_rw	1.620s	268.107us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	1.011m	3.929ms	50	50	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	1.265m	17.912ms	48	50	96.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	1.265m	17.912ms	48	50	96.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	1.317m	22.075ms	50	50	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	24.490s	2.613ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	17.040s	1.086ms	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	17.040s	1.086ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	17.040s	1.086ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	12.620s	544.180us	50	50	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	1.011m	3.929ms	50	50	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	17.040s	1.086ms	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	17.040s	1.086ms	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	17.040s	1.086ms	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	12.620s	544.180us	50	50	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	12.620s	544.180us	50	50	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	17.040s	1.086ms	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	12.620s	544.180us	50	50	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	17.040s	1.086ms	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	12.620s	544.180us	50	50	100.00
V2S		TOTAL			165	165	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	30.670s	6.065ms	25	50	50.00
V3		TOTAL			25	50	50.00
		TOTAL			1081	1110	97.39

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	16	16	14	87.50
V2S	6	6	6	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.73	99.04	98.11	98.40	100.00	99.02	98.41	91.17

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:836) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 23 failures:
- Test keymgr_stress_all_with_rand_reset has 23 failures.
  - 1.keymgr_stress_all_with_rand_reset.103341444907803207556135268647268010069538546208860844109240596010044954068495
    Line 302, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/1.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 113430141 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10004 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 113430141 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 5.keymgr_stress_all_with_rand_reset.43368723149224589000580581623975041006972869972787228832800430697296903128523
    Line 486, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/5.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1138356957 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1138356957 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 21 more failures.
UVM_ERROR (cip_base_scoreboard.sv:242) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_operation_err triggered unexpectedly has 2 failures:
- Test keymgr_hwsw_invalid_input has 2 failures.
  - 10.keymgr_hwsw_invalid_input.21173915455067364293105371587669400424874493769046464554323020881251057602797
    Line 363, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/10.keymgr_hwsw_invalid_input/latest/run.log
```
  UVM_ERROR @  24761328 ps: (cip_base_scoreboard.sv:242) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_operation_err triggered unexpectedly
  UVM_INFO @  24761328 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 33.keymgr_hwsw_invalid_input.112404912292638413892819844498891428166601353896056528598626749916179972768872
    Line 469, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/33.keymgr_hwsw_invalid_input/latest/run.log
```
  UVM_ERROR @  60439684 ps: (cip_base_scoreboard.sv:242) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_operation_err triggered unexpectedly
  UVM_INFO @  60439684 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:755) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 2 failures:
- Test keymgr_stress_all_with_rand_reset has 2 failures.
  - 32.keymgr_stress_all_with_rand_reset.20703448998497553893753845834797243027631912982974960576622621446153468493286
    Line 271, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/32.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 568494379 ps: (cip_base_vseq.sv:755) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 568494379 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 35.keymgr_stress_all_with_rand_reset.16366541044540216953032316891044297967154990040161941366263759145092656649850
    Line 396, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/35.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 118888727 ps: (cip_base_vseq.sv:755) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 118888727 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[*], act_key.key[*]} !== keys_a_array[state][cdi][dest] (* [*] vs * [*]) AES key at state StOwnerIntKey for Attestation Aes has 1 failures:

Test keymgr_stress_all has 1 failures.

5.keymgr_stress_all.13621400959954959884138402670820716485331965581459353096812606269406409833834
Line 585, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/5.keymgr_stress_all/latest/run.log

  UVM_ERROR @ 100785528 ps: (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[1], act_key.key[0]} !== keys_a_array[state][cdi][dest] (10000429949883575769399280904873188492489501974266648818256367716274365512442037629750144362101436721247689276635178658387162521617225513671018649493576407 [0xbef115578e52c9f1cab3946ef834344e239355d3a27b48b4c312d7c26c4179b2c48dbb7694b74cd005ea254b06860573daf4219ef6cd812f4096e3fadbbe1ad7] vs 10000429949883575769399280904873188492489501974266648818256367716274365512442037629750144362101436721247689276635178658387162521617225513671018649493576407 [0xbef115578e52c9f1cab3946ef834344e239355d3a27b48b4c312d7c26c4179b2c48dbb7694b74cd005ea254b06860573daf4219ef6cd812f4096e3fadbbe1ad7]) AES key at state StOwnerIntKey for Attestation Aes
  UVM_INFO @ 100785528 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_scoreboard.sv:304) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 1 failures:
- Test keymgr_stress_all has 1 failures.
  - 22.keymgr_stress_all.11224722557964176618994114021507687952449129157085453253856707831700742889477
    Line 2862, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/22.keymgr_stress_all/latest/run.log
```
  UVM_ERROR @ 3110655340 ps: (cip_base_scoreboard.sv:304) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @ 3110655340 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```