KEYMGR Simulation Results

Wednesday August 14 2024 23:02:33 UTC

GitHub Revision: `584c3d46af`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 75916000169703078066460267353397937307391759551032957123310220571514951708138

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	34.880s	3.946ms	50	50	100.00
V1	random	keymgr_random	54.020s	5.951ms	50	50	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.130s	29.690us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	1.440s	362.358us	20	20	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	16.330s	667.824us	5	5	100.00
V1	csr_aliasing	keymgr_csr_aliasing	7.520s	265.261us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.210s	37.540us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.440s	362.358us	20	20	100.00
		keymgr_csr_aliasing	7.520s	265.261us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	2.627m	11.174ms	49	50	98.00
V2	sideload	keymgr_sideload	36.090s	2.899ms	49	50	98.00
		keymgr_sideload_kmac	29.000s	11.641ms	50	50	100.00
		keymgr_sideload_aes	59.380s	7.395ms	50	50	100.00
		keymgr_sideload_otbn	41.580s	1.740ms	50	50	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	20.040s	1.931ms	50	50	100.00
V2	lc_disable	keymgr_lc_disable	24.030s	792.723us	50	50	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	9.700s	462.517us	50	50	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	56.780s	4.094ms	50	50	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	1.082m	4.107ms	50	50	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	10.420s	600.542us	50	50	100.00
V2	stress_all	keymgr_stress_all	9.708m	95.811ms	48	50	96.00
V2	intr_test	keymgr_intr_test	0.980s	13.884us	50	50	100.00
V2	alert_test	keymgr_alert_test	1.110s	28.251us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	6.180s	1.106ms	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	6.180s	1.106ms	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.130s	29.690us	5	5	100.00
		keymgr_csr_rw	1.440s	362.358us	20	20	100.00
		keymgr_csr_aliasing	7.520s	265.261us	5	5	100.00
		keymgr_same_csr_outstanding	4.640s	336.616us	20	20	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.130s	29.690us	5	5	100.00
		keymgr_csr_rw	1.440s	362.358us	20	20	100.00
		keymgr_csr_aliasing	7.520s	265.261us	5	5	100.00
		keymgr_same_csr_outstanding	4.640s	336.616us	20	20	100.00
V2		TOTAL			736	740	99.46
V2S	sec_cm_additional_check	keymgr_sec_cm	22.490s	1.008ms	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	22.490s	1.008ms	5	5	100.00
		keymgr_tl_intg_err	9.420s	549.441us	20	20	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	5.250s	285.422us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	5.250s	285.422us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	5.250s	285.422us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	5.250s	285.422us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	14.920s	476.583us	20	20	100.00
V2S	prim_count_check	keymgr_sec_cm	22.490s	1.008ms	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	22.490s	1.008ms	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	9.420s	549.441us	20	20	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	5.250s	285.422us	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	2.627m	11.174ms	49	50	98.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	54.020s	5.951ms	50	50	100.00
		keymgr_csr_rw	1.440s	362.358us	20	20	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	54.020s	5.951ms	50	50	100.00
		keymgr_csr_rw	1.440s	362.358us	20	20	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	54.020s	5.951ms	50	50	100.00
		keymgr_csr_rw	1.440s	362.358us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	24.030s	792.723us	50	50	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	1.082m	4.107ms	50	50	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	1.082m	4.107ms	50	50	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	54.020s	5.951ms	50	50	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	28.350s	2.730ms	49	50	98.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	22.490s	1.008ms	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	22.490s	1.008ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	22.490s	1.008ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	1.028m	3.704ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	24.030s	792.723us	50	50	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	22.490s	1.008ms	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	22.490s	1.008ms	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	22.490s	1.008ms	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	1.028m	3.704ms	50	50	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	1.028m	3.704ms	50	50	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	22.490s	1.008ms	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	1.028m	3.704ms	50	50	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	22.490s	1.008ms	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	1.028m	3.704ms	50	50	100.00
V2S		TOTAL			164	165	99.39
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	26.610s	2.484ms	29	50	58.00
V3		TOTAL			29	50	58.00
		TOTAL			1084	1110	97.66

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	16	16	13	81.25
V2S	6	6	5	83.33
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.74	99.04	97.95	98.47	100.00	99.02	98.41	91.27

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:867) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 20 failures:
- Test keymgr_stress_all_with_rand_reset has 20 failures.
  - 2.keymgr_stress_all_with_rand_reset.93920295390355873261191397496148107006853617643206834195376873291522240967873
    Line 746, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/2.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 244918198 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 244918198 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 6.keymgr_stress_all_with_rand_reset.15058397812696685464877465100050753515884378236558144976896735276776120305105
    Line 904, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/6.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 611532765 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 611532765 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 18 more failures.

UVM_ERROR (cip_base_scoreboard.sv:304) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 5 failures:

Test keymgr_sideload_protect has 1 failures.

10.keymgr_sideload_protect.10462245967060824389585556100594503017192337947276937894090575462040727697286
Line 338, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/10.keymgr_sideload_protect/latest/run.log

  UVM_ERROR @  30691354 ps: (cip_base_scoreboard.sv:304) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @  30691354 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_stress_all has 2 failures.

31.keymgr_stress_all.45766800604307435794856744755176253870632138471950733409326556516963535224949
Line 1366, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/31.keymgr_stress_all/latest/run.log

  UVM_ERROR @ 272922066 ps: (cip_base_scoreboard.sv:304) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @ 272922066 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

32.keymgr_stress_all.44901193617744710004376782194723514787478937049261140582565710989047174447538
Line 5140, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/32.keymgr_stress_all/latest/run.log

  UVM_ERROR @ 994597412 ps: (cip_base_scoreboard.sv:304) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @ 994597412 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_cfg_regwen has 1 failures.

37.keymgr_cfg_regwen.91966077323952981119130712892807336538851359699231766196080150026975791777926
Line 718, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/37.keymgr_cfg_regwen/latest/run.log

  UVM_ERROR @  42350000 ps: (cip_base_scoreboard.sv:304) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @  42350000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_sideload has 1 failures.

42.keymgr_sideload.85749219548414830726471501379980136999824591740657555189002420251963977210727
Line 329, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/42.keymgr_sideload/latest/run.log

  UVM_ERROR @ 112303491 ps: (cip_base_scoreboard.sv:304) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @ 112303491 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data !=gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.sw_share1_output_*` has 1 failures:
- Test keymgr_stress_all_with_rand_reset has 1 failures.
  - 12.keymgr_stress_all_with_rand_reset.87865354247997129371111380203222756276074549303882000184243055217663672005603
    Line 1427, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/12.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 751225198 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (0 [0x0] vs 0 [0x0]) reg name: keymgr_reg_block.sw_share1_output_2
  UVM_INFO @ 751225198 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```