KEYMGR Simulation Results

Monday August 12 2024 23:02:30 UTC

GitHub Revision: `c082b8981f`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 107262934208806092150901079363789224644653433402469901409990667510497383888850

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	19.940s	1.118ms	50	50	100.00
V1	random	keymgr_random	1.146m	3.033ms	50	50	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.470s	34.353us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	1.360s	90.042us	20	20	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	41.190s	25.552ms	5	5	100.00
V1	csr_aliasing	keymgr_csr_aliasing	8.020s	963.251us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.310s	58.979us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.360s	90.042us	20	20	100.00
		keymgr_csr_aliasing	8.020s	963.251us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	2.042m	4.614ms	49	50	98.00
V2	sideload	keymgr_sideload	35.970s	2.819ms	50	50	100.00
		keymgr_sideload_kmac	35.170s	1.430ms	50	50	100.00
		keymgr_sideload_aes	46.950s	4.279ms	50	50	100.00
		keymgr_sideload_otbn	47.100s	1.604ms	50	50	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	27.500s	7.214ms	50	50	100.00
V2	lc_disable	keymgr_lc_disable	14.600s	553.000us	48	50	96.00
V2	kmac_error_response	keymgr_kmac_rsp_err	10.270s	448.635us	50	50	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	35.750s	1.515ms	50	50	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	1.004m	4.421ms	48	50	96.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	23.580s	4.553ms	50	50	100.00
V2	stress_all	keymgr_stress_all	5.082m	52.405ms	47	50	94.00
V2	intr_test	keymgr_intr_test	0.980s	244.368us	50	50	100.00
V2	alert_test	keymgr_alert_test	1.130s	161.273us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	3.870s	605.853us	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	3.870s	605.853us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.470s	34.353us	5	5	100.00
		keymgr_csr_rw	1.360s	90.042us	20	20	100.00
		keymgr_csr_aliasing	8.020s	963.251us	5	5	100.00
		keymgr_same_csr_outstanding	4.190s	131.074us	20	20	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.470s	34.353us	5	5	100.00
		keymgr_csr_rw	1.360s	90.042us	20	20	100.00
		keymgr_csr_aliasing	8.020s	963.251us	5	5	100.00
		keymgr_same_csr_outstanding	4.190s	131.074us	20	20	100.00
V2		TOTAL			732	740	98.92
V2S	sec_cm_additional_check	keymgr_sec_cm	17.690s	840.528us	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	17.690s	840.528us	5	5	100.00
		keymgr_tl_intg_err	8.910s	289.847us	20	20	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	4.960s	183.790us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	4.960s	183.790us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	4.960s	183.790us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	4.960s	183.790us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	15.260s	515.934us	20	20	100.00
V2S	prim_count_check	keymgr_sec_cm	17.690s	840.528us	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	17.690s	840.528us	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	8.910s	289.847us	20	20	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	4.960s	183.790us	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	2.042m	4.614ms	49	50	98.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	1.146m	3.033ms	50	50	100.00
		keymgr_csr_rw	1.360s	90.042us	20	20	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	1.146m	3.033ms	50	50	100.00
		keymgr_csr_rw	1.360s	90.042us	20	20	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	1.146m	3.033ms	50	50	100.00
		keymgr_csr_rw	1.360s	90.042us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	14.600s	553.000us	48	50	96.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	1.004m	4.421ms	48	50	96.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	1.004m	4.421ms	48	50	96.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	1.146m	3.033ms	50	50	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	27.870s	4.467ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	17.690s	840.528us	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	17.690s	840.528us	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	17.690s	840.528us	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	1.145m	11.109ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	14.600s	553.000us	48	50	96.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	17.690s	840.528us	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	17.690s	840.528us	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	17.690s	840.528us	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	1.145m	11.109ms	50	50	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	1.145m	11.109ms	50	50	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	17.690s	840.528us	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	1.145m	11.109ms	50	50	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	17.690s	840.528us	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	1.145m	11.109ms	50	50	100.00
V2S		TOTAL			165	165	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	30.620s	3.529ms	29	50	58.00
V3		TOTAL			29	50	58.00
		TOTAL			1081	1110	97.39

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	16	16	12	75.00
V2S	6	6	6	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.77	99.04	98.11	98.61	100.00	99.02	98.41	91.19

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:848) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 21 failures:
- Test keymgr_stress_all_with_rand_reset has 21 failures.
  - 0.keymgr_stress_all_with_rand_reset.69371256455334409691703747266614984379507192621765485710244137749296730370133
    Line 493, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/0.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 381581362 ps: (cip_base_vseq.sv:848) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 381581362 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.keymgr_stress_all_with_rand_reset.79720785350921706425043822703777882305638996131653005081092910133017257584868
    Line 365, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/4.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 116542125 ps: (cip_base_vseq.sv:848) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10006 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 116542125 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 19 more failures.
UVM_ERROR (cip_base_scoreboard.sv:304) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 3 failures:
- Test keymgr_hwsw_invalid_input has 1 failures.
  - 33.keymgr_hwsw_invalid_input.23536162313031208838904185260890812097637215997138343814738839574311596193346
    Line 378, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/33.keymgr_hwsw_invalid_input/latest/run.log
```
  UVM_ERROR @ 361649417 ps: (cip_base_scoreboard.sv:304) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @ 361649417 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test keymgr_stress_all has 2 failures.
  - 35.keymgr_stress_all.45687850218980550023621804716200433059311709034392978119271114369017759533656
    Line 1768, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/35.keymgr_stress_all/latest/run.log
```
  UVM_ERROR @ 3314181584 ps: (cip_base_scoreboard.sv:304) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @ 3314181584 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 39.keymgr_stress_all.7777806788777503328101242165948885187313252542983189569061582653986507766982
    Line 654, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/39.keymgr_stress_all/latest/run.log
```
  UVM_ERROR @ 274419740 ps: (cip_base_scoreboard.sv:304) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @ 274419740 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data !=gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.sw_share1_output_*` has 2 failures:
- Test keymgr_lc_disable has 1 failures.
  - 3.keymgr_lc_disable.5193886839055428250801340421126942924042324152922794956204559351058388033500
    Line 295, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/3.keymgr_lc_disable/latest/run.log
```
  UVM_ERROR @  38019857 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (0 [0x0] vs 0 [0x0]) reg name: keymgr_reg_block.sw_share1_output_1
  UVM_INFO @  38019857 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test keymgr_stress_all has 1 failures.
  - 33.keymgr_stress_all.86967475494329766058901442592385876851216942163890676349007891683304192789235
    Line 1876, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/33.keymgr_stress_all/latest/run.log
```
  UVM_ERROR @ 889970889 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (0 [0x0] vs 0 [0x0]) reg name: keymgr_reg_block.sw_share1_output_5
  UVM_INFO @ 889970889 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (keymgr_scoreboard.sv:692) [scoreboard] Check failed item.d_data == addr_phase_op_status (* [*] vs * [*]) has 1 failures:
- Test keymgr_lc_disable has 1 failures.
  - 38.keymgr_lc_disable.86565621601609603491615457731340941950304394185607587638189293851611487261068
    Line 386, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/38.keymgr_lc_disable/latest/run.log
```
  UVM_ERROR @  21141909 ps: (keymgr_scoreboard.sv:692) [uvm_test_top.env.scoreboard] Check failed item.d_data == addr_phase_op_status (2 [0x2] vs 3 [0x3])
  UVM_INFO @  21141909 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_scoreboard.sv:242) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_operation_err triggered unexpectedly has 1 failures:
- Test keymgr_hwsw_invalid_input has 1 failures.
  - 42.keymgr_hwsw_invalid_input.47529896448612957806922641104661669535658352936793039341987586759497800711594
    Line 448, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/42.keymgr_hwsw_invalid_input/latest/run.log
```
  UVM_ERROR @  14944651 ps: (cip_base_scoreboard.sv:242) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_operation_err triggered unexpectedly
  UVM_INFO @  14944651 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (keymgr_scoreboard.sv:794) [scoreboard] Check failed item.d_data ==gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.start` has 1 failures:
- Test keymgr_cfg_regwen has 1 failures.
  - 48.keymgr_cfg_regwen.17355972925068505414396966081607923583569315979390481806001919970580515852546
    Line 361, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/48.keymgr_cfg_regwen/latest/run.log
```
  UVM_ERROR @   9265392 ps: (keymgr_scoreboard.sv:794) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (0 [0x0] vs 1 [0x1]) reg name: keymgr_reg_block.start
  UVM_INFO @   9265392 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

KEYMGR Simulation Results

Monday August 12 2024 23:02:30 UTC

GitHub Revision: c082b8981f

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 107262934208806092150901079363789224644653433402469901409990667510497383888850

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `c082b8981f`