KEYMGR Simulation Results

Saturday August 10 2024 23:02:23 UTC

GitHub Revision: `07b417ef03`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 2196818177928134427831197337249851347498377272679561983541244979366753055772

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	40.840s	5.366ms	50	50	100.00
V1	random	keymgr_random	54.030s	8.967ms	50	50	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.500s	108.121us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	1.800s	573.812us	20	20	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	24.770s	1.779ms	5	5	100.00
V1	csr_aliasing	keymgr_csr_aliasing	9.310s	783.992us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.810s	925.862us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.800s	573.812us	20	20	100.00
		keymgr_csr_aliasing	9.310s	783.992us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	1.027m	6.026ms	50	50	100.00
V2	sideload	keymgr_sideload	34.070s	5.404ms	50	50	100.00
		keymgr_sideload_kmac	45.030s	4.058ms	50	50	100.00
		keymgr_sideload_aes	19.340s	522.058us	50	50	100.00
		keymgr_sideload_otbn	57.890s	7.680ms	50	50	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	20.330s	985.586us	50	50	100.00
V2	lc_disable	keymgr_lc_disable	6.270s	151.632us	48	50	96.00
V2	kmac_error_response	keymgr_kmac_rsp_err	11.140s	537.401us	50	50	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	1.375m	6.882ms	50	50	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	41.150s	1.763ms	49	50	98.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	30.680s	4.241ms	50	50	100.00
V2	stress_all	keymgr_stress_all	6.471m	37.466ms	48	50	96.00
V2	intr_test	keymgr_intr_test	0.950s	15.010us	50	50	100.00
V2	alert_test	keymgr_alert_test	1.020s	18.324us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	5.140s	143.103us	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	5.140s	143.103us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.500s	108.121us	5	5	100.00
		keymgr_csr_rw	1.800s	573.812us	20	20	100.00
		keymgr_csr_aliasing	9.310s	783.992us	5	5	100.00
		keymgr_same_csr_outstanding	4.960s	518.506us	20	20	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.500s	108.121us	5	5	100.00
		keymgr_csr_rw	1.800s	573.812us	20	20	100.00
		keymgr_csr_aliasing	9.310s	783.992us	5	5	100.00
		keymgr_same_csr_outstanding	4.960s	518.506us	20	20	100.00
V2		TOTAL			735	740	99.32
V2S	sec_cm_additional_check	keymgr_sec_cm	20.950s	733.804us	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	20.950s	733.804us	5	5	100.00
		keymgr_tl_intg_err	8.890s	532.835us	20	20	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	5.810s	677.539us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	5.810s	677.539us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	5.810s	677.539us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	5.810s	677.539us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	14.100s	1.699ms	20	20	100.00
V2S	prim_count_check	keymgr_sec_cm	20.950s	733.804us	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	20.950s	733.804us	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	8.890s	532.835us	20	20	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	5.810s	677.539us	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	1.027m	6.026ms	50	50	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	54.030s	8.967ms	50	50	100.00
		keymgr_csr_rw	1.800s	573.812us	20	20	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	54.030s	8.967ms	50	50	100.00
		keymgr_csr_rw	1.800s	573.812us	20	20	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	54.030s	8.967ms	50	50	100.00
		keymgr_csr_rw	1.800s	573.812us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	6.270s	151.632us	48	50	96.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	41.150s	1.763ms	49	50	98.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	41.150s	1.763ms	49	50	98.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	54.030s	8.967ms	50	50	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	18.500s	1.651ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	20.950s	733.804us	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	20.950s	733.804us	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	20.950s	733.804us	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	56.910s	8.537ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	6.270s	151.632us	48	50	96.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	20.950s	733.804us	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	20.950s	733.804us	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	20.950s	733.804us	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	56.910s	8.537ms	50	50	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	56.910s	8.537ms	50	50	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	20.950s	733.804us	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	56.910s	8.537ms	50	50	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	20.950s	733.804us	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	56.910s	8.537ms	50	50	100.00
V2S		TOTAL			165	165	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	26.200s	2.164ms	29	50	58.00
V3		TOTAL			29	50	58.00
		TOTAL			1084	1110	97.66

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	16	16	13	81.25
V2S	6	6	6	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.72	99.04	97.99	98.37	100.00	99.02	98.41	91.22

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:836) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 20 failures:
- Test keymgr_stress_all_with_rand_reset has 20 failures.
  - 0.keymgr_stress_all_with_rand_reset.87733497509627831909441455643870812250858966480525694632949052273994118504022
    Line 722, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/0.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 214559809 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 214559809 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.keymgr_stress_all_with_rand_reset.111434089576739158400659222656774608444497237699326471041329869804016552215311
    Line 340, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/2.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 441687765 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 441687765 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 18 more failures.

UVM_ERROR (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[*], act_key.key[*]} !== keys_a_array[state][cdi][dest] (* [*] vs * [*]) AES key at state StOwnerKey for Attestation Aes has 1 failures:

Test keymgr_lc_disable has 1 failures.

9.keymgr_lc_disable.48864530701511132704496765325085870894556462012616583859506520128737329612979
Line 479, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/9.keymgr_lc_disable/latest/run.log

  UVM_ERROR @ 574105326 ps: (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[1], act_key.key[0]} !== keys_a_array[state][cdi][dest] (7881648240361345244617704481940204306487001902646297402190311896047466356933731402543865273006902090880265612923517983792542728088217638883206480977106385 [0x967cb1b0ac5276a98c9d558b63e539358689ffffc5fc80cd28fac61f15b72687607d2fa9132fb9edf61cd02fb08ea32e80c50aa03230c9b792b1e6c8eace95d1] vs 7881648240361345244617704481940204306487001902646297402190311896047466356933731402543865273006902090880265612923517983792542728088217638883206480977106385 [0x967cb1b0ac5276a98c9d558b63e539358689ffffc5fc80cd28fac61f15b72687607d2fa9132fb9edf61cd02fb08ea32e80c50aa03230c9b792b1e6c8eace95d1]) AES key at state StOwnerKey for Attestation Aes
  UVM_INFO @ 574105326 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[*], act_key.key[*]} !== keys_a_array[state][cdi][dest] (* [*] vs * [*]) AES key at state StCreatorRootKey for Sealing Aes has 1 failures:

Test keymgr_lc_disable has 1 failures.

23.keymgr_lc_disable.107621919793088185263333947411184822780084060793575270249442785192015205261205
Line 370, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/23.keymgr_lc_disable/latest/run.log

  UVM_ERROR @  47337846 ps: (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[1], act_key.key[0]} !== keys_a_array[state][cdi][dest] (7941636493072681208615976668820563770048791374596076992412459339242484735433356510275145279862286672411738788740015315413638773861930817516637158551419001 [0x97a1e91b56d60710c1e603e1fb092df6359b60e54ffd1033aa3a9e214a2072a7e8cf548e3b9542ff21630173fd57838a6ebce041aebf6f9a0cb16d2aa59d7879] vs 7941636493072681208615976668820563770048791374596076992412459339242484735433356510275145279862286672411738788740015315413638773861930817516637158551419001 [0x97a1e91b56d60710c1e603e1fb092df6359b60e54ffd1033aa3a9e214a2072a7e8cf548e3b9542ff21630173fd57838a6ebce041aebf6f9a0cb16d2aa59d7879]) AES key at state StCreatorRootKey for Sealing Aes
  UVM_INFO @  47337846 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_vseq.sv:755) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test keymgr_stress_all_with_rand_reset has 1 failures.
  - 26.keymgr_stress_all_with_rand_reset.37054910890882834875945462491757515049710434977412108939738070636836912715577
    Line 270, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/26.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 651311740 ps: (cip_base_vseq.sv:755) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 651311740 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data !=gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.sw_share0_output_*` has 1 failures:
- Test keymgr_stress_all has 1 failures.
  - 31.keymgr_stress_all.79000851276808883485454859691680755878940971326207122997049981699470099352739
    Line 961, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/31.keymgr_stress_all/latest/run.log
```
  UVM_ERROR @ 2141793293 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (335213765 [0x13faf4c5] vs 335213765 [0x13faf4c5]) reg name: keymgr_reg_block.sw_share0_output_4
  UVM_INFO @ 2141793293 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_scoreboard.sv:304) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 1 failures:
- Test keymgr_hwsw_invalid_input has 1 failures.
  - 34.keymgr_hwsw_invalid_input.58252307109734331835047381995810832516782653814680227233711826987596474218071
    Line 338, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/34.keymgr_hwsw_invalid_input/latest/run.log
```
  UVM_ERROR @   6623952 ps: (cip_base_scoreboard.sv:304) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @   6623952 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data !=gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.sw_share1_output_*` has 1 failures:
- Test keymgr_stress_all has 1 failures.
  - 40.keymgr_stress_all.62176429214928783055198244285376242658747975139980502047467908357462246587114
    Line 2741, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/40.keymgr_stress_all/latest/run.log
```
  UVM_ERROR @ 881822448 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (0 [0x0] vs 0 [0x0]) reg name: keymgr_reg_block.sw_share1_output_1
  UVM_INFO @ 881822448 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```