KEYMGR Simulation Results

Friday August 09 2024 23:02:07 UTC

GitHub Revision: 07b417ef03

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 39866585070056138360117926942905553094756411441088058786676399955088054585836

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	47.600s	5.963ms	50	50	100.00
V1	random	keymgr_random	47.570s	4.323ms	50	50	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.370s	113.754us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	1.520s	52.517us	20	20	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	32.250s	5.145ms	5	5	100.00
V1	csr_aliasing	keymgr_csr_aliasing	13.460s	363.180us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.340s	55.361us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.520s	52.517us	20	20	100.00
		keymgr_csr_aliasing	13.460s	363.180us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	2.018m	9.044ms	50	50	100.00
V2	sideload	keymgr_sideload	40.810s	1.499ms	50	50	100.00
		keymgr_sideload_kmac	1.038m	6.303ms	50	50	100.00
		keymgr_sideload_aes	1.036m	6.626ms	50	50	100.00
		keymgr_sideload_otbn	1.105m	6.059ms	50	50	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	21.630s	1.193ms	50	50	100.00
V2	lc_disable	keymgr_lc_disable	17.900s	2.031ms	49	50	98.00
V2	kmac_error_response	keymgr_kmac_rsp_err	6.950s	1.659ms	50	50	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	1.032m	7.395ms	50	50	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	1.185m	9.858ms	50	50	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	19.000s	3.202ms	50	50	100.00
V2	stress_all	keymgr_stress_all	4.832m	53.694ms	49	50	98.00
V2	intr_test	keymgr_intr_test	0.940s	15.922us	50	50	100.00
V2	alert_test	keymgr_alert_test	1.130s	104.669us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	5.610s	621.697us	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	5.610s	621.697us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.370s	113.754us	5	5	100.00
		keymgr_csr_rw	1.520s	52.517us	20	20	100.00
		keymgr_csr_aliasing	13.460s	363.180us	5	5	100.00
		keymgr_same_csr_outstanding	3.720s	392.388us	20	20	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.370s	113.754us	5	5	100.00
		keymgr_csr_rw	1.520s	52.517us	20	20	100.00
		keymgr_csr_aliasing	13.460s	363.180us	5	5	100.00
		keymgr_same_csr_outstanding	3.720s	392.388us	20	20	100.00
V2		TOTAL			738	740	99.73
V2S	sec_cm_additional_check	keymgr_sec_cm	24.590s	1.250ms	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	24.590s	1.250ms	5	5	100.00
		keymgr_tl_intg_err	10.250s	282.275us	20	20	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	5.020s	305.230us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	5.020s	305.230us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	5.020s	305.230us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	5.020s	305.230us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	15.070s	3.022ms	20	20	100.00
V2S	prim_count_check	keymgr_sec_cm	24.590s	1.250ms	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	24.590s	1.250ms	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	10.250s	282.275us	20	20	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	5.020s	305.230us	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	2.018m	9.044ms	50	50	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	47.570s	4.323ms	50	50	100.00
		keymgr_csr_rw	1.520s	52.517us	20	20	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	47.570s	4.323ms	50	50	100.00
		keymgr_csr_rw	1.520s	52.517us	20	20	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	47.570s	4.323ms	50	50	100.00
		keymgr_csr_rw	1.520s	52.517us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	17.900s	2.031ms	49	50	98.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	1.185m	9.858ms	50	50	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	1.185m	9.858ms	50	50	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	47.570s	4.323ms	50	50	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	16.180s	1.662ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	24.590s	1.250ms	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	24.590s	1.250ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	24.590s	1.250ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	19.220s	7.041ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	17.900s	2.031ms	49	50	98.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	24.590s	1.250ms	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	24.590s	1.250ms	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	24.590s	1.250ms	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	19.220s	7.041ms	50	50	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	19.220s	7.041ms	50	50	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	24.590s	1.250ms	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	19.220s	7.041ms	50	50	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	24.590s	1.250ms	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	19.220s	7.041ms	50	50	100.00
V2S		TOTAL			165	165	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	26.360s	2.675ms	38	50	76.00
V3		TOTAL			38	50	76.00
		TOTAL			1096	1110	98.74

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	16	16	14	87.50
V2S	6	6	6	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.73	99.04	98.07	98.33	100.00	99.02	98.41	91.22

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:836) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 11 failures:

  • Test keymgr_stress_all_with_rand_reset has 11 failures.

    • 1.keymgr_stress_all_with_rand_reset.39528166025267623227054594031710581288226165926098444604129867661433545182089
      Line 401, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/1.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 406039052 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 406039052 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.keymgr_stress_all_with_rand_reset.26381803850988759323408193934741391382850399183094878522790668000555968419127
      Line 519, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/2.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 638724055 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 638724055 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 9 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:304) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 2 failures:

  • Test keymgr_lc_disable has 1 failures.

    • 37.keymgr_lc_disable.16820610751575721020797619718367617045913038183061361379251035616506106587111
      Line 325, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/37.keymgr_lc_disable/latest/run.log

        UVM_ERROR @  47592441 ps: (cip_base_scoreboard.sv:304) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:2000
        UVM_INFO @  47592441 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test keymgr_stress_all has 1 failures.

    • 44.keymgr_stress_all.103687155353487899395771342528704775972227336736254931488846246217322569888378
      Line 274, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/44.keymgr_stress_all/latest/run.log

        UVM_ERROR @  13122595 ps: (cip_base_scoreboard.sv:304) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
        UVM_INFO @  13122595 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:755) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:

  • Test keymgr_stress_all_with_rand_reset has 1 failures.

    • 45.keymgr_stress_all_with_rand_reset.50140523601451840408729640398181735610671148888987630593020855114986562431405
      Line 665, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/45.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 462996257 ps: (cip_base_vseq.sv:755) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 462996257 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• lint
• 2024.08.09_07.47.19
• 2024.08.08_08.59.07
• 2024.08.07_08.51.57
• 2024.08.06_09.24.40
• 2024.08.05_10.52.11
• 2024.08.04_06.40.30